TC3097-8
Preliminary Data Sheet
Lite End Multiport Repeater Interface Controller
Features
Functionally conforms to Section 9 in the IEEE 802.3 specification. 9 network connection (ports) per chip including: – 1 AUI PORT with fully compatible and drive capability (50m AUI cable). – 8 TP PORT with fully compatible and drive capability (100m TP cable). Cascadable for large multiple LEMRIC hub applications. On-chip Elasticity buffer, Manchester encoder and decoder. Separate partition state machine for each port. Embeded LED output driver for each port partition status, each port link/receive status (TP port), global jam status, and global jabber status. No external glue logic is required. Embedded predistortion resistors for every TP port. Build in power reset circuit, no extra glue logic required. Crystal/Oscillater optional applicable. Manchester code violation detection and reporting. Support MAU Jabber Lockup Protection function. Support Auto Partition/Reconnection function to isolate a faulty segment's collision activity. Fully integrated Link Test logic with enable/disable option, conforming to the 10BASE-T standard. Fully integrated polarity detect/correct logic with enable/disable option for per TP port. Low power consumption; fully load < 900 mW. CMOS device feature high integration with a single + 5V supply. 100-pin QFP package.
General Description
The TC3097 Lite End Multiport Repeater Interface Controller (LEMRIC) may be used to implement an IEEE 802.3 multiport repeater unit. It fully satisfies the IEEE 802.3 repeater specification including the functions defined by the repeater, segment partition and jabber lockup protection state machines. The LEMRIC has an on-chip phase-locked-loop (PLL) for Manchester data decoding, a Manchester encoder, and an Elasticity Buffer for preamble regeneration. In addition, it provides direct LED display driver pins for per port LINK/RCV status, per port partition jabber status, global jam and jabber lockup status indications. Each LEMRIC can connect up to 9 cable segments via its network interface ports. One port is fully Attachment Unit Interface (AUI) compatible and is able to connect to an external Medium Attachment Unit (MAU) using the maximum length of AUI cable. The other 8 ports have integrated 10BASE-T transceivers. In addition, large repeater units may be constructed by cascading LEMRICs together over the Inter-LEMRIC bus.
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Preliminary Data Sheet
Table Of Contents
Features .............................................................................................................................................................. 1 General Description ............................................................................................................................................ 1 Table Of Contents ............................................................................................................................................... 2 1 Pin Description.......................................................................................................................................... 4 1.1 Config (pin 2 is connected to GND) ..................................................................................... 4 2 Principles Of Operation ............................................................................................................................ 7 2.1 Reset .................................................................................................................................... 7 2.2 Clock and data Recovery ..................................................................................................... 7 2.3 Functional State diagrams ................................................................................................... 8 2.3.1 TP Port Auto-Partition State Diagram ..................................................................... 8 2.3.2 AUI Port Auto-Partition State Diagram .................................................................. 10 2.3.3 Global State Diagram ............................................................................................ 12 2.3.4 Counters and Timers............................................................................................. 15 Automatic Preamble Regeneration ....................................................................... 17 2.3.5 2.3.6 Inter-LEMRIC Bus Operation ................................................................................ 19 2.3.7 Port Block functions .............................................................................................. 26 3 Absolute Maximum Ratings................................................................................................................. 29 4 D.C. Characteristics................................................................................................................................ 29 5 Switching Characteristics ....................................................................................................................... 30 6 Package Detail .......................................................................................................................................... 35
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Preliminary Data Sheet
TC3097-8 Connection Diagram Config (pin 2 is connected to GND)
R X VG VI DNNND7 DDCCDB
R X I 7 A
T X O 7 R B
T R X X O 7GV I RND6 ADDB
R X I 6 A
T R O 6 R B
T R O 6 R A
R X I 5 B
R X I 5 A
T X O 5 R B
T X R O X 5GVI RND4 ADDB
R X I 4 A
T X O 4 R B
T X O 4V G RDNNNN ADCCCD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TXO8RA TXO8RB RXI8A RXI8B VDD TXO9RA TXO9RB RXI9A RXI9B GND PALED1 PALED2 PALED3 PALED4 PALED5 PALED6 PALED7 PALED8 PALED9 GND
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 45 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
TC3097-8 100pin QFP
TXO3RA TXO3RB VDD RXI3B RXI3A TXO2RA TXO2RB RXI2B RXI2A TX1B TX1A RX1B RX1A VDD CD18 AGND CD1A CP1_0 VCO_I AVDD
VGCJ DNOA DDLB EL DE D
L R L E D 1
L R L E D 2
L R L E D 3
L R L E D 4
L R L E D 5
L R L E D 6
L R L E D 7
L R L E D 8
L G I I I AAAA RNRRRCCCY L DEDCK KT X E OINN Z ZZ D 9
C O L N Z
RGCCVT TT EN LLDEEE SDKKDSSS E TTT 12 T 134 Z
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Preliminary Data Sheet
1
1.1
Pin
Pin No.
Description
Symbol I/O I Description Twisted-Pair Receive Input Positive
Config (pin 2 is connected to GND)
Netw ork Interface Pins 42, 46, 58, RXI2A to RXI9A 64, 68, 74, 83, 88 43, 47, 59, RXI2B to RXI9B 65, 69, 75, 84, 89 45, 50, 56, 62, 66, 72, 81, 86 44, 49, 57, 63, 67, 73, 82, 87 38 39 40 41 34 36 TXO2RA to TXO9RA TXO2RB to TXO9RB RX1A RX1B TX1A TX1B CD1A CD1B
I
Twisted-Pair Receive Input Negative
O
Twisted-Pair Transmit Output Positive
O
Twisted-Pair Transmit Output Negative
I I O O I I
AUI Receive Input Positive AUI Receive Input Negative AUI Receive Output Positive AUI Receive Output Negative AUI Collision Detect Input Positive AUI Collision Detect Input Negative
Pin No.
Symbol
I/O P P P P P P P P
Description Ground pins for TP port 1 to port 8 output pins. Power pins for TP port 1 to TP port 8 output pins. Ground pin for internal digital circuit of this device. Power pin for internal digital circuit of this device. Ground pins for digital output pins. Power pins for digital output pins. Ground pin for PLL decoder internal circuit. Power pin for PLL decoder internal circuit.
Pow er & Ground Pins 61, 71, 79 GND 48, 60, 70, VDD 85 51, 90, 100 GND 37, 55, 76, VDD 80 2, 14, 24 GND 1, 27 35 31 VDD AGND AVDD
Pin No.
Symbol
I/O I O
Description ACKnowledge Input: Input to the network port’s arbitration chain. ACKnowledge Output: Output from the network port’s arbitration chain.
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Inter-LEMRIC Bus Pins 19 ACKI 18 ACKO
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TC3097-8
Preliminary Data Sheet
Pin No. Symbol I/O B,Z Description Inter-LEMRIC Data: When asserted as an output this signal provides a serial data stream in NRZ format. This signal is asserted by a LEMRIC when it is receiving data from one of its network segments. The default condition of this signal is to be an input. In this state, it may be driven by other devices on the Inter-LEMRIC bus. Inter-LEMRIC Enable: When asserted as an output this signal provides an activity-framing enable for the serial data stream. The signal is asserted by a LEMRIC when it is receiving data from one of its network segments. The default condition of this signal is to be an input. In this state it may be driven by other devices on the inter-LEMRIC bus. Inter-LEMRIC Clock: When asserted as an output this signal provides a clock signal for the serial data stream. Data (XIRD) is changed on the falling edge of the clock. The default condition of this signal is to be an input. When an input, XIRD is sampled on the rising edge of the clock. In this state it may be driven by other devices on the Inter-LEMRIC bus. Collision on Port N: This denotes that a collision is occurring on the port receiving the data packet (Port N). The default condition of this signal is to be an input. In this state it may be driven by the other devices on the Inter-LEMRIC bus. Activity on Port N: This is a bi-directional signal. The LEMRIC asserts this signal when data or collision information is received from one of its network segments. The LEMRIC senses this signal when this or another LEMRIC in a multi-LEMRIC system is receiving data or collision information. Activity on ANY Port Excluding Port N: This is a bi-directional signal. The LEMRIC asserts this signal when a transmit collision is experienced or multiple ports have active collisions on their network segments. The LEMRIC senses this signal when this LEMRIC or other LEMRICs in a multi-LEMRIC system are experiencing transmission collision or multiple ports have active collisions on their network segments. Inter-LEMRIC Bus Pins 16 IRD
15
IREZ
B,Z
17
IRC
B,Z
22
COLNZ
B,Z
20
ACTNZ
B,Z
21
AYXNZ
B,Z
Pin No.
Symbol
I/O O
Description Global Collision LED (Active-Low): This CMOS output indicates the status of the LEMRIC's any collision activity. Global Jabber LED (Active-Low): This CMOS output indicates when the LEMRIC's watchdog timer begins to jab and stays active until end of the unjab wait period.
LED Driver Pins 3 COLED
4
JABLED
O
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Pin No. Symbol I/O O Description Link/Receive LED (active-Low): This CMOS output goes active when the link integrity test is pass on LEMRIC's TP port network segment and blinks when this device is receiving from its link passing TP port segment. AUI Receive LED (Active-Low): This CMOS output is powered on active and blinking when this device is receiving from its AUI port network segment. Port Partition Jabber LED (Active-Low): This CMOS output goes active when the LEMRIC's network connection port is partitioned from its network segment and then goes inactive when its network connection port is reconnection from its network segment. LED Driver Pins 6-13 LRLED2 to LRLED9
5
LRLED1
O
91-99
PALED1 to PALED9
O
Pin No.
Symbol
I/O B
Description These pins are used to facilitate device testing. When not in test mode, these pins should be left open. [Note:] Pins TEST3 and TEST4 can be used to modify the build in 10BASE-T operation. TEST1 can be used to configure LED display mode (ICPLUS or AMD compatible mode). Refer to port Block Function section for more details.
TEST Support Pins 28 TEST1 29 TEST3 30 TEST4
Pin No.
Symbol
I/O I
Description Optional device Reset. A low on this pin causes the device to reset. RESET must be high for normal operation, when not used, please leave open. System Clock. 20 MHz, 50% nominal, 40/60% worst case, duty cycle. The worst-case frequency tolerance and duty cycle limit the range over which the LEMRIC will operate correctly. However, since this clock is used for Manchester data transmission, jitter performance will degrade if clock sources with relatively large tolerances are used.
RESET & CLOCK Pins 23 RESETZ
25 26
CLK1 CLK2
I O
Pin No.
Symbol
I/O I
Description Phase Lock Loop delay line external filter. This pin should be connected correctly with a capacitor to AVDD or causing the analog PLL of the device to be failed. Phase Lock Loop VCO external filter. This pin should be connected correctly with a RC filter circuit to AVDD or causing the analog PLL of the device to be failed.
Decoder Filer Pins 33 CP1_O
32
VCO_I
I
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2
2.1
Principles Of Operation
Reset
The LEMRIC resets when XRESETZ (pin 25) is pulsed low. While reset, the LEMRIC ignores all energy and collision inputs, unjabs all ports, and initializes all timers, counters, and state machines. At the end of reset (XRESETZ goes high), all the LEDs are turned off and the XLRLED1 is turned on. The minimum XRESETZ low pulse is one second to let the power on LED test visually distinguishable. The LEMRIC is fully operational when it exits reset.
2.2
Clock and data Recovery
The clock and data recovery circuit (Manchester decoder) is a linear circuit, which it recovers the NRZ data and clock from the Manchester encoded serial data stream. Data from the active port is routed to the decoder and the recovered data is written into the FIFO.
1
Manchester Data
0
1
0
0
1
1
0
1
0
1
1
NRZ Data
NRZ Clock
Figure 1. Manchester Data - NRZ Data Relationship
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Preliminary Data Sheet
2.3 Functional State diagrams
The following state diagrams describe the auto-partition and global state machines implemented in the LEMRIC. The notation and variables used in each diagram are described below. 2.3.1 TP Port Auto-Partition State Diagram
A partitioning state machine is implemented for each TP port. Individual Tw5 and Tw6 timers and collision counters are implemented for each state machine. 2.3.1.1 State Diagram Notation and Variables. = & + {[term]} X CC(X) DIPresent(X) Assign the right side constant or expression result to the left side variable. Logical ”AND” operator. Logical ”OR” operator when used in a state-exiting expression. Arithmetic addition when used otherwise. Group term for logical evaluation. Number identifier for the particular TP port. Values: Integers from 1 to 8 Consecutive collision count for TP port X. Values: Integers from 0 to 31 Carrier from the MAU on TP port X. Values: Idle-Port carrier is not active. Active-Port carrier is active. TP port X carrier to the global state machine. Values: Idle-Port carrier has been gated off by the partition state machine. DIPresent(X)-Port carrier is passed on to the global state machine. Status of transmission to the MAU on TP port X. Values: Idle-Not transmitting to the port MAU. Active-Transmitting to the port MAU. Inter-LEMRIC that is Port N or Port M collision. Values: Idle-/COLN is not active. Active-/COLN is active. Inter-LEMRIC that is not Port N or Port M collision. Values: Idle-/ANYXN is not active. Active-/ANYXN is active. Enable Tw5 initializes and starts the PORT Tw5 timer. Tw5Done indicates that the timer has expired. Enable Tw6 initializes and starts the port Tw6 timer. /Tw6Done indicates that the timer is running. Tw6Done indicates that the timer has expired.
Datain(X)
TEN(X)
/COLN
/ANYXN
Tw5 Tw6
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RESET
COUNT CLEAR - 0
CC(X) = 0 Datain(X) = DIPresent(X)
TEN(X) = Idle & DIPresent(X)=Idle
COLLISION COUNT IDLE - 1 Datain(X) = DIPresent(X)
TEN(X)=Active + DIPresent(X)=Active W ATCH FOR COLLISION - 2
Datain(X) = DIPresent(X) Enable Tw5
PARTITION W AIT - 4
Datain(X) = Idle
DIPresent(X)=Idle & TEN(X)=Idle & /COLN,/ANYXN=Idle
{[TEN(X)=Active & DIPresent(X)=Idle] + [TEN(X)=Idle & DIPresent(X)=Active]} & Tw5Done & /COLN,/ANYXN=Idle
TEN(X)=Idle & DIPresent(X)=Idle
[/COLN=Active + /ANYXN=Active + TEN(X)=Active] & DIPresent(X)=Active
PARTITION HOLD - 5
Datain(X) = Idle
COLLISION COUNT INCREMENT - 3
CC(X) = CC(X) + 1 Datain(X) = DIPresent(X) EnableTw6
CC(X) >= 31 + [TEN(X)=Active & DIPresent(X)=Active & Tw6Done]
TEN(X)=Active + DIPresent(X)=Active
TEN(X)=Idle & DIPresent(X)=Idle & CC(X) < 31 & /Tw6Done
PARTITION COLLISION W ATCH - 6
Datain(X) = Idle EnableTw5
[/COLN=Active + ANYXN=Active + TEN(X)=Active] & DIPresent(X)=Active TEN(X)=Idle & DIPresent(X)=Idle & /COLN,/ANYXN=Idle
{[TEN(X)=Active & DIPresent(x)=Idle] + [TEN(X)=Idle & DIPresent(X)=Active]} & Tw5Done & /COLN, /ANYXN=Idle
W AIT TO RESTORE PORT - 7
Datain(X) = Idle CC(X) = 0
TEN(X)=Idle & DIPresent(X)=Idle Figure 2. Partition State Diagram for TP Port X
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2.3.2 AUI Port Auto-Partition State Diagram A partition state machine is implemented for each AUI port. Individual Tw5 and Tw6 timers and collision counters are implemented for each state machine. 2.3.2.1 State Diagram Notation and Variables. = & + {[term]} Y CC(Y) DIPresent(Y) Assign the right side constant or expression result to the left side variable. Logical ”AND” operator. Logical ”OR” operator when used in a state-exiting expression. Arithmetic addition when used otherwise. Group term for logical evaluation. Number identifier for the particular AUI port. Values: Integers 0 and 1 Consecutive collision count for AUI port Y Values: Integers from 0 to 31 Carrier from the MAU on AUI port Y. Values: Idle-Port carrier is not active. Active-Port carrier is active. AUI port carrier to the global state machine. Values: Idle-Port carrier has been gated off by the partition state machine. DIPresent(Y)-Port carrier is passed on to the global state machine. Collision indication from the MAU on AUI Port Y. Values: /SQE-Port collision is not active. SQE-Port collision is active. AUI port collision to the global state machine. Values: /SQE-Port collision has been gated off by the partition state machine. CIPresent(Y)-Port collision is passed on to the global state machine. Inter-LEMRIC that is Port N or Port M collision. Values: Idle-/COLN is not active. Active-/COLN is active. Inter-LEMRIC that is not Port N or Port M collision. Values: Idle-/ANYXN is not active. Active-/ANYXN is active. Enable Tw5 initializes and starts the PORT Tw5 timer. Tw5Done indicates that the timer has expired. Enable Tw6 initializes and starts the port Tw6 timer. /Tw6Done indicates that the timer is running. Tw6Done indicates that the timer has expired.
Datain(Y)
CIPresent(Y)
Collin(Y)
/COLN
/ANYXN
Tw5 Tw6
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R ESET
CO U N T CLEAR - 0
CC ( Y ) = 0 D a ta in (Y ) = D I P r e s e n t ( Y ) C o llin ( Y ) = C IP r e s e n t( Y )
CO L L I S IO N C O U N T ID L E - 1
Da ta in ( Y ) = D IP r e s e n t( Y ) C o llin ( Y ) = C I P r e s e n t ( Y )
D I P r esen t( Y) =A c t iv e + C I P r esen t( Y) =S Q E W A T C H FO R C O L L IS IO N - 2
D IP r es ent( Y ) = Id le & C IP r es ent( Y ) = /S Q E
Da ta in ( Y ) = D IP r e s e n t( Y ) C o llin ( Y ) = C I P r e s e n t ( Y ) E n a b le T w 5
P A RT IT I O N W A I T - 4
D a ta in (Y ) = I d le C o llin ( Y ) = / S Q E
D I P r ese n t( Y) =Idle & C I Pr e s e n t( Y ) = /SQ E & /C O L N , /A N Y X N = Id le D IP r es ent( Y ) = A c tiv e & C IP r es ent( Y ) = /S Q E & Tw5Done & /C O L N , /A N Y X N = I d le
D IP r e s en t( Y) =I dle & C IPr e s e n t( Y ) = / SQ E
{ [ /C O L N = A c tiv e + /A N Y X N = A c tiv e ] & D IP r ese n t( Y ) =A ct iv e } + CIP r e s e n t( Y ) = S Q E
P A RT IT I O N HO L D - 5
D a ta in (Y ) = Id le C o llin ( Y ) = /S Q E
D IP r ese n t( Y ) =A ctiv e + CIP r e s e n t( Y ) = S Q E
CO L L IS I O N CO U N T IN C R E M E NT - 3 C C (Y) = C C (Y) + 1 D a t a in ( Y ) = D IP r e s e n t( Y ) C o ll i n ( Y ) = C I P r e s e n t ( Y ) E n a b le T w 6
P A R TITION COL L I S IO N W A TC H - 6
D a ta in ( Y ) = Id le C o llin ( Y ) = /S Q E E n a b le T w 5
C C (Y) > = 31 + [C IP r e s e n t( Y ) = S Q E & T w6D one]
D IP r e s en t( Y) =I dle & C IPr e s e n t( Y ) = / SQ E CC( Y ) < 3 1 & / T w 6 Do n e
/C O L N = A c tiv e + A N Y X N = A c tiv e + C IP r e s e n t( X ) = S Q E
C I P r e s en t ( Y ) =Idle & D I P r e s en t ( Y ) =Idle & /C O L N ,/ A N Y X N = Id le
C IPr e s e n t( Y ) = / SQ E & D IP r ese n t( Y ) =A ct iv e & T w 5D one & /C O L N , /A N Y X N =I d le
W A IT T O R EST O R E PO R T - 7 D a t a in ( Y ) = I d le C o llin ( Y ) = / S Q E C C (Y ) = 0
C I P res ent (Y )= / S Q E & D I P res ent( Y )= I d le F ig u r e 3 . P a r titio n S t a t e D ia g r a m f o r A U I P o r t Y
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2.3.3 Global State Diagram A single global state machine is implemented for the LEMRIC and operates independently of the auto-partition state machines. The machine state can be read externally on three pins when XRESETZ is high. The table below defines the values assigned to these pins for each state. XTEST2/GS2 0 0 0 1 1 1 XTEST1/GS1 0 0 1 0 0 1 XTEST0/GS0 0 1 1 0 1 0 State 0 1 3 4 5 6 State Name Idle Send Data Receive Collision Transmit Collision One Port Left Blind
2.3.3.1 State Diagram Notation and Variables. = & + : < {[term]} Tw1 Tw2 AllDatatSent OUT(P) Assign the right side constant or expression result to the left side variable. Logical ”AND” operate. Logical ”OR” operator. Denotes that a variable assignment expression follows. Denotes assignment of the expression result following the arrow to the variable preceding the arrow. Group term for logical evaluation. Enable Tw1 initializes and start the global Tw1 timer. Tw1Done indicates that the timer has expired. Tw2Done indicates that the Tw2 timer has expired. Flag indicating that all the received bits have been sent. Type of output the LEMRIC is sending to port P. Values : Idle-The LEMRIC is not transmitting. Data-The LEMRIC is sending Preamble, data or IDL to port P. Jam-The LEMRIC is sending Jam to port P. Status of port P carrier. All AUI and TP ports are considered. Values : Idle-Port P carrier is not active. Active-Port P carrier is active. Status of AUI collision on port P. Values : /SQE-Port P collision is not active. SQE-Port P collision is active. Indicates the number of bits transmitted to port P. Values : Positive integers. Function that returns the identifier of a port-passing test. For example, Port (TPDatain=Active) returns an integer identifying the active TP port. If more than one port passes the test, Only one of the acceptable values is returned. Values : Integers from 0 to 8 N is defined by the Port function (see above). It identifies the port that caused an exit from the ldle state to the Send Data or Receive Collision states.
Datain(P)
Collin(P)
TT(P) Port(test)
N
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M M is defined by the Port function (see above). It identifies the single port that caused an exit from the Transmit Collision to the One Port Left state. Values : Integers from 0 to 8. General test, which is true if one and only one port is active due to carrier or collision. All TP and AUI ports are considered. General test, which is true if greater than one port is active due to carrier or collision. All TP and AUI ports are considered. General test, which is true if one or more ports are active due to carrier or collision. All TP and AUI ports are considered. General test, which is true if any port other than port N, meets the test condition. For example, TT (ANYXN) < 96 is true if a port other than port N was soured with fewer than 96 bits. All TP and AUI ports are considered. General test, which is true if any port other than port M, is active due to carrier or collision. All TP and AUI ports are considered. General test, which is true if all ports other than port N meet the test condition. For example TT (ALLXN) > = 96 is true if all ports other than port N were soured with at least 96 bits. All TP and AUI ports are considered. General test, which is true if all ports other than port M meet the test condition. All TP and AUI ports considered.
ONLY1 >1 ANY ANYXN
ANYXM ALLXN
ALLXM
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Power On
IDLE Out(ALL) = Idle
START BEGIN
UCT
Datain(ANY) = Act. & Collin(ALL) = /SQE :[N = 96 & AllDataSent
Out(ALLXN) = Jam
TRANSMIT COLLISION Out(ALL) = Jam
Collin(ANYXN) = SQE
Collin(ALL) = /SQE & TT(ALL) >= 96 & Tw2Done
Collin(ONLY1) = SQE & TT(ALL) >= 96 :[ M = 96 & Tw2Done
Collin(ANYXM) = SQE
WAIT
StartTw1 Out(ALL) = Idle
Collin(ANY) = SQE + Tw1Done
Figure 4. Global State Diagram for Multiple TP Ports and AUI Port
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2.3.4 Counters and Timers The counters and timers specified on IEEE 802.3. Section 9, are implemented in the LEMRIC. The function and values chosen for each is described below. 2.3.4.1 Tw 1 Tw1 is the wait timer for the “End of Transmit” recovery time and it is 8 bit-times in duration. It starts when the LEMRIC ends transmission of a packet and prevents the LEMRIC from receiving this transmission (loop-back energy from the MAU) as a new receiving entity. 2.3.4.2 Tw 2 Tw2 is the wait timer for the end of carrier recovery time and is 3 bit-times in duration. It starts when collision on AUI port has ended. Tw2 prevents the LEMRIC from premature detecting the true end-of-collision due to signal uncertainty on the segment at the end of a collision. Refer to the following figure. If a collision (SQE) is detected on AUI segment, the Tw2 timer becomes armed. Tw2 begins timing when collision is idle (/SQE). After Tw2 is done, the timer remains idle until the next AUI collision.
RESET
IDLE Tw2Done Collin(A NY)=S Q E ARM Tw2NotDone Collin(ALL)=/S Q E E nable Tw2 TIMING T w2=Done
Figure 5. Tw 2 State Diagram .
2.3.4.3 Tw 3 Tw3 is the wait timer for length of continuous output and it has duration of 65536 bit-times . It starts when transmission of a packet begins. If Tw3 expires before the end of packet transmission, the LEMRIC enters the MAU jabber lockup protection condition and interrupts transmission for period Tw4. Refer to the figure 6 for further details. 2.3.4.4 Tw 4 Tw4 is the wait timer for time to disable output for MAU jabber lockup protection and it has duration of 96 bit-times . It starts d when Tw3 expires. While Tw4 is active, transmission to all ports is disabled. The global state machine is reset to the idle state, the FIFO controller is also reset, and the clock recovery circuit continues to decode the incoming data stream. If the port is still active when Tw4 expires, the LEMRIC will resume transmission beginning with preamble. The MAU lockup LED (XJABLED) is turned on to indicates the suspension of transmission. Refer to the following figure.
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TC3097-8
Preliminary Data Sheet
RESET
ID L E
D is a b le O u t = O F F
O U T (A N Y )= A c t iv e
T IM E O U T P U T D is a b le O u t = O F F E n a b le T w 3
O U T (A L L ) = I d le
T w 3 = D o n e & O U T (A N Y )= A c t iv e
D IS A B L E O U T P U T D is a b le O u t = O N E n a b le T w 4
Tw4=Done
F ig u r e 6 . M A U ja b b e r L o c k u p P r o te c tio n S ta te D ia g r a m
2.3.4.5 Tw 5 Tw5 is the auto-partition wait timer for length of packet without collision and it has duration of 512 bit-times. It starts when carrier (or collision on AUI ports) from a port becomes active. If a collision is detected before Tw5 expires, the collision count for that port is incremented and the port Tw6 timer will be started. Tw5 is also used in the auto-partition algorithm to exit the Partition collision Watch state. A separate Tw5 timer is implemented for each of the TP and AUI ports. Refer to the auto-partition state diagrams for specific timer operation. 2.3.4.6 Tw 6 Tw6 is the auto-partition wait timer for excessive length of collision and it has duration of 1024 bit-times. It starts if a collision (multiple active port or SQE) is detected before Tw5 expires. If the collision condition persists when Tw6 expires. The energy and data from that port are partitioned (jabbed). A separate Tw6 timer is implemented for each of the TP and AUI ports. Refer to the auto-partition state diagrams for specific timer operation. 2.3.4.7 Collision counter The collision counter maintains the number of consecutive collisions for a particular port. If the collision limit is reached, the energy and data from that port are partitioned (jabbed). A separate collision counter with limit 31 is implemented for each of the TP and AUI ports. 2.3.4.8 Transmit Timer The transmit timer counts the number of bits transmitted to a port. If the total number of bits transmitted is less than 96 (due to reception of a packet fragment), the LEMRIC will enter the Receive Collision global state and transmit Jam until the transmit timer reaches a count of 96. There by extending the bit stream to greater or equal to 96 bits time. The transmit timer is cleared when the LEMRIC enters the Transmit Collision global state. This ensures that at least 96 bits of jam signals are transmitted to all ports before the LEMRIC exits the Transmit Collision state. This also means that the LEMRIC will have transmitted more than 96 bits of jam signals to all but one port if the transmit collision state was entered from the Receive collision state. Refer to the following figure and the global state diagrams for transmit timer operation.
Confidential. Copyright © 2003, IC Plus Corp. 16/35 July 21. 2003 TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
R E SET
T T ID L E
T T (X) = 0
O U T (X )= A c tive & B it T ran s m itte d
C O UNTIN G T T(X ) = T T (X )+ 1
HOLD
T T (X )
B it T ra n s m itte d
O U T ( X ) = I d le + G lo b a l S ta ts S - > T c o llis io n
Figure 7 . T ransm it T im e r S ta te D iagra m fo r P ort X .
2.3.5
Automatic Preamble Regeneration
Automatic preamble regeneration (APRG) prevents the preamble from shrinking as a packet is passed from repeater to repeater or station to station. This shrinking, or loss of bits, is due to the bit cost of determing the presence of carrier and synchronizing of the Manchester data for NRZ data and clock recovery. The LEMRIC compensates for the bit loss by transmitting greater or equal to 56 bits of preamble before sending the Start of Frame Delimiter (SFD) pattern. 2.3.5.1 APRG Circuit Operation When carrier is detected, the LEMRIC begins sending preamble and searches for the SFD pattern in the recovered NRZ data. The delay from carrier transition to the first transmitted bit of preamble is four to five bit-times for AUI carrier and eight to nine bit-times for TP carrier. The LEMRIC begins to search for the eight-bit SFD pattern 15 to 16 bits after the carrier transition. When the SFD pattern is detected, the data followed by the SFD is loaded into a 64-bit FIFO. After the preamble bits are sent, the SFD pattern will be sent next, and then finally the FIFO data will be transmitted. Since at least 56 bits of preamble must be sent, the FIFO must be of sufficient depth to store the data after the SFD pattern. A FIFO depth of 64 is chosen to allow the processing of packet with very few bits of preamble before SFD. The FIFO watermark is achieved by reloading the FIFO with part of the SFD pattern. A preamble counter maintains the number of preamble bits transmitted, and is implemented such that the total count equals 56 plus the number of SFD bits not reloaded into the FIFO. For a watermark of four bits, the preamble counter counts to 60 (56 preamble bits plus the first four bits of SFD). The received packet must contain at least 16 preambles bits for the LEMRIC to detect SFD. There is no upper limit on the number of preamble bits received. The latency of bits through the LEMRIC is inversely related to the number of preamble bits received. That is the data in a packet with a small number (less than 56) of preamble bits must be stored (and therefore be held a longer period of time) until the full preamble can be regenerated.
Confidential. Copyright © 2003, IC Plus Corp. 17/35 July 21. 2003 TC3097-8-DS-R24
TC3097-8
Preliminary Data Sheet
For a packet with a large number (greater or equal to 56) of preamble bits, the latency will approach the processing time of the LEMRIC (including watermark) to get a bit from the input through the FIFO to the output. If the number of preamble bits received is greater than 56, the LEMRIC will add up to four preamble bits to the packet for TP carrier and up to eight preamble bits for AUI carrier. The leading edge of the first preamble bit transmitted by the LEMRIC, as seen on the line. Denotes the beginning of a 100 nanosecond positive (TTL logic one). 2.3.5.2 APRG State Diagram The following state diagram describes the LEMRIC APRG operation. When carrier is detected, the APRG circuit waits from four to noise bit-times and then begins sending preamble. The preamble counter (PC) increments for each preamble bit sent. When the SFD pattern is detected (all eight bits), the data bits are loaded into the FIFO and the SFD pattern is sent. The error paths indicate some sort of packet abort, such as collision, Manchester code violation, FIFO error, or premature end of packet. The state diagram notation is similar to that of the global state diagram.
RESET
IDLE OUT = Idle PC = 0 Carrier PREAMBLE DELAY OUT = Idle Error Delay Complete LOOK FOR SFD OUT = Preamble Bit Error
SFD Detected : [FIFO < - Data after SFD]
COUNT PC = PC + 1
PREAMBLE COUNT OUT = Preamble Bit Error PC > = 60 OUT SFD OUT = Remaining SFD Bits Error DATA OUT = FIFO Data Error+FIFO Empty PC
