TMS320C6000

TMS320C6000 FAMILY: EMIF Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 1 TMS320C6000 FAMILY: EMIF Introduction. Characteristics, signals, memory map, alignment. Configuration registers. Types of interface. Asynchronous interface. Introduction, waveforms. Case Study I: Peripheral connection. Case Study II: Memory connection. Interface with synchronous static memories. Synchronous static memories. Interface description. Example. Interface with synchronous dynamic memories. SDRAM memories. Interface description. Example. Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 2 Need for an EMIF Need for EMIF): Traditional DSP (with noan EMIF Peripheral/ Memory H/W Interface DSP When interfacing a slow peripheral/memory to a fast DSP, some hardware interface is required. This hardware interface requires fast components in order to keep up with the DSP. Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 3 Need for an EMIF (II) Need for EMIF): Traditional DSP (with noan EMIF Peripheral/ Memory H/W Interface DSP Drawback of the hardware interface: High cost (additional components). Power consumption. Difficult to debug. Cannot be upgraded. Prone to errors. Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 4 The EMIF The EMIF The EMIF supports a glueless interface to several external devices, including: Synchronous burst SRAM (SBSRAM). Synchronous DRAM (SDRAM). Asynchronous devices, including SRAM, ROM and FIFO’s. An external shared-memory device. For more information on different memory types see spra631.pdf A detailed description for each memory type interface can be found in: Asynchronous SRAM: spra542a.pdf Synchronous burst SRAM: spra533.pdf Synchronous DRAM: spra433b.pdf Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 5 The EMIF The C621x/C671x services requests of the external bus from the The EMIF requestors: On-chip Enhanced Direct Memory Access (EDMA) controller. External shared-memory device controller. EMIF L1P Cache C6000 DSP core Instruction Fetch Other Peripherals Enhanced DMA Controller Instruction Dispatch L2 Memory Instruction Decode Data Path A A Register File Interrupt Selector Power Down Logic Boot Configuration L1D Cache L1 S1 M1 D1 Data Path B B Register File D2 M2 S2 L2 Control Registers Control Logic Test In–Circuit Emulation Interrupt Control PLL Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 6 MEMORY MAP Byte Address 0000_0000 64K x 8 Internal (L2 cache) External Memory Async (SRAM, ROM, etc.) Sync (SBSRAM, SDRAM) 0180_0000 On-chip Peripherals Internal Memory Unified (data or prog) Unified prog) 4 blocks - each can be blocks RAM or cache 8000_0000 9000_0000 A000_0000 B000_0000 FFFF_FFFF 0 256M x 8 External 1 256M x 8 External 2 256M x 8 External 3 256M x 8 External Level 1 Cache 4KB Program 4KB Data Not in map 4K P CPU 4K D L2 64K Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 7 MEMORY MAP (II) Description Description Internal RAM (L2) mem EMIF control regs Cache configuration reg L2 base addr & count regs L1 base addr & count regs L2 flush & clean regs CE0 mem attribute regs CE1 mem attribute regs CE2 mem attribute regs CE3 mem attribute regs HPI control reg McBSP0 regs McBSP1 regs Timer0 regs Timer1 regs Interrupt selector regs EDMA parameter RAM EDMA control regs QDMA regs QDMA pseudo-regs McBSP0 data McBSP1 data CE0, 256 MBytes CE1, 256 MBytes CE2, 256 MBytes CE3, 256 MBytes Origin Origin 0x00000000 0x01800000 0x01840000 0x01844000 0x01844020 0x01845000 0x01848200 0x01848240 0x01848280 0x018482c0 0x01880000 0x018c0000 0x01900000 0x01940000 0x01980000 0x019c0000 0x01a00000 0x01a0ffe0 0x02000000 0x02000020 0x30000000 0x34000000 0x80000000 0x90000000 0xA0000000 0xB0000000 Length 0x00010000 0x00000024 0x00000004 0x00000020 0x00000020 0x00000008 0x00000010 0x00000010 0x00000010 0x00000010 0x00000004 0x00000028 0x00000028 0x0000000c 0x0000000c 0x0000000c 0x00000800 0x00000020 0x00000014 0x00000014 0x04000000 0x04000000 0x10000000 0x10000000 0x10000000 0x10000000 8 Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados C6211/C6711 EMIF Features Features Bus Width # Memory Spaces Addressable Space (Mbytes) Synchronous Clocking Width Support Supported Memory Type at CE1 Control Signals Synchronous memory in system Additional registers PDT Support ROM/Flash Asynchronous memory I/O Pipeline SBSRAM C621x / C671x 32 4 512 Independent ECLKIN 8/16/32 All types Mixed all control signals Both SDRAM and SBSRAM SDEXT No Yes Yes Yes Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 9 C6713 EMIF Signals C6211/C6711 EMIF Signals ECLKIN ECLKOUT ED[31:0]† EA[21:2] CE[3:0] BE[3:0] Enhanced data memory controller External memory interface (EMIF) ARDY AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE HOLD HOLDA Control registers BUSREQ MUXed Asynch/SDRAM/SBSRAM control Shared by all external interfaces Clock signals: ECLKIN ECLKOUT Data bus: ED[31:0] Address bus: EA[21:2] Byte enable: BE[3:0] Control signals: Asynchronous ready. Memory type depending. Bus arbitration: Internal peripheral bus Hold Hold acknowledge. Bus request. 10 For a description of the signals see: \Links\signals.pdf Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados C6211/C6711 EMIF Configuration C6211/C6711 EMIF Configuration The following need to be configured when interfacing the DSP to an external device using the EMIF: (1) Memory space control registers (software): These registers describe the type and timing of the external memory to be used. (2) EMIF chip enable (hardware): There are four chip enable (CE0, CE1, CE2 and CE3) that are used when accessing a specific memory location (e.g. if you try to access memory 0x9000 0000 then CE1 will be activated, see next slide). Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 11 C6211/C6711 EMIF Memory Spaces Memory Block Description Internal RAM (L2) Reserved EMIF Registers L2 Registers HPI Registers McBSP 0 Registers McBSP 1 Registers Timer 0 Registers Timer 1 Registers Interrupt selector Registers EDMA RAM and EDMA Registers Reserved QDMA Registers Reserved MCBSP 0/1 Data Reserved EMIF CE0 EMIF CE1 EMIF CE2 EMIF CE3 Reserved Block Size (Bytes) 64K 24M-64K 256k 256k 256k 256k 256k 256k 256k 256k 256k 64M-256k 52 736M-52 256M 1G 256M 256M 256M 256M 1G HEX Address Range 0000 0000 - 0000 FFFF 0001 0000 - 017F FFFF 0180 0000 - 0183 FFFF 0184 0000 - 0187 FFFF 0188 0000 - 018B FFFF 018C 0000 - 018F FFFF 0190 0000 - 0193 FFFF 0194 0000 - 0197 FFFF 0198 0000 - 019B FFFF 019C 0000 - 019F FFFF 01A0 0000 - 01A3 FFFF 01A4 0000 - 01FF FFFF 0200 0000 - 0200 FFFF 0200 0034 - 2FFF FFFF 3000 0000 - 3FFF FFFF 4000 0000 - 7FFF FFFF 8000 0000 - 8FFF FFFF 9000 0000 - 9FFF FFFF A000 0000 - AFFF FFFF B000 0000 - BFFF FFFF C000 0000 - FFFF FFFF Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 12 Memory Space Control Registers Memory Map 0000_0000 Space Control Registers Global Control 0180_0000 Peripherals CE0 Control CE1 Control CE2 Control CE3 Control SDRAM Control SDRAM Refresh Prd 180_0000 180_0008 180_0004 180_0010 180_0014 180_0018 180_001C Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 13 Memory Space Control Registers C6211/C6711 EMIF EMIF global Global Control (GBLCTL): theRegisters control register configures parameters that are common to all the CE spaces. Polarity definition (x). Signal enable (x). 31 Rsv R, +0 16 15 Rsv R,+0 14 Rsv R ,+0 W 13 Rsv R ,+1 W 12 Rsv R ,+1 W 11 BUSREQ 10 ARDY R,+x 9 8 7 NO HOLD R , +0 W 6 Rsv R,+1 5 Rsv R,+1 4 3 2 Rsv R,+0 1 Rsv R,+0 0 Rsv R+ ,0 HOLD HOLDA R,+x R,+x CLK1EN CLK2EN R+ ,0 R , +1 W R , +1 W Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 14 EMIF Registers Question: Why do we need different spaces? Answer: Different spaces allow different types of devices to be used at the same time. CE0, CE1, CE2, CE3 space control registers (CECTL): are used to specify the type and the read and write timing used for a particular space. 31 Write setup RW, +1111 15 TA R, +11 14 13 Read strobe RW, +111111 28 27 Write strobe RW, +111111 8 7 MTYPE RW, +0010† 22 21 20 19 Read setup RW, +1111 3 Write hold MSB ‡ RW, +0 2 0 16 Write hold RW, +11 4 Read hold RW, +011 † MTYPE default value is RW, +0000. ‡ For C621x/C671x, this field is reserved. R,+0. Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 15 EMIF Registers Field READ SETUP WRITE SETUP READ STROBE WRITE STROBE READ HOLD WRITE HOLD MTYPE Description † Setup width. Number of clock cycles of setup for address (EA) and byte enables (/BE(0-3)) before read strobe (/ARE) or write strobe (/AWE) falling. On the first access to a CE space, this is also the setup after /CE falling. Strobe width. The width of read strobe (/ARE) and write strobe (/AWE) in clock* cycles. Hold width. Number of clock cycles that address (EA) and byte strobes (/BE(0-3)) are held after read strobe (/ARE) or write strobe (/AWE) rising. These fields are extended by one bit on the ‘C6211/’C6711. Memory type ‘C6201/’C6202/’C6701 only: MTYPE = 000b: 8-bit-wide ROM (CE1 only) MTYPE = 001b: 16-bit-wide ROM (CE1 only) MTYPE = 010b: 32-bit-wide asynchronous interface ‘C6211/’C6711 only: MTYPE = 0000b: 8-bit-wide asynchronous interface MTYPE = 0001b: 16-bit-wide asynchronous interface MTYPE = 0010b: 32-bit-wide asynchronous interface Turnaround time. Controls the number of ECLKOUT cycles between a read and a write or between two reads. † TA ‡ † Clock = CLKOUT1 for ‘C6201/’C6202/’C6701.Clock = ECLKOUT for ‘C6211/’C6711. ‡ Applies to ‘C6211/’C6711 only. Avoid bus contention Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 16 MEMORY WIDTH & BYTE ALIGNMENT Memory type ASRAM Memory width x8 x16 x32 Maximum addressable bytes per CE space 1M 2M 4M 1M 2M 4M 32M 64M 128M Address output on EA[21:2] A[19:0] A[20:1] A[21:2] A[19:0] A[20:1] A[21:2] See section 10.5 See section 10.5 See section 10.5 Represents ED[31:24] TMS320C621x/C671x ED[23:16] ED[15:8] ED[7:0] Byte address Halfword address Word address Byte address Halfword address Word address Byte address Halfword address Word address 32-bit device SBSRAM x8 x16 x32† 16-bit device big endian 16-bit device little endian SDRAM x8 x16 x32 8-bit device big endian 8-bit device little endian Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 17 TMS320C6000 FAMILY: EMIF Introduction. Characteristics, signals, memory map, alignment. Configuration registers. Types of interface. Asynchronous interface. Introduction, waveforms. Case Study I: Peripheral connection. Case Study II: Memory connection. Interface with synchronous static memories. Synchronous static memories. Interface description. Example. Interface with synchronous dynamic memories. SDRAM memories. Interface description. Example. Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 18 ASYNCHRONOUS INTERFACE It uses a Intel approach: two command signals to define the access direction and validate the rest of the signals used for decoding: Read: ARE Write: AWE These signals define the active part of the access cycle. The rest of signals used for decoding must be stables during the active part. Address and control signals /ARE /AWE Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 19 ASYNCHRONOUS INTERFACE Asynchronous read timing example (2/3/1) Setup 2 ECLKOUT Strobe 3 Hold 1 CE BE[3:0] EA[21:2] ED[31:0] AOE ARE BE Address Read D AWE ARDY Active part: 3 cycles. Decoded signals are stable 2 cycles before active part. Data captured at the end of active part. Decoded signals remain stable 1 cycle after active part. RDY signal is tested at the beginning of the last cycle of the active part. Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 20 ASYNCHRONOUS INTERFACE Asynchronous write timing example (2/3/1) Setup 2 ECLKOUT CE BE[3:0] EA[21:2] ED[31:0] AOE ARE AWE ARDY BE1 A1 D1 BE2 A2 D2 Strobe 3 Hold 1 Setup 2 Strobe 3 Hold 1 Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 21 ASYNCHRONOUS INTERFACE Ready operation: Wait state insertion Setup 2 ECLKOUT CE BE[3:0] EA[21:2] ED[31:0] AOE ARE AWE ARDY BE Address D Programmed strobe 4 Ready sampled Strobe extended 3 Hold 1 Data latched Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 22 ASYNCHRONOUS INTERFACE Turnaround Time HOLD ECLKOUT td /CEx td /BE[3:0] td EA [21:2] tohz(m) ED [31:0] td /AOE /ARE /AWE ARDY td td td TA = 2 SETUP Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 23 REAL WAVEFORMS: READ ACCESS Setup = 2 ECLKOUT 1 CEx 1 BE[3:0] 1 EA[21:2] Address 3 4 ED[31:0] 1 AOE/SDRAS/SSOE 5 ARE/SDCAS/SSADS AWE/SDWE/SSWE 6 ARDY 5 Read Data 2 BE 2 2 2 Strobe = 3 Not Ready Hold = 2 7 6 7 Outputs: Delay time max: 7 ns Ingeniería Electrónica Data capture: Setup time min: 6.5 ns Hold time min: 1 ns ARDY test: Setup time min: 3 ns Hold time min: 2.3 ns 24 Sistemas Electrónicos Digitales Avanzados REAL WAVEFORMS: WRITE ACCESS Setup = 2 ECLKOUT 8 CEx 8 BE[3:0] 8 EA[21:2] 8 ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS 10 AWE/SDWE/SSWE 7 6 ARDY 6 7 10 Write Data Address 9 BE 9 9 9 Strobe = 3 Not Ready Hold = 2 Outputs: Delay time max: 7 ns Ingeniería Electrónica ARDY test: Setup time min: 3 ns Hold time min: 2.3 ns 25 Sistemas Electrónicos Digitales Avanzados PROGRAMMABLE PARAMETERS All of then are expressed as TECLKOUT units: SETUP ≥ 1 (0 is treated as 1) STROBE ≥ 1 (0 is treated as 1) HOLD ≥ 0 TURNAROUND ≥ 0 TECLKOUT depends on system design: For DSK6713: TECLKOUT= 50 MHz => TECLKOUT = 20 ns. Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 26 TYPICAL APPLICATIONS The asynchronous interface is usually used to add extend the system resources by adding: External peripheral with parallel interface: This kind of peripherals usually have an asynchronous interface. Asynchronous memory banks: Easy design but reduced band width => restricted to non volatile memories (i.e FLASH) We will see two examples: Peripheral connection: A/D y D/A. Asynchronous memory banks connection. Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 27 TMS320C6000 FAMILY: EMIF Introduction. Characteristics, signals, memory map, alignment. Configuration registers. Types of interface. Asynchronous interface. Introduction, waveforms. Case Study I: Peripheral connection. Case Study II: Memory connection. Interface with synchronous static memories. Synchronous static memories. Interface description. Example. Interface with synchronous dynamic memories. SDRAM memories. Interface description. Example. Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 28 EMIF CASE STUDY (I) DSK interface EMIF Case Study to: AD768 DAC. AD9220 ADC. AD9220 ADC Channel 1 DSK E M I F AD9220 ADC AD768 DAC AD768 DAC Channel 2 Channel 1 Channel 2 Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 29 EMIF CASE STUDY: AD768 DAC Specification: Case Study: AD768 DAC EMIF FEATURES: 30 msps Update Rate 16-Bit Resolution Linearity: 1/2 LSB DNL @ 14 Bits 1 LSB INL @ 14 Bits Fast Settling: 25ns Full-Scale Settling to 0.025% SFDR @ 1 MHZ Output: 86 dBc THD @ 1 MHZ Output: 71 dBc Low Glitch Impulse: 35 pV-s Power Dissipation: 465 mW On-chip 2.5V reference Edge Triggered Latches Multiplying Reference Capability APPLICATIONS: Arbitrary Waveform Generation Communications Waveform Reconstruction Vector Stroke Display AD768 data sheet Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 30 EMIF CASE STUDY: AD768 DAC EMIF Case Study: Functional Block Diagram: AD768 DAC FUNCTIONAL BLOCK DIAGRAM DCOM VDD DB15 (MSB) AD768 M SBs: SEGMENTED CURRENT SOURCES AND SWITCHES MS B DECODER and EDGETRIGGERED BIT LATCHES LSBs: CURRENT SOURCES, SWITCHES, AND 12k R-2R LADDERS 1K 1K INOUTA INOUTB LADCOM 2.5 v BANDGAP REFERENCE CONTROL AMP VEE DB0 (LSB) CLOCK NC REFCOM REFOUT IREFIN NR AD768 data sheet Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 31 EMIF CASE STUDY: AD768 DAC EMIF Case Study: AD768 DAC Timing: tS = 10 ns tH = 5 ns tLPW = 10 ns NOTE: for DSK6713 TECLKOUT= 50 MHz => TECLKOUT = 20 ns. AD768 data sheet Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 32 EMIF CASE STUDY: AD768 DAC C6713EMIF Case Study: Timing: DAC Asynchronous Write AD768 Setup = 2 ECLKOUT 8 CEx 8 BE[3:0] 8 EA[21:2] 8 ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS 10 AWE/SDWE/SSWE 7 6 ARDY 6 7 10 Write Data Address 9 BE 9 9 9 Strobe = 3 Not Ready Hold = 2 Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 33 SETTING ASYNC TIMING 31 RW, +1111 28 27 22 21 Write Setup 15 TA 14 13 Write Strobe RW, +111111 Write Hold 20 19 RW, +1111 16 Read Setup 2 0 RW, +11 8 7 4 Read Strobe RW, + 111111 MTYPE RW, +0010 3 Write Hold MSB RW, +0 Read Hold RW, +11 CE3 Set CE3 and to 32-bit ASYNC .equ mvkl.s1 mvkh.s1 ldw nop 4 and set stw .d1 1800014h CE3, A0 CE3, A0 *A0, A1 A1, A1, A1, 0xff0f, A1 Note: There are more 5, 5, A1 MTYPE options. See: *A0 \Links\spru190d.pdf 34 000b = 8-bit-wide ROM 001b = 16-bit-wide ROM 010b = 32-bit-wide Async 011b = 32-bit-wide SDRAM 100b = 32-bit-wide SBSRAM Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados SETTING ASYNC TIMING EMIF Case Hardware Interface:Study: AD768 DAC Analogue Out (Chan2) D/A Analogue Buffering CLK /XAWE /XCE3 16 XD[0..15] Analogue Out (Chan1) CLK D/A 16 XD[16..31] AD768 data sheet Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 35 EMIF CASE STUDY: AD768 DAC EMIF Case Study: AD9220 ADC Specifications: FEATURES Monolithic 12-Bit A/D Converter Product Family Family Members Are: AD9221, AD9223, and AD9220 Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS and 10 MSPS Low Power Dissipation: 59 mW, 100 mW and 250 mW Single +5V Supply Integral Nonlinearity Error: 0.5 LSB Differential Nonlinearity Error: 0.3 LSB Input Referred Noise: 0.09LSB Complete On-Chip Sample-and-Hold Amplifier and Voltage Reference Signal-to-Noise and Distortion Ratio: 70dB Spurious-Free Dynamic Range: 86dB Out-of-range Indicator Straight Binary Output Data 28-Lead SOIC and 28-Lead SSOP AD9220 data sheet Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 36 DaughtercardConnector EMIF CASE STUDY: AD9220 ADC Functional Block Diagram: AD9220 data sheet 37 Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados EMIF CASE STUDY: AD9220 ADC EMIF Case Study: AD9220 ADC Timing: tC = 100 ns tCH = 45 ns tCL = 45 ns tOD = 19 ns NOTE: for DSK6713 TECLKOUT= 50 MHz => TECLKOUT = 20 ns. AD9220 data sheet 38 Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados EMIF CASE STUDY: AD9220 ADC EMIF Case Study: AD9220 C6713 Asynchronous Read Timing: ADC Setup = 2 ECLKOUT 1 CEx 1 BE[3:0] 1 EA[21:2] Address 3 4 ED[31:0] 1 AOE /SDRAS/SSOE 5 ARE/SDCAS/SSADS AWE/SDWE/SSWE 6 ARDY 5 Read Data 2 BE 2 2 2 Strobe = 3 Not Ready Hold = 2 7 6 7 Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 39 SETTING ASYNC TIMING 31 RW, +1111 28 27 22 21 Write Setup 15 TA 14 13 Write Strobe RW, +111111 Write Hold 20 19 RW, +1111 16 Read Setup 3 2 0 RW, +11 8 Read Strobe RW, + 111111 MTYPE Write Hold MSB RW, +0010 RW, +0 7 4 Read Hold RW, +011 Set CE3 and to 32-bit ASYNC CE3 .equ mvkl.s1 mvkh.s1 ldw nop 4 and set stw .d1 1800014h CE3, A0 CE3, A0 *A0, A1 A1, 0xff0f, A1 A1, 5, 5, A1 A1, *A0 000b = 8-bit-wide ROM 001b = 16-bit-wide ROM 010b = 32-bit-wide Async 011b = 32-bit-wide SDRAM 100b = 32-bit-wide SBSRAM Note: There are more MTYPE options. See: \Links\spru190d.pdf 40 Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados EMIF CASE STUDY: AD9220 ADC Hardware Interface: Analogue I n (Chan2) A/D Analogue Buffering CLK 16 CLK /OE XTOUT0 /XAOE /XCE3 Analogue I n (Chan1) CLK CLK /OE A/D 16 Latch 16 XD[16..31] AD9220 data sheet Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 41 EMIF CASE STUDY: Sharing the bus Both ADCs and DACs are mapped to the same address space (CE3 = 0xB000 0000). 16 16 XD[0..15] A/D CLK DaughtercardConnector Latch CLK /OE Latch 16 XD[0..15] XTOUT0 /XAOE /XCE3 CLK CLK /OE A/D Latch 16 XD[16..31] /CE3 0 0 1 /XAOE 0 1 x /XAWE 1 0 x /OE 0 1 1 DAC_CLK 1 0 1 D/A CLK 16 XD[0..15] /XAOE activates the latched A/D output only during the read sequence /XAWE /XCE3 CLK D/A 16 XD[16..31] Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados DaughtercardConnector 16 42 EMIF CASE STUDY: Daughter board interface Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 43 EMIF CASE STUDY: Hardware The INTDSK1115 daughter card from ATE Communications contains: CODEC. 2 x ADC (AD9920). 2 x DAC (AD768). See schematics for further details: \Links\Schematics Page 1.pdf \Links\Schematics Page 2.pdf \Links\Schematics Page 3.pdf \Links\Schematics Page 4.pdf Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 44 EMIF CASE STUDY: Hardware It requires +12V, -12V and 5V power supplies: Daughter card Connector Pin 1 2 3 4 Signal +12V -12V DGND +5V +12V -12V GND +5V DSK Warning: Do NOT supply power to J4 and J8 at the same time. Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 45 EMIF CASE STUDY: Hardware Procedure: (1) Set the EMIF registers. (2) Set the internal timer to generate the sampling frequency. (3) Ensure that the DSK6211_6711.gel is loaded. (4) Write the functions for reading and writing from/to the ADC and DAC respectively. (5) Set the interrupts. Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 46 EMIF CASE STUDY: Software EMIF EMIF Case Control Register: (1) Setting the GlobalStudy: Software - EMIF 31 16 Rsv 15 14 13 12 11 BUSREQ 10 9 8 7 NO HOLD 6 5 4 CLK1EN 3 CLK2EN 2 1 0 Rsv Rsv Rsv Rsv ARDY HOLD HOLDA Rsv Rsv Rsv Rsv Rsv Slight changes for ‘6713 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 3 3 0 0 The GBLCTL register is common to all spaces and can be configured as follows: #define EMIF_GCTL 0x01800000 *(unsigned int *) EMIF_GCTL = 0x3300 Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 47 EMIF CASE STUDY: Software EMIF Setting the CE Control Register: Which space can be used to access the ADCs? From the DSK6211_6711.gel (DSK6211_6711_gel.pdf) file we can see that the CE2 and CE3 are not used and are available on the Daughter card interface. In this application the CE3 space has been used. Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 48 EMIF CASE STUDY: Software EMIF Setting the CE3 Control Register: MTYPE? A/D 2 A/D 1 D/A 1 D/A 2 Memory address B0000000 32-bits The memory is configured as 32-bit asynchronous. Therefore: MTYPE = 0010b. Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 49 EMIF CASE STUDY: Software EMIF Setting the CE3 Control Register: MTYPE = 0010b: 32-bit async Read/Write Hold = 011b: 3 x ECLKOUT Read/Write Strobe = 111111b: 31 x ECLKOUT Read/Write Setup = 1111b: 15 x ECLKOUT Therefore the CE3 space can be configured as follows: Too conservative timing desing #define EMIF_CE3 0x01800014 *(unsigned int *) EMIF_CE3 = 0xffffff23 Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 50 EMIF CASE STUDY: Software Timer Setting the sample rate: Using the internal timer (2) Select a timer: there are two timers available, Timer 0 and Timer 1. The two internal timers are controlled by six memorymapped registers (3 registers each): (a) Timer control registers: sets the operating modes. (b) Timer period registers: holds the number of timer clock cycles to count. (c) Timer counters: holds current value of the incrementing counter. Note: the timer clock is the CPU clock divided by 4. 51 Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados EMIF CASE STUDY: Software Timer Register Timer control Timer period Timer counter Address Timer 0 Timer 1 0x0194 0000 0x0198 0000 0x0194 0004 0x0198 0004 0x0194 0008 Description Sets the operating mode Holds the number of timer clock cycles to count 0x0198 0008 Holds the current counter value Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 52 EMIF CASE STUDY: Software Timer Initialise the timer: CPU Frequency = FCPU = 150000000 Hz 4000 Hz Sampling rate = SRATE = TPRD = FCPU 150000000 = = 468.75 4 x 2 x 4000 32000 = 0x01D5 Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 53 EMIF CASE STUDY: Software Timer #define FCPU #define SRATE #define TPRD 150000000 /* CPU clock frequency */ 800000 /* data sample rate 800kHz */ (FCPU/(4*2*SRATE)) /* timer period, using the clock mode */ /* Handle for the timer device */ TIMER_Handle hTimer; void start_timer1() { *(unsigned volatile int *)TIMER1_CTRL = 0x000; /* Disable output of Timer 1 */ IRQ_map(IRQ_EVT_TINT1,8); hTimer = TIMER_open(TIMER_DEV1, TIMER_OPEN_RESET); /* Configure up the timer. */ TIMER_configArgs(hTimer, TIMER_CTL_OF(0x000003c1), TIMER_PRD_OF(TPRD), TIMER_CNT_OF(0) ); /* Start Timer 1 in clock mode */ *(unsigned volatile int *)TIMER1_CTRL = 0x3C1;//clock mode /* Finally, enable the timer which will drive everything. */ TIMER_start(hTimer); } Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 54 EMIF CASE STUDY: Loading GEL (3) For the DSK6211 and DSK6711 select the DSK6211_6711.gel using: Method 1: File:Load GEL Location: ti\cc\gel\ Method 2: You can automatically execute a specific GEL function at startup as follows: (1) Select Setup CCS. (2) Select the C6x11 DSK and right click. (3) Select the “Startup GEL file(s)”. (4) Type the file location as shown: Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 55 EMIF CASE STUDY: Loading GEL Ingeniería Electrónica Sistemas Electrónicos Digitales Avanzados 56 EMIF CASE STUDY: Reading and writing to the A/D y D/A (4) The ADC and DAC are memory-mapped and therefore can be accessed just like accessing a memory. #define INTDSK_CE3 0xB0000000 unsigned int analogue_in = 0; unsigned int analogue_out = 0; interrupt void timerINT1 (void) { analogue_in = *(unsigned volatile int *) INTDSK_CE3; /* data processing */ ad1 = analogue_in & 0xffff0000; ad2 = analogue_in & 0x0000ffff; ad1 = ad1