EM565161

E tronTech Features • Single Power Supply Voltage, 2.3 ~ 3.6 V • Power Down Features Using CE1#, CE2, LB# and UB# • Low Power Dissipation • Data retention Supply Voltage: 1.0V to 3.6V • Direct TTL Compatibility for All Input and Output • W ide Operating Temperature Range: -40°C to 85°C • Standby current (maximum) @ VDD = 3.6 V Part Number EM565161BA/BJ-55 EM565161BA/BJ-70 EM565161BA/BJ-55E/70E EM565161 512K x 16 Low Power SRAM Preliminary, Rev 0.9 01/2002 Pin Assignment 48-Ball BGA (CSP), Top View 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CE2 B DQ8 UB# A3 A4 CE1# DQ 0 C DQ9 DQ 10 A5 A6 DQ1 DQ 2 Typical 2 µA 2 µA 14 µA IDDS2 Maximum 35 µA 25 µA 80 µA D GND DQ 11 A17 A7 DQ3 VDD E VDD DQ 12 GND A16 DQ4 GND F DQ 14 DQ 13 A14 A15 DQ5 DQ 6 Ordering Information Part Number EM565161BJ-70 EM565161BA-70 EM565161BA-70E EM565161BJ-55 EM565161BA-55 EM565161BA-55E Speed 70 ns 70 ns 70 ns 55 ns 55 ns 55 ns IDDS2 25 µA 25 µA 80 µA 35 µA 35 µA 80 µA Package 6x9 BGA 8x10 BGA 8x10 BGA 6x9 BGA 8x10 BGA 8x10 BGA G DQ 15 NC A12 A13 W E# DQ 7 H A18 A8 A9 A10 A11 NC Pin Names Symbol A0 – A18 DQ0-DQ15 CE1#,CE2 OE# W E# LB#,UB# GND VDD NC Function Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Read/Write Control Input Data Byte Control Inputs Ground Power Supply No Connection Overview The EM565161 is an 8M-bit SRAM organized as 512K words by 16 bits. It is designed with advanced CMOS technology. This Device operates from a single power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when CE1# or both UB# and LB# are asserted high or CE2 is asserted low. There are three control inputs. CE1# and CE2 are used to select the device and for data retention control, and output enable (OE#) provides fast memory access. Data byte control pin (LB#,UB#) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating range from –40°C to 85°C, the EM565161 can be used in environments exhibiting extreme temperature conditions. Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. E tronTech Block Diagram EM565161 A0 VDD M EMO RY CELL ARRAY 5 12 k x 1 6 A18 GND D Q0 D Q1 D Q2 D Q3 D Q4 D Q5 D Q6 D Q7 SENSE AMP D Q8 D Q9 D Q1 0 D Q1 1 D Q1 2 D Q1 3 D Q1 4 D Q1 5 C OL U M N ADD R ES S D EC OD ER W E# UB# LB# OE# CE1# CE2 P OW ER D OW N C IR C UIT Preliminary 2 Rev 0.9 Jan 2002 E tronTech Operating Mode Mode CE1# CE2 OE# WE# LB# L Read L H L H H L L W rite L H X L H L L Output Disabled L H Standby X X H X L X X X X X X X X X H X X H H X X H High-Z High-Z H H H X UB# L L H L L H X DQ0~DQ7 DOUT High-Z DOUT DIN High-Z DIN High-Z EM565161 DQ8~DQ15 DOUT DOUT High-Z DIN DIN High-Z High-Z High-Z Power IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO High-Z IDDS Note:X=don’t care. H=logic high. L=logic low. Absolute Maximum Ratings Supply voltage, VDD Input voltages, VIN Input and output voltages, VI/O Operating temperature, TOPR Storage temperature, TSTRG Soldering Temperature (10s), TSOLDER Power dissipation, PD -0.3 to +4.6V -0.3 to +4.6V -0.5 to VDD +0.5V -40 to +85°C -55 to +150°C 240°C 1W Preliminary 3 Rev 0.9 Jan 2002 E tronTech DC Recommended Operating Conditions (Ta=-40°C to 85°C) Symbol VDD VIH VIL Parameter Power Supply Voltage Input High Voltage Input Low Voltage Min 2.3 2.2 -0.3 (2) EM565161 Typ 3.0 − − − Max 3.6 VDD + 0.3 0.6 3.6 (1) Unit V VDR Data Retention Supply Voltage Note: (1) Overshoot : VDD +2.0V in case of pulse width ≤ 20ns (2) Undershoot : -2.0V in case of pulse width ≤ 20ns 1.0 DC Characteristics (Ta = -40°C to 85°C, VDD = 2.3V to 3.6V) Parameter Input low current Output low voltage Output high voltage Operating current Symbol IIL VOL VOH IDD1 IDD2 Standby current IDDS1 IIN = 0V to VDD IOL = 2.1 mA IOH = -1.0 mA CE1# = VIL and CE2 = VIH and IOUT = 0mA Other Input = VIH / VIL CE1# = VIH or CE2 = VIL CE1# = VDD – 0.2V or IDDS2 UB# and LB# = VDD-0.2V or CE2 = 0.2V -70 − − 2 25 -55 Cycle time = min Cycle time = 1µs Test Conditions Min -1 − VDD – 0.15 − − − − Typ* Max Unit − − − 12 − − 2 1 0.4 − 35 mA 5 0.3 35 µA mA µA V V -55E/70E Notes: * Typical value are measured at Ta = 25°C. 14 80 Capacitance (Ta = 25°C; f = 1 MHz) Parameter Input capacitance Input/Output capacitance Symbol CIN Min − Max 8 Unit pF pF Test Conditions VIN = GND VIO = GND CIO 10 − Notes: This parameter is periodically sampled and is not 100% tested. Preliminary 4 Rev 0.9 Jan 2002 E tronTech Read Cycle EM565161 AC Characteristics and Operating Conditions (Ta = -40°C to 85°C, VDD = 2.3V to 3.6V) EM565161 Symbol tRC tAA tCO1 tCO2 tOE tBA tLZ tOLZ tBLZ tHZ tOHZ tBHZ tOH Write Cycle EM565161 Symbol tWC tWP tCW tBW tAS tWR tWHZ tOW tDS tDH Write cycle time Write pulse width Chip Enable to end of write Data Byte Control to end of Write Address setup time Write Recovery time WE# Low to Output in High-Z WE# High to Output in Low-Z Data Setup Time Data Hold Time Parameter 55 45 45 45 0 0 − 5 25 0 -55 -70 Unit − − − − − − 20 − − − ns Min Max Min Max − − − − − − 20 − − − 70 55 60 60 0 0 − 5 30 0 Read cycle time Address access time Chip Enable (CE1#) Access Time Chip Enable (CE2) Access Time Output enable access time Data Byte Control Access Time Chip Enable Low to Output in Low-Z Output enable Low to Output in Low-Z Data Byte Control Low to Output in Low-Z Chip Enable High to Output in High-Z Output Enable High to Output in High-Z Data Byte Control High to Output in High-Z Output Data Hold Time Parameter 55 − − − − − 10 5 10 − − − 10 -55 -70 Unit − 70 70 70 35 70 − − − 25 25 25 − ns Min Max Min Max − 55 55 55 25 55 − − − 20 20 20 − 70 − − − − − 10 5 10 − − − 10 AC Test Condition • Output load : 60pF + one TTL gate • Input pulse level : 0.4V, 2.4V • Timing measurements : 0.5 x VDD • tR, tF : 5ns Preliminary 5 Rev 0.9 Jan 2002 E tronTech Read Cycle (See Note 1) tR C EM565161 Address tA A tO H tC O 1 CE1# CE2 tC O 2 tH Z tO E OE# tO H Z tB A UB # , LB# tB L Z tO L Z tL Z tB H Z DOUT V A L ID D A T A O U T Preliminary 6 Rev 0.9 Jan 2002 E tronTech Write Cycle1 (WE# Controlled)(See Note 4) tW C EM565161 Address tA S tW P tW R W E# tC W CE1# CE2 tC W tB W UB# , LB# tW H Z tO W DOUT (S e e N o te 2 ) (S e e N o te 3 ) tD S tD H D IN (S e e N ote 5 ) V A L ID D A T A IN (S e e N ote 5 ) Preliminary 7 Rev 0.9 Jan 2002 E tronTech Write Cycle 2 (CE1# Controlled)(See Note 4) tW C EM565161 A ddres s tAS tW P tW R W E# tC W CE1# CE2 tC W tBW UB# , LB# tB L Z tW H Z DOUT tL Z tD S tD H D IN (S e e N o te 5 ) V A L ID D A T A IN Preliminary 8 Rev 0.9 Jan 2002 E tronTech Write Cycle 3 (CE2 Controlled)(See Note 4) tW C EM565161 A ddres s tAS tW P tW R W E# tC W CE1# CE2 tC W tW H Z DOUT tL Z tD S tD H D IN (S e e N o te 5 ) V A L ID D A T A IN Preliminary 9 Rev 0.9 Jan 2002 E tronTech Write Cycle4 (UB#, LB# Controlled)(See Note 4) tW C EM565161 A ddres s tAS tW P tW R W E# tC W CE1# CE2 tC W tBW UB# , LB# tB L Z tW H Z DOUT tL Z tD S tD H D IN (S e e N o te 5 ) V A L ID D A T A IN Note: 1. WE# remains HIGH for the read cycle. 2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high impedance. 3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain at high impedance. 4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. Preliminary 10 Rev 0.9 Jan 2002 E tronTech Data Retention Characteristics (Ta = -40°C to 85°C) Symbol Parameter CE1# ≥ VDD – 0.2V VDR Data Retention Supply Voltage or UB# = LB# ≥ VDD – 0.2V or CE2 ≤ 0.2V, VIN ≥ VDD – 0.2V or VIN ≤ 0.2V tSDR tRDR Chip Deselect to Data Retention Mode Time Recovery Time 0 tRC 1.0 Min EM565161 Typ Max Unit − 3.6 V − − − − ns ns CE1# or UB#/LB# Controlled Data Retention Mode tS D R VDD 2 .7 V D a ta R e te n tio n M o d e tR D R 2 .2 V VDR CE1#, U B # /L B # GND N o te 1 CE2 Controlled Data Retention Mode VDD 2.7 V CE2 tSDR tRD R Data Reten tion M ode VDR Note 2 0.4 V GND Note: 1. CE1# ≥ VDD – 0.2V or UB# = LB# ≥ VDD – 0.2V 2. CE2 ≤ 0.2V Preliminary 11 Rev 0.9 Jan 2002 E tronTech Package Diagrams 48-Ball (8mm x 10mm) BGA Units in mm T O P VIEW EM565161 BO T T O M V IE W 0.10 S 0.25 S C C P IN 1 C O R N E R A B P IN 1 C O R N E R 0.30 3 4 5 6 6 5 4 3 0.05(48X) 2 1 1 2 A B C A B C E F G H 10 .0 0.1 5.25 D D E 0.75 F G H -B0.75 0.52 0.02 -A0.23 0.03 0.20(4X) 8.0 3.75 0.1 D -CSE AT IN G PLA NE 0.36 1.20 MA X 0.02 0.05 0.15 Preliminary 12 D Rev 0.9 Jan 2002 E tronTech Package Diagrams 48-Ball (6mm x 9mm) BGA Units in mm T O P V IE W BOT TO M VIEW 0.10 S 0.25 S P IN 1 C O R N E R EM565161 C C P IN 1 C O R N E R A B 0 .3 0 (4 8 X ) 6 5 4 3 2 1 123456 7 8 9 10 11 12 L -B0 .7 5 3 .7 5 -A0 . 2 0 (4 X ) 0 .1 0 -CSEA TING P LA NE Preliminary 13 Rev 0.9 Jan 2002