EtronTech
Features
• Organized as 1M words by 16 bits • Fast Cycle Time : 60/65/70/85ns • Fast Page Cycle Time : 18/20/25/30ns • Page Read Operation by 8 words • Standby Current(ISB1): 100uA • Deep power-down Current : 10uA (Memory cell data invalid) • Byte data control: LB# (DQ0 - 7), UB# (DQ8 - 15) • Compatible with low power SRAM • Single Power Supply Voltage : 3.0V±0.3V • Package Type : 48-ball FBGA, 6x8mm
EM566169BC
1M x 16 Pseudo SRAM
Rev 0.6 Apr. 2004 Pad Assignment
1 2 3 4 5 6
A
LB#
OE#
A0
A1
A2
CE2
B
DQ8
UB#
A3
A4
CE1#
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSS
DQ11
A17
A7
DQ3
VCC
Ordering Information
Part Number
EM566169BC-60/65/70/85
E
VCC
DQ12
NC
A16
DQ4
VSS
Speed(ns)
60/65/70/85
F
DQ14
DQ13
A14
A15
DQ5
DQ6
Pin Description
Symbol A0 – A19 DQ0 – DQ15 CE1# CE2 OE# W E# LB# UB# VCC/VCCQ VSS/VSSQ Function Address Inputs Data Inputs/Outputs Chip Enable Standby Mode Output Enable Write Control Lower Byte Control Upper Byte Control Power Supply Ground
G
DQ15
A19
A12
A13
WE#
DQ7
H
A18
A8
A9
A10
A11
NC
Overview
The EM566169 is a 16M-bit Pseudo SRAM organized as 1M words by 16 bits. It is designed with advanced CMOS technology specified RAM featuring low power static RAM compatible function and pin configuration. This device operates from a single power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when CE1# or both UB# and LB# are asserted high or CE2 is asserted low. There are three control inputs. CE1# and CE2 are used to select the device, and output enable (OE#) provides fast memory access. Data byte control pins (LB#,UB#) provide lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed wide operating range, the EM566169 can be used in environments exhibiting extreme temperature conditions.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech
Pin Location
Symbol Location Symbol Location Symbol Location Symbol Location Symbol A0 A3 A8 H2 A16 E4 DQ3 D5 DQ11 A1 A4 A9 H3 A17 D3 DQ4 E5 DQ12 A2 A5 A10 H4 A18 H1 DQ5 F5 DQ13 A3 B3 A11 H5 A19 G2 DQ6 F6 DQ14 A4 B4 A12 G3 NC H6 DQ7 G6 DQ15 A5 C3 A13 G4 DQ0 B6 DQ8 B1 CE1# A6 C4 A14 F3 DQ1 C5 DQ9 C1 CE2 A7 D4 A15 F4 DQ2 C6 DQ10 C2 OE#
EM566169BC
Location Symbol Location D2 WE# G5 E2 LB# A1 F2 UB# B2 F1 VCC D6 G1 VCC E1 B5 GND D1 A6 GND E6 A2 NC E3
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EtronTech
Block Diagram
Standby/Deep Power Down Mode Control
EM566169BC
VCC VSS Refresh Control
M emory Cell Array Refresh Counter Row Address Decoder
1M x 16
A0 – A19
Address Buffer
DQ0 – DQ7 DQ8 – DQ15
Input Data Control
Sense AMP
Output Data Control
Column Decoder
Address Buffer
CE1# CE2 OE# WE# LB# UB# Control Logic
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EtronTech
Operating Mode
CE1# CE2 OE# WE# LB# UB# DQ0~DQ7 DQ8~DQ15 X L X X X X High-Z H H X X X X High-Z L H X X H H High-Z L H H H L X High-Z L H H H X L High-Z L H L H L H D-out L H L H H L High-Z L H L H L L D-out L H X L L H D-in L H X L H L High-Z L H X L L L D-in Note: X=don’t care. H=logic high. L=logic low. High-Z High-Z High-Z High-Z High-Z High-Z D-out D-out High-Z D-in D-in Mode Deselect Deselect Deselect Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
EM566169BC
Power Deep Power Down Standby Standby Active Active Active Active Active Active Active Active
Absolute Maximum Ratings
Supply voltage, VCC Input voltages, VIN
1)
-0.2 to +3.6V -0.2 to VCC + 0.3V -2.0 to +3.6V* 100 mA -25 to +85°C -65 to +125°C 240°C 1W
Input and output voltages, VIN, VOUT Output short circuit current ISH Operating temperature, TA Storage temperature, TSTRG Soldering Temperature (10s), TSOLDER Power dissipation, PD
Note: Absolute maximum DC requirements contains stress ratings only. Functional operation at the absolute maximum limits is not implied or guaranteed. Extended exposure to maximum ratings may affect device reliability.
Recommended DC Operating Conditions
Symbol VCC VSS VIH VIL Notes: 1. Overshoot: VCC + 2.0V in case of pulse width ≤ 20ns 2. Undershoot: -2.0V in case of pulse width ≤ 20ns 3. Overshoot and undershoot are sampled, not 100% tested. Parameter Power Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 0 2.2 -0.2
2)
Typ. 3.0 − − −
Max. 3.3 0 VCC+0.2 +0.6
1)
Unit V V V V
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EtronTech
DC Characteristics
Symbol ILI Parameter Input Leakage Current Output Leakage Current Test Conditions VIN = VSS to VCC VIO = VSS to VCC CE1# = VIH, CE2 = VIL or OE# = VIH or WE# = VIL Cycle time = Min., 100% duty, 70ns/85ns Operating Current I = 0mA, CE1# = VIL, CE2 = @ Min Cycle Time IO VIH, VIN = VIH or VIL 60ns/65ns CE1# = VCC – 0.2V and CE2 = VCC – 0.2V, Other inputs = VSS ~ VCC ISBD VOL VOH Deep Power Down (0Mb refresh) Output Low Voltage Output High Voltage CE1# ≤ 0.2V and CE2 ≤ 0.2V, Other inputs = VSS ~ VCC IOL = 2.1mA IOH = -1.0mA
EM566169BC
Min. -1 Max. 1 Unit µA
ILO
-1
1
µA
35 − 45 mA
ICC1
ISB1
Standby Current (CMOS)
−
100
µA
− − 2.4
10 0.4 −
µA V V
Capacitance (Ta = 25°C; f = 1 MHz)
Parameter Input capacitance Output capacitance Symbol CIN COUT Min − − T yp − − Max 8 10 Unit pF pF T est Conditions VIN = GND VOUT = GND
Notes: These parameters are sampled and not 100% tested.
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EtronTech
AC Characteristics and Operating Conditions (Ta = -25°C to 85°C, VCC = 2.7V to 3.3V)
Symbol Parameter Read Cycle tRC tAA tCO1 tCO2 tOE tBA tLZ tOLZ tBLZ tHZ tOHZ tBHZ tOH tPM tPC tPA Read Cycle Time Address Access Time Chip Enable (CE1#) Access Time Chip Enable (CE2) Access Time Output Enable access time Data Byte Control Access Time Chip Enable Low to Output in LowZ Output enable Low to Output in Low-Z Data Byte Control Low to Output in Low-Z Chip Enable High to Output in High-Z Output Enable High to Output in High-Z Data Byte Control High to Output in High-Z Output Data Hold Time Normal to Page Read Cycle Time Page Cycle Time Page Mode Address Access Time Write Cycle tWC tWP tAW tCW tBW tAS tWR tWHZ tOW tDW tDH Write Cycle Time Write Pulse Width Address Valid to End of Write Chip Enable to End of Write Data Byte Control to End of Write Address Setup Ttime Write Recovery Time WE# Low to Output in High-Z WE# High to Output in Low-Z Data to Write Overlap Data Hold Time 5 30 0 60 45 50 50 50 0 0 20 5 30 0 65 50 55 55 55 0 0 20 70 50 60 60 60 0 0 − 5 30 0 10 60 18 18 15000 10 5 10 20 20 20 10 65 20 20 15000 60 15000 60 60 60 45 60 10 5 10 25 25 25 65 15000 65 65 65 45 65 70 − − − − − 10 5 10 − − − 10 70 25 -60 Min Max -65 Min Max Min
EM566169BC
-70 Max
-85 Min Max
Unit
15000 70 70 70 45 70 − − − 25 25 25 − 15000
85 − − − − − 10 5 10 − − − 10 85 30
15000 ns 85 85 85 45 85 − − − 35 35 35 − − 30 ns ns ns ns ns ns ns ns ns ns ns ns
15000 ns ns ns
25
−
− − − − − − − 20 − − −
85 60 70 70 70 0 0 − 5 35 0
− − − − − − − 30 − − −
ns ns ns ns ns ns ns ns ns ns ns
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EtronTech
AC Test Condition
• Output load : 30pF + one TTL gate • Input pulse level : 0.4V, 2.4 • Timing measurements : 0.5 x VCC • tR, tF : 5ns
EM566169BC
AC Test Loads
RL = 50 Ω DOUT Z0 = 50 Ω Note: 1. Including scope and jig capacitance
1 CL
VL = 1.5 V = 30 pF
State Diagram
Deep Power Down Exit Sequence Deep Power Down Entry Sequence
CE1# = VIH or VIL, CE2=VIH
Deep Power Down Mode
CE2=VIH CE2=VIL
Power on
Initial State (Wait 200µ s)
Active
CE1# =VIL, CE2=VIH, CE2=VIL
Power Up Sequence
CE2=VIH, CE1# =VIH or UB#, LB# =VIH
Standby
Standby Mode Characteristics
Power Mode Standby Deep Power Down Memory Cell Data Valid Invalid Standby Current (µA) 100 10 Wait Time 0 ns 200 µs
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EtronTech
Timing Diagrams Read Cycle 1 – Addressed Controlled
1)
EM566169BC
tRC Address tAA tOH Data Out Previous Data Valid tOH Data Valid
Read Cycle 2 – CE1# Controlled
2)
tRC Address tAA tCO CE1# tLZ tHZ tBA UB#, LB# tBLZ tBHZ tOH
tOE OE# tOLZ Data Out High-Z
tOHZ Data Valid High-Z
Notes: 1. CE1# = OE# = VIL, CE2 = WE# = VIH, UB# or/and LB# = VIL 2. CE2 = WE# = VIH
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EtronTech
EM566169BC
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EtronTech
Page Read Operation(8 words access)
tPM tRC A3 ~Amax
EM566169BC
A0, A1, A2 tAA CE1# tCO tOE tPA
tPC
UB#, LB# OE# Data Out High-Z
High-Z
Note(1)
Note (1) : Maxium 8 word. Random page read is supported within addresses(A0, A1,A2). (2) : CE2 and WE# are fixed high in Page Read Operation.
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EtronTech
Write Cycle 1 – WE# Controlled
1) 2)
EM566169BC
tWC Address tAW CE1# tCW tWR
UB#, LB#
tBW
WE# tAS Data In High-Z
tWP tDW Data Valid tWHZ tOW tDH High-Z
Data Out
Data Undefined
Write Cycle 2 – CE1# Controlled
1) 2)
tWC Address tAW tAS CE1# tCW tWR
UB#, LB#
tBW
WE#
tWP tDW tDH
Data In
Data Valid
Data Out
High-Z
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EtronTech
Write Cycle 3 – UB#, LB# Controlled
1) 2)
EM566169BC
tWC
Address tAW CE1# tCW tWR
UB#, LB# tAS
tBW
WE#
tWP tDW tDH
Data In
Data Valid
Data Out
High-Z
Notes: 1. CE2 = VIH 2. CE2 = WE# = VIH
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EtronTech
Deep Power Down Mode – Entry and Exit
200µs
EM566169BC
~ ~
CE2
1µs
Normal Operation Suspend
Deep Power Down Mode
W ake Up Normal Operation
~ ~
CE1#
Power Up
200µs
~ ~
VCC
CE2
CE1#
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EtronTech
Avoid Timing
EM566169BC
Etron Pseudo SRAM has a timing which is not supported at read operation. If your system has multiple invalid address signal shorter than tRC during over 15µs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during 15 µs shown as in Avoidable timing 1 or toggle CE1# to high ( tRC) one time at least shown as in Avoidable Timing 2.
Abnormal Timing
15µs
CE1#
WE# < tRC Address
Avoidable Timing 1
15µs
CE1#
WE# tRC
Address
Avoidable Timing 2
15µs tRC
CE1#
WE#
< tRC Address
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Apr. 2004
≧
≧
≧
≧ ≧ ≧
EtronTech
Package Diagrams 48-Ball BGA Units in mm
TOP VIEW
EM566169BC
BOTTOM VIEW
0.075
S S
C C
PIN 1 CORNER
0.15
PIN 1 CORNER
A
B
0.30 3 4 5 6 6 5 4 3
0.05(48X) 2 1
1
2
8.0
0.02
0.52
0.03
0.23
0.12MAX -C0. 1 5 1.20 MAX
SEATING PLANE
0.04 0.05
0.32
15
Rev 0.6
±
±
0.1
-B0.75 3.75 -A6.0 0.1
±
±
±
Apr. 2004