EM567168

EtronTech Features • Organized as 2M words by 16 bits • Fast Cycle Time : 55ns, 70ns • Standby Current : 100uA • Deep power-down Current : 10uA (Memory cell data invalid) • Byte data control: LB# (DQ0 - 7), UB# (DQ8 - 15) • Compatible with low power SRAM • Single Power Supply Voltage : 3.0V±0.3V • Package Type : 48-ball FBGA, 6x8mm EM567168 2M x 16 Pseudo SRAM Rev 1.1 Apr. 2004 Pin Assignment 48-Ball BGA, Top View 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CE2 B DQ8 UB# A3 A4 CE1# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 Pin Description Symbol A0 – A20 DQ0 – DQ15 CE1# CE2 OE# W E# LB# UB# VCC VSS Function Address Inputs Data Inputs/Outputs Chip Enable Deep Power Down Output Enable Write Control Lower Byte Control Upper Byte Control Power Supply Ground D VSS DQ11 A17 A7 DQ3 VCC E VCC DQ12 NC A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 Overview The EM567168 is a 32M-bit Pseudo SRAM organized as 2M words by 16 bits. It is designed with advanced CMOS technology specified RAM featuring low power static RAM compatible function and pin configuration. This device operates from a single power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when CE1# or both UB# and LB# are asserted high or CE2 is asserted low. There are three control inputs. CE1# and CE2 are used to select the device, and output enable (OE#) provides fast memory access. Data byte control pins (LB#,UB#) provide lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed wide operating range, the EM567168 can be used in environments exhibiting extreme temperature conditions. Pin Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol A0 A3 A8 H2 A16 E4 DQ3 D5 DQ11 A1 A4 A9 H3 A17 D3 DQ4 E5 DQ12 A2 A5 A10 H4 A18 H1 DQ5 F5 DQ13 A3 B3 A11 H5 A19 G2 DQ6 F6 DQ14 A4 B4 A12 G3 A20 H6 DQ7 G6 DQ15 A5 C3 A13 G4 DQ0 B6 DQ8 B1 CE1# A6 C4 A14 F3 DQ1 C5 DQ9 C1 CE2 A7 D4 A15 F4 DQ2 C6 DQ10 C2 OE# Location Symbol Location D2 WE# G5 E2 LB# A1 F2 UB# B2 F1 VCC D6 G1 VCC E1 B5 GND D1 A6 GND E6 A2 NC E3 Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech Block Diagram Standby/Deep Power Down Mode Control EM567168 VCC VSS Refresh Control M emory Cell Array Refresh Counter Row Address Decoder 2M x 16 A0 – A20 Address Buffer DQ0 – DQ7 DQ8 – DQ15 Input Data Control Sense AMP Output Data Control Column Decoder Address Buffer CE1# CE2 OE# WE# LB# UB# Control Logic 2 Rev 1.1 Apr. 2004 EtronTech Operating Mode CE1# CE2 OE# WE# LB# UB# DQ0~DQ7 DQ8~DQ15 H X L L L L L L L L L H L H H H H H H H H H X X X H H L L L X X X X X X H H H H H L L L X X H L X L H L L H L X X H X L H L L H L L High-Z High-Z High-Z High-Z High-Z D-out High-Z D-out D-in High-Z D-in High-Z High-Z High-Z High-Z High-Z High-Z D-out D-out High-Z D-in D-in Mode Deselect Deselect Deselect Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write EM567168 Power Standby Deep Power Down Standby Active Active Active Active Active Active Active Active Note: X=don’t care. H=logic high. L=logic low. 1) Absolute Maximum Ratings Supply voltage, VCC Input voltages, VIN -0.2 to +3.6V -0.2 to VCC + 0.3V -2.0 to +3.6V* 100 mA -25 to +85°C -65 to +125°C 240°C 1W Input and output voltages, VIN, VOUT Output short circuit current ISH Operating temperature, TA Storage temperature, TSTRG Soldering Temperature (10s), TSOLDER Power dissipation, PD Note: Absolute maximum DC requirements contains stress ratings only. Functional operation at the absolute maximum limits is not implied or guaranteed. Extended exposure to maximum ratings may affect device reliability. Recommended DC Operating Conditions Symbol VCC VSS VIH VIL Notes: 1. Overshoot: VCC + 2.0V in case of pulse width ≤ 20ns 2. Undershoot: -2.0V in case of pulse width ≤ 20ns 3. Overshoot and undershoot are sampled, not 100% tested. Parameter Power Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 0 2.2 -0.2 2) Typ. 3.0 − − − Max. 3.3 0 VCC+0.2 +0.6 1) Unit V V V V 3 Rev 1.1 Apr. 2004 EtronTech DC Characteristics Symbol ILI Parameter Input Leakage Current Output Leakage Current Test Conditions VIN = VSS to VDD VIO = VSS to VDD CE1# = VIH, CE2 = VIL or OE# = VIH or WE# = VIL Operating Current @ Min Cycle Time Cycle time = Min., 100% duty, IIO = 0mA, CE1# = VIL, CE2 = VIH, VIN = VIH or VIL Cycle time = 1µs, 100% duty ICC2 Operating Current @ Max Cycle Time (1µs) IIO = 0mA, CE1# ≤ 0.2V, CE2 ≥ VDD -0.2V, VIN ≤ 0.2V or VIN ≥ VDD -0.2V ISB1 Standby Current (CMOS) CE1# = VDD – 0.2V and CE2 = VDD – 0.2V, Other inputs = VSS ~ VCC ISBD VOL VOH Deep Power Down Output Low Voltage Output High Voltage CE2 ≤ 0.2V, Other inputs = VSS ~ VCC IOL = 2.1mA IOH = -1.0mA − 2.4 − − 55ns − 70ns Min. -1 EM567168 Max. 1 Unit µA ILO -1 1 µA 45 mA 35 ICC1 5 mA 100 µA 10 0.4 − µA V V Capacitance (Ta = 25°C; f = 1 MHz) Parameter Input capacitance Output capacitance Symbol CIN COUT Min − − T yp − − Max 8 10 Unit pF pF T est Conditions VIN = GND VOUT = GND Notes: These parameters are sampled and not 100% tested. 4 Rev 1.1 Apr. 2004 EtronTech Symbol Parameter Min Read Cycle tRC tAA tCO1 tCO2 tOE tBA tLZ tOLZ tBLZ tHZ tOHZ tBHZ tOH tWC tWP tAW tCW tBW tAS tWR tWHZ tOW tDW tDH Read cycle time Address access time Chip Enable (CE1#) Access Time Chip Enable (CE2) Access Time Output enable access time Data Byte Control Access Time Chip Enable Low to Output in Low-Z Output enable Low to Output in Low-Z Data Byte Control Low to Output in Low-Z Chip Enable High to Output in High-Z Output Enable High to Output in High-Z Data Byte Control High to Output in High-Z Output Data Hold Time Write Cycle Write Cycle Time Write Pulse Width Address Valid to End of Write Chip Enable to End of Write Data Byte Control to End of Write Address Setup Ttime Write Recovery Time WE# Low to Output in High-Z WE# High to Output in Low-Z Data to Write Overlap Data Hold Time 55 45 45 45 45 0 0 − 5 30 0 − − − − − − − 20 − − − 70 50 60 60 60 0 0 − 5 30 0 55 − − − − − 10 5 10 − − − 10 − 55 55 55 25 55 − − − 20 20 20 − 70 − − − − − 10 5 10 − − − 10 -55 Max Min EM567168 AC Characteristics and Operating Conditions (Ta = -25°C to 85°C, VCC = 2.7V to 3.3V) -70 Max Unit − 70 70 70 35 70 − − − 25 25 25 − − − − − − − − 20 − − − ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns AC Test Condition • Output load : 50pF + one TTL gate • Input pulse level : 0.4V, 2.4 • Timing measurements : 0.5 x VCC • tR, tF : 5ns 5 Rev 1.1 Apr. 2004 EtronTech AC Test Loads RL = 50 Ω DOUT Z0 = 50 Ω Note: 1. Including scope and jig capacitance 1 CL EM567168 VL = 1.5 V = 50 pF State Diagram Deep Power Down Exit Sequence Deep Power Down Entry Sequence CE1# = VIH or VIL, CE2=VIH Deep Power Down Mode CE2=VIL CE2=VIH Power on Initial State (Wait 200µ s) Active CE2=VIH, CE1# =VIH or UB#, LB# =VIH CE2=VIL Power Up Sequence CE1# =VIL, CE2=VIH, UB# & LB# or/and LB# = VIL Standby Mode Standby Mode Characteristics Power Mode Standby Deep Power Down Memory Cell Data Valid Invalid Standby Current (µA) 100 10 Wait Time (µs) 0 200 6 Rev 1.1 Apr. 2004 EtronTech Timing Diagrams Read Cycle 1 – Addressed Controlled 1) EM567168 tRC Address tAA tOH Data Out Previous Data Valid tOH Data Valid Read Cycle 2 – CE1# Controlled 2) tRC Address tAA tCO CE1# tLZ tHZ tBA UB#, LB# tBLZ tBHZ tOH tOE OE# tOLZ Data Out High-Z tOHZ Data Valid High-Z Notes: 1. CE1# = OE# = VIL, CE2 = WE# = VIH, UB# or/and LB# = VIL 2. CE2 = WE# = VIH 7 Rev 1.1 Apr. 2004 EtronTech Write Cycle 1 – WE# Controlled 1) 2) EM567168 tWC Address tAW CE1# tCW tWR UB#, LB# tBW WE# tAS Data In High-Z tWP tDW Data Valid tWHZ tOW tDH High-Z Data Out Data Undefined Write Cycle 2 – CE1# Controlled 1) 2) tWC Address tAW tAS CE1# tCW tWR UB#, LB# tBW WE# tWP tDW tDH Data In Data Valid Data Out High-Z 8 Rev 1.1 Apr. 2004 EtronTech Write Cycle 3 – UB#, LB# Controlled 1) 2) EM567168 tWC Address tAW CE1# tCW tWR UB#, LB# tAS tBW WE# tWP tDW tDH Data In Data Valid Data Out High-Z Notes: 1. CE2 = VIH 2. CE2 = WE# = VIH 9 Rev 1.1 Apr. 2004 EtronTech Deep Power Down Mode 200µs EM567168 ~ ~ CE2 1µs Normal Operation Suspend Mode Deep Power Down Mode W ake Up Normal Operation ~ ~ CE1# Power Up 200µs ~ ~ VCC CE2 CE1# 10 Rev 1.1 Apr. 2004 EtronTech Avoid Timing EM567168 Etron Pseudo SRAM has a timing which is not supported at read operation. If your system has multiple invalid address signal shorter than tRC during over 15µs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during 15 µs shown as in Avoidable timing 1 or toggle CE1# to high ( tRC) one time at least shown as in Avoidable Timing 2. Abnormal Timing 15µs CE1# WE# < tRC Address Avoidable Timing 1 15µs CE1# WE# tRC Address Avoidable Timing 2 15µs tRC CE1# WE# < tRC Address 11 Rev 1.1 Apr. 2004 ≧ ≧ ≧ ≧ ≧ ≧ EtronTech Package Diagrams 48-Ball BGA Units in mm TOP VIEW EM567168 BOTTOM VIEW 0.075 S S C C PIN 1 CORNER 0.15 PIN 1 CORNER A B 0.30 3 4 5 6 6 5 4 3 0.05(48X) 2 1 1 2 8.0 0.02 0.52 0.03 0.23 0.12MAX -C0. 1 5 1.20 MAX SEATING PLANE 0.04 0.05 0.32 12 Rev 1.1 ± ± 0.1 -B0.75 3.75 -A6.0 0.1 ± ± ± Apr. 2004