EM637327Q-7

EtronTech Features • • • • • • EM637327 1Mega x 32 SGRAM Preliminary (08/99) Pin Assignment (Top View) D Q2 9 VSSQ D Q3 0 D Q3 1 VSS NC NC NC NC NC NC NC NC NC NC VDD DQ 0 DQ 1 VSSQ DQ 2 • • • • • • • • Fast access time from clock: 4.5/5.5/5.5/6 ns Fast clock rate: 200/166/143/125 MHz Fully synchronous operation Internal pipelined architecture Dual internal banks (512K x 32bit x 2bank) Programmable Mode - CAS# Latency: 1, 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst-Read-Single-Write - Load Color or Mask register Burst stop function Individual byte controlled by DQM0-3 Block write and write-per-bit capability Auto Refresh and Self Refresh 2048 refresh cycles/32ms Single +3.3V ± 0.3V power supply Interface: LVTTL JEDEC 100-pin Plastic package - QFP (body thickness=2.8mm) - TQFP1.4 (body thickness=1.4mm) 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DQ 3 V DDQ DQ 4 DQ 5 VSSQ DQ 6 DQ 7 V DDQ DQ16 DQ17 VSSQ DQ18 DQ19 V DDQ V DD VSS DQ20 DQ21 VSSQ DQ22 DQ23 V DDQ DQ M0 DQ M2 WE# CA S# RA S# CS 0# BS A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQ28 V DDQ DQ27 DQ26 VSSQ DQ25 DQ24 V DDQ DQ15 DQ14 VSSQ DQ13 DQ12 V DDQ VSS V DD DQ11 DQ10 VSSQ DQ 9 DQ 8 V DDQ NC DQ M3 DQ M1 CL K CKE DSF NC A8 (AP) Overview The EM637327 SGRAM is a high-speed CMOS synchronous graphics DRAM containing 32 Mbits. It is internally configured as a dual 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM637327 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth. 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 A7 A6 A5 A4 VSS A10 NC NC NC NC NC NC NC NC NC VDD A3 A2 A1 A0 Key Specifications EM637327 - 5/6/7/8 5/6/7/8 ns 25/30/35/40 ns 4.5/5.5/5.5/6 ns 55/60/63/72 ns tCK3 tRAS tAC3 tRC Clock Cycle time(min.) Row Active time(max.) Access time from CLK(max.) Row Cycle time(min.) Ordering Information Part Number EM637327Q-5 EM637327TQ-5 EM637327Q-6 EM637327TQ-6 EM637327Q-7 EM637327TQ-7 EM637327Q-8 EM637327TQ-8 Frequency 200 MHz 200 MHz 166 MHz 166 MHz 143 MHz 143 MHz 125 MHz 125 MHz Package QFP TQFP1.4 QFP TQFP1.4 QFP TQFP1.4 QFP TQFP1.4 Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech Block Diagram 1Mega x 32 SGRAM EM637327 CLK CLOCK BUFFER Row Decoder Column Decoder 2048 X 256 X 32 CELL ARRAY (BANK #0) Sense Amplifier DQM0~3 CKE CS# RAS# CAS# WE# DSF COMMAND DECODER CONTROL SIGNAL GENERATOR COLUMN COUNTER A8 COLOR REGISTER MASK REGISTER DQS BUFFER DQ0 ¢x DQ31 MODE REGISTER A0 A7 A9 A10 BS REFRESH COUNTER ADDRESS BUFFER SPECIAL MODE REGISTER Sense Amplifier Row Decoder 2048 X 256 X 32 CELL ARRAY (BANK #1) Column Decoder Preliminary 2 August 1999 EtronTech Pin Descriptions 1Mega x 32 SGRAM EM637327 Table 1. Pin Details of EM637327 Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SGRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When both banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low standby power. Input Bank Select: BS defines to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. BS is also used to program the 11th bit of the Mode and Special Mode registers. CKE BS A0-A10 Input Address Inputs: A0-A10 are sampled during the BankActivate command (row address A0-A10) and Read/Write command (column address A0-A7 with A8 defining Auto Precharge) to select one location out of the 512K available in the respective bank. During a Precharge command, A8 is sampled to determine if both banks are to be precharged (A8 = HIGH). The address inputs also provide the op-code during a Mode Register Set or Special Mode Register Set command. CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. Input Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. Input Column Address Strobe: The CAS# signal conjunction with the RAS# and WE# signals and When RAS# is held "HIGH" and CS# is asserted asserting CAS# "LOW." Then, the Read or Write "LOW" or "HIGH." defines the operation commands in is latched at the positive edges of CLK. "LOW," the column access is started by command is selected by asserting WE# RAS# CAS# WE# Input Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. Input Define Special Function: The DSF signal defines the operation commands in conjunction with the RAS# and CAS# and WE# signals and is latched at the positive edges of CLK. The DSF input is used to select the masked write disable/enable command and block write command, and the Special Mode Register Set cycle. DSF Preliminary 3 August 1999 EtronTech 1Mega x 32 SGRAM EM637327 DQM0 - Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer DQM3 controls. The I/O buffers are placed in a high-z state when DQM is sampled HIGH. Input data is masked when DQM is sampled HIGH during a write cycle. Output data is masked (two-clock latency) when DQM is sampled HIGH during a read cycle. DQM3 masks DQ31DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7DQ0. DQ0- Input/ Data I/O: The DQ0-31 input and output data are synchronized with the positive edges of DQ31 Output CLK. The I/Os are byte-maskable during Reads and Writes. The DQs also serve as column/byte mask inputs during Block Writes. NC VDDQ VSSQ VDD VSS No Connect: These pins should be left unconnected. Supply DQ Power: Provide isolated power to DQs for improved noise immunity. Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. Supply Power Supply: +3.3V±0.3V Supply Ground Preliminary 4 August 1999 EtronTech Operation Mode 1Mega x 32 SGRAM EM637327 Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command BankActivate & Masked Write Disable BankActivate & Masked Write Enable BankPrecharge PrechargeAll Write Block Write Command Write and AutoPrecharge Block Write and AutoPrecharge Read Read and Autoprecharge Mode Register Set Special Mode Register Set No-Operation Burst Stop Device Deselect AutoRefresh SelfRefresh Entry SelfRefresh Exit State Idle(3) Idle(3) Any Any Active(3) Active(3) Active(3) Active(3) Active(3) Active(3) Idle Idle(5) Any Active(4) Any Idle Idle Idle (SelfRefresh) CKEn-1 CKEn DQM(7) BS A8 ADDR CS# RAS# CAS# WE# DSF H H H H H H H H H H H H H H H H H L H H L L H X X X X X X X X X X X X X X X H L H L L H H X X X X X X X X X X X X X X X X X X X X X X X L V V V X V V V V V V V X X X X X X X X X X X X V V L H L L H H L H L X X X X X X X X X X X X V V X X V V V V V V V V X X X X X X X X X X X L L L L L L L L L L L L L L H L L H L X H L X H L X L L L L H H H H H H L L H H X L L X H X X H X X H X H H H H L L L L L L L L H H X L L X H X X H X X H X H H L L L L L L H H L L H L X H H X H X X H X X H X X L H L L L H L H L L L H X L X L L X X X X L X X L X X Clock Suspend Mode Entry Power Down Mode Entry Active Any(6) Active Any (PowerDown) Clock Suspend Mode Exit Power Down Mode Exit Data Write/Output Enable Data Mask/Output Disable Active Active H X H XX X X X X Note: 1. V=Valid X=Don't Care L=Low level H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. The Special Mode Register Set is also available in Row Active State. 6. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode. 7. DQM0-3 Preliminary 5 August 1999 EtronTech Commands 1 1Mega x 32 SGRAM EM637327 BankActivate & Masked Write Disable command (RAS# = "L", CAS# = "H", WE# = "H", DSF = "L", BS = Bank, A0-A10 = Row Address) The BankActivate command activates the idle bank designated by the BS (Bank Select) signal. By latching the row address on A0 to A9 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.) from the time of bank activation. A subsequent BankActivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). The minimum time interval between successive BankActivate commands to the same bank is defined by tRC(min.). The SGRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of both banks. tRRD(min.) specifies the minimum time required between activating different banks. After this command is used, the Write command and the Block Write command perform the no mask write operation. T0 T1 T2 T3 .............. Bank A Row Addr. RAS# - CAS# delay (tRCD) Bank A Col Addr. .............. Bank B Row Addr. RAS# - RAS# delay time (tRRD) R/W A with AutoPrecharge Tn+3 Tn+4 Tn+5 Tn+6 CLK ADDRESS Bank A Row Addr. COM MAND Bank A Activate NOP NOP .............. Bank B Activate NOP NOP Bank A Activate RAS# Cycle time (tRC) AutoPrecharge Begin : "H" or "L" BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3) 2 BankActivate & Masked Write Enable command (refer to the above figure) (RAS# = "L", CAS# = "H", WE# = "H", DSF = "H", BS = Bank, A0-A10 = Row Address) The BankActivate command activates the idle bank designated by BS signal. After this command is performed, the Write command and the Block Write command perform the masked write operation. In the masked write and the masked block write functions, the I/O mask data that was stored in the write mask register is used. BankPrecharge command (RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Bank, A8 = "L", A0-A7, A9-A10 = Don't care) The BankPrecharge command precharges the bank disignated by BS signal. The precharged bank is switched from the active state to the idle state. This command can be asserted anytime after tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. PrechargeAll command (RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Don't care, A8 = "L", A0-A7, A9-A10 = Don't care)The PrechargeAll command precharges both banks simultaneously and can be issued even if both banks are not in the active state. Both banks are then switched to the idle state. Read command (RAS# = "H", CAS# = "L", WE# = "H", DSF = "L", BS = Bank, A8 = "L", A0-A7 = Column Address) The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is issued. During read bursts, the valid data-out element from the starting column address will be available following the CAS# latency after the issue of the Read command. Each subsequent dataout element will be valid by the next positive clock edge (refer to the following figure). The DQs go 3 4 5 Preliminary 6 August 1999 EtronTech T0 T1 T2 1Mega x 32 SGRAM EM637327 into high-impedance at the end of the burst unless other command is initiated. The burst length, burst sequence, and CAS# latency are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). T3 T4 T5 T6 T7 T8 CLK COM MAND READ A NOP NOP NOP NOP NOP NOP NOP NOP CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Burst Read Operation(Burst Length = 4, CAS# Latency = 1, 2, 3) The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function may be interrupted by a subsequent Read or Write/Block Write command to the same bank or the other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read command can occur on any clock cycle following a previous Read command (refer to the following figure). T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COM MAND READ A READ B NOP NOP NOP NOP NOP NOP NOP CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3) The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write/Block Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write/Block Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with high-impedance on the DQ pins must occur between the last read data and the Write/Block Write command (refer to the following three figures). If the data output of the burst read occurs at the second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the Write/Block Write command to avoid internal bus contention. Preliminary 7 August 1999 EtronTech T0 T1 T2 CLK DQM 1Mega x 32 SGRAM T3 T4 T5 T6 EM637327 T7 T8 COM MAND NOP READ A NOP NOP NOP NOP WRITE B NOP NOP DQ's DOUT A0 Must be Hi-Z before the Write Command DI NB 0 DINB1 DINB 2 : "H" or "L" Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 3) T0 CLK 1 Clk Interval DQM T1 T2 T3 T4 T5 T6 T7 T8 COM MAND NOP NOP BANKA ACTIVATE NOP READ A WRITE A NOP NOP NOP CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's DIN A0 Must be Hi-Z before the Write Command DIN A0 DIN A1 DIN A2 DIN A3 DIN A1 DIN A2 DIN A3 : "H" or "L" Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 1, 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COM MAND NOP NOP READ A NOP NOP WRITE B NOP NOP NOP CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's DOUT A0 DIN B0 Must be Hi-Z before the Write Command DIN B0 DIN B 1 DIN B2 DIN B3 DIN B 1 DIN B2 DIN B3 : "H" or "L" Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 1, 2) A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank. The following figure shows the optimum time that BankPrecharge/ PrechargeAll command is issued in different CAS# latency. Preliminary 8 August 1999 EtronTech T0 CLK Bank, Col A T1 T2 ADDRESS 1Mega x 32 SGRAM T3 T4 T5 T6 EM637327 T7 T8 Bank(s) Bank, Row tRP COM M AND READ A NOP NOP NOP Precharge NOP NOP Activate NOP CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2 , DQ's CAS# latency=3 tCK3 , DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Read to Precharge (CAS# Latency = 1, 2, 3) 6 Read and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", DSF = "L", BS = Bank, A8 = "H", A0-A7 = Column Address) The Read and AutoPrecharge command automatically performs the precharge operation after the read operation. Once this command is given, any subsequent command cannot occur within a time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge function is ignored. Write command (RAS# = "H", CAS# = "L", WE# = "L", DSF = "L", BS = Bank, A8 = "L", A0-A7 = Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is issued. During write bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). The DQs remain with high-impedance at the end of the burst unless another command is initiated. The burst length and burst sequence are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 7 COM MAND NOP WRITE A NOP NOP NOP NOP NOP NOP NOP DQ0 - DQ3 DIN A0 DIN A1 DIN A2 DIN A3 don't care The first data element and the write are registered on the same clock edge. Extra data is masked. Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3) Any Write performed to a row that was opened via an BankActivate & Masked Write Enable command is a masked write (Write-Per-Bit). Data is written to the 32 cells (bits) at the selected column location subject to the data stored in the Mask register. The overall mask consists of the DQM inputs, which mask on a per-byte basis, and the Mask register, which masks also on a per-bit basis. This is shown in the following block diagram. Preliminary 9 August 1999 EtronTech DSF BankActivate command D CK Q 1Mega x 32 SGRAM DQM0 EM637327 DRAM CELL DQ7 MR7 DQ6 MR6 DQ5 MR5 DQ4 MR4 DQ3 MR3 DQ2 MR2 DQ1 MR1 DQ0 MR0 0 = Masked 1 = Not Masked Note: Only the lower byte is shown. The operation is identical for other bytes. Write Per Bit (I/O Mask) Block Diagram A write burst without the auto precharge function may be interrupted by a subsequent Write/Block Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from Write/Block Write command can occur on any clock cycle following the previous Write command (refer to the following figure). T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 COMMAND NOP WRITE A WRITE B NOP NOP NOP NOP NOP NOP 1 Clk Interval DQ's DIN A0 DIN B0 DIN B 1 DIN B2 DIN B3 Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3) The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input data must be removed from the DQs at least one clock cycle before the Preliminary 10 August 1999 EtronTech T0 CLK T1 T2 1Mega x 32 SGRAM EM637327 T6 T7 T8 first read data appears on the outputs (refer to the following figure). Once the Read command is registered, the data inputs will be ignored and writes will not be executed. T3 T4 T5 COM MAND NOP WRITE A READ B NOP NOP NOP NOP NOP NOP CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DIN A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DIN A0 don't care DOUT B0 DOUT B1 DOUT B2 DOUT B3 DIN A0 don't care don't care DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data for the write is masked. Input data must be removed from the DQ's at least one clock cycle before the Read data appears on the outputs to avoid data contention. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3) The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals tWR /tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure). T0 CLK T1 T2 T3 T4 T5 T6 DQM tRP COM MAND WRITE NOP Precharge NOP NOP Activate NOP ADDRESS BA N K COL n DIN n DIN n+ 1 BANK (S) tWR ROW DQ : don't care Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2. Write to Precharge When the Burst-Read-Single-Write mode is selected, the write burst length is 1 regardless of the read burst length (refer to Figures 21 and 22 in Timing Waveforms). 8 Block Write command (RAS# = "H", CAS# = "L", WE# = "L", DSF = "H", BS = Bank, A8 = "L", A3-A7 = Column Address, DQ0-DQ31 = Column Mask) The block writes are non-burst accesses that write to eight column locations simultaneously. A single data value, which was previously loaded in the Color register, is written to the block of eight consecutive column locations addressed by inputs A3~A7. The information on the DQs which are Preliminary 11 August 1999 EtronTech 1Mega x 32 SGRAM EM637327 registered coincident with the Block Write command is used to mask specific column/byte combinations within the block. The mapping of the DQ inputs to the column/byte combinations is shown in following table. The overall Block Write mask consists of a combination of the DQM inputs, the Mask register, and the column/byte mask information, as shown in the following figure. The DQM and Mask register masking operates normally as for a Write command, with the exception that the mask information is applied simultaneously to all eight columns. Therefore, in a Block Write, a given bit is written only if a "0" is registered for the corresponding DQM input, a "1" is registered for the corresponding DQ signal, and the corresponding bit in the Mask register is "1". Block of Columns (selected by A3-A7 registered coincident with Block Write command) Row in Bank (selected by A0-A9, and BS registered coincident with BankActivate Command) Column Mask DQ0 on the DQ DQ1 inputs DQ2 DQ3 (registered DQ4 coincident DQ5 with Block DQ6 Write Command DQ7 DSF BankActivate command DQ CK DQM0 MR0 MR 1 Mask Register (previously loaded from corresponding DQ inputs) MR2 MR3 MR4 MR5 MR6 MR7 CR0 CR 1 CR2 CR3 CR4 CR5 CR6 CR7 Note: Only the lower byte is shown. The operation is identical for other bytes. Block-Write Masking Block Diagram Preliminary 12 August 1999 EtronTech DQ Inputs DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Column Address DQ Planes A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Controlled 0~7 0~7 0~7 0~7 0~7 0~7 0~7 0~7 8~15 8~15 8~15 8~15 8~15 8~15 8~15 8~15 1Mega x 32 SGRAM DQ Inputs DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 EM637327 Controlled 16~23 16~23 16~23 16~23 16~23 16~23 16~23 16~23 24~31 24~31 24~31 24~31 24~31 24~31 24~31 24~31 Column Address DQ Planes A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A block write access requires a time period of tBWC to execute, so in general, there should be m NOP cycles(m equals (tBWC - tCK)/tCK rounded up to the next whole number), after the Block Write command. However, BankActivate or BankPrecharge commands to the other bank are allowed. When following a Block Write with a BankPrecharge or PrechargeAll command to the same bank, tBPL must be met. 9 Write and AutoPrecharge command (refer to the following figure) (RAS# = "H", CAS# = "L", WE# = "L", DSF = "L", BS = Bank, A8 = "H", A0-A7 = Column Address) The Write and AutoPrecharge command performs the precharge operation automatically after the write operation. Once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in this command and the auto precharge function is ignored. T0 CLK Bank A Activate Write A AutoPrecharge T1 T2 T3 T4 T5 T6 T7 T8 COM MAND NOP NOP NOP NOP NOP NOP NOP tDAL CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DIN A0 DIN A1 DIN A0 DIN A1 * * * * tDAL tDAL DIN A0 DIN A1 tDAL= tWR + tRP Begin AutoPrecharge Bank can be reactivated at completion of tDAL Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 1, 2, 3) Preliminary 13 August 1999 EtronTech 10 1Mega x 32 SGRAM EM637327 Block Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", DSF = "H", BS = Bank, A8 = "H", A3-A7 = Column Address, DQ0-DQ31 = Column Mask) The Block Write and AutoPrecharge command performs the precharge operation automatically after the block write operation. Once this command is given, any subsequent command can not occur within a time delay of {tBPL + tRP(min.)}. Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", DSF = "L", BS, A0-A9 = Register Data) The mode register stores the data for controlling the various operating modes of SGRAM. The Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the Mode register to make SGRAM useful for a variety of different applications. The default values of the Mode Register after power-up are undefined; therefore this command must be issued at the power-up sequence. The state of pins A0~A8 and BS in the same cycle is the data written to the mode register. One clock cycle is required to complete the write in the mode register (refer to the following figure). The contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as both banks are in the idle state. T0 CLK t CK2 CKE Clock min. CS# T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 11 RAS# CA S# WE# DSF BS A9 Address Key A0 - A 8 DQM tRP DQ Hi-Z PrechargeAll Mode Register Set Command Any Command Mode Register Set Cycle (CAS# Latency = 1, 2, 3) The mode register is divided into various fields depending on functionality. Preliminary 14 August 1999 EtronTech • A2 0 0 0 0 1 1 1 1 • A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1Mega x 32 SGRAM EM637327 Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 1, 2, 4, 8, or full page. A0 Burst Length 1 2 4 8 Reserved Reserved Reserved Full Page Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode. Sequential Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only supports burst length of 4 and 8. A3 0 1 Addressing Mode Sequential Interleave --- Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device. The internal column address is varied by the Burst Length as shown in the following table. When the value of column address, (n + m), in the table is larger than 255, only the least significant 8 bits are effective. Data n Column Address 0 n 1 n+1 2 n+2 3 n+3 4 n+4 5 n+5 6 n+6 7 n+7 - 255 n+255 256 n 257 n+1 - 2 words: Burst Length 4 words: 8 words: Full Page: Column address is repeated until terminated. --- Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. Data n Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A7 A7 A7 A7 A7 A7 A7 A7 A6 A6 A6 A6 A6 A6 A6 A6 A5 A5 A5 A5 A5 A5 A5 A5 Column Address A4 A4 A4 A4 A4 A4 A4 A4 A3 A3 A3 A3 A3 A3 A3 A3 A2 A2 A2 A2 A1 A1 A0 A0# 4 words 8 words Burst Length A1# A0 A1# A0# A0 A0# A2# A1 A2# A1 A2# A1# A0 A2# A1# A0# Preliminary 15 August 1999 EtronTech • 1Mega x 32 SGRAM EM637327 CAS# Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min) ≤ CAS# Latency X tCK A6 0 0 0 0 1 A5 0 0 1 1 X A4 0 1 0 1 X CAS# Latency Reserved 1 clock 2 clocks 3 clocks Reserved • Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation. A8 0 0 1 A7 0 1 X Test Mode normal mode Vendor Use Only Vendor Use Only • Single Write Mode (A9) This bit is used to select the write mode. When the A9 bit is "0", the Burst-Read-BurstWrite mode is selected. When the A9 bit is "1", the Burst-Read-Single-Write mode is selected. A9 0 1 Single Write Mode Burst-Read-Burst-Write Burst-Read-Single-Write 12 Special Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", DSF = "H", BS, A0-A9 = Register Data) The special mode register is used to load the Color and Mask registers, which are used in Block Write and masked Write cycles. The control information being written to the Special Mode register is applied to the address inputs and the data to be written to either the Color register or the Mask register is applied to the DQs. When A6 is "HIGH" during a Special Mode Register Set cycle, the Color register will be loaded with the data on the DQs. Similarly, when A5 is "HIGH" during a Special Mode Register Set cycle, the Mask register will be loaded with the data on the DQs. A6=A5=1 in the Special Mode Register Set cycle is illegal. Functions Leave Unchanged Load Mask Register Load Color Register BS X X X A9 ~ A7 X X X A6 0 0 1 A5 0 1 0 A4 ~ A0 X X X Illegal X X 1 1 X One clock cycle is required to complete the write in the Special Mode register. This command can be issued during the active state. As in a write operation, this command accepts the data needed through DQ pins. Therefore, it should be attended not to induce bus contention. 13 No-Operation command (RAS# = "H", CAS# = "H", WE# = "H") The No-Operation command is used to perform a NOP to the SGRAM which is selected (CS# is Low). This prevents unwanted commands from being registered during idle or wait states. Preliminary 16 August 1999 EtronTech 14 1Mega x 32 SGRAM EM637327 Burst Stop command (RAS# = "H", CAS# = "H", WE# = "L", DSF = "L") The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only effective in a read/write burst without the auto precharge function. The terminated read burst ends after a delay equal to the CAS# latency (refer to the following figure). The termination of a write burst is shown in the following figure. T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP NOP NOP Burst Stop NOP NOP NOP NOP CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 The burst ends after a delay equal to the CAS# latency. DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Termination of a Burst Read Operation (Burst Length > 4, CAS# Latency = 1, 2, 3) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 COM MAND NOP WRITE A NOP NOP Burst Stop NOP NOP NOP NOP CAS# latency=1, 2, 3 DQ's DIN A0 DIN A1 DIN A2 don't care Input data for the Write is masked. Termination of a Burst Write Operation (Burst Length = X, CAS# Latency = 1, 2, 3) 15 Device Deselect command (CS# = "H") The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation command. AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms) (RAS# = "L", CAS# = "L", WE# = "H", DSF = "L", CKE = "H", BS, A0-A9 = Don't care) The AutoRefresh command is used during normal operation of the SGRAM and is analogous to CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh operation must be performed 2048 times within 32ms. The time required to complete the auto refresh operation is specified by tRC(min.). To provide the AutoRefresh command, both banks need to be in the idle state and the device must not be in power down mode (CKE is high in the previous cycle). This command must be followed by NOPs until the auto refresh operation is completed. The precharge time requirement, tRP(min), must be met before successive auto refresh operations are performed. 16 Preliminary 17 August 1999 EtronTech 17 1Mega x 32 SGRAM EM637327 SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms) (RAS# = "L", CAS# = "L", WE# = "H", DSF = "L", CKE = "L", BS, A0-A9 = Don't care) The SelfRefresh is another refresh mode available in the SGRAM. It is the preferred refresh mode for data retention and low power operation. Once the SelfRefresh command is registered, all the inputs to the SGRAM become "don't care" with the exception of CKE, which must remain LOW. The refresh addressing and timing is internally generated to reduce power consumption. The SGRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command). SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms) (CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H") This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a burst of 2048 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh mode. Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in Timing Waveforms) (CKE = "L") When the SGRAM is operating the burst cycle, the internal CLK is suspended(masked) from the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while CLK is suspended. On the other hand, when both banks are in the idle state, this command performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (32ms) since the command does not perform any refresh operations. Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing Waveforms) (CKE= "H") When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active state. tPDE(min.) is required when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end of this command. Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H") During a write cycle, the DQM signal functions as a Data Mask and can control every word of the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device selection, byte selection and bus control in a memory system. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and DQM3 controls DQ24 to DQ31. DQM masks the DQ's by a byte regardless that the corresponding DQ's are in a state of write-per-bit masking or pixel masking. Each DQM0-3 corresponds to DQ0-7, DQ8-15, DQ16-23, and DQ24-31. 18 19 20 21 Preliminary 18 August 1999 EtronTech Absolute Maximum Rating Symbol VIN, VOUT VDD, VDDQ TOPR TSTG TSOLDER PD IOUT Item Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature 1Mega x 32 SGRAM EM637327 Note 1 1 1 1 1 1 1 Rating - 0.3~VDD + 0.3 - 0.3~4.6 0~70 - 55~150 260 1 50 Unit V V °C °C °C W mA Soldering Temperature (10s) Power Dissipation Short Circuit Output Current Recommended D.C. Operating Conditions (Ta = 0~70°C) Symbol VDD VDDQ VIH VIL Parameter Power Supply Voltage Power Supply Voltage(for I/O Buffer) LVTTL Input High Voltage LVTTL Input Low Voltage Min. 3.0 3.0 2.0 - 0.3 Typ. 3.3 3.3 ¡Ð ¡Ð Max. 3.6 3.6 VDD + 0.3 0.8 Unit V V V V Note 2 2 2 2 Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C) Symbol CI CI/O Parameter Input Capacitance Input/Output Capacitance Min. ¡Ð ¡Ð Max. 5 7 Unit pF pF Note: These parameters are periodically sampled and are not 100% tested. Preliminary 19 August 1999 EtronTech 1Mega x 32 SGRAM EM637327 Recommended D.C. Operating Conditions (VDD = 3.3V± 0.3V, Ta = 0~70°C) Description/Test condition Symbol Operating Current 1 bank operation IDD1 tRC ≥ tRC(min), Outputs Open Address changed once during tCK(min). Burst Length = 2 Precharge Standby Current in non-power down mode IDD2N tCK = tCK(min), CS# ≥ VIH, CKE ≥ VIH(min) Input signals are changed once during 30ns. Precharge Standby Current in non-power down mode IDD2NS tCK = ∞, CKE ≥ VIH(min), Input signals are stable. Precharge Standby Current in power down mode IDD2P tCK = tCK(min), CKE ≤ VIL(max) Precharge Standby Current in power down mode IDD2PS tCK = ∞, CKE ≤ VIL(max) Active Standby Current in power down mode IDD3P CKE ≤ VIL(max), tCK = tCK(min) Active Standby Current in non-power down mode IDD3N CKE ≥ VIH(min), tCK = tCK(min) Operating Current (Burst mode) IDD4 tCK=tCK(min), Outputs Open, Multi-bank interleave,gapless data Refresh Current IDD5 tRC ≥ tRC(min) Self Refresh Current IDD6 CKE ≤ 0.2V Operating Current (Block Write) IDD7 tCK = tCK(min), Outputs Open, tBWC = tBWC(min). Min - 5/6/7/8 Max. Unit Note 3 200/180/160/150 30 15 2 2 3 50 290/260/230/200 200/180/160/150 2 230/200/170/150 mA 3 3 3 3, 4 3 Parameter IIL IOL VOH VOL Description Input Leakage Current ( 0V ≤ VIN ≤ VDD, All other pins not under test = 0V ) Output Leakage Current Output disable, 0V ≤ VOUT ≤ VDDQ) LVTTL Output "H" Level Voltage ( IOUT = -2mA ) LVTTL Output "L" Level Voltage ( IOUT = 2mA ) Min. -5 -5 2.4 ¡Ð Max. 5 5 ¡Ð 0.4 Unit Note µA µA V V Preliminary 20 August 1999 EtronTech Symbol A.C. Parameter 1Mega x 32 SGRAM EM637327 Electrical Characteristics and Recommended A.C. Operating Conditions (VDD = 3.3V± 0.3V, Ta = 0~70° C) (Note: 5, 6, 7, 8) - 5/6/7/8 Min. Max. Unit Note tRC tRCD tRP tRRD tRAS tWR tCK1 tCK2 tCK3 tCH tCL tAC1 tAC2 tAC3 tCCD tOH tLZ tHZ tIS tIH tSRX tPDE tRSC tBWC tBPL tREF Row cycle time (same bank) RAS# to CAS# delay (same bank) Precharge to refresh/row activate command (same bank) Row activate to row activate delay (different banks) Row activate to precharge time (same bank) Write recovery time CL* = 1 Clock cycle time Clock high time Clock low time Access time from CLK (positive edge) CAS# to CAS# Delay time Data output hold time Data output low impedance Data output high impedance Data/Address/Control Input set-up time Data/Address/Control Input hold time Minimum CKE "High" for SelfRefresh exit PowerDown Exit set-up time (Special) Mode Register Set Cycle time Block Write Cycle time Block Write to Precharge command period Refresh time CL* = 1 CL* = 2 CL* = 3 CL* = 2 CL* = 3 55/60/63/72 15/18/21/24 15/18/21/24 10/12/14/16 25/30/35/40 5/6/7/8 -/18/21/24 -/9/10/12 5/6/7/8 2/2/2.5/3 2/2/2.5/3 -/16/19/22 -/7/8/10 4.5/5.5/5.5/6 1 2 1/1/1/2 3/4/5/6 1.5 1 5/6/7/8 3/4/5/6 5/6/7/8 10/12/14/16 10/12/14/16 32 ms ns Cycle 100,000 ns 9 9 9 9 9 10 11 11 11 10 8 11 11 11 9 * CL is CAS# Latency. Preliminary 21 August 1999 EtronTech Note: 1Mega x 32 SGRAM EM637327 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 4. These parameters depend on the output loading. Specified values are obtained with the output open. 5. Power-up sequence is described in Note 10. 6. A.C. Test Conditions LVTTL Interface Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signals Reference Level of Input Signals 3 .3V 1.2k Ω 1.4V / 1.4V Reference to the Under Output Load (B) 2.4V / 0.4V 1ns 1.4V 1 .4V 50Ω Z0= 5 0 Ω Output 30pF 87 0 Ω Output 30pF LVTTL D.C. Test Load (A) LVTTL A.C. Test Load (B) 7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed slope (1 ns). 8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels. 9. These parameters account for the number of clock cycle and depend on the operating frequency of the clock as follows: the number of clock cycles = specified value of timing/Clock cycle time (count fractions as a whole number) 10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter. 11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [ ( tR + tF ) / 2 -1] ns should be added to the parameter. Preliminary 22 August 1999 EtronTech 12. Power up Sequence 1Mega x 32 SGRAM EM637327 Power up must be performed in the following sequence. 1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time. 2) After power-up, a pause of 200µseconds minimum is required. Then, it is recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance. 3) Both banks must be precharged. 4) Mode Register Set command must be asserted to initialize the Mode register. 5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device. Preliminary 23 August 1999 EtronTech Timing Waveforms 1Mega x 32 SGRAM EM637327 Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T 15 T16 T 17 T18 T19 T20 T21 T22 tCH CKE tCL t IS t IS t IH tCK2 Begin AutoPrecharge Bank A Begin AutoPrecharge Bank B t IS CS# RAS# CA S# WE# DSF BS tIH A8 RAx RBx RAy RAz RBy t IS A0 -A7 RBx CAx RBx CBx RAy CAy RAz RBy DQM tRCD Hi-Z tRC Ax0 Ax1 Ax2 Ax3 tDAL Bx0 Bx1 Bx2 t IS Bx3 Ay0 t IH Ay1 Ay2 tWR Ay3 tRP tRRD DQ Activate Write with Activate Write with Activate Command AutoPrecharge Command AutoPrecharge Command Bank A Command Bank B Command Bank A Bank A Bank B Write Command Bank A Precharge Command Bank A Activate Command Bank A Activate Command Bank B Preliminary 24 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 1Mega x 32 SGRAM EM637327 T11 T12 T13 Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2) T6 T7 T8 T9 T10 tCH tCL CKE tCK2 t IS Begin AutoPrecharge Bank B t IS CS# tIH t IH RA S# CA S# WE# DSF BS t IH A8 RAx RBx RAy t IS A0 - A7 RAx CAx RBx CBx RAy tRRD tRAS DQM Hi-Z DQ tRC tRCD tAC2 tLZ Ax0 Ax1 Bx0 Bx1 tAC2 tHZ tRP tOH Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Precharge Command Bank A t HZ Activate Command Bank A Preliminary 25 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CA S# WE# DSF BS A8 RAx A0~A7 RAx CAx DQM tRP tRC tRC DQ Ax0 Ax1 Ax2 Ax3 PrechargeAll AutoRefresh Command Command AutoRefresh Command Activate Command Bank A Read Command Bank A Preliminary 26 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 1Mega x 32 SGRAM EM637327 Figure 4. Power on Sequene and Auto Refresh (CBR) T10 T11 T12 T13 T14 T15 T16 T 17 T18 T19 T20 T21 T22 tCK2 CKE High level is reauired Minimum of 2 Refresh Cycles are required CS# RAS# CAS# WE# DSF BS A8 Address Key A0-A7 DQM tRP DQ Hi-Z tRC PrechargeALL Command Inputs must be stable for 200 µs 1st AutoRefresh Command Mode Register Set Command 2nd Auto Refresh Command Any Command Preliminary 27 August 1999 EtronTech T0 T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 5. Self Refresh Entry & Exit Cycle T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 Clock *Note 1 *Note 2 *Note 4 *Note 3 tRC(min) tSRX *Note 7 CKE tPDE t IS CS# *Note 5 *Note 6 RAS# *Note 8 *Note 8 CA S# BS A0 - A 8 WE # DSF DQM DQ Hi-Z Hi-Z Self Refresh Enter SelfRefresh Exit AutoRefresh Note: To Enter SelfRefresh Mode 1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in SelfRefresh mode as long as CKE stays "low". Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh. Note: To Exit SelfRefresh Mode 4. System clock restart and be stable before returning CKE high. 5. Enable CKE and CKE should be set high for minimum time of tSRX. 6. CS# starts from high. 7. Minimum tRC is required after CKE going high to complete SelfRefresh exit. 8. 1024 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses burst refresh. Preliminary 28 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 1Mega x 32 SGRAM EM637327 Figure 6.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=1) T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CA S# WE# DSF BS A8 RAx A0- A7 RAx CAx DQM tHZ DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Read Command Bank A Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Preliminary 29 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 6.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T 15 T16 T 17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CA S# WE# DSF BS A8 RAx A0 -A7 RAx CAx DQM t HZ DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Read Command Bank A Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Preliminary 30 August 1999 EtronTech T0 CLK T1 T 2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 6.3. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T 15 T16 T 17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CA S# WE# DSF BS A8 RAx A0 -A7 RAx CAx DQM tHZ DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Read Command Bank A Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Preliminary 31 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 1Mega x 32 SGRAM EM637327 Figure 7.1. Clock Suspension During Burst Write (Using CKE) (Burst Length = 4, CAS# Latency = 1) T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CA S# WE# DSF BS A8 RAx A0- A7 RAx CAx DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 Activate Clock Suspend Clock Suspend Command 1 Cycle 2 Cycles Bank A Write Command Bank A Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Preliminary 32 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 7.2. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T 15 T16 T 17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CA S# WE# DSF BS A8 RAx A0 -A7 RAx CAx DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 Activate Command Bank A Clock Suspend Clock Suspend 1 Cycle 2 Cycles Write Command Bank A Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Preliminary 33 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 7.3. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T 15 T16 T 17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CA S# WE# DSF BS A8 RAx A0- A7 RAx CAx DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 Activate Command Bank A Clock Suspend Clock Suspend 1 Cycle 2 Cycles Write Command Bank A Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Preliminary 34 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 8. Power Down Mode and Clock Mask (Burst Lenght=4, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T 15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE t IS tPDE Valid CS# RAS# CA S# WE# BS A8 RAx A0~A7 RAx CAx DQM tHZ Hi-Z DQ ACTIVE STANDBY Activate Read Command Command Bank A Bank A Power Down Power Down Mode Entry Mode Exit Ax0 Ax1 Ax2 Ax3 PRECHARGE STANDBY Clock Mask Start Clock Mask End Precharge Command Bank A Power Down Mode Entry Power Down Mode Exit Any Command Preliminary 35 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 9.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=1) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CA S# WE# DSF BS A8 RAw RAz A0~A7 RAw CAw CAx CAy RAz CAz DQ M DQ Hi-Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3 Activate Command Bank A Read Command Bank A Read Command Bank A Read Command Bank A Precharge Read Command Command Bank A Bank A Activate Command Bank A Preliminary 36 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 9.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CA S# WE# DSF BS A8 RAw RAz A0~A7 RAw CAw CAx CAy RAz CAz DQ M DQ Hi-Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3 Activate Command Bank A Read Command Bank A Read Command Bank A Read Command Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A Preliminary 37 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 9.3. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CA S# WE# DSF BS A8 RAw RAz A0~A7 RAw CAw CAx CAy RAz CAz DQ M DQ Hi-Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Activate Command Bank A Read Command Bank A Read Command Bank A Read Command Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A Preliminary 38 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 10.1. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=1) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CA S# WE# DSF BS A8 RBw RBz A0~A7 RBw CBw CBx CBy RBz CBz DQ M DQ Hi-Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3 Activate Command Bank A Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank B Activate Command Bank B Write Command Bank B Preliminary 39 August 1999 EtronTech 1Mega x 32 SGRAM EM637327 Figure 10.2. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=2) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CA S# WE# DSF BS A8 RBw RBz A0~A7 RBw CBw CBx CBy RBz CBz DQ M DQ Hi-Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3 Activate Command Bank A Write Command Bank B Write Command Bank B Write Command Bank B Precharge Command Bank B Activate Command Bank B Write Command Bank B Preliminary 40 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 10.3. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T 15 T16 T 17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CA S# WE# DSF BS A8 RBw RBz A0~A7 RBw CBw CBx CBy RBz CBz DQ M DQ Hi-Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 Activate Command Bank A Write Command Bank B Write Command Bank B Write Command Bank B Precharge Command Bank B Activate Command Bank B Write Command Bank B Preliminary 41 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 11.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=1) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE High CS# RAS# CA S# WE# DSF BS A8 RBx RAx RBy A0~A7 RBx CBx RAx CAx RBy CBy tRCD DQ M Hi-Z Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1 By2 tAC1 tRP DQ Activate Command Bank B Read Command Bank B Activate Precharge Command Command Bank A Bank B Activate Read Command Command Bank B Bank A Read Command Bank B Precharge Command Bank A Preliminary 42 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 11.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CA S# WE# DSF BS A8 RBx RAx RBy A0~A7 RBx CBx RAx CAx RBy CBy tRCD DQ M tAC2 tRP DQ Hi-Z Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1 Activate Command Bank B Read Command Bank B Activate Command Bank A Precharge Command Bank B Read Command Bank A Activate Command Bank B Read Command Bank B Preliminary 43 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 11.3. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE High CS# RAS# CA S# WE# DSF BS A8 RBx RAx RBy A0~A7 RBx CBx RAx CAx RBy CBy tRCD DQ M tAC3 tRP DQ Hi-Z Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 Activate Command Bank B Read Command Bank B Activate Command Bank A Read Command Bank A Precharge Command Bank B Activate Command Bank B Read Command Bank B Precharge Command Bank A Preliminary 44 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 12.1. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=1) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RBx RAy A0~A7 RAx CAx RBx CBx RAy CAy tRCD DQ M tRP t WR DQHi-Z DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Precharge Command Bank B Write Command Bank A Preliminary 45 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 12.2. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RBx RAy A0~A7 RAx CAx RBx CBx RAy CAy DQ M tRCD tWR* tRP tWR* DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B * tWR > tWR(min.) Preliminary 46 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 12.3. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RBx RAy A0~A7 RAx CAx RBx CBx RAy CAy tRCD DQ M tWR* tRP tWR* DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B * tWR > tWR(min.) Preliminary 47 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CA S# WE# DSF BS A8 RAx A0~A7 RAx CAx CAy CAz DQ M DQ Hi-Z Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az3 Activate Command Bank A Read Command Bank A Read Write The Write Data Command is Masked with a Command Bank A Bank A Zero Clock Latency The Read Data is Masked with a Two Clock Latency Precharge Command Bank B Preliminary 48 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CA S# WE# DSF BS A8 RAx A0~A7 RAx CAx CAy CAz DQ M DQ Hi-Z Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az3 Activate Command Bank A Read Command Bank A Write The Write Data Command is Masked with a Bank A Zero Clock Latency Read Command Bank A The Read Data is Masked with a Two Clock Latency Preliminary 49 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 13.3. Read and Write Cycle (Burst Length=4, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CA S# WE# DSF BS A8 RAx A0~A7 RAx CAx CAy CAz DQ M DQ Hi-Z Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az3 Activate Command Bank A Read Command Bank A Write The Write Data Read Command is Masked with a Command Bank A Zero Clock Bank A Latency The Read Data is Masked with a Two Clock Latency Preliminary 50 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1) T9 T10 T11 T12 T13 T14 T 15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CA S# WE# DSF BS A8 RAx RBw A0~A7 RAx RAx RBw CBw CBx CBy CAy CBz DQM DQ Hi-Z tRCD tAC1 Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B Read Command Bank B Read Command Bank B Read Command Bank A Read Command Bank B Precharge Command Bank A Precharge Command Bank B Preliminary 51 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CA S# WE# DSF BS A8 RAx RAx A0~A7 RAx CAy RAx CBw CBx CBy CAy CBz DQ M tRCD tAC2 DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B Read Command Bank B Read Command Bank B Read Command Bank A Read Command Bank B Precharge Command Bank A Precharge Command Bank B Preliminary 52 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T 15 T16 T 17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CA S# WE# DSF BS A8 RAx RBx A0~A7 RAx CAx RBx CBx CBy CBz CAy DQ M tRCD tAC3 DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 By0 By1 Bz0 Bz1 Ay0 Ay1 Ay2 Ay3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B Read Command Bank B Read Command Bank B Read Prechaerge Command Command Bank A Bank B Precharge Command Bank A Preliminary 53 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1) T9 T10 T11 T12 T13 T14 T 15 T16 T 17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CA S# WE# DSF BS A8 RAx RBw A0~A7 RAx CAx RBw CBw CBx CBy CAy CBz tRP DQM tRCD tRRD tWR tRP DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 Activate Activate Command Command Bank A Bank B Write Command Bank A Write Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B Preliminary 54 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T15 T16 T 17 T18 T19 T20 T21 T22 tCK2 CKE CS# RA S# CA S# WE# DSF BS A8 RAx RBw A0~A7 RAx CAx RBw CBw CBx CBy CAy CBz DQM tRCD tRRD tRP t WR tRP DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B Preliminary 55 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CA S# WE# DSF BS A8 RAx RBw A0~A7 RAx CAx RBw CBw CBx CBy CAy CBz DQ M tRCD tRRD > tRRD(min) tWR tRP tWR(min) DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 Activate Command Bank A Activate Command Bank B Write Command Bank A Write Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B Preliminary 56 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=1) T9 T10 T11 T12 T13 T14 T 15 T16 T 17 T18 T19 T20 T21 T22 tCK1 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RBx RBy RBz A0~A7 RAx CAx RBx CBx CAy RBy CBy RBz CBz DQ M DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3 Bz0 Bz1 Bz2 Bz3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Activate Command Bank B Read with Auto Precharge Command Bank A Read with Auto Precharge Command Bank B Activate Command Bank B Read with Auto Precharge Command Bank B Preliminary 57 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CA S# DSF WE# BS A8 RAx RBx RBy RAz A0~A7 RAx CAx RBx CBx RAy RBy CBy RAz CAz DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3 Az0 Az1 Az2 Activate Command Bank A Read Command Bank A Activate Read with Command Auto Precharge Bank B Command Bank B Read with Activate Read with Activate Read with Auto Precharge Command Auto Precharge Command Auto Precharge Command Bank B Command Bank A Command Bank A Bank B Bank A Preliminary 58 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 16.3. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T 15 T16 T 17 T18 T19 T20 T21 T22 tCK3 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RBx RBy A0~A7 RAx CAx RBx CBx CAy RBy CBy DQ M DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3 Activate Command Bank A Activate Command Bank B Read Command Bank A Read with Auto Precharge Command Bank B Read with Auto Precharge Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Preliminary 59 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=1) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RBx RBy RAz A0~A7 RAx CAx RBx CBx CAy RBy CBy RAz CAz DQ M DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3 DAz0 DAz0 DAz0 DAz0 Activate Command Bank A Write Command Bank A Write with Activate Command Auto Precharge Command Bank B Bank B Write with Auto Precharge Command Bank A Write with Activate Command Auto Precharge Command Bank B Bank B Activate Command Bank A Write with Auto Precharge Command Bank A Preliminary 60 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RBx RBy RAz A0~A7 RAx CAx RBx CBx CAy RBy CBy RAz CAz DQ M DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3 Activate Command Bank A Write Command Bank A Activate Write with Command Auto Precharge Bank B Command Bank B Write with Auto Precharge Command Bank A Activate Write with Activate Write with Command Auto Precharge Command Auto Precharge Bank B Command Bank A Command Bank B Bank A Preliminary 61 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 17.3. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T 15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE CS# High RAS# CA S# WE# DSF BS ` A8 RAx RBx RBy A0~A7 RAx CAx RBx CBx CAy RBy CBy DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3 Activate Command Bank A Activate Command Bank B Write Command Bank A Write with Auto Precharge Command Bank B Write with Auto Precharge Command Bank A Activate Command Bank B Write with Auto Precharge Command Bank B Preliminary 62 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=1) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RBx RBy A0~A7 RAx CAx RBx CBx RBy DQ M tRRD tRP DQ Hi-Z Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Bx+7 Activate Activate Command Command The burst counter wraps Bank A Bank B from the highest order page address back to zero Read during this time interval Command Bank A Read Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Precharge Command Bank B Burst Stop Activate Command Command Bank B Preliminary 63 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T 15 T16 T 17 T18 T19 T20 T21 T22 tCK2 CKE CS# High RAS# CA S# WE# DSF BS A8 RAx RBx RBy A0~A7 RAx CAx RBx CBx RBy DQM tRP DQ Hi-Z Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Activate Command Bank A Read Command Bank A Activate Read Precharge Command Command Full Page burst operation does not Command Bank B Bank B terminate when the burst length is satisfied; Bank B The burst counter wraps the burst counter increments and continues from the highest order bursting beginning with the starting address. page address back to zero Burst Stop during this time interval Command Activate Command Bank B Preliminary 64 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 18.3. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RBx RBy A0~A7 RAx CAx RBx CBx RBy DQ M tRP DQ Hi-Z Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Full Page burst operation does not Precharge terminate when the burst length is Command Bank B satisfied; the burst counter increments and continues bursting beginning with the Burst Stop starting address. Command Activate Command Bank B Preliminary 65 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=1) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RBx RBy A0~A7 DQ M RAx CAx RBx CBx RBy DQ Hi-Z DAx DAx+ 1 DAx+ 2 DAx+ 3 DA x- 1 DAx DAx+ 1 DBx DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+ 6 DBx+ 7 Activate Command Bank A Activate Command Bank B The burst counter wraps from the highest order Write page address back to zero Command during this time interval Bank A Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Data is ignored Precharge Command Bank B Burst Stop Activate Command Command Bank B Preliminary 66 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RBx RBy A0~A7 RAx CAx RBx CBx RBy DQ M DQ Hi-Z DAx DAx+ 1 DAx+ 2 DAx+ 3 DA x- 1 DAx DAx+ 1 DBx DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+ 6 Activate Command Bank A Write Command Bank A Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Data is ignored Precharge Command Bank B Burst Stop Command Activate Command Bank B Preliminary 67 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RBx RBy A0~A7 RAx CAx RBx CBx RBy DQ M Data is ignored DQ Hi-Z DAx DAx+ 1 DAx+ 2 DAx+ 3 DA x- 1 DAx DAx+ 1 DBx DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 Activate Command Bank A Write Command Bank A Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Precharge Command Bank B Burst Stop Command Activate Command Bank B Preliminary 68 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 1Mega x 32 SGRAM EM637327 Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency=2) T8 T9 T10 T11 T12 T13 T14 T 15 T16 T 17 T18 T19 T20 T21 T22 tCK2 CKE High C S# RAS# C A S# WE # DSF BS A8 RAx A0 ~A7 RAx CAx CAy CAz DQM0 DQM1~3 DQ0 - DQ7 Ax0 Ax1 Ax2 DAy1 DAy2 Az1 Az2 DQ8 - DQ31 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az2 Az3 Activate Command Bank A Read Upper 3 Bytes Lower Byte Command are masked is masked Bank A Write Upper 3 Bytes Read Command are masked Command Bank A Bank A Lower Byte is masked Lower Byte is masked Preliminary 69 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 1Mega x 32 SGRAM EM637327 Figure 21. Burst Read and Single Write Operation (Burst Length=4, CAS# Latency=2) T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx A0~A7 RAx CAx CAw CAx CAy CAz DQM0 DQM1~3 Hi-Z DQ0 - DQ7 Ax0 Ax1 Ax2 Ax3 DQw0 Ay0 Ay1 Ay3 Az0 Hi-Z DQ8 - DQ31 Ax0 Ax1 Ax2 Ax3 DQw0 DQx0 Ay0 Lower Byte is masked Lower Byte is masked Ay2 Ay3 Az0 Activate Command Bank A Read Command Bank A Single Write Single Write Command Command Bank A Bank A Read Command Bank A Single Write Command Bank A Lower Byte is masked Preliminary 70 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 1Mega x 32 SGRAM EM637327 Figure 22. Full Page Burst Read and Single Write Operation (Burst Length=Full Page, CAS# Latency=3) T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE High CS# RAS# CA S# WE# DSF BS A8 RAv A0~A7 RAv CAv CAw CAx CAy DQM0 DQM1~3 DQ0 - DQ7 Av0 Av1 Av2 Av3 DQw0 DQx0 Ay0 Ay1 Ay2 Ay3 DQ8 - DQ31 Av0 Av1 Av2 Av3 DQw0 DQx0 Ay0 Ay1 Ay2 Ay3 Activate Command Bank A Read Command Bank A Burst Stop Command Single Write Single Write Command Command Bank A Bank A Read Command Bank A Burst Stop Command Preliminary 71 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 23. Random Row Read (Interleaving Banks) (Burst Length=2, CAS# Latency=1) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE High Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A CS# RAS# CA S# WE# DSF BS A8 RBu RAu RBv RAv RBw RAw RBx RAx RBy RAy RBz RAz A0~A7 RBu CBu RAu CAu RBv CBv RAv CAv RBw CBw RAw CAw RBx CBx RAx CAx RBy CBy RAy CAy RBz CBz RAz DQM t RP tRP t RP t RP tRP tRP tRP tRP tRP t RP DQ Bu0 Bu1 Au0 Au1 Bv0 Bv1 Av0 Av1 Bw0 Bw1 Aw0 Aw1 Bx0 Bx1 Ax0 Ax1 By0 By1 Ay0 Ay1 Bz0 Activate Command Bank B Activate Activate Activate Activate Activate Activate Activate Activate Activate Activate Activate Command Command Command Command Command Command Command Command Command Command Command Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Read Read Read Read Read Read Read Read Read Read Read Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Preliminary 72 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 24. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CA S# WE# DSF BS A8 RAx RBx RBw A0~A7 RAx RBx CAx CBx CAy CBy CAz CBz RBw tRP DQM tRRD DQ tRCD Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2 Activate Command Bank A Activate Command Bank B Read Command Bank B Read Read Command Command Bank A Bank A Read Command Bank B Read Command Bank A Read Command Bank B Precharge Command Bank B (Precharge Temination) Activate Command Bank B Preliminary 73 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 25. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CA S# WE# DSF BS A8 RAx RBx RBw A0~A7 RAx RBx CAx CBx CAy CBy CAz CBz RBw t WR DQ M tRP tRRD DQ tRCD DAx0 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2 Activate Command Bank A Activate Write Command Command Bank B Bank B Write Write Command Command Bank A Bank A Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank B (Precharge Temination) Write Data is masked Activate Command Bank B Preliminary 74 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 26.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CA S# WE# DSF BS A8 RAx RAy RAz A0~A7 RAx CAx RAy CAy RAz CAz t WR tRP DQ M tRP Precharge Termination of a Read Burst. DQ DAx0 DAx1 DAx2 DAx3 DAx4 Ay0 Ay1 Ay2 DAz0 DAz1 DAz2 DAz3 DAz4 DAz5 DAz6 DAz7 Activate Precharge Termination Command of a Write Burst. Bank A Write data is masked. Write Command Bank A Read Precharge Command Command Bank A Bank A Activate Command Bank A Precharge Write Command Command Bank A Bank A Activate Command Bank A Preliminary 75 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 26.2. Precharge Termination of a Burst (Burst Length=8 or Full Page, CAS# Latency=2) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RAy RAz A0~A7 RAx CAx RAy CAy RAz CAz t WR DQ M tRP tRP tRP DQ DAx0 DAx1 DAx2 DAx3 Ay0 Ay1 Ay2 Az0 Az1 Az2 Activate Command Bank A Write Command Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A Precharge Command Bank A Activate Command Bank A Precharge Termination of a Write Burst. Write data is masked. Precharge Read Command Command Bank A Bank A Precharge Termination of a Read Burst Preliminary 76 August 1999 EtronTech T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1Mega x 32 SGRAM EM637327 Figure 26.3. Precharge Termination of a Burst (Burst Length=4, 8 or Full Page, CAS# Latency=3) T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE High CS# RAS# CA S# WE# DSF BS A8 RAx RAy RAz A0~A7 RAx CAx RAy CAy RAz t WR DQ M tRP tRP DQ DAx0 DAx1 Ay0 Ay1 Ay2 Activate Command Bank A Write Command Bank A Write Data is masked Precharge Command Bank A Activate Command Bank A Read Command Bank A Precharge Command Bank A Activate Precharge Termination Command of a Read Burst Bank A Precharge Termination of a Write Burst Preliminary 77 August 1999 EtronTech 1Mega x 32 SGRAM EM637327 100 Pin 14x20 mm Package Outline Drawing Information D D1 (D3) (E3) E1 E A A θ L (L1) PIN #1 SECTION A - A e A A2 SEATING PLANE y b C A1 Packaging Dimensions Unit = mm EM637327Q-XX Symbol A A1 A2 b C D D1 D3 E E1 E3 e L L1 y θ Definition Overall Height Stand Off Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Reference Terminal Dimension Package Body Reference Lead Pitch Foot Length Lead Length Coplanarity Lead Angle min 0.25 2.60 0.22 0.13 22.95 19.90 16.95 13.90 normal max 3.40 3.00 0.38 0.23 23.45 20.10 17.45 14.10 EM637327TQ-XX min 0.05 1.35 0.22 0.09 21.90 19.90 15.90 13.90 normal 0.10 1.40 0.32 22.00 20.00 18.85 REF. 16.00 14.00 12.35 REF. 0.65 REF. 0.60 1.00 REF. max 1.60 0.15 1.45 0.38 0.20 22.10 20.10 16.10 14.10 0.65 2.80 0.30 0.15 23.20 20.00 18.85 REF. 17.20 14.00 12.35 REF. 0.65 REF. 0.80 1.60 REF. 0.95 0.10 7.00° 0.45 0.75 0.10 7.00° 0.00° 0.00° Preliminary 78 August 1999