EM63A165TS-6G

EtronTech EM63A165 16Mega x 16 Synchronous DRAM (SDRAM) (Rev 1.1, Apr., 2007) Pin Assignment (Top View) Features • • • • • • • • • • • • Fast access time from clock: 5/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation Internal pipelined architecture 4M word x 16-bit x 4-bank Programmable Mode registers - CAS# Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function Auto Refresh and Self Refresh 8192 refresh cycles/64ms CKE power down mode Single +3.3V power supply Interface: LVTTL 54-pin 400 mil plastic TSOP II Lead-free package VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD DQML /WE /CAS /RAS /CS BA0 BA1 A10(AP) A0 A1 A2 A3 VDD Overview The EM63A165 SDRAM is a high-speed CMOS synchronous DRAM containing 256 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM63A165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC DQMU CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS Key Specifications - 6/7 EM63A165 tCK3 tAC3 tRAS tRC Clock Cycle time(min.) 6/7 ns Access time from CLK(max.) 5/5.4 ns Row Active time(min.) 42/45 ns Row Cycle time(min.) 60/63 ns Ordering Information Part Number Frequency Package EM63A165TS-6G 166MHz TSOP II EM63A165TS-7G 143MHz TSOP II Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech EM63A165 Block Diagram CLOCK CLOCK CLOCL BUFFER CKE De co der CS# RAS# CAS# WE# UDQM LDQM COMMAND DECODER CONTROL SIGNAL GENERATOR Column Decoder COLUMN COUNTER Buffer MODE REGISTER A0 ~ A12 BA0 BA1 4 MX16 CELL ARRAY (BANK #A) De co der ADDRESS BUFFER DQ0 | DQ15 4 MX16 CELL ARRAY (BANK #B) Column Decoder REFRESH COUNTER De co der 4 MX16 CELL ARRAY (BANK #C) Column Decoder De co der 4 MX16 CELL ARRAY (BANK #D) Column Decoder 2 Rev 1.1 Apr. 2007 EtronTech EM63A165 Pin Descriptions Table 1. Pin Details of EM63A165 Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low standby power. BA0,BA1 Input Bank Select: BA0,BA1 input select the bank for operation. BA1 BA0 Select Bank 0 0 BANK #A 0 1 BANK #B 1 0 BANK #C 1 1 BANK #D A0-A12 Input Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge) to select one location out of the 4M available in the respective bank. During a Precharge command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH). The address inputs also provide the op-code during a Mode Register Set command. CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. RAS# Input Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. CAS# Input Column Address Strobe: The CAS# signal defines the operation commands in conjunction with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS# "LOW." Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH." 3 Rev 1.1 Apr. 2007 EtronTech EM63A165 WE# Input Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. LDQM, UDQM Input Data Input/Output Mask: Controls output buffers in read mode and masks Input data in write mode. DQ0-DQ15 Input / Output NC/RFU - VDDQ Supply Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os are maskable during Reads and Writes. No Connect: These pins should be left unconnected. DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V± 0.3V ) VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. (0V) VDD Supply Power Supply: +3.3V ± 0.3V VSS Supply Ground 4 Rev 1.1 Apr. 2007 EtronTech EM63A165 Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command BankActivate State CKEn-1 CKEn DQM BA0,1 A10 A0-9,12 CS# RAS# CAS# WE# Idle(3) H X X V BankPrecharge Any H X X V L PrechargeAll Any H X X X Row address L L H H X L L H L H X L L H L Column address (A0 ~ A8) L H L L L H L L L H L H L H L H L L L L Write Active(3) H X X V L Write and AutoPrecharge Active(3) H X X V H Read Active(3) H X X V L Read and Autoprecharge Active(3) H X X V H Mode Register Set Idle H X X No-Operation Any H X X X X X L H H H Active(4) H X X X X X L H H L Device Deselect Any H X X X X X H X X X AutoRefresh Idle H H X X X X L L L H SelfRefresh Entry Idle H L X X X X L L L H L H X X X X H X X X L H H H H L X X X X X X X X H L X X X X H X X X L H H H Active L H X X X X X X X X Any L H X X X X H X X X L H H H X X X X Active H X H X X X X X X Note: 1. V=Valid X=Don't Care L=Low level H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode. X Burst Stop SelfRefresh Exit Idle (SelfRefresh) Clock Suspend Mode Entry Active Power Down Mode Entry Any(5) Clock Suspend Mode Exit Power Down Mode Exit Column address (A0 ~ A8) OP code (PowerDown) Data Write/Output Enable Active H X Data Mask/Output Disable 5 L X X X Rev 1.1 Apr. 2007 EtronTech EM63A165 Commands 1 BankActivate (RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A12 = Row Address) The BankActivate command activates the idle bank designated by the BA0,1 signals. By latching the row address on A0 to A12 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.) from the time of bank activation. A subsequent BankActivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). The minimum time interval between successive BankActivate commands to the same bank is defined by tRC(min.). The SDRAM has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of the four banks. tRRD(min.) specifies the minimum time required between activating different banks. After this command is used, the Write command and the Block Write command perform the no mask write operation. T0 T1 T2 T3 Tn+3 CLK Tn+4 Tn+5 Tn+6 .............. ADDRESS Bank A Row Addr. Bank A Col Addr. .............. Bank B Row Addr. R/W A with AutoPrecharge .............. Bank B Activate RAS# - RAS# delay time (tRRD) RAS# - CAS# delay (tRCD) COMM AND Bank A Activate NOP NOP Bank A Row Addr. NOP NOP Bank A Activate RAS# Cycle time (tRC) AutoPrecharge Begin : "H" or "L" BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3) 2 BankPrecharge command (RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9, A11 and A12 = Don't care) The BankPrecharge command precharges the bank disignated by BA signal. The precharged bank is switched from the active state to the idle state. This command can be asserted anytime after tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. 3 PrechargeAll command (RAS# = "L", CAS# = "H", WE# = "L", BAs = Don’t care, A10 = "H", A0-A9, A11 and A12 = Don't care) The PrechargeAll command precharges all banks simultaneously and can be issued even if all banks are not in the active state. All banks are then switched to the idle state. 4 Read command (RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A8 = Column Address) The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is issued. During read bursts, the valid data-out element from the starting column address will be available following the CAS# latency after the issue of the Read command. Each subsequent data-out element will be valid by the next positive clock edge (refer to the following figure). The DQs go into high-impedance at the end of the burst unless other command is initiated. The burst length, burst sequence, and CAS# latency are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). 6 Rev 1.1 Apr. 2007 EtronTech T0 T1 EM63A165 T2 T3 T4 T5 T6 T7 NOP NOP NOP NOP T8 CLK COMMAND READ A NOP NOP DOUT A0 CAS# latency=2 tCK2, DQ's DOUT A1 DOUT A2 DOUT A0 CAS# latency=3 tCK3, DQ's NOP NOP DOUT A3 DOUT A1 DOUT A2 DOUT A3 Burst Read Operation(Burst Length = 4, CAS# Latency = 2, 3) The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function may be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read command can occur on any clock cycle following a previous Read command (refer to the following figure). T0 T1 T2 T3 T4 T5 T6 T7 NOP NOP NOP NOP DOUT B2 DOUT B3 T8 CLK COMMAND READ A READ B CAS# latency=2 tCK2, DQ's NOP DOUT A0 CAS# latency=3 tCK3, DQ's DOUT B0 DOUT A0 DOUT B1 DOUT B0 DOUT B1 NOP DOUT B2 NOP DOUT B3 Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with high-impedance on the DQ pins must occur between the last read data and the Write command (refer to the following three figures). If the data output of the burst read occurs at the second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the Write command to avoid internal bus contention. T0 T1 T2 NOP READ A NOP T3 T4 T5 T6 T7 T8 NOP NOP CLK DQM COMMAND NOP NOP DQ's NOP DOUT A0 Must be Hi-Z before the Write Command WRITE B DINB 0 DINB1 DINB 2 : "H" or "L" Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 3) 7 Rev 1.1 Apr. 2007 EtronTech T0 T1 EM63A165 T2 T3 T4 CLK T5 T6 T7 T8 1 Clk Interval DQM COMMAND NOP NOP BANKA ACTIVATE READ A NOP CAS# latency=2 tCK2, DQ's WRITE A NOP DIN A0 DIN A1 NOP NOP DIN A2 DIN A3 : "H" or "L" Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND NOP NOP READ A NOP NOP CAS# latency=2 tCK2, DQ's WRITE B NOP DIN B0 DIN B1 NOP NOP DIN B2 DIN B3 : "H" or "L" Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 2) A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank. The following figure shows the optimum time that BankPrecharge/ PrechargeAll command is issued in different CAS# latency. T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK ADDRESS Bank, Col A Bank, Row Bank(s) tRP COMMAND CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's READ A NOP NOP DOUT A0 NOP Precharge NOP DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 NOP Activate NOP DOUT A3 Read to Precharge (CAS# Latency = 2, 3) 5 Read and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A8 = Column Address) 8 Rev 1.1 Apr. 2007 EtronTech 6 EM63A165 The Read and AutoPrecharge command automatically performs the precharge operation after the read operation. Once this command is given, any subsequent command cannot occur within a time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge function is ignored. Write command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A8 = Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is issued. During write bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). The DQs remain with high-impedance at the end of the burst unless another command is initiated. The burst length and burst sequence are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). T0 T1 T2 T3 T4 T5 T6 T7 T8 WRITE A NOP NOP NOP NOP NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 don't care CLK COM M AND NOP DQ0 - DQ3 The first data element and the write are registered on the same clock edge. Extra data is masked. Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3) A write burst without the auto precharge function may be interrupted by a subsequent Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from Write command can occur on any clock cycle following the previous Write command (refer to the following figure). T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP NOP NOP NOP NOP NOP DIN B1 DIN B2 DIN B3 CLK COM MAND NOP WRITE A WRITE B 1 Clk Interval DQ's DIN A0 DIN B0 Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3) The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). Once the Read command is registered, the data inputs will be ignored and writes will not be executed. 9 Rev 1.1 Apr. 2007 EtronTech T0 T1 EM63A165 T2 T3 T4 T5 T6 T7 T8 NOP NOP NOP CLK COMMAND NOP WRITE A READ B CAS# latency=2 tCK2, DQ's DIN A0 don't care CAS# latency=3 tCK3, DQ's DIN A0 don't care NOP NOP NOP DOUT B0 don't care DOUT B1 DOUT B0 DOUT B2 DOUT B1 DOUT B3 DOUT B2 DOUT B3 Input data must be removed from the DQ's at least one clock cycle before the Read data appears on the outputs to avoid data contention. Input data for the write is masked. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) 10 Rev 1.1 Apr. 2007 EtronTech EM63A165 The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure). T0 T1 T2 T3 T4 T5 T6 CLK DQM tRP COMMAND WRITE ADDRESS BANK COL n Precharge NOP NOP NOP Activate BANK (S) NOP ROW tWR DIN n DQ DIN n+ 1 : don't care Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2. Write to Precharge 7 Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H", A0-A8 = Column Address) The Write and AutoPrecharge command performs the precharge operation automatically after the write operation. Once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in this command and the auto precharge function is ignored. T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Bank A Activate COMMAND NOP NOP Write A AutoPrecharge NOP CAS# latency=2 tCK2, DQ's DIN A0 DIN A1 CAS# latency=3 tCK3, DQ's DIN A0 DIN A1 NOP * * * NOP NOP NOP tDAL tDAL Begin AutoPrecharge Bank can be reactivated at completion of tDAL tDAL= tWR + tRP Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 2, 3) 8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A12 = Register Data) The mode register stores the data for controlling the various operating modes of SDRAM. The Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the Mode register to make SDRAM useful for a variety of different applications. The default values of the Mode Register after power-up are undefined; therefore this command must be issued at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the mode register. One clock cycle is required to complete the write in the mode register (refer to the following figure). The contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state. 11 Rev 1.1 Apr. 2007 EtronTech T0 EM63A165 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCK2 CKE Clock min. CS# RAS# CAS# WE# A11 A10 Address Key A0-A9 DQM DQ tRP Hi-Z PrechargeAll Mode Register Set Command Any Command Mode Register Set Cycle (CAS# Latency = 2, 3) The mode register is divided into various fields depending on functionality. Address BS0,1 A12~10 Function RFU* RFU* A9 A8 A7 WBL 0 0 A6 A5 A4 CAS Latency A3 BT A2 A1 A0 Burst Length *Note: RFU (Reserved for future use) should stay “0” during MRS cycle. 12 Rev 1.1 Apr. 2007 EtronTech EM63A165 • Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8, or full page. A2 A1 A0 Burst Length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Full Page Full Page Length : 512 • Burst Type Field (A3) The Burst Type can be one of two modes, Interleave Mode or Sequential Mode. A3 Burst Type 0 Sequential 1 Interleave --- Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device. The internal column address is varied by the Burst Length as shown in the following table. When the value of column address, (n + m), in the table is larger than 255, only the least significant 8 bits are effective. Data n 0 1 2 3 4 5 6 7 - 255 256 257 - Column Address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 - 2 words: Burst Length 4 words: 8 words: Full Page: Column address is repeated until terminated. --- Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. Data n Column Address Burst Length Data 0 A8 A0 A7 A6 A5 A4 A3 A2 A1 Data 1 A8 A0# A7 A6 A5 A4 A3 A2 A1 Data 2 A8 A0 A7 A6 A5 A4 A3 A2 A1# Data 3 A8 A0# A7 A6 A5 A4 A3 A2 A1# Data 4 A8 A0 A7 A6 A5 A4 A3 A2# A1 13 4 words 8 words Rev 1.1 Apr. 2007 EtronTech EM63A165 Data 5 A8 A0# A7 A6 A5 A4 A3 A2# A1 Data 6 A8 A0 A7 A6 A5 A4 A3 A2# A1# Data 7 A8 A0# A7 A6 A5 A4 A3 A2# A1# • CAS# Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min) ≤ CAS# Latency X tCK A6 A5 A4 CAS# Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 X X Reserved • Write Burst Length (A9) This bit is used to select the burst write length. 9 A9 Write Burst Length 0 Burst 1 Single Bit No-Operation command (RAS# = "H", CAS# = "H", WE# = "H") The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low). This prevents unwanted commands from being registered during idle or wait states. 14 Rev 1.1 Apr. 2007 EtronTech 10 EM63A165 Burst Stop command (RAS# = "H", CAS# = "H", WE# = "L") The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only effective in a read/write burst without the auto precharge function. The terminated read burst ends after a delay equal to the CAS# latency (refer to the following figure). The termination of a write burst is shown in the following figure. T0 T1 T2 T3 NOP NOP T4 T5 T6 T7 T8 NOP NOP NOP NOP CLK COMMAND READ A NOP Burst Stop The burst ends after a delay equal to the CAS# latency. CAS# latency=2 tCK2, DQ's DOUT A0 CAS# latency=3 tCK3, DQ's DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Termination of a Burst Read Operation (Burst Length ＞ 4, CAS# Latency = 2, 3) T0 T1 T2 T3 T4 NOP NOP Burst Stop DIN A1 DIN A2 don't care T5 T6 T7 T8 NOP NOP NOP NOP CLK COMMAND CAS# latency= 2, 3 DQ's NOP WRITE A DIN A0 Input data for the Write is masked. Termination of a Burst Write Operation (Burst Length = X, CAS# Latency = 1, 2, 3) 15 Rev 1.1 Apr. 2007 EtronTech EM63A165 11 Device Deselect command (CS# = "H") The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation command. 12 AutoRefresh command (RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", A0-A12 = Don't care) The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh operation must be performed 8192 times within 64ms. The time required to complete the auto refresh operation is specified by tRC(min.). To provide the AutoRefresh command, all banks need to be in the idle state and the device must not be in power down mode (CKE is high in the previous cycle). This command must be followed by NOPs until the auto refresh operation is completed. The precharge time requirement, tRP(min), must be met before successive auto refresh operations are performed. 13 SelfRefresh Entry command (RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A12 = Don't care) The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for data retention and low power operation. Once the SelfRefresh command is registered, all the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW. The refresh addressing and timing is internally generated to reduce power consumption. The SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command). 14 SelfRefresh Exit command This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh mode. 15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L") When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (64ms) since the command does not perform any refresh operations. 16 Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H") When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active state. tPDE(min.) is required when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end of this command. 17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H") During a write cycle, the DQM signal functions as a Data Mask and can control every word of the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device selection, byte selection and bus control in a memory system. 16 Rev 1.1 Apr. 2007 EtronTech EM63A165 Absolute Maximum Rating Symbol Item Rating Unit Note VIN, VOUT Input, Output Voltage - 0.5 ~ 4.6 V 1 VDD, VDDQ Power Supply Voltage -0.5 ~ 4.6 V 1 TA Operating Temperature 0 ~ 70 °C 1 TSTG Storage Temperature - 65 ~ 150 °C 1 TSOLDER Soldering Temperature (10 second) 260 °C 1 PD Power Dissipation 1 W 1 IOUT Short Circuit Output Current 50 mA 1 Recommended D.C. Operating Conditions (TA = 0~70°C) Symbol Parameter Min. Typ. Max. Unit Note VDD Power Supply Voltage 3.0 3.3 3.6 V 2 VDDQ Power Supply Voltage(for I/O Buffer) 3.0 3.3 3.6 V 2 VIH LVTTL Input High Voltage 2.0 3.0 VDDQ +0.3 V 2 VIL LVTTL Input Low Voltage - 0.3 0 0.8 V 2 Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C) Symbol CI CI/O Parameter Input Capacitance Input/Output Capacitance Min. Max. Unit 2.5 5 pF 4 6.5 pF Note: These parameters are periodically sampled and are not 100% tested. 17 Rev 1.1 Apr. 2007 EtronTech EM63A165 Recommended D.C. Operating Conditions (VDD = 3.3V ± 0.3V, TA = 0~70°C) Description/Test condition Operating Current tRC ≥ tRC(min), Outputs Open One bank active Precharge Standby Current in non-power down mode tCK = tck(min), CS# ≥ VIH(min), CKE ≥ VIH Input signals are changed very 2clks Precharge Standby Current in non-power down mode TCK = ∞, CLK ≤ VIL(max), CKE ≥ VIH Precharge Standby Current in power down mode tCK = tck(min), CKE ≤ VIL(max) Precharge Standby Current in power down mode TCK = ∞, CKE ≤ VIL(max) Active Standby Current in non-power down mode tCK = tck(min), CKE ≥ VIH(min), CS# ≥ VIH(min) Input signals are changed very 2clks Active Standby Current in non-power down mode CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞ Operating Current (Burst mode) tCK =tCK(min), Outputs Open, Multi-bank interleave Refresh Current tRC ≥ tRC(min) Self Refresh Current VIH ≥ VDD - 0.2, 0V ≤ VIL ≤ 0.2V Symbol - 6/7 Max. IDD1 130/130 IDD2N 20 IDD2NS 15 IDD2P 2 IDD2PS 1 IDD3N 30 IDD3NS 20 IDD4 160/160 3, 4 IDD5 160 3 IDD6 3 Unit Note 3 3 3 mA Parameter Description Min. Max. IIL Input Leakage Current ( 0V ≤ VIN ≤ VDD, All other pins not under test = 0V ) - 10 10 µA IOL Output Leakage Current Output disable, 0V ≤ VOUT ≤ VDDQ) - 10 10 µA VOH LVTTL Output "H" Level Voltage ( IOUT = -2mA ) 2.4 － V VOL LVTTL Output "L" Level Voltage ( IOUT = 2mA ) － 0.4 V 18 Unit Note Rev 1.1 Apr. 2007 EtronTech EM63A165 Electrical Characteristics and Recommended A.C. Operating Conditions (VDD = 3.3V±0.3V, TA = 0~70°C) (Note: 5, 6, 7, 8) -6/7 Symbol tRC tRFC tRCD tRP tRRD tRSC tRAS tWR tCK2 tCK3 A.C. Parameter Min. Row cycle time (same bank) Refresh cycle time Unit Note 60/63 60/70 RAS# to CAS# delay (same bank) Precharge to refresh/row activate command (same bank) Row activate to row activate delay (different banks) Mode register set cycle time 15/20 15/20 12/14 12/14 Row activate to precharge time (same bank) Write recovery time Clock cycle time Max. 42/45 120000 12/14 CL* = 2 -/12 CL* = 3 6/7 ns 9 tCH Clock high time 2/2.5 10 tCL Clock low time 2/2.5 10 tAC2 tAC3 Access time from CLK (positive edge) tOH Data output hold time tLZ Data output low impedance 0 tHZ Data output high impedance 2.5/2.7 tIS Data/Address/Control Input set-up time 1.8/1.8 10 tIH Data/Address/Control Input hold time 1 10 tT Transition time of CLK 1 tREF Refresh interval time CL* = 2 -/6.5 CL* = 3 5/5.4 10 2.5/2.7 9 5/5.4 8 10 7.8 µs * CL is CAS# Latency. Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to VSS. Overshoot VIH(Max) = VDD+2.0V for pulse width ≤ 3ns. Undershoot VIL(Min) = -2.0V for pulse width ≤ 3ns. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 4. These parameters depend on the output loading. Specified values are obtained with the output open. 5. Power-up sequence is described in Note 11. 19 Rev 1.1 Apr. 2007 EtronTech EM63A165 6. A.C. Test Conditions LVTTL Interface Reference Level of Output Signals 1.4V / 1.4V Input Signal Levels 2.4V / 0.4V Transition Time (Rise and Fall) of Input Signals 1ns Reference Level of Input Signals 1.4V VOUT 50pF Output Loading 7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed slope (1 ns). 8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels. 9. If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter. 10. Assumed input rise and fall time tT ( tR & tF ) = 1 ns If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 11. Power up Sequence Power up must be performed in the following sequence. 1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time. 2) After power-up, a pause of 200µseconds minimum is required. Then, it is recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance. 3) All banks must be precharged. 4) Mode Register Set command must be asserted to initialize the Mode register. 5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device. 20 Rev 1.1 Apr. 2007 EtronTech EM63A165 Timing Waveforms Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCL tCH tCK2 t IS CKE t IS Begin AutoPrecharge Bank A t IH Begin AutoPrecharge Bank B t IS CS# RAS# CAS# WE# BA0,1 tIH RAx A10 RBx RAy RAz RBy RAz RBy t IS A0-A9,A11 & A12 CAx RBx RBx CBx RAy CAy DQM tRCD DQ tDAL tRC Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 t IS Bx1 Bx2 Activate Write with Activate Write with Activate Command AutoPrecharge Command AutoPrecharge Command Bank A Command Bank B Command Bank A Bank A Bank B 21 tWR tIH Bx3 Ay0 Write Command Bank A Ay1 Ay2 tRP tRRD Ay3 Precharge Command Bank A Activate Command Bank A Activate Command Bank B Rev 1.1 Apr. 2007 EtronTech Figure 2. AC EM63A165 Parameters for Read Timing (Burst Length=2, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 CLK tCK2 tCH tCL CKE Begin AutoPrecharge Bank B t IS tIH t IH t IS CS# RAS# CAS# WE# BA0,1 t IH A10 RBx RAx RAy t IS A0-A9,A11 & A12 RAx CAx CBx RBx tRRD RAy tRAS tRC DQM tAC2 t LZ tRCD Hi-Z DQ tAC2 Ax0 tRP t HZ Ax1 Bx0 t HZ t OH Activate Command Bank A Read Command Bank A Activate Command Bank B 22 Bx1 Read with Auto Precharge Command Bank B Precharge Command Bank A Activate Command Bank A Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9,A11 & A12 RAx DQM tRP tRC CAx tRC Ax0 Ax1 DQ PrechargeAll Command AutoRefresh Command AutoRefresh Command 23 Activate Command Bank A Ax2 Ax3 Read Command Bank A Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 4. Power on Sequence and Auto Refresh (CBR) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High level is reauired Minimum of 2 Refresh Cycles are required CS# RAS# CAS# WE# BA0,1 A10 Address Key A0-A9,A11 & A12 DQM DQ tRP Hi-Z PrechargeALL Command Inputs must be stable for 200 µs 1st AutoRefresh Command Mode Register Set Command tRC 2nd Auto Refresh Command 24 Any Command Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 5. Self Refresh Entry & Exit Cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CLK *Note 2 *Note 4 *Note 1 tRC(min) tPDE *Note 3 CKE *Note 7 tSRX *Note 5 t IS *Note 6 CS# RAS# *Note 8 *Note 8 CAS# BA0,1 A0-A9,A11 & A12 WE# DQM DQ Hi-Z Hi-Z Self Refresh Enter SelfRefresh Exit AutoRefresh Note: To Enter SelfRefresh Mode 1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in SelfRefresh mode as long as CKE stays "low". Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh. To Exit SelfRefresh Mode 1. System clock restart and be stable before returning CKE high. 2. Enable CKE and CKE should be set high for minimum time of tSRX. 3. CS# starts from high. 4. Minimum tRC is required after CKE going high to complete SelfRefresh exit. 5. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses burst refresh. 25 Rev 1.1 Apr. 2007 EtronTech Figure 6.1. EM63A165 Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T 7 T8 T9 T10 T 11 T1 T13 T14 T15 T16 T17 T1 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BA0,1 A10 A0-A9,A11 & A12 RAx RAx CAx DQM tHZ DQ Hi-Z Ax3 Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Clock Suspend Clock Suspend 1 Cycle 2 Cycles Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock 26 Rev 1.1 Apr. 2007 EtronTech Figure 6.2. EM63A165 Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BA0,1 A10 A0-A9,A11 & A12 RAx RAx CAx DQM tHZ DQHi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Clock Suspend 1 Cycle Ax3 Ax2 Clock Suspend 2 Cycles Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock 27 Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 6.3. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=3) T0 T 1 T 2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BA0,1 A10 A0-A9,A11 & A12 RAx RAx CAx DQM tHZ DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Clock Suspend Clock Suspend 2 Cycles 1 Cycle Ax3 Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock 28 Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 7.1. Clock Suspension During Burst Write (Using CKE) (Burst Length = 4, CAS# Latency = 1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9,A11 RAx CAx & A12 DQM DQ Hi-Z DAx0 DAx1 Activate Clock Suspend Command 1 Cycle Bank A Write Command Bank A DAx2 Clock Suspend 2 Cycles DAx3 Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock 29 Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 7.2. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T2 2 CLK tCK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9,A11 & A12 RAx CAx DQM DQ Hi-Z DAx0 Activate Command Bank A DAx1 DAx2 Clock Suspend Clock Suspend 1 Cycle 2 Cycles DAx3 Clock Suspend 3 Cycles Write Command Bank A Note: CKE to CLK disable/enable = 1 clock 30 Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 7.3. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9,A11 RAx & A12 CAx DQM DQ Hi-Z DAx0 Activate Command Bank A DAx1 DAx2 Clock Suspend Clock Suspend 1 Cycle 2 Cycles DAx3 Clock Suspend 3 Cycles Write Command Bank A Note: CKE to CLK disable/enable = 1 clock 31 Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 8. Power Down Mode and Clock Mask (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 tPDE t IS CKE Valid CS# RAS# CAS# WE# BA0,1 RAx A10 RAx A0~A9,A11 CAx & A12 DQM tHZ Hi-Z Ax0 DQ ACTIVE STANDBY Activate Read Command Command Bank A Bank A Power Down Power Down Mode Entry Mode Exit Ax1 Ax2 Clock Mask Start Clock Mask End Ax3 Precharge Command Bank A Power Down Mode Entry 32 PRECHARGE STANDBY Power Down Mode Exit Any Command Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 9.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BA0,1 A10 RAz RAw RAw CAw A0~A9,A11 CAx CAy RAz CAz & A12 DQM DQ Hi-Z Aw0 Activate Command Bank A Read Command Bank A Aw1 Aw2 Aw3Ax0 Read Command Bank A Ax1 Ay0 Ay1 Ay2 Read Command Bank A Ay3 Az0 Az1 Az2 Az3 Precharge Read Command Command Bank A Bank A Activate Command Bank A 33 Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 9.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAz RAw RAw A0~A9,A11 & A12 CAw CAx RAz CAy CAz DQM DQ Hi-Z Aw0 Activate Command Bank A Read Command Bank A Aw1 Aw2 Read Command Bank A Aw3 Ax1 Ay0 Ax0 Read Command Bank A 34 Ay1 Ay2 Az0 Ay3 Precharge Activate Command Command Bank A Bank A Az1 Az2 Az3 Read Command Bank A Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 9.3. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BA0,1 A10 RAz RAw A0~A9,A11 & A12 RAw CAw CAy CAx CAz RAz DQM DQ Hi-Z Aw0 Activate Command Bank A Read Command Bank A Aw1 Aw2 Read Command Bank A Aw3 Read Command Bank A 35 Ax0 Ax1 Ay0 Ay1 Precharge Command Bank A Ay2 Az0 Ay3 Activate Command Bank A Read Command Bank A Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 10.1. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 RBz RBw RBw CBw CBy CBx RBz CBz & A12 DQM DQHi-Z DBw0DBw1DBw2 Activate Command Bank A Write Command Bank B DBw3 DBx0 DBx1 DBy0 DBy1 Write Command Bank A DBy2 DBy3 Write Command Bank B Precharge Command Bank B Activate Command Bank B 36 DBz0 DBz1 DBz2 DBz3 Write Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 10.2. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BA0,1 RBz RBw A10 RBw A0~A9,A11 CBw CBx CBy RBz CBz & A12 DQM DQ Hi-Z DBw0 DBw1DBw2 DBw3 DBx0 DBx1DBy0 DBy1 Activate Command Bank A Write Command Bank B Write Command Bank B Write Command Bank B 37 DBy2 DBy3 Precharge Activate Command Command Bank B Bank B DBz0 DBz1DBz2 DBz3 Write Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 10.3. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BA0,1 A10 RBw A0~A9,A11 & A12 RBw RBz CBw CBx CBy RBz CBz DQM DQ Hi-Z DBz0 DBz1 DBz2 DBw0 DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Activate Command Bank A Write Command Bank B Write Command Bank B Write Command Bank B 38 Precharge Command Bank B Activate Command Bank B Write Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 11.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE High CS# RAS# CAS# WE# BA0,1 RAx RBx A10 RAx RBx CBx A0~A9,A11 RBy CAx CBy tRCD & A12 tRP tAC1 DQM DQ RBy Hi-Z Bx0 Activate Command Bank B Read Command Bank B Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Precharge Command Bank B Activate Read Command Command Bank B Bank A Activate Command Bank A 39 Ax4 Ax5 Ax6 Ax7 By0 Read Command Bank B By1 By2 Precharge Command Bank A Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 11.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BA0,1 RBx A10 RAx RBx A0~A9,A11 & A12 RAx CBx tRCD RBy RBy CAx tAC2 tRP DQM Hi-Z DQ Activate Command Bank B Bx0 Read Command Bank B CBy Bx1 Bx2 Bx3 Bx4 Activate Command Bank A Bx5 Bx6 Bx7 Ax0 Precharge Command Bank B Read Command Bank A 40 Ax1 Activate Command Bank B Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1 Read Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 11.3. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RBx RBx A0~A9,A11 & A12 RAx CBx tRCD RBy RBy CAx tAC3 tRP DQM Hi-Z DQ Activate Command Bank B Bx0 Read Command Bank B CBy Bx1 Bx2 Bx3 Bx4 Bx5 Read Command Bank A Activate Command Bank A 41 Bx6 Bx7 Precharge Command Bank B Ax0 Ax1 Ax2 Activate Command Bank B Ax3 Ax4 Ax5 Ax6 Read Command Bank B Ax7 By0 Precharge Command Bank A Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 12.1. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKEHigh CS# RAS# CAS# WE# BA0,1 A10 RAx A0~A9,A11 & A12 RAx CAx RBx RAy RBx CBx RAy tRCD tRP CAy tWR DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 Activate Command Bank A Write Command Bank A DAy0 DAy1 DAy2 DAy3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3DBx4 DBx5 DBx6 DBx7 Activate Command Bank B Write Command Bank B 42 Precharge Command Bank A Activate Command Bank A Precharge Command Bank B Write Command Bank A Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 12.2. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0~A9,A11 & A12 RAx RAy RBx CAx RBx tRCD RAy CBx tWR* tRP CAy tWR* DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 DAx4DAx5 Activate Write Command Command Bank A Bank A DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1DAy2 Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A DAy3 DAy4 Write Command Bank A Precharge Command Bank B * tWR > tWR(min.) 43 Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 12.3. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BA0,1 A10 RAx A0~A9,A11 & A12 RAx RBx CAx RAy RAy CBx RBx tRCD tWR* CAy tRP tWR* DQM Hi-Z DQ Activate Command Bank A DAx0 DAx1 DAx2 DAx3DAx4 DAx5 Write Command Bank A DAx6 DAx7 DBx0 DBx1DBx2 Activate Command Bank B Write Command Bank B DBx3 DBx4 DBx5 DBx6 DBx7DAy0 Precharge Command Bank A Activate Command Bank A Write Command Bank A DAy1 DAy2 DAy3 Precharge Command Bank B * tWR > tWR(min.) 44 Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx CAx A0~A9,A11 & A12 CAy CAz DQM DQ Hi-Z Ax0 Ax1 Activate Command Bank A Read Command Bank A Ax2 Ax3 DAy0DAy1 DAy3 Az0 Read The Write Data Write Command is Masked with a Command Bank A Zero Clock Bank A Latency 45 Az1 Az3 The Read Data is Masked with a Two Clock Latency Precharge Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0~A9,A11 & A12 RAx CAx CAz CAy DQM DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Write The Write Data Command is Masked with a Bank A Zero Clock Latency 46 Az0 Read Command Bank A Az1 Az3 The Read Data is Masked with a Two Clock Latency Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 13.3. Read and Write Cycle (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0~A9,A11 & A12 RAx CAy CAx CAz DQM DQ Hi-Z Ax0 Activate Command Bank A Ax1 Ax2 Ax3 Read Command Bank A DAy0 DAy1 DAy3 Read Write The Write Data Command is Masked with a Command Bank A Bank A Zero Clock Latency 47 Az0 Az1 Az3 The Read Data is Masked with a Two Clock Latency Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RBw RAx RAx RBw CBw CBx Ax3 Bw0 Bw1 CBy CAy CBz tRCD tAC1 DQM DQ RAx Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Activate Command Bank B Read Command Bank B Bx0 Bx1 Read Command Bank B By0 Read Command Bank B 48 By1 Ay0 Read Command Bank A Ay1 Bz0 Read Command Bank B Bz1 Precharge Command Bank A Bz2 Bz3 Precharge Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0~A9,A11 & A12 RAx DQM RAx CAy tRCD RAx CBy CAy CBz By0 By1 Ay0 tAC2 DQ Hi-Z Ax0 Activate Command Bank A CBx CBw Read Command Bank A Ax1 Ax2 Activate Command Bank B Ax3 Bw0 Read Command Bank B Bw1 Read Command Bank B 49 Bx0 Bx1 Read Command Bank B Read Command Bank A Ay1 Read Command Bank B Precharge Command Bank A Bz0 Bz1 Bz2 Bz3 Precharge Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RAx RBx RAx CAx tRCD DQM RBx CBx CBz CAy tAC3 DQ Hi-Z Ax0 Activate Command Bank A CBy Read Command Bank A Activate Command Bank B Ax1 Ax2 Read Command Bank B Ax3 Bx0 Read Command Bank B 50 Bx1 By0 By1 Read Command Bank B Bz0 Bz1 Ay0 Read Prechaerge CommandCommand Bank A Bank B Ay1 Ay2 Ay3 Precharge Command Bank A Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0~A9,A11 & A12 RAx RBw CAx RBw CBw CBx CBy CBz CAy tRP tWR tRP tRCD DQM tRRD DQ Hi-Z DAx0 Activate Command Bank A DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 Activate Command Bank B Write Command Bank B Write Command Bank B DBy1 DAy0 DAy1 Write Command Bank B Write Command Bank A 51 Write Command Bank A DBz0 DBz1 Write Command Bank B Precharge Command Bank A DBz2 DBz3 Precharge Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0~A9,A11 & A12 RAx DQM RBw CAx RBw CBw CBx CBy CAy tRCD CBz tRP tWR tRP tRRD DQ Hi-Z DAx0DAx1 DAx2 DAx3DBw0 DBw1 DBx0 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B DBx1DBy0 Write Command Bank B 52 DBy1DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RAx RBw RAx CAx RBw CBw CBx CBy CAy tRCD DQM CBz tWR tRP tWR(min) tRRD > tRRD(min) DQ Hi-Z DAx0 DAx1 DAx2 DAx3DBw0 Activate Command Bank A Activate Command Bank B Write Command Bank A DBw1DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 Write Command Bank B Write Command Bank B 53 Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE High CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RAx RAx RBy RBx RBx CBx CAx CAy RBz RBy CBy RBz CBz DQM DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Ax3 Bx0 Activate Command Bank B Read with Auto Precharge Command Bank B Bx1 Bx2 Bx3 Ay0 Ay1 Activate Command Bank B Read with Auto Precharge Command Bank A 54 Ay2 Ay3 By0 Read with Auto Precharge Command Bank B By1 By2 By3 Bz0 Bz1 Bz2 Bz3 Activate Command Bank B Read with Auto Precharge Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RAx RAx RBx CAx RAz RBy RBx CBx RAy RBy CBy RAz CAz DQM DQ Hi-Z Activate Command Bank A Ax0 Read Command Bank A Ax1 Ax2 Ax3 Activate Read with Command Auto Precharge Bank B Command Bank B Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3 Az0 Az1 Az2 Activate Activate Read with Read with Read with Auto Precharge Command Auto Precharge Command Auto Precharge Bank B Bank A Command Command Command Bank A Bank B Bank A 55 Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 16.3. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BA0,1 A10 RAx RBx A0~A9,A11 & A12 RAx CAx RBx RBy CBx CAy CBy RBy DQM DQ Hi-Z Activate Command Bank A Ax0 Activate Command Bank B Read Command Bank A Ax1 Ax2 Read with Auto Precharge Command Bank B Ax3 Bx0 Bx1 Bx2 Read with Auto Precharge Command Bank A 56 Bx3 Ay0 Activate Command Bank B Ay1 By0 By1 Ay2 Ay3 By2 By3 Read with Auto Precharge Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE High CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RAx RBx RAx CAx RBx RBy CBx RBy CAy RAz CBy RAz CAz DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBy1 DBy2 DBy3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1DAy2 DAy3 DBy0 Activate Command Bank A Write Command Bank A Activate Write with Command Auto Precharge Bank B Command Bank B Write with Auto Precharge Command Bank A Activate Write with Command Auto Precharge Bank B Command Bank B 57 DAz0 DAz0 DAz0DAz0 Activate Command Bank A Write with Auto Precharge Command Bank A Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RAx RAx RBy RBx CAx RBx CBx CAy RBy RAz CBy RAz CAz DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 DBx0 DBx1DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 Write Command Bank A Activate Write with Command Auto Precharge Bank B Command Bank B Write with Auto Precharge Command Bank A 58 DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3 Write with Activate Activate Write with Command Auto Precharge Command Auto Precharge Command Bank B Bank A Command Bank A Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 17.3. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# ` BA0,1 A9 RAx RBx A0~A9,A11 & A12 RAx CAx RBx RBy CBx CAy RBy CBy DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 Activate Command Bank B Write Command Bank A Write with Auto Precharge Command Bank B Write with Auto Precharge Command Bank A 59 Activate Command Bank B DBy0 DBy1 DBy2DBy3 Write with Auto Precharge Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE High CS# RAS# CAS# WE# BA0,1 RAx A10 A0~A9,A11 & A12 RAx RBx CAx RBy RBx RBy CBx tRP tRRD DQM Hi-Z DQ Ax Ax+1 Ax+2 Ax-2 Ax-1 Activate Command Bank B The burst counter wraps from the highest order Read page address back to zero Command during this time interval Bank A Activate Command Bank A Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Read Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. 60 Bx+6 Bx+7 Precharge Command Bank B Burst Stop Activate Command Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BA0,1 RBx RAx A10 RAx A0~A9,A11 & A12 CAx RBy CBx RBx RBy tRP DQM DQ Hi-Z Activate Command Bank A Ax Read Command Bank A Ax+1 Ax+2Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4Bx+5 Bx+6 Activate Read Precharge Full Page burst operation does not Command Command Command Bank B Bank Bterminate when the burst length is satisfied; Bank B The burst counter wraps the burst counter increments and continues from the highest order bursting beginning with the starting address. page address back to zero Burst Stop during this time interval Command 61 Activate Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 18.3. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RBx RAx RAx CAx RBy RBy CBx RBx tRP DQM DQ Hi-Z Activate Command Bank A Ax Read Command Bank A Activate Command Bank B Ax+1 Ax+2 Ax-2 Ax-1 Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval 62 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Full Page burst operation does not Precharge Command terminate when the burst length is Bank B satisfied; the burst counter increments and continues bursting beginning with the Burst Stop starting address. Command Activate Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE High CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RBx RAx RAx CAx RBx RBy RBy CBx DQM DQ Hi-Z DBx DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 Activate Command Bank B The burst counter wraps from the highest order Write page address back to zero Command during this time interval Bank A Activate Command Bank A DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+ 6 DBx+ 7 Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. 63 Data is ignored Precharge Command Bank B Burst Stop Activate Command Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RAx RAx RBx CAx RBx RBy RBy CBx DQM DQ Hi-Z Activate Command Bank A DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 DBx Write Command Bank A DBx+ 1DBx+ 2 DBx+ 3 Activate Write Command Command Bank B Bank B The burst counter wraps Full Page burst operation does not terminate when the burst from the highest order page address back to zero length is satisfied; the burst counter increments and continues bursting during this time interval beginning with the starting address. 64 DBx+ 4 DBx+ 5 DBx+ 6 Data is ignored Precharge Command Bank B Burst Stop Command Activate Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RBx RAx RAx CAx RBx RBy RBy CBx DQM Data is ignored DQ Hi-Z Activate Command Bank A DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 DBx Write Command Bank A Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. 65 Precharge Command Bank B Burst Stop Command Activate Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 RAx RAx CAy CAx CAz & A12 LDQM UDQM DQ0 - DQ7 Ax0 Ax1 Ax1 DQ8 - DQ15 Activate Command Bank A Read Upper 3 Bytes Commandare masked Bank A DAy1DAy2 Ax2 Ax2 Lower Byte is masked Ax3 DAy0 DAy1 DAy3 Write Upper 3 Bytes Read Command are masked Command Bank A Bank A 66 Az0 Az1 Az2 Az1 Az2 Lower Byte is masked Az3 Lower Byte is masked Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 21. Random Row Read (Interleaving Banks) (Burst Length=2, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE High Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RAu RBu CBu RBu RAu CAu RBv RAv RBv CBv RAv tRP DQM Bu0 DQ Activate Command Bank B Read Bank B with Auto Precharge Au1 Activate Command Bank B Read Bank A with Auto Precharge CAv tRP Bu1 Au0 Activate Command Bank A RBw Activate Command Bank A Read Bank B with Auto Precharge RBw CBw tRP Bv0 Bv1 Av1 Activate Command Bank B RAx RAw CAw RBx tRP Av0 Read Bank A with Auto Precharge RBx RAw tRP Bw0 Bw1 Activate Command Bank A Read Bank B with Auto Precharge 67 CBx RAx CAx tRP Aw0 Activate Command Bank B Read Bank A with Auto Precharge Aw1Bx0 Read Bank B with Auto Precharge RAy RBy CBy RAy CAy RBz tRP Bx1 Activate Command Bank A RBz RBy tRP Ax0 Activate Command Bank B Read Bank A with Auto Precharge CBz RAz tRP Ax1 By0 tRP By1 Ay0 Ay1 Activate Command Bank A Read Bank B with Auto Precharge RAz Activate Command Bank B Read Bank A with Auto Precharge Bz0 Activate Command Bank A Read Bank B with Auto Precharge Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 22. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0~A9,A11 & A12 RAx RBx RBx RBw CAx CBx CAy CBy CAz CBz RBw tRP DQM tRRD tRCD DQ Ax0 Activate Command Bank A Bx0 Ay0 Ay1 Read Read Command Command Bank B Read Bank B Read Command Command Bank A Bank A Activate Command Bank B By0 Read Command Bank A 68 By1 Az0 Az1 Read Command Bank B Az2 Bz0 Bz1 Bz2 Precharge Command Bank B (Precharge Temination) Activate Command Bank B Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 23. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RAx RBx RAx RBw RBx CAx CBx CAy CBy CAz CBz RBw tWR tRP DQM tRRD tRCD DQ DAx0 DBx0DAy0 Activate Command Bank A DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 Write Command Bank B Write Write Command Command Bank A Bank A Activate Command Bank B Write Command Bank B Write Command Bank A 69 Write Command Bank B DBz2 Precharge Command Bank B (Precharge Temination) Activate Write Data Command Bank B is masked Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 24.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RAx RAx RAz RAy CAx RAy CAy RAz CAz tRP tWR tRP Precharge Termination of a Read Burst. DQM DQ DAx0 DAx1 DAx2 DAx3 DAx4 Ay0 Read Activate Precharge Termination Precharge Command Command Command of a Write Burst. Bank A Bank A Write data is masked. Bank A Write Activate Command Command Bank A Bank A 70 DAz0 Ay1 Ay2 Precharge Command Bank A DAz1 DAz2 DAz3 DAz4 DAz5 DAz6 DAz7 Write Command Bank A Activate Command Bank A Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 24.2. Precharge Termination of a Burst (Burst Length=8 or Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RAx RAx RAz RAy RAy CAx RAz CAy tWR tRP CAz tRP tRP DQM DQ DAx0 DAx1 DAx2 DAx3 Activate Command Bank A Precharge Write Command Command Bank A Bank A Precharge Termination of a Write Burst. Write data is masked. Ay0 Ay1 Activate Command Bank A Read Command Bank A 71 Az0 Ay2 Precharge Command Bank A Activate Command Bank A Az1 Az2 Precharge Read Command Command Bank A Bank A Precharge Termination of a Read Burst Rev 1.1 Apr. 2007 EtronTech EM63A165 Figure 24.3. Precharge Termination of a Burst (Burst Length=4, 8 or Full Page, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BA0,1 A10 A0~A9,A11 & A12 RAx RAx RAz RAy CAy RAy CAx tWR RAz tRP tRP DQM DQ Ay0 DAx0 DAx1 Activate Command Bank A Write Command Bank A Write Data is masked Precharge Command Bank A Read Command Bank A Activate Command Bank A Precharge Command Bank A Ay1 Ay2 Activate Precharge Termination Command of a Read Burst Bank A Precharge Termination of a Write Burst 72 Rev 1.1 Apr. 2007 EtronTech EM63A165 54 Pin TSOP II Package Outline Drawing Information 28 HE E 0.254 54 θ° L L1 1 27 B S Symbol e y Dimension in inch Min Normal Max 0.047 0.002 0.00395 0.0059 0.0411 0.012 0.015 0.016 0.0047 0.0065 0.0083 0.872 0.8755 0.879 0.3960 0.400 0.4040 0.0315 - C A1 A2 A D L L1 Dimension in mm Min Normal Max 1.194 0.05 0.1 0.150 1.044 0.3 0.35 0.40 0.120 0.165 0.210 22.149 22.238 22.327 10.058 10.16 10.262 0.80 - A A1 A2 B c D E e HE 0.462 0.466 0.470 11.735 L 0.016 0.020 0.0235 0.406 L1 0.033 S 0.035 y 0.004 θ 0° 5° 0° Notes: 1. Dimension D&E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash. 4. Controlling dimension : mm 73 11.8365 0.50 0.84 0.88 - 11.938 0.597 0.10 5° Rev 1.1 Apr. 2007