1ED34x1Mc12M (1ED-X3 Analog)
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
Single-channel 5.7 kV (rms) isolated gate driver IC with adjustable DESAT and
soft-off
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650 V, 1200 V, 1700 V, 2300 V IGBTs, SiC, and Si MOSFETs
40 V absolute maximum output supply voltage
±3 A, ±6 A, and ±9 A typical sinking and sourcing peak output current
Separate source and sink outputs for hard switching and with active Miller clamp/clamp driver
Adjustment pins for parameter configuration from input side
Precise VCEsat detection (DESAT) with fault output and adjustable filter time and leading edge blanking time
with resistor at ADJB pin
Adjustable IGBT soft turn-off after desaturation detection with resistor at ADJA pin
Operation at high ambient temperature up to 125 °C with over-temperature shut down at 160 °C (±10 °C)
Tight IC-to-IC propagation delay matching (tPDD,max = 30 ns)
Undervoltage lockout protection with hysteresis for input and output side with active shut-down
High common-mode transient immunity CMTI = 200 kV/µs
Small space-saving DSO-16 fine-pitch package with large creepage distance (>8 mm)
Safety certification
- UL 1577 recognized (File E311313) with VISO,test = 6840 V (rms) for 1 s, VISO = 5700 V (rms) for 60 s
- VDE 0884-11 approval (Certificate no. 40053980) with VIORM = 1767 V (peak, reinforced)
Evaluation board available EVAL-1ED3491MX12M
Potential applications
•
•
•
•
•
•
•
•
Industrial motor drives - compact, standard, premium, servo drives
Solar inverters
UPS systems
Welding
Commercial and agricultural vehicles (CAV)
Commercial air-conditioning (CAC)
High-voltage isolated DC-DC converters
Isolated switch mode power supplies (SMPS)
PG-DSO-16
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22.
Datasheet
www.infineon.com/gdisolated
Please read the Important Notice and Warnings at the end of this document
1.10
2021-10-08
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
Device information
Device information
Product type
Output current
CLAMP type1)
Isolation class Marking
OPN
1ED3431MC12M
3 A (typ)
CLAMP
reinforced
3431MC12
1ED3431MC12MXUMA1
1ED3461MC12M
6 A (typ)
CLAMPDRV
reinforced
3461MC12
1ED3461MC12MXUMA1
1ED3491MC12M
9 A (typ)
CLAMPDRV
reinforced
3491MC12
1ED3491MC12MXUMA1
1ED3431MU12M
3 A (typ)
CLAMP
UL 1577
3431MU12 1ED3431MU12MXUMA1
1ED3461MU12M
6 A (typ)
CLAMPDRV
UL 1577
3461MU12 1ED3461MU12MXUMA1
1ED3491MU12M
9 A (typ)
CLAMPDRV
UL 1577
3491MU12 1ED3491MU12MXUMA1
1)
Please refer to Chapter 4.5.4.1 for circuit connection to avoid damage to the gate driver IC
Description
The 1ED34x1Mc12M family (X3 Analog) consists of galvanically isolated single channel gate driver ICs in a small
PG-DSO-16 package with a large creepage and clearance of 8 mm. The gate driver ICs provide a typical peak
output current of 3 A, 6 A, and 9 A.
Adjustable control and protection functions are included to simplify the design of highly reliable systems. All
parameter adjustments are done from the input side, including adjustable DESAT filter time, leading edge
blanking time, and soft-off current level with only two resistors..
All logic I/O pins are supply voltage dependent 3.3 V or 5 V CMOS compatible and can be directly connected to a
microcontroller.
The data transfer across the galvanic isolation is realized by the integrated coreless transformer technology.
VCC1
VCC2H
IN,H
DESAT,H
RDYC, FLT_N
EiceDRIVERTM
ON,H
DESAT SoftOff
ADJ,H
OFF.H
CLAMP,H
GND2,H
CPU
GND1
VEE2,H
VCC1
VCC2,L
IN,L
DESAT,L
RDYC, FLT_N
ADJ,L
EiceDRIVERTM
ON,L
DESAT SoftOff
OFF,L
CLAMP,L
GND2,L
GND1
Figure 1
Datasheet
VEE2,L
Typical application
2
1.10
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EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
Table of contents
Table of contents
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Related products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.1
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4
4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.3
4.3.3.1
4.4
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.5.2.1
4.5.2.2
4.5.2.2.1
4.5.3
4.5.4
4.5.4.1
4.5.5
4.6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Start-up and fault clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input side undervoltage lockout, VCC1 UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output side under-voltage lockout, VCC2 UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input side logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
IN non-inverting driver input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
RDYC ready status output, fault-off and fault clear input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RDYC fault-off input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RDYC fault clear input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FLT_N status output and fault-off input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
FLT_N fault-off input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
DESAT behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DESAT filter and leading edge blanking time adjustment with ADJB . . . . . . . . . . . . . . . . . . . . . . . . 19
Gate driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Turn-on behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Turn-off and fault turn-off behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Hard switching turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Soft turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Soft-off current source adjustment with ADJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Active shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Active Miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
CLAMP output types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Switch-off timeout until forced switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Short circuit clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5
5.1
5.2
5.3
5.4
5.4.1
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Voltage supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Datasheet
3
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Datasheet
Table of contents
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
5.4.9
Logic input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Active Miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Soft-off current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Over-temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6
6.1
6.2
Insulation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Certified according to VDE 0884-11 reinforced insulation (Certificate no. 40053980) . . . . . . . . . . . 41
Recognized under UL 1577 (File E311313) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8
8.1
8.2
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Reference layout for thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Printed circuit board guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Datasheet
4
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Datasheet
1 Block diagram
1
Block diagram
VCC1
IN
UVLO1
2
UVLO2
PWM logic
7
TX
opt.
14
VCC2
10
CLAMP
CLAMPDRV
12
ON
11
OFF
13
DESAT
15
GND2
CLAMP control
and detection
RX
VEE2
1
VCC2
FLT_N
6
Output control
with hardswitching and
SoftOff
1
RDYC
5
VEE2
LOGIC
1
TRX
TRX
LOGIC
VCC2
ADJB
4
ADJA
3
DESAT control
and detection
2
1
GND1
Figure 2
Datasheet
1
VEE2
8
9
16
GND1
VEE2
VEE2
Block diagram
5
1.10
2021-10-08
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
2 Related products
2
Related products
Note:
Please consider the gate driver IC power dissipation and insulation requirements for the selected
power switch and operating condition.
Product group
Product name
Description
™
IKQ75N120CS6
High Speed 1200 V, 75 A IGBT with anti-parallel diode in TO247-3
IKW15N120BH6
High Speed 1200 V, 15 A IGBT with anti-parallel diode in TO247
IHW40N120R5
Reverse conducting 1200 V, 40 A IH IGBT with integrated diode in
TO247
TRENCHSTOP
IGBT Discrete
CoolSiC™ SiC
IMBF170R650M1
MOSFET Discrete
IMBG120R045M1H
™
CoolSiC SiC
MOSFET Module
TRENCHSTOP™
IGBT Modules
Datasheet
1700 V, 650 mΩ SiC MOSFET in TO263-7 package
1200 V, 45 mΩ SiC MOSFET in TO263-7 package
IMZ120R350M1H
1200 V, 350 mΩ SiC MOSFET in TO247-4 package
FS45MR12W1M1_B11
EasyPACK™ 1B 1200 V / 45 mΩ sixpack module
FF23MR12W1M1_B11
EasyDUAL™ 1B 1200 V, 23 mΩ half-bridge module
FF6MR12W2M1_B11
EasyDUAL™ 2B 1200 V, 6 mΩ half-bridge module
F3L11MR12W2M1_B74
EasyPACK™ 2B 1200 V, 11 mΩ 3-Level module in Advanced NPC
(ANPC) topology
F4-23MR12W1M1_B11
EasyPACK™ 1B 1200 V, 23 mΩ fourpack module
F4-100R17N3E4
EconoPACK™ 3 1700 V, 100 A fourpack IGBT module
F4-200R17N3E4
EconoPACK™ 3 1700 V, 200 A fourpack IGBT module
FS150R17N3E4
EconoPACK™ 3 1700 V, 150 A sixpack IGBT module
FF650R17IE4
PrimePACK™ 3 1700 V, 650 A half-bridge dual IGBT module
FF1000R17IE4
PrimePACK™ 3 1700 V, 1000 A half-bridge dual IGBT module
FF1200R17IP5
PrimePACK™ 3+ 1700 V, 1200 A dual IGBT module
FF1500R17IP5
PrimePACK™ 3+ 1700 V, 1500 A dual IGBT module
FF1500R17IP5R
PrimePACK™ 3 1700 V, 1500 A dual IGBT module
FF1800R17IP5
PrimePACK™ 3+ 1700 V, 1800 A dual IGBT module
FP10R12W1T7_B11
EasyPIM™ 1B 1200 V, 10 A three phase input rectifier PIM IGBT
module
FS100R12W2T7_B11
EasyPACK™ 2B 1200 V, 100 A sixpack IGBT module
FP150R12KT4_B11
EconoPIM™ 3 1200V three-phase PIM IGBT module
FS200R12KT4R_B11
EconoPACK™ 3 1200 V, 200 A sixpack IGBT module
6
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Datasheet
3 Pin configuration and functionality
3
Pin configuration and functionality
The pin assignment at the gate driver IC generally differentiates between the input side and the output side.
Table 1
General pin assignment
Pins
Designation
1 to 8
input side, input logic signal side, or low voltage side
9 to 16
output side, driver power side, or high voltage side
For simplicity reasons the driver is described as an IGBT driver. For use with MOSFETs and other power switches
simply replace any mentioning of collector and emitter with their corresponding pin names.
3.1
Pin configuration
Table 2
Pin configuration table abbreviations
Abbreviation
Description
Pin type
PWR
Power supply and gate current output pins
I/O
Digital input and output pin
I
Digital input pin
GND
Ground reference pin
AI
Analog input pin
Buffer type
OD
Open drain output
CMOS
CMOS compatible input threshold levels
PP
Push/pull output buffer
special
Special output/input function, see individual description
Pull device
PD
Pull-down resistor
CS
Current source
Table 3
Pin configuration
Pin
no.
Pin name
Pin type
Buffer type Pull
device
Function
1
GND1
GND
–
–
Ground input side
2
VCC1
PWR
–
–
Positive power supply input side
3
ADJA
AI
special
CS
Parameter adjust set A
4
ADJB
AI
special
CS
Parameter adjust set B
5
RDYC
I/O
OD, CMOS
–
Combined ready output, high active and fault clear
input and soft-off input, low active
6
FLT_N
I/O
OD, CMOS
–
Fault output, low active and soft- off input, low active
CMOS
PD, 40 kΩ
Non inverted driver input
7
IN
I
(table continues...)
Datasheet
7
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Datasheet
3 Pin configuration and functionality
Table 3
(continued) Pin configuration
Pin
no.
Pin name
Pin type
Buffer type Pull
device
Function
8
GND1
GND
–
–
Ground input side
9
VEE2
GND
–
–
Negative power supply output side
10
CLAMP
PWR
OD
–
Active Miller clamping, open drain to VEE2
(1ED3431M only)
10
CLAMPDRV PWR
PP
–
Active miller clamping, clamp driver for external
MOSFET (1ED3461M, 1ED3491M)
11
OFF
PWR, AI
OD
–
Driver sink output
12
ON
PWR, AI
OD
–
Driver source output
13
DESAT
AI
special
CS, 500 µA Enhanced desaturation protection
14
VCC2
PWR
–
–
Positive power supply output side
15
GND2
AI
–
–
Signal ground output side
16
VEE2
GND
–
–
Negative power supply output side
Figure 3
Figure 4
Datasheet
1
GND1
VEE2 16
2
VCC1
GND2 15
3
ADJA
VCC2 14
4
ADJB
5
RDYC
ON 12
6
FLT_N
OFF 11
7
IN
8
GND1
DESAT
13
CLAMP 10
VEE2
9
PG-DSO-16 (top view) with CLAMP
1
GND1
VEE2 16
2
VCC1
GND2 15
3
ADJA
4
ADJB
5
RDYC
ON 12
6
FLT_N
OFF 11
7
IN
8
GND1
VCC2 14
DESAT
13
CLAMPDRV
10
VEE2
9
PG-DSO-16 (top view) with CLAMPDRV
8
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2021-10-08
EiceDRIVER™ 1ED34x1Mc12M Enhanced
Datasheet
3 Pin configuration and functionality
3.2
Pin functionality
GND1
Reference ground of the input side. Connect direct to input signal ground.
VCC1
Positive power supply terminal of the input side, connect to 5 V or 3.3 V for proper operation. Place a decoupling
capacitor close to this pin and GND1.
ADJA and ADJB parameter adjust input for set A or B
The pins ADJA and ADJB are used to adjust two sets of independent parameters of output functions.
Connect a resistor between 1.33 kΩ and 28.0 kΩ to GND1 to adjust each parameter. All valid resistor values
belong to the E96-series with 1% tolerance.
Connecting ADJA to GND1 uses a default value for soft switch-off. Connecting it to VCC1 is disabling the gate
driver IC.
Connecting ADJB to GND1 is disabling the gate driver IC. Connecting it to VCC1 is setting the function to
minimum values.
RDYC ready status output, fault-off input and fault-clear input
Open-drain output reports the correct operation of the device, ready output is high active. Fault-clear input and
fault-off input clears a gate driver fault or switch the gate driver output to off with fault-off function, input is low
active. Connect to a microcontroller with 5 V or 3.3 V I/O with an external pull-up resistor to VCC1. A typical value
for this resistor is 2.2 kΩ. The RDCY signal is referenced to GND1.
FLT_N fault output and fault-off input
Open-drain output reports the failures related to operating of the inverter system to the microcontroller, fault
output is active low. Fault-off input switch the gate driver output to off with fault-off function, input is low
active. Connect to a microcontroller with 5 V or 3.3 V I/O with an external pull-up resistor to VCC1. A typical value
for this resistor is 2.2 kΩ. The FLT_N signal is referenced to GND1.
IN non inverting gate driver input
IN input controls the output of the gate driver IC, the IGBT is turned on if IN is set to high. Connect to a PWM
output of the microcontroller with 5 V or 3.3 V IO. An internal pull-down resistor ensures IGBT off-state if not
connected. A minimum pulse width of typical 103 ns is defined to make the gate driver IC robust against glitches
at IN.
VEE2
Negative power supply terminal of the output side. Connect to a voltage of 0 V to -25 V referenced to GND2 for
proper operation. Place a decoupling capacitor close to the following pins:
•
VCC2 and VEE2
•
GND2 and VEE2
If no negative supply voltage is used, all VEE2 pins have to be connected to GND2.
CLAMP Miller clamp output, CLAMPDRV Miller clamp pre-driver output
CLAMP: High-current clamp output to hold the gate voltage low during collector-emitter-voltage rise. Connect
directly to the gate of the IGBT.
CLAMPDRV: Clamp pre-driver output for the use of an external clamp switch. Connect directly to the gate of a
n-channel MOSFET.
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3 Pin configuration and functionality
OFF driver output
High-current driver sink output to discharge the gate of the external IGBT.The gate driver IC also sinks the
Soft-off current at this pin. Connect to the gate of the IGBT via a chosen turn-off gate resistor.
ON driver output
High-current driver source output to charge the gate of the external IGBT and turn it on and sense input for the
CLAMP function. Connect to the gate of the IGBT via a chosen turn-on gate resistor.
DESAT enhanced desaturation detection input
Desaturation detection input to monitor the IGBT collector-emitter voltage (VCE) to detect desaturation caused
by short circuit events. Connect to the collector of the driven IGBT via a series connection of a protection
resistor and a high-voltage diode. The DESAT signal is referenced to GND2.
VCC2
Positive power supply terminal of the output side. Connect to sufficient supply voltage referenced to GND2 for
proper operation. Place a decoupling capacitor close to the following pins:
• VCC2 and VEE2
• VCC2 and GND2
GND2 reference ground
Reference ground of the output side. Connect to common voltage of a bipolar supply and the emitter of the
IGBT. Place a decoupling capacitor close to the following pins:
• VCC2 and GND2
• GND2 and VEE2
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4 Functional description
4
Functional description
The 1ED34x1Mc12M family (X3 Analog) consists of galvanically isolated single channel gate driver ICs with
adjustable feature parametrization by two simple resistors. All adjustments can be done from the low voltage
input side.
To start-up the gate driver IC for normal operation both input and output sides of the gate driver IC need to be
powered.
The 1ED34x1Mc12M family (X3 Analog) is designed to support various supply configurations on the input and
output side. On the output side unipolar and bipolar supply is possible.
The output stage is realized as rail-to-rail. There the gate driver voltage follows the supply voltage without an
additional voltage drop. In addition it provides an easy clamping of the gate voltage during short circuit of an
external IGBT.
The RDYC status output reports correct operation of the gate driver IC like sufficient voltage supply. The FLT_N
status output reports failures in the application like desaturation detection.
To ensure safe operation the gate driver IC is equipped with an input and output side under-voltage lockout
circuit. The UVLO levels are optimized for IGBTs.
The desaturation detection circuit protects the external IGBT from destruction at a short circuit. The gate driver
IC reacts on a DESAT fault by turning off the IGBT with the adjustable soft-off method.
The soft turn-off function is used to switch-off the external IGBT in overcurrent conditions in a soft-controlled
manner to protect the IGBT against collector emitter over-voltages.
An active Miller clamp function protects the IGBT from parasitic turn-on in fast switching applications.
4.1
Start-up and fault clearing
For normal operation both input and output sides of the gate driver IC need to be powered. A low level at the
FLT_N pin always indicates a fault condition. In this case the IC starts internal mechanisms for fault clearing.
Input side start-up
1.
Voltage at VCC1 reaches the input UVLO threshold: input side of gate driver IC starts operating
2.
FLT_N follows input supply voltage
3.
Records resistor programmable function from ADJA and ADJB
4.
Waits until output side is powered
5.
Initiates internal start-up: Transfers configured values to output side
6.
Performs internal self-test
The start-up delay takes approx. 200 µs and is part of the complete start-up time tSTART1.
Output side start-up
1.
Voltage at VCC2 reaches the output UVLO threshold: output side of gate driver IC starts operating
2.
Activates OFF gate driver output: connected gate stays discharged
3.
Waits until input side is powered
4.
Initiates internal start-up: Receives configured values from input side
5.
Performs internal self-test
The start-up delay takes approx. 200 µs and is part of the complete start-up time tSTART2.
The gate driver IC releases RDYC to high to signal a successful start-up and its readiness to operate. The gate
driver IC will follow the status of the IN signal.
Clearing a fault with RDYC to low cycle
1.
2.
Set IN to low
Set RDYC to low for a duration longer than the fault clear time tCLRMIN
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4 Functional description
3.
4.
Release RDYC to high
a.
If the source of the fault is no longer present, FLT_N is released to high
b.
If another fault source is active, FLT_N stays low and the cycle needs to be repeated
Continue PWM operation
4.2
Supply
The 1ED34x1Mc12M family (X3 Analog) is designed to support various supply configurations. The input side can
be used with a 3.3 V or 5 V supply.
The output side requires either an unipolar supply (VEE2 = GND2) or a bipolar supply.
•
Individual supply voltages between VCC2 and GND2 or GND2 and VEE2 shall not exceed 25 V.
•
The total supply voltage between VCC2 and VEE2 shall not exceed 35 V.
To ensure safe operation of the gate driver IC, it is equipped with an input and output side undervoltage lockout
circuit.
Unipolar supply
In unipolar supply configuration the gate driver IC is typically supplied with a positive voltage of 15 V at VCC2.
GND2 and VEE2 are connected together and this common potential is connected to the IGBT emitter.
+3V3
10k
10k
VCC1
VCC2
100n
1k
DESAT
SGND
GND1
ON
IN
IN
RDYC
OFF
1R
1R
RDYC
FLT_N
FLT_N
ADJA
ADJB
Figure 5
+15V
1µ
CLAMP
GND2
VEE2
Application example with unipolar supply (1ED3431M)
Bipolar supply
For bipolar supply the gate driver IC is typically supplied with a positive voltage of 15 V at VCC2 and a negative
voltage of -8 V or -15 V at VEE2 relative to GND2.
Between VCC2 and VEE2 the maximum potential difference is 35 V.
+3V3
SGND
10k
10k
VCC1
VCC2
100n
RDYC
FLT_N
IN
OFF
1R
1R
RDYC
FLT_N
ADJA
ADJB
Figure 6
1k
DESAT
GND1
ON
IN
+15V
1µ
CLAMP
GND2
1µ
VEE2
-8V
Application example with bipolar supply (1ED3431M)
Negative supply prevents a parasitic turn-on due to the additional voltage margin to the gate turn-on threshold.
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4 Functional description
VEE2 over GND2 supply connection check
The gate driver IC has a built-in connection check for VEE2. A loss of VEE2 connection will be detected and
signaled via RDYC.
4.2.1
Input side undervoltage lockout, VCC1 UVLO
To ensure correct operation of the input side and safe operation of the application the gate driver IC is equipped
with an input supply undervoltage lockout for VCC1.
UVLO behavior during start-up:
1.
The voltage at the supply terminal VCC1 reaches the VUVLO1H threshold
2.
The gate driver IC reads the ADJA and ADJB resistor values and transfers the configuration to the output
side
3.
The IC releases the RDYC output to high and is ready to operate.
The start-up delay takes approx. 200 µs and is part of the complete start-up time tSTART1.
UVLO behavior during shut-down:
•
If the supply voltage VVCC1 of the input side drops below VUVLO1L the RDYC signal is switched to low and the
output will be switched off.
The fault signal FLT_N follows the input supply voltage.
IN
VUVLO1H
VCC1
VCC2
VUVLO1L
tPDRDYC
tSTART1
ON+OFF
RDYC
tUV1LRDYC
tPDRDYC
FLT_N
Figure 7
UVLO VCC1 behavior
4.2.2
Output side under-voltage lockout, VCC2 UVLO
To ensure correct operation of the output side and safe operation of the IGBT in the application, the gate driver
IC is equipped with an output supply undervoltage lockout for VCC2 versus GND2.
UVLO behavior during start-up:
•
If the voltage at the supply terminal VCC2 reaches the VUVLO2H threshold the RDYC output is released to high
and the gate driver IC is ready to operate.
The start-up delay takes approx. 200 µs and is part of the complete start-up time tSTART2.
UVLO behavior during shut-down:
•
If the supply voltage VVCC2 of the output side drops below VUVLO2L the RDYC signal is switched to low and the
output will be switched off.
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4 Functional description
IN
VCC1
VUVLO2H
VUVLO2L
VCC2
ON+OFF
tPDRDYC
tUV2LOFF
RDYC
tSTART2
tUV2LRDYC
FLT_N
Figure 8
UVLO VCC2 behavior
Any VUVLO2L event will lead to a fault-off and a RDYC low level. Depending of the level of the voltage drop, the
gate driver IC either stays in a not ready state and waits for the supply voltage to recover, or it will fully reset the
gate driver IC. Both variants differ in the necessary delay of RDYC release after the supply voltage has recovered.
After a reset, the gate driver IC needs to fully restart until it becomes ready again.
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4.3
Input side logic
The input threshold levels are always CMOS compliant. The threshold levels are 30% of VCC1 for low level and
70% of VCC1 for high level.
The 1ED34x1Mc12M family (X3 Analog) has three input pins (IN, ADJA, ADJB) and two I/O pins (RDYC, FLT_N) at
the input side.
4.3.1
IN non-inverting driver input
The input pin has a positive logic. To turn on the associated IGBT apply a logic high signal at the IN pin. A
minimum pulse width of typical 103 ns is defined to make the IC robust against glitches at IN.
4.3.2
RDYC ready status output, fault-off and fault clear input
The RDYC pin is a logic input and open drain output and has three different functions:
•
RDYC as ready status output of all ready sources
•
RDYC as fault-off input
•
RDYC as fault clear input
In a typical application the RDYC pins of all gate driver ICs in the inverter are connected together and form a
single wire RDYC signal.
An external pull-up resistor is required to ensure RDYC status output during operation.
Ready sources
•
•
•
•
•
the input side is properly supplied, VCC1 supply above UVLO1 threshold
the output side is properly supplied with a positive voltage, VCC2 supply above UVLO2 threshold
no VEE2 over GND2 failure
Internal signal transmission is operating nominal
the ON pin monitoring of the gate driver is below VEE2 + 2 V, IGBT has to be off at start-up
4.3.2.1
RDYC fault-off input
Pulling RDYC to low disables the operation of the gate driver IC. The gate driver IC ignores IN signals as long as
the RDYC pin stays low and the IC uses its fault-off function to switch-off the IGBT.
The defined minimum pulse width makes the IC robust against glitches at RDYC. The gate driver ignores pulses
with a shorter duration.
IN
RDYC
tRDYCMIN
tPDRDYC
ON+OFF
Figure 9
tSSIO
tRDYCMIN
tSSIO
VEE2 + 2V
RDYC short pulse behavior of external manipulation of the RDYC pin
After an external RDYC low signal the IC is actively pulling RDYC to low until the voltage at ON pin falls below the
VEE2+2 V threshold.
The RDYC fault-off input is active low.
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4 Functional description
4.3.2.2
RDYC fault clear input
Setting RDYC to low for longer than the fault clear time tCLRMIN will reset the stored fault signal at pin FLT_N with
the rising edge of RDYC. Additionally the following conditions have to be met as well:
•
PWM IN pin level needs to be low,
•
voltage at ON pin has dropped below the VEE2+2 V threshold, and
•
triggering fault condition is no longer present.
The typical fault clear time tCLRMIN is 1.0 µs.
IN
FLT event
FLT_N
tDESATFLT
ON+OFF
tDESATFLT
VEE2 + 2V
tSSIO
tSSIO
RDYC
>tCLRMIN
Figure 10
>tCLRMIN
RDYC fault clear timing
RDYC
VIH
FLT_N
Figure 11
RDYC fault clear rising edge to FLT_N
4.3.3
FLT_N status output and fault-off input
The FLT_N pin is a logic input and open drain output and has two different functions:
• FLT_N as fault-status output for fault sources
• FLT_N as fault-off input
In a typical application the FLT_N pins of all gate driver ICs in the inverter are connected together and form a
single wire FLT_N signal.
An external pull-up-resistor is required to ensure FLT_N status output during operation.
Fault sources
The following fault sources can trigger a FLT_N pin to low and initiate a fault turn-off:
• desaturation detection of IGBT
• gate driver over temperature protection
4.3.3.1
FLT_N fault-off input
Pulling FLT_N to low disables the operation of the gate driver IC. The gate driver IC ignores IN signals as long as
the FLT_N pin stays low and the IC uses its fault-off function to switch-off the IGBT.
The defined minimum pulse width makes the gate driver IC robust against glitches at FLT_N.
After a low at the FLT_N pin either internally or externally applied, the fault event is latched until cleared.
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4 Functional description
The FLT_N fault-off input is active low.
IN
FLT_N
tFLT_NMIN
tFLT_NMIN
tPDFLT_N
ON+OFF
RDYC
>tCLRMIN
Figure 12
Datasheet
>tCLRMIN
FLT_N short pulse behavior of external manipulation of the FLT_N pin cleared by RDYC
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4.4
Desaturation protection
The desaturation detection circuit protects the external IGBT from destruction at a short circuit. The
desaturation protection follows the given sequence:
1.
Voltage at DESAT pin reaches DESAT threshold level, for a period of time exceeding the filter time
2.
Gate driver IC output switches the external IGBT off, using the soft-off method
3.
Gate driver IC switches FLT_N pin to low to indicate the fault to a connected microcontroller
4.
Short circuit situation is resolved
•
after the voltage at the ON pin has dropped below the VEE2+2 V threshold,
•
no other fault condition is present,
•
the input has been turned off and
•
the fault has been cleared using the RDYC low cycle method
VCC2
+15V
D
A
CVCC2
DESAT
RDESAT
DDESAT
LOGIC
FLT_off
OFF
RG
GND2
Figure 13
DESAT circuit (only relevant pins shown)
The 1ED34x1Mc12M family (X3 Analog) has a fixed DESAT threshold level of typical 9.18 V. If lower threshold
levels are required, the DESAT resistor can be increased. Larger DESAT resistor values lead to lower DESAT
threshold voltages. The threshold voltage reduction is equal to the DESAT current multiplied by the DESAT
resistance.
The high-precision internal current source results in a minimum impact on the DESAT detection variation.
4.4.1
DESAT behavior
The DESAT function offers a leading edge blanking time and filters to optimize the DESAT detection for
application usage.
The leading edge blanking inhibits threshold detection during an IGBT turn on phase. The typical IGBT turn on
behavior starts with charging of the gate, commutation of the application load current and finally VCE voltage
decrease to VCEsat voltage levels. To prevent the gate driver IC from detecting a false DESAT event, leading edge
blanking pauses the DESAT circuit until the time tDESATleb has elapsed.
Following the leading edge blanking time, the gate driver IC forces the DESAT current into the external
DESAT circuit. The current typically flows through a protection resistor, a fast high voltage diode and the
collector-emitter path of the IGBT. The resulting voltage at the DESAT pin is the sum of the voltage drop across
this path.
During a short circuit condition, the VCE voltage increases, resulting in a reverse polarity condition of the DESAT
diode. The remaining DESAT current also increases the voltage level at the DESAT pin and triggers the DESAT
threshold. If the pin voltage level stays above the threshold for the duration of the DESAT filter time tDESATfilter,
the gate driver IC registers the DESAT event and acts accordingly.
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4 Functional description
The internal processing time after DESAT threshold crossing, filtering and beginning of fault-off is defined as
tDESATOUT. The duration of the gate discharge during fault-off is defined as tFLTOFFtot and is depending on the
soft-off function and the gate load.
IN
tPDRDYC
tPDON
tFLTOFFtot
OUT
tDESATfilter
tDESATOUTS
VDESAT
tDESATleb
DESAT
VCE
tDESATFLT
FLT_N
RDYC
>tCLRMIN
Figure 14
DESAT timing with leading edge blanking, filter and reaction times
4.4.2
DESAT filter and leading edge blanking time adjustment with ADJB
The ADJB pin configures the DESAT leading edge blanking time and DESAT filter time:
•
A resistor from ADJB to GND1 sets the DESAT leading edge blanking time and the DESAT filter time used
during DESAT detection
•
Use resistors from the E96 resistor-series with 1% tolerance values to achieve accurate parameter
configuration
•
The gate driver IC reads the resistor value once during start-up
•
Connecting ADJB to GND1 inhibits the gate driver operation and stops the start-up sequence
•
Connecting ADJB to VCC1 disables the filtering resulting in minimum response times
Table 4
DESAT filter time
set up
DESAT filter timing ADJB adjustment
1
2
3
4
5
6
7
Resistance at ADJB <
1.33 kΩ
to GND1
1.05 kΩ
or tied
to GND1
1.58 kΩ
1.91 kΩ
2.26 kΩ
2.74 kΩ
3.32 kΩ
4.02 kΩ
4.87 kΩ
typ. tDESATleb
650 ns
650 ns
650 ns
650 ns
650 ns
650 ns
650 ns
1775 ns
1975 ns
2375 ns
2775 ns
3175 ns
3575 ns
3975 ns
typ. tDESATfilter
Datasheet
stopped 0
inhibit 650 ns
gate
1575 ns
driver
operatio
n
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Table 4
DESAT filter time
set up
DESAT filter timing ADJB adjustment
9
10
11
12
13
14
15
default
Resistance at ADJB 5.90 kΩ
to GND1
7.15 kΩ
8.66 kΩ
10.7 kΩ
13.7 kΩ
17.4 kΩ
23.2 kΩ
28.0 kΩ
>45.3 kΩ
or tied
to VCC1
typ. tDESATleb
1150 ns
1150 ns
1150 ns
1150 ns
1150 ns
1150 ns
1150 ns
1150 ns
400 ns
typ. tDESATfilter
3975 ns
3575 ns
3175 ns
2775 ns
2375 ns
1975 ns
1775 ns
1575 ns
225 ns
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4.5
Gate driver output
The gate driver output side uses MOSFETs to provide a rail-to-rail output. Therefore, the gate drive voltage
follows the supply voltage closely.
Due to the low internal voltage drop, the switching behavior of the IGBT is predominantly governed by the
external gate resistor. The gate driver IC offers separate sink and source outputs to adapt the gate resistor for
turn-on and turn-off separately without additional bypass components.
The cell value x in the following table is placeholder for high or low and indicates that this pin does not
influence the resulting gate driver output state. The arrow (→) in cells indicate the transition initiated by the pin
of the logic input and gate driver supply pins resulting in a transition to the gate driver output state as listed.
Table 5
Driver output state including transition behavior
Logic input and gate driver supply
IN
RDYC
FLT_N
Gate driver output
VCC1
VCC2
ON
OFF
Static gate driver output state: on and off
high
high
high
high
high
high
tri-state
low
high
high
high
high
tri-state
low
Transition to not ready and static not ready state
x
high → low
high
high
high
→ tri-state
→ fault off
x
low
high
high
high
tri-state
low
Transition to fault and static fault state
x
high
high → low
high
high
→ tri-state
→ fault off
x
high
low
high
high
tri-state
low
Transition with VCC1 power loss and unsupplied input side
x
x
x
high → low
high
→ tri-state
→ fault off
x
x
x
low
high
tri-state
low
Transition with VCC2 power loss and unsupplied output side
x
x
x
x
high → low
→ tri-state
→ fault off
x
x
x
x
low
tri-state
active shut down
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4 Functional description
4.5.1
Turn-on behavior
The 1ED34x1Mc12M family (X3 Analog) is optimized for hard switching turn-on. A turn-on command switches
the ON pin internally to VCC2.
4.5.2
Turn-off and fault turn-off behavior
The gate driver IC supports different turn-off sequences to adapt to different applications and IGBT currents
during normal switching operation and in the case of a fault.
Table 6
Turn-off reason
Turn-off sequences
Turn-off sequence
Remark
Hard switching
normal off
Soft turn-off
X
fault turn-off
X
adjustable via ADJA
The gate driver fault turn-off behavior can be configured with the ADJA pin
Once started, the fault turn-off sequence cannot be interrupted by an IN = low turn-off signal.
FLT_N or RDYC
tPDRDYCS, tPDFLT_NS
VOUT = 80%
ON + OFF (soft-off)
Figure 15
Fault turn-off sequence initiated by FLT_N or RDYC
VDESAT
DESAT
tDESATfilter,n
tDESATOUTS
VOUT = 80%
ON + OFF (soft-off)
Figure 16
Fault turn-off sequence initiated by DESAT event
4.5.2.1
Hard switching turn-off
The gate driver IC supports hard switching turn-off during normal switching operation. Switching the IGBT gate
off by turning on the discharge MOSFET in the output stage, the OFF pin is switched to VEE2 pin.
4.5.2.2
Soft turn-off
The soft turn-off function protects the IGBT against collector-emitter overvoltage during turn off in an
overcurrent condition. It turns-off the IGBT with a reduced gate current to reduce the di/dt induced
overvoltage..
The IGBT gate is connected via OFF to an internal current sink circuit. The discharge current is typically lower
than the hard switch-off current used for normal operation. Since soft turn-off is a single event after a failure,
the gate driver IC can handle the additional power dissipation internally.
Soft turn-off can be configured with the ADJA pin. The function is only active during fault turn-off.
The adjustable range depends on the current strength of the gate driver IC:
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•
•
•
1ED3431M: 15 mA - 233 mA
1ED3461M: 29 mA - 466 mA
1ED3491M: 44 mA - 699 mA
4.5.2.2.1
Soft-off current source adjustment with ADJA
The ADJA pin configures the Soft-off function and current level:
•
A resistor from ADJA pin to GND1 sets the Soft-off current level for the fault-off function
•
Use resistors from the E96 resistor-series with 1% tolerance values to achieve accurate parameter
configuration
•
The gate driver IC reads the resistor value once during start-up
•
Connecting ADJA to GND1 results in a Soft-off function for fault-off with a predefined value
•
Connecting ADJA to VCC1 inhibits the gate driver operation and stops the start-up sequence
Table 7
Soft-off set up
Soft-off adjustment with ADJA
default
0
1
2
3
4
5
6
7
Resistance from < 1.05 kΩ
ADJA to GND1
or tied to
GND1
1.33 kΩ
1.58 kΩ
1.91 kΩ
2.26 kΩ
2.74 kΩ
3.32 kΩ
4.02 kΩ
4.87 kΩ
typ. ICSOFF
1ED3431M
146 mA
15 mA
29 mA
44 mA
58 mA
73 mA
87 mA
102 mA
116 mA
typ. ICSOFF
1ED3461M
291 mA
29 mA
58 mA
87 mA
116 mA
146 mA
175 mA
204 mA
233 mA
typ. ICSOFF
1ED3491M
437 mA
44 mA
87 mA
131 mA
175 mA
218 mA
262 mA
306 mA
349 mA
Table 7
Soft-off set up
Soft-off adjustment with ADJA
9
10
11
12
13
14
15
stopped
Resistance from 5.90 kΩ
ADJA to GND1
7.15 kΩ
8.66 kΩ
10.7 kΩ
13.7 kΩ
17.4 kΩ
23.2 kΩ
28.0 kΩ
>45.3 kΩ or
tied to VCC1
typ. ICSOFF
1ED3431M
131 mA
146 mA
160 mA
175 mA
189 mA
204 mA
218 mA
233 mA
typ. ICSOFF
1ED3461M
262 mA
291 mA
320 mA
349 mA
379 mA
408 mA
437 mA
466 mA
inhibit gate
driver
operation
typ. ICSOFF
1ED3491M
393 mA
437 mA
480 mA
524 mA
568 mA
612 mA
655 mA
699 mA
Datasheet
8
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Datasheet
4 Functional description
4.5.3
Active shut-down
The active shut-down feature ensures a safe IGBT off-state, if the output chip is not supplied. It protects the
IGBT against a floating gate. The IGBT gate is always clamped via OFF to VEE2.
4.5.4
Active Miller clamp
The 1ED34x1Mc12M family (X3 Analog) is equipped with an active Miller clamp function to protect the IGBT from
parasitic turn-on in fast switching applications.
After a turn-off command the gate driver IC follows the implemented sequence:
1.
Discharge of the IGBT gate while monitoring the voltage level at the ON pin
2.
Detection of a voltage at the ON pin less than a level of VEE2 + 2.0 V
3.
Filtering of the detection to avoid false CLAMP activation and not to influence regular turn-off behavior
4.
Activating clamp function to keep IGBT gate at VEE2 level
4.5.4.1
CLAMP output types
The CLAMP output stage offers two operating modes:
•
direct gate clamping with an open drain output for medium clamping current, 1ED3431M variants
•
pre-driver output, to clamp IGBT gate with external transistor for high clamping current, 1ED3461M and
1ED3491M variants
Direct gate clamping
Direct gate clamping with an open drain output is tailored for direct clamping of IGBT gate to VEE2. The output
current capability is typically 2 A. Useful IGBT current rating for direct gate clamping is a collector current of
typically smaller than 100 A. Connect the CLAMP pin directly to the gate with low inductive tracks.
+3V3
SGND
10k
10k
VCC1
VCC2
100n
DESAT
GND1
ON
IN
RDYC
FLT_N
IN
FLT_N
ADJB
Datasheet
OFF
1k
1R
1R
RDYC
ADJA
Figure 17
+15V
1µ
CLAMP
GND2
VEE2
Application example with unipolar supply (1ED3431M)
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4 Functional description
IN
tPDOFF
VVEE2 +2V
ON
tCLAMPfilter
tONCLAMP
OFF
CLAMP
CLAMP tri state
Figure 18
CLAMP active low
CLAMP tri state
Direct clamp output behavior
Pre-driver output
Track inductance and clamp output resistance reduces the clamping capability for large IGBTs. In this case,
select the pre-driver output product variant with an external MOSFET.
The external small signal n-channel MOSFET transistor in combination with the pre-driver output enables
clamping of high gate currents. Connect the MOSFET between the CLAMPDRV output, VEE2 pin, and IGBT gate.
Due to the pre-driver configuration the clamp current is only limited by the external clamp MOSFET transistor.
Depending on the external MOSFET a Miller current clamping up to 20 A can be reached. The clamping MOSFET
has to be placed close to the IGBT gate to minimize track resistance and inductance.
+3V3
SGND
10k
10k
VCC1
VCC2
100n
RDYC
FLT_N
GND1
IN
FLT_N
ADJB
Datasheet
OFF
1R
1R
RDYC
ADJA
Figure 19
1k
DESAT
ON
IN
+15V
1µ
CLAMPDRV
GND2
1µ
VEE2
-8V
Application example with bipolar supply and CLAMP pre-driver output (1ED3461M,
1ED3491M)
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4 Functional description
IN
tPDOFF
VVEE2 +2V
ON
tCLAMPfilter
tONCLAMP
OFF
CLAMPDRV
CLAMP DRV low
CLAMP DRV active high
Figure 20
Clamp pre-driver output behavior
4.5.5
Switch-off timeout until forced switch-off
CLAMP DRV low
The gate driver IC is equipped with a switch-off timeout monitoring feature. In case the pin monitoring
comparator has not registered an off-state within the timeout time this feature activates a forced switch-off.
The monitoring feature secures the IGBT switch-off in case of a connection failure between the OFF output
and the IGBT gate or a faulty gate resistor. In a forced switch-off all available output switch-off paths (OFF and
CLAMP/CLAMPDRV) will be used to hard switch-off the IGBT after such an event.
OFF activated
VVEE2 +2V
ON
(soft-off)
tCTSOOS
ON
(hard switch-off)
VVEE2 +2V
tCTT
TO switch-off inactive
Figure 21
tCTT
TO switch-off active
Switch-off timeout behavior
The timing diagram shows the switch-off timeout behavior from the moment of OFF output activation until the
timeout has elapsed and the CLAMP output is activated.
4.6
Short circuit clamping
The integrated short circuit clamping diode limits the IGBT gate over voltage during a short circuit. The over
voltage is typically triggered by the capacitive feedback of the Miller capacitance.
The internal diodes from ON and CLAMP to VCC2 limit the gate driver voltage to a value slightly higher than the
supply voltage. These diode paths are rated for a maximum current of 0.75 A and the duration of 6 µs. Add an
external Schottky diode if higher currents are expected or a tighter clamping is desired. Also use an external
diode if the active Miller clamping circuit uses the pre-driver output configuration.
Datasheet
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Datasheet
4 Functional description
VCC2
+15V
VCC2
ON
ON
OFF
OFF
CLAMP
Figure 22
Datasheet
+15V
CLAMP
GND2
GND2
VEE2
VEE2
Short circuit clamping circuitry
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5 Electrical parameters
5
Electrical parameters
5.1
Absolute maximum ratings
Note:
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to
destruction of the integrated circuit. Unless otherwise noted all voltages are given with respect to
their respective GND (GND1 for pins 1 to 8, GND2 for pins 9 to 16).
Table 8
Absolute maximum ratings
Parameter
Symbol
Values
Min.
Max.
Unit
Note /
Test Condition
Input to output offset voltage
VOFFSET
–
2300
V
VVEE2,max-VVEE2,min
with VVEE2,max ≥
VGND1
≥ VVEE2,min1) 2)
Supply voltage input side
VVCC1
-0.3
6.5
V
–
Logic input voltage (IN)
VLogicIN
-0.3
6.5
V
–
Logic input voltage (RDYC, FLT_N)
VLogicRF
-0.3
6.5
V
–
Logic input voltage (ADJA, ADJB)
VLogicAD
-0.3
6.5
V
–
Open drain logic output current (RDYC, FLT_N)
ILogicOC
–
10
mA
–
Positive supply voltage output side
VVCC2
-0.3
40
V
–
Negative supply voltage output side
VVEE2
-40
0.3
V
–
Maximum supply voltage difference output
side (VVCC2 - VVEE2)
Vmax2
–
40
V
–
DESAT input voltage
VDESAT
-0.3
VVCC2 +0.3 V
–
CLAMP input voltage
VCLAMP
VVEE2 -0.3
VVCC2 +0.3 V
3)
Maximum CLAMP output current
ICLAMP
–
2.4
t < 5 µs
Gate driver output voltage (ON, OFF)
VOUT
VVEE2 -0.3
Vmax2 +0.3 V
–
Maximum CLAMP to VCC2 diode IGBT short
circuit clamping time
tCLP
–
6
µs
ICLAMP/OUT = 0.75 A
Junction temperature
TJ
-40
150
°C
–
Storage temperature
TStg
-55
150
°C
–
Power dissipation, input side
PD,IN
–
100
mW
@TA = 25 °C
Power dissipation, output side
PD,OUT
–
700
mW
@TA = 25°C4)
ESD capability: Human body model
VESDHBM
–
2
kV
5)
ESD capability: Charged device model
VESDCDM
–
500
V
6)
1)
2)
3)
4)
A
for functional operation only
See also Chapter 6 on page 41
May be exceeded during short circuit clamping.
Derating the power above 65°C with 8 mW/°C
Datasheet
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Datasheet
5 Electrical parameters
5)
6)
According to ANSI/ESDA/JEDEC-JS-001-2017 (discharging a 100 pF capacitor through a 1.5 kΩ series
resistor).
According to ANSI/ESDA/JEDEC-JS-002-2014 (TC = test condition in volt)
5.2
Thermal parameters
Thermal performance may change significantly with layout and heat dissipation of components in close
proximity.
Figure 23
Reference layout for thermal data (Two layer PCB; copper thickness 35 μm; left: top
layer; right: bottom layer)
The PCB layout represents the reference layout used for the thermal characterization. Pins 1 and 8 (GND1)
and pins 9 and 16 (VEE2) require ground plane connections for achieving maximum power dissipation. The
1ED34x1Mc12M family (X3 Analog) is conceived to dissipate most of the heat generated through these pins.
Table 9
Thermal parameters
Parameter
Symbol
Value
Unit
Note / Test Condition
Thermal resistance junction to
ambient
RTHJA,OUT
122
K/W
8
K/W
@TA = 65°C, PD, OUT = 400 mW,
PD, IN = 50 mW, 4 layer test PCB,
PG-DSO-16
Characterization parameter junction ΨJtop
to package top input side
5.3
Note:
Operating parameters
Within the operating range the IC operates as described in the functional description. Unless
otherwise noted all voltages are given with respect to their respective GND (GND1 for pins 1 to 8,
GND2 for pins 9 to 16).
Table 10
Operating parameters
Parameter1)
Symbol
Values
Min.
Max.
Unit
Note /
Test Condition
Supply voltage input side
VVCC1
3.0
5.5
V
–
Logic input voltages (IN, RDYC, FLT_N)
VLogicIN
-0.3
5.5
V
–
Positive supply voltage output side
VVCC2
13
25
V
–
Negative supply voltage output side
VVEE2
-25
0
V
–
(table continues...)
Datasheet
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5 Electrical parameters
Table 10
(continued) Operating parameters
Parameter1)
Symbol
Values
Min.
Max.
Unit
Note /
Test Condition
Supply voltage difference output side
(VVCC2 - VVEE2)
Vmax2
13
35
V
–
Ambient temperature
TA
-40
125
°C
2)
Switching frequency
fSW
0
250
kHz
max PD applies
Common mode transient immunity
|CMTI|
0
200
V/ns
VOFFSET,test =
1500 V
1)
2)
Parameter is not subject to production test - verified by design/characterization
TJ has to be below over temperature protection temperature TOTPOFF
Datasheet
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5 Electrical parameters
5.4
Note:
Electrical characteristics
The electrical characteristics include the spread of values in supply voltages, load, and junction
temperatures within the operating parameters unless specified otherwise. Typical values represent
the median values at TA = 25°C. Unless otherwise noted all voltages are given with respect to their
respective GND (GND1 for pins 1 to 8, GND2 for pins 9 to 16).
5.4.1
Voltage supply
Table 11
Voltage supply
Parameter
Symbol
Values
Min.
VCC1 UVLO threshold
Typ.
Unit
Note or Test
Condition
Max.
VUVLO1H
–
2.95
3.05
V
–
VUVLO1L
2.6
2.8
–
V
–
VCC1 UVLO hysteresis
(VUVLO1H - VUVLO1L)
VHYS1
0.1
0.14
–
V
–
VCC1 quiescent current
IQ1
–
2.4
4.0
mA
VVCC1 = 3.3 V, IN =
High, RDYC = High,
FLT_N = High
VCC1 operating current
IO1
–
2.4
4.0
mA
VVCC1 = 3.3 V, IN =
16 kHz, 50%, RDYC =
High, FLT_N = High
VCC2 UVLO threshold
VUVLO2H,0
–
12.0
12.6
V
VUVLO2L,0
10.4
11.0
–
V
VCC2 UVLO hysteresis
(VUVLO2H,0 - VUVLO2L,0)
VHYS2,0
0.75
1.0
–
V
VEE2 not connected
detection threshold
VVEE2,NC
–
0.5
–
V
VVEE2 - VGND2
VCC2 quiescent current
IQ2
–
3.9
5
mA
VVCC2 = 15 V, VVEE2
= -8 V, OUT = High,
DESAT = Low
VCC2 operating current
IO2
–
3.9
5
mA
VVCC2 = 15 V, VVEE2 =
-8 V, OUT = 16 kHz,
50%, DESAT = Low,
CLOAD = 100 pF
Datasheet
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5 Electrical parameters
5.4.2
Logic input and output
Table 12
Logic input and output
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or Test
Condition
Max.
Logic low input voltage (IN,
RDYC, FLT_N)
VLogicINL
–
–
30
%
of VVCC1
Logic high input voltage (IN,
RDYC, FLT_N)
VLogicINH
70
–
–
%
of VVCC1
Logic low output voltage (RDYC, VRDYC5,
FLT_N)
VFLT_N5
–
–
300
mV
ISINK = 5 mA
Logic input pull down resistor
(IN)
RINPD
33
40
47
kΩ
–
Logic input pull down resistor
(RDYC, FLT_N)
RRDYCPD,
RFLT_NPD
0.8
1.0
1.2
MΩ
–
5.4.3
Analog input
Resistor values outside of the 1% tolerance range results in the gate driver IC selecting either the lower or higher
step for the corresponding function.
Table 13
Analog input
Parameter1)
Symbol
Values
Min.
Analog input resistor (ADJA,
ADJB)
Datasheet
Typ.
Note or Test
Condition
kΩ
all resistor values are
from the E96-series
with 1% tolerance
Max.
RADJx0
–
1.33
–
RADJx1
–
1.58
–
RADJx2
–
1.91
–
RADJx3
–
2.26
–
RADJx4
–
2.74
–
RADJx5
–
3.32
–
RADJx6
–
4.02
–
RADJx7
–
4.87
–
RADJx8
–
5.90
–
RADJx9
–
7.15
–
RADJx10
–
8.66
–
RADJx11
–
10.7
–
RADJx12
–
13.7
–
RADJx13
–
17.4
–
RADJx14
–
23.2
–
RADJx15
–
28.0
–
32
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5 Electrical parameters
1)
Parameter is not subject to production test - verified by design/characterization
Datasheet
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5 Electrical parameters
5.4.4
Note:
Gate driver
High and low level output currents are absolute values without an information of current direction.
Table 14
Gate driver
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or Test
Condition
High level output
voltage
VON0
–
VVCC2 + 0.87
VVCC2 + 1.01
V
ION = 500 mA1)
High level output peak
current 1ED3431M
ION
2.6
3.8
–
A
2) 3) C
High level output on
resistance 1ED3431M
RDSON,H
0.51
1.12
2.24
Ω
ION = 67 mA3)
Low level output peak
current 1ED3431M
IOFF
2.0
2.5
–
A
2) 4) C
Low level ouput on
resistance 1ED3431M
RDSON,L
0.31
0.82
1.64
Ω
IOFF = 67 mA4)
High level output peak
current 1ED3461M
ION
5.2
7.5
–
A
2) 3) C
High level output on
resistance 1ED3461M
RDSON,H
0.26
0.56
1.13
Ω
ION = 133 mA3)
Low level output peak
current 1ED3461M
IOFF
4.0
5.0
–
A
2) 4) C
Low level ouput on
resistance 1ED3461M
RDSON,L
0.16
0.41
0.83
Ω
IOFF = 133 mA4)
High Level output peak ION
current 1ED3491M
7.9
11
–
A
2) 3) C
High level output on
resistance 1ED3491M
RDSON,H
0.17
0.38
0.75
Ω
ION = 200 mA3)
Low Level output peak
current 1ED3491M
IOFF
6.0
7.5
–
A
2) 4) C
Low level ouput on
resistance 1ED3491M
RDSON,L
0.11
0.28
0.55
Ω
IOFF = 200 mA4)
Active Shut Down
Voltage OFF 1ED3431M
VACTSD5)
–
–
VVEE2 +2.4
V
IOUT = 67 mA,VVCC2
open
Active Shut Down
Voltage OFF 1ED3461M
VACTSD5)
–
–
VVEE2 +2.4
V
IOUT = 133 mA,VVCC2
open
Active Shut Down
Voltage OFF 1ED3491M
VACTSD5)
–
–
VVEE2 +2.4
V
IOUT = 200 mA,VVCC2
open
1)
2)
3)
4)
LOAD = 33 nF
LOAD = 33 nF
LOAD = 68 nF
LOAD = 68 nF
LOAD = 100 nF
LOAD = 100 nF
Integrated diode ON vs. VCC2 clamping test
Parameter is not subject to production test - verified by design/characterization
IN = High, ON = High; VCC2-ON = 15 V; RG = 0.1 Ω; VCC2 = 15 V; VEE2 = -8 V
IN = Low, OFF = Low; OFF-VEE2 = 15 V; RG = 0.1 Ω; VCC2 = 15 V; VEE2 = -8 V
Datasheet
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5 Electrical parameters
5)
With reference to VEE2
5.4.5
Active Miller clamp
Table 15
Active Miller clamp
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or Test
Condition
Max.
VCLAMPH0
–
VVCC2 +1.5
VVCC2 +1.63
V
ICLAMP = 500 mA1) 2)
VCLAMPH1
–
VVCC2 +0.9
VVCC2 +1.1
V
ICLAMP = 50 mA1) 2)
Clamp-driver high
VCLAMPDH1
level output voltage
V
(1ED3461M, 1ED3491M) CLAMPDH2
VVEE2+7.5
VVEE2+9.5
VVEE2+11.5
V
ICLAMPH = 5 mA3)
VVEE2+4.5
VVEE2+6.7
–
V
ICLAMPH = 50 mA3)
Clamp-driver high level ICLAMPH
output peak current
(1ED3461M, 1ED3491M)
0.20
0.27
–
A
4) VCC2 = 15 V; VEE2 =
Clamp/Clamp-driver
output low level
current
ICLAMPL,2
1.1
1.8
–
A
Clamp/Clamp-driver
output low level
current
ICLAMPL,5
2.2
3.5
–
A
Clamp/Clamp-driver
output low level ON
resistance
RDSON,CLP
0.50
0.85
1.35
Ω
ICLAMPL = 200 mA
Clamp threshold
voltage
VON_CLAMP
1.5
2.0
2.5
V
Related to VEE2
Clamp filter time
tCLAMPfilter
195
235
275
ns
16 +
tCLAMPfilter
23 +
tCLAMPfilter
35 +
tCLAMPfilter
ns
4) 5) C
CLAMP reaction time in tCLAMPD_ON 24 +
CLAMP driver mode
tCLAMPfilter
35 +
tCLAMPfilter
53 +
tCLAMPfilter
ns
4) 6) C
Switch-off time-out
time
tCTT
–
2.4
–
µs
4)
Switch-off time-out
soft-off offset time
tCTSOOS
–
2.4
–
µs
4) additional time-out
High level clamp
voltage
CLAMP reaction time in tCLAMP_ON
CLAMP mode
1)
2)
3)
4)
5)
0 V; CCLAMP = 100 nF;
RCLAMP = 1 Ω
4) VCC2 = 15 V; VEE2
= 0 V; VCLAMP = 2 V;
CCLAMP = 100 nF;
RCLAMP = 0.1 Ω
4) VCC2 = 15 V; VEE2
= 0 V; VCLAMP = 5 V;
CCLAMP = 100 nF;
RCLAMP = 0.1 Ω
LOAD = 100 pF
LOAD = 100 pF
delay during soft-off
Integrated diode CLAMP vs. VCC2 clamping test
only valid for direct clamping: IN = High, OUT = High
only valid for clamp pre-driver output: IN = Low, OUT = Low
Parameter is not subject to production test - verified by design/characterization
CLAMP mode reaction time specified with 3.3 kΩ pull-up from CLAMP to 3.3 V, from CLAMP threshold until
reaching 0.8 V (falling) at CLAMP pin
Datasheet
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5 Electrical parameters
6)
CLAMP driver mode reaction time specified from CLAMP threshold until reaching 0.8 V (rising) at
CLAMP(DRV) pin
5.4.6
Dynamic characteristics
Dynamic characteristics are measured with VVCC1 = 5 V, VVCC2 = 15 V and VVEE2 = -8 V unless specified otherwise.
Table 16
Dynamic characteristics
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or Test
Condition
Max.
Input pulse suppression
time IN
tINMIN
98
103
108
ns
–
Input pulse suppression
time RDYC/FLT_N for
enable / fault off
tRDYCMIN,
tFLT_NMIN
85
100
115
ns
–
Input pulse width RDYC
for FLT_N reset (Fault
clear time)
tCLRMIN
–
1.0
1.2
µs
Input IN to output
propagation delay ON
tPDON
226
244
270
ns
CLOAD = 100 pF, VIN =
70%, VOUT=20%
Input IN to output
propagation delay OFF
tPDOFF
218
236
262
ns
CLOAD = 100 pF, VIN =
30%, VOUT=80%
Input to output
tPDISTO
propagation delay
distortion (tPDOFF - tPDON)
-23
-8
7
ns
CLOAD = 100 pF
Input IN to output
propagation delay
distortion between any
devices (tPDON-tPDON) or
(tPDOFF-tPDOFF)
tPDD
–
–
30
ns
1) same conditions
State synchronization
time between input and
output
tSSIO
–
–
13
µs
1)
Input RDYC to output on
propagation delay
tPDRDYC
447
523
600
ns
CLOAD = 100 pF; IN
high; VRDYC = 70%,
VOUT=20%
Input RDYC or FLT_N
to Soft-off output
propagation delay
tPDRDYCS,
tPDFLT_NS
323
361
407
ns
CLOAD = 100 pF, VSignal
= 30%, VOUT=80%,
Soft-off function
ICSOFF,15
Input RDYC or FLT_N to
hard switch-off output
propagation delay
tPDRDYCH,
tPDFLT_NH
303
342
384
ns
CLOAD = 100 pF, VSignal
= 30%, VOUT=80%,
OFF function
Rise time 1ED3431M
tRISE
–
15
30
ns
CLOAD = 1 nF, VOUT:
20% to 80%
(VIN, VVCC1, VVCC2 and
VVEE2, CLOAD, TA)
(table continues...)
Datasheet
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Datasheet
5 Electrical parameters
Table 16
(continued) Dynamic characteristics
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or Test
Condition
Max.
Fall time 1ED3431M
tFALL
–
15
30
ns
CLOAD = 1 nF, VOUT:
80% to 20%
Rise time 1ED3461M
tRISE
–
15
30
ns
CLOAD = 2.2 nF, VOUT:
20% to 80%
Fall Time 1ED3461M
tFALL
–
15
30
ns
CLOAD = 2.2 nF, VOUT:
80% to 20%
Rise Time 1ED3491M
tRISE
–
15
30
ns
CLOAD = 3.3 nF, VOUT:
20% to 80%
Fall Time 1ED3491M
tFALL
–
15
30
ns
CLOAD = 3.3 nF, VOUT:
80% to 20%
1)
Parameter is not subject to production test - verified by design/characterization
5.4.7
Desaturation protection
All parameters valid for VCC1 = 5 V, VCC2 = 15 V, and VEE2 = 0 V unless specified otherwise.
Table 17
Desaturation protection
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or Test
Condition
Max.
DESAT charge current
IDESATC
470
500
525
µA
VDESAT = 0 V
DESAT voltage divider
resistance
RDVD
259
312.5
366
kΩ
between DESAT and
GND2 pins
DESAT clamp and
discharge ON
resistance
RDSON,D
–
7.7
25.0
Ω
IDESATD = 200 mA
DESAT threshold level
VDESAT
8.88
9.18
9.48
V
–
DESAT leading edge
blanking time
tDESATleb,d
356
400
444
ns
tDESATleb,s
597
650
703
ns
tDESATleb,l
1077
1150
1223
ns
ADJB depending, VON
20% rising to VDESAT
= 1 V, CLOAD = 100 pF,
CDESAT = 2 pF,
225
263
ns
ADJB = VCC1
ADJB depending
DESAT filter time
(default)
tDESATfilter,def 190
DESAT filter time (ADJB tDESATfilter,A
adjustable)
tDESATfilter,B
1476
1575
1684
ns
1667
1775
1895
ns
tDESATfilter,C
1857
1975
2105
ns
tDESATfilter,D
2238
2375
2526
ns
tDESATfilter,E
2619
2775
2947
ns
tDESATfilter,F
3000
3175
3368
ns
(table continues...)
Datasheet
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Datasheet
5 Electrical parameters
Table 17
(continued) Desaturation protection
Parameter
Symbol
Values
Min.
DESAT sense to FLT_N
low delay
Typ.
Max.
Note or Test
Condition
tDESATfilter,G
3381
3575
3789
ns
tDESATfilter,H
3762
3975
4211
ns
tDESATFLT
623
743
883
ns
VFLT_N = 30%, IFLT _N
= 5 mA, tDESATfilter,def,
CFLT_N = 100 pF
287 +
tDESATfilter
333 +
tDESATfilter
382 +
tDESATfilter
ns
VOUT = 80%, CLOAD =
100 pF, ICSOFF,15
DESAT sense to OFF low tDESATOUTS
delay, Soft-off
Datasheet
Unit
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Datasheet
5 Electrical parameters
5.4.8
Soft-off current source
Soft-off current source values specified at OFF pin at VOFF = 3 V with unipolar supply of VVCC2 = 15 V.
Table 18
Current source turn-off
Parameter
Symbol
Values
Min.
Soft-off current source
current 1ED3431M
Soft-off current source
current 1ED3461M
Typ.
Unit
Note or Test
Condition
depends on resistor
value at ADJA
Max.
ICSOFF,0
10
15
19
mA
ICSOFF,1
24
29
36
mA
ICSOFF,2
35
44
52
mA
ICSOFF,3
47
58
70
mA
ICSOFF,4
58
73
87
mA
ICSOFF5
70
87
105
mA
ICSOFF,6
82
102
122
mA
ICSOFF,7
93
116
140
mA
ICSOFF,8
105
131
157
mA
ICSOFF,9
116
146
175
mA
ICSOFF,10
128
160
192
mA
ICSOFF,11
140
175
210
mA
ICSOFF,12
151
189
227
mA
ICSOFF,13
163
204
245
mA
ICSOFF,14
175
218
262
mA
ICSOFF,15
186
233
280
mA
ICSOFF,0
22
29
36
mA
ICSOFF,1
45
58
72
mA
ICSOFF,2
70
87
105
mA
ICSOFF,3
93
116
140
mA
ICSOFF,4
116
146
175
mA
ICSOFF,5
140
175
210
mA
ICSOFF,6
163
204
245
mA
ICSOFF,7
186
233
280
mA
ICSOFF,8
210
262
314
mA
ICSOFF,9
233
291
349
mA
ICSOFF,10
256
320
384
mA
ICSOFF,11
280
349
419
mA
ICSOFF,12
303
379
454
mA
ICSOFF,13
326
408
489
mA
ICSOFF,14
349
437
524
mA
depends on resistor
value at ADJA
(table continues...)
Datasheet
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Datasheet
5 Electrical parameters
Table 18
(continued) Current source turn-off
Parameter
Symbol
Values
Min.
Soft-off current source
current 1ED3491M
Typ.
373
466
559
mA
ICSOFF,0
34
44
54
mA
ICSOFF,1
70
87
105
mA
ICSOFF,2
105
131
157
mA
ICSOFF,3
140
175
210
mA
ICSOFF,4
175
218
262
mA
ICSOFF,5
210
262
314
mA
ICSOFF,6
245
306
367
mA
ICSOFF,7
280
349
419
mA
ICSOFF,8
314
393
472
mA
ICSOFF,9
349
437
524
mA
ICSOFF,10
384
480
577
mA
ICSOFF,11
419
524
629
mA
ICSOFF,12
454
568
681
mA
ICSOFF,13
489
612
734
mA
ICSOFF,14
524
655
786
mA
ICSOFF,15
559
699
839
mA
Over-temperature protection
Table 19
Over-temperature protection
Symbol
Values
Min.
Over-temperature
protection level
1)
Max.
ICSOFF,15
5.4.9
Parameter1)
Unit
TOTPOFF
150
Typ.
160
Unit
Max.
170
Note or Test
Condition
depends on resistor
value at ADJA
Note or Test
Condition
°C
Parameter is not subject to production test - verified by design/characterization
Datasheet
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Datasheet
6 Insulation characteristics
6
Insulation characteristics
The following isolation classes are available for the 1ED34x1Mc12M family (X3 Analog).
Table 20
Product isolation classes
Product name
Marking
Insulation characteristics
Values specified in
UL values
1ED34x1MU12M
34x1MU12
UL 1577 certified insulation
-
Table 23
1ED34x1MC12M
34x1MC12
Reinforced insulation
Table 22
Table 23
Table 21
Safety limiting values
This coupler is suitable for rated insulation only within the given safety ratings. Compliance with the safety
ratings shall be ensured by means of suitable protective circuits.
Description
Symbol
Characteristic
Unit
Maximum ambient safety temperature
TS
150
°C
PSI
100
mW
PSO
1000
mW
Maximum input-side power dissipation at TA = 25°C
Maximum output-side power dissipation at TA
= 25°C1)
Maximum driver output current (ON, OFF)2)
1ED3431MC
1ED3461MC
1ED3491MC
1)
2)
IOUT
A
2.4
4.8
7.2
IC output-side power dissipation is derated linearly at 8 mW/°C above 65 °C
Maximum pulse length of t = 5 µs
6.1
Certified according to VDE 0884-11 reinforced insulation (Certificate
no. 40053980)
Valid for parts with part name 1ED34x1MC12M, x indicate different variants.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety
ratings shall be ensured by means of suitable protective circuits.
Table 22
Reinforced insulation according to VDE 0884-11
Description
Symbol
Characteristic
Unit
Installation classification per EN 60664-1, Table 1
for rated mains voltage ≤ 150 V (rms)
for rated mains voltage ≤ 300 V (rms)
for rated mains voltage ≤ 600 V (rms)
for rated mains voltage ≤1000 V (rms)
–
I-IV
I-IV
I-III
I-II
Climatic classification
40/125/21
–
Pollution degree (EN 60664-1)
2
–
Minimum external clearance
CLR
>8
mm
Minimum external creepage
CPG
>8
mm
Minimum comparative tracking index
CTI
400
–
(table continues...)
Datasheet
41
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Datasheet
6 Insulation characteristics
Table 22
(continued) Reinforced insulation according to VDE 0884-11
Description
Symbol
Characteristic
Unit
Apparent charge, method a
Vpd(ini),a = VIOTM, Vpd(m) = 1.6 × VIORM, tini = 1 min
qC
109
Ω
Maximum rated transient isolation voltage
VIOTM
8000
V (peak)
Maximum repetitive insulation voltage
VIORM
1767
V (peak)
Maximum surge isolation voltage for reinforced isolation
VTEST = VIOSM × 1.6
VIOSM
6875
V (peak)
Insulation capacitance
CIO
1.7
pF
6.2
Recognized under UL 1577 (File E311313)
Table 23
Recognized under UL 1577
Description
Symbol
Characteristic
Unit
Insulation withstand voltage/1 min
VISO
5700
V (rms)
Insulation test voltage/1 s
VISO, TEST
6840
V (rms)
Datasheet
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Datasheet
7 Package information
Package information
1)
1)
6.4
7.5
0.35 x 45°
°
8
0°...
0.15±0.05
Stand Off
(2.35)
2.65 Max
7
(0.25)
Seating plane
Coplanarity
9
1
8
Bottom View
9
16
8
1
10.3
16
0.7±0.2
Pin1 Marking
0.65
2)
0.33±0.08
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width
All dimensions are in units mm
The drawing is in compliance with ISO 128-30, Projection Method 1 [
]
Figure 24
Datasheet
PG-DSO-16-28/33 - 300 mil 16-pin fine pitch plastic green dual small outline package
43
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Datasheet
8 Application notes
8
Application notes
8.1
Reference layout for thermal data
Figure 25
Reference layout for thermal data (Two layer PCB; copper thickness 35 μm; left: top
layer; right: bottom layer)
The PCB layout represents the reference layout used for the thermal characterization. Pins 1 and 8 (GND1)
and pins 9 and 16 (VEE2) require ground plane connections for achieving maximum power dissipation. The
1ED34x1Mc12M family (X3 Analog) is conceived to dissipate most of the heat generated through these pins.
8.2
Printed circuit board guidelines
Following factors should be taken into account for an optimum PCB layout.
•
Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits.
•
The same minimum distance between two adjacent high-side isolated parts of the PCB should be
maintained to increase the effective isolation and reduce parasitic coupling.
•
In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be
kept as short as possible.
Revision history
Revision history
Reference
Description
v2.1
(2021-02-15)
•
•
•
•
(2021-09-01)
New version number schema: Target/Preliminary datasheet: 0.XY; Final datasheet: 1.XY
1.10
(2021-10-08)
•
•
•
Datasheet
Change footnotes to table notes
added param VOFFSET
update package drawing to latest revision
update certification status
Certification information update (VDE certification)
Fix unit and conditions in certification table according to standards
Related product table update
44
1.10
2021-10-08
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2021-10-08
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2021 Infineon Technologies AG
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
IFX-fiz1584344472005
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