1ED44173N01BXTSA1

1ED44173N01B Single-channel low-side MOSFET gate driver IC with fast OCP Features             Potential applications Over-current detection (OCP) with negative voltage input -0.246 V over-current threshold with accurate ±5% tolerance Single pin for fault output and enable Programmable fault clear time Under voltage lockout for MOSFETs CMOS Schmitt-triggered inputs 3.3 V, 5 V and 15 V input logic compatible 25 V VCC voltage supply support (max) Output in phase with input -10 VDC negative Input capability of OCP pin 3 kV ESD HBM RoHS compliant      Digitally controlled PFC Home appliances Air conditioner Industrial applications General purpose low-side gate driver for singlesingle-ended topologies Description The 1ED44173N01B is a low-voltage, power MOSFET non-inverting gate driver. Proprietary latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output. The output driver features a current buffer stage. The 1ED44173N01B has OCP pin for over current protection sense and a FAULT status output (Once it is active, EN/FLT pin is internally pulled down). The EN/FLT needs to be outside pulled up to provide normal operation, pulling EN/FLT low disable the driver. Internal circuitry on VCC pin provides an under voltage lockout protection that holds output low until VCC supply voltage is within operating range. Vin+ Vcc Vout 1ED44173N01B Vdd 4 RFLTC 5 EN/FLT I/O2 OUT 3 Vcc COM 2 OCP 1 µC 6 I/O1 IN CFLTC Rcs Gnd Figure 1 (Refer to lead assignments for correct pin configuration). This diagram show electrical connections only. Please refer to our application notes and design tips for proper circuit board layout. Vin- Typical application Ordering information Product type 1ED44173N01B Package PG-SOT23-6-3 Standard pack Form Orderable part number Quantity Tape and Reel 3000 1ED44173N01BXTSA1 Product validation Qualified for industrial applications according to the relevant tests of JEDEC JESD47/22 and J-STD-020. Datasheet Please read the Important Notice and Warnings at the end of this document www.infineon.com/gdLowSide Page 1 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection Table of contents 1 Block diagram........................................................................................................................ 3 2 2.1 2.2 Pin configuration and functionality .......................................................................................... 4 Pin configuration ..................................................................................................................................... 4 Input/output logic truth table ................................................................................................................ 5 3 Qualification information........................................................................................................ 6 4 4.1 4.2 4.3 4.4 Electrical parameters ............................................................................................................. 7 Absolute maximum ratings ..................................................................................................................... 7 Recommended operating conditions..................................................................................................... 7 Static electrical characteristics ............................................................................................................... 8 Dynamic electrical characteristics .......................................................................................................... 8 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Application information and additional details .......................................................................... 9 MOSFET gate driver ................................................................................................................................. 9 Switching and timing relationships ........................................................................................................ 9 Input logic compatibility ....................................................................................................................... 10 Undervoltage lockout (VCC) ................................................................................................................... 10 Over current protection (OCP) .............................................................................................................. 11 Fault reporting and programmable fault clear timer .......................................................................... 12 Enable input .......................................................................................................................................... 12 6 Package outline: PG-SOT23-6-3 .............................................................................................. 14 7 Tape and reel details ............................................................................................................. 15 8 Part marking information ...................................................................................................... 16 9 Similar products ................................................................................................................... 17 10 Related documents ............................................................................................................... 18 Revision history............................................................................................................................. 19 Datasheet www.infineon.com/gdLowSide 2 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection 1 Block diagram Vcc Vcc UVLO & Filter 1 4 3.3 V PWM disable logic 2.15 M EN/FLT 3 OUT 2 COM 1 OCP 5 Fault output UVLO QFLT VOCTH OCP IN Figure 2 6 Filter Block diagram Datasheet www.infineon.com/gdLowSide 3 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection 2 Pin configuration and functionality 2.1 Pin configuration Table 1 Pin configuration Pin no. Name Function 1 OCP Current sense input 2 COM Ground 3 OUT Gate drive output 4 VCC 5 EN/FLT 6 IN Supply Voltage Enable, fault reporting and fault clear time program pin, three functions: 1. Logic input to enable I/O functionality. I/O logic functions when ENABLE is high. 2. Fault reporting function like over-current or undervoltage lockout, this pin has negative logic and an open-drain output. 3. Fault clear time program with external resistor and capacitor. Logic input for gate driver output (OUT), in phase 4 Vcc 5 EN/FLT 6 Figure 3 IN OUT 3 COM 2 OCP 1 PG-SOT23-6-3 (top view) Datasheet www.infineon.com/gdLowSide 4 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection 2.2 Input/output logic truth table Table 2 Input/output logic truth table IN L H UVLO1) H H OCP2) L L 𝐄𝐍/𝐅𝐋𝐓 3) H H OUT L H X L X L L X H H L L OUT = L, EN/FLT= L, (Over current protection will disable input signals until EN/FLT returns to high level.) X H X L L OUT = L (Externally pull down EN/FLT pin will disable I/O logic until EN/FLT returns to high level.) 1) 2) 3) Note OUT = L OUT = H OUT = L, EN/FLT= L, (UVLO protection will disable input signals until EN/FLT returns to high level.) UVLO “L” state is under-voltage protection. OCP “H” state is over-current protection. EN/FLT “H” state is EN/FLT pin externally pulling up and internally pull down MOSFET (QFLT) is off. (See Block Diagram.) Datasheet www.infineon.com/gdLowSide 5 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection 3 Qualification information Industrial 1) Comments: This family of ICs has passed JEDEC’s Industrial Qualification level qualification. Consumer qualification level is granted by extension of the higher Industrial level. MSL1 2) 260°C Moisture sensitivity level (per JEDEC standard J-STD-020) 1.5 kV Charged device model (per ANSI/ESDA/JEDEC standard JS-002) ESD 3 kV Human body model (per ANSI/ESDA/JEDEC standard JS-001) Class II, Level A IC latch-up test (per JESD78) RoHS compliant Yes 1) Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales representative for further information. 2) Higher MSL ratings may be available for the specific package types listed here. Please contact your Infineon sales representative for further information. Datasheet www.infineon.com/gdLowSide 6 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection 4 Electrical parameters 4.1 Absolute maximum ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. The device may not function or not be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Table 3 Symbol VCC VO VOCP VEN/FLT VIN PD RthJA TJ TS TL 4.2 Absolute maximum ratings Definition Min Max Fixed supply voltage Output voltage (OUT) Voltage at current sense pin (OCP) Voltage at enable and fault reporting pin (EN/FLT) Logic input voltage ( IN ) Package power dissipation @ TA ≤ 25°C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) – 0.3 - 0.3 – 10 – 0.3 – 10 — — – 40 – 55 — 25 VCC + 0.3 VCC +0.3 VCC + 0.3 VCC + 0.3 0.5 250 150 150 260 PG-SOT23-6 Units V W °C/W °C Recommended operating conditions For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to COM unless otherwise stated in the table. Table 4 Symbol VCC VO VOCP VEN/FLT VIN TA Recommended operating conditions Definition Min Max Fixed supply voltage Output voltage Voltage at current sense pin (OCP) Voltage at enable and fault reporting pin (EN/FLT) Logic input voltage ( IN ) Ambient temperature 8.6 COM -5 0 –5 – 40 20 VCC VCC VCC VCC 125 Datasheet www.infineon.com/gdLowSide 7 of 20 Units V °C 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection 4.3 Static electrical characteristics VCC = 15V, TA = 25°C unless otherwise specified. The VINL, VINH, VENL, VENH, VOCTH, and IIN, IFLT parameters are referenced to COM and are applicable to input leads: IN, OCP and EN/FLT. The VO and IO parameters are referenced to COM and are applicable to the output lead: OUT. Table 5 Static electrical characteristics Symbol Definition VCCUV+ VCC supply undervoltage positive going threshold VCCUV- VCC supply undervoltage negative going threshold VCCUVH Vcc supply undervoltage lockout hysteresis VINL Logic “0” input voltage (OUT = LO) VINH Logic “1” input voltage (OUT = HI) VENL Logic “0” disable voltage VENH Logic “1” enable voltage VOH High level output voltage, VCC -VOUT VOL Low level output voltage, VOUT VOCTH Current limit threshold voltage IIN+ Logic “1” input bias current IN pin IINLogic “0” input bias current IN pin IQCC Quiescent VCC supply current IO+ Output sourcing short circuit pulsed current IOOutput sinking short circuit pulsed current IFLT EN/FLT pull down sinking current VACTSD 4.4 Active shut down voltage Min Typ Max Units Test Conditions 7.4 6.7 — 0.8 1.9 0.8 1.9 — — -259 35 -10 — 2 2 18 8.0 7.3 0.7 1.0 2.1 1.0 2.1 0.02 0.02 -246 50 -6 700 2.6 2.6 — 8.6 7.8 — 1.2 2.3 1.2 2.3 0.1 0.1 -233 70 — 1200 — — — mA — 2.0 2.3 V V IO = 2 mA IO = 2 mA mV µA A VIN = 5 V VIN = 0 V VIN = 0 V or 5 V VO = 0 V, PW ≤ 2 µs VO = 15 V, PW ≤ 2 µs VEN/FLT = 0.4 V VCC = open, IOUT-/IO- = 0.1 Dynamic electrical characteristics VCC = 15 V, TA = 25°C, and CL = 1000 pF unless otherwise specified. Table 6 Dynamic electrical characteristics Symbol Definition Min Typ Max Units ton toff tr tf Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time 27 27 — — 34 34 5 5 45 45 — — tDISA Disable propagation delay 27 34 45 tOCPDEL Over current protection propagation delay — 97 140 tOCPFLT OCP to low level EN/FLT signal delay — 97 150 tFLTC FAULT clear time 80 103 130 µs tBLK Over current protection blanking time 30 50 80 ns VCC supply UVLO filter time * — 2 — µs tvCCUV Test Conditions Figure 6 VIN pulse = 5 V ns Figure 12 VEN pulse = 5 V Figure 9, Figure 10 REN = 10 kΩ to VCC VOCP pulse = - 0.5 V Figure 9, Figure 10 Vdd = 3.3 V RFLTC = 1MΩ to Vdd, CFLTC = 150pF to COM RFLT = 0 Ω, CFLT = NC VOCP pulse = - 0.5 V Figure 8 *Parameter verified by design, not tested in production. Datasheet www.infineon.com/gdLowSide 8 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection 5 Application information and additional details Information regarding the following topics is included as subsections within this section of the datasheet. • MOSFET gate driver • Switching and timing relationships • Input logic compatibility • Undervoltage lockout protection • Over current protection (OCP) • Fault reporting and programmable fault clear timer • Enable input See the 1ED44173N01B Application Note AN2020-09 Low-side MOSFET driver with fast over current protection and fault/enable (negative current sense) for interface circuit examples and recommended layout guidelines. 5.1 MOSFET gate driver The 1ED44173N01B is designed to drive MOSFET power devices. Figure 4Error! Reference source not found. and Figure 5 i llustrate several parameters associated with the gate driver functionality of the driver. The output current of the driver, used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VOUT. Figure 4 Gate output sourcing current Figure 5 5.2 Switching and timing relationships Gate output sinking current The relationships between the input and output signals of the 1ED44173N01B are illustrated below Figure 6. From the figure, we can see the definitions of several timing parameters (i.e. ton, toff, tr, and tf) associated with this device. 50% 50% IN ton tr toff 90% OUT Datasheet www.infineon.com/gdLowSide tf 90% 10% 10% 9 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection Figure 6 5.3 Switching time waveforms Input logic compatibility The input of this IC is compatible with standard CMOS and TTL outputs. The 1ED44173N01B has been designed to be compatible with 3.3 V, 5 V and 15 V logic-level signals. The input high threshold (VINH) is typ. 2.1 V and low threshold (VINL) is typ. 1 V. Input hysteresis offers enhanced noise immunity. The 1ED44173N01B includes an important feature: wherein, whenever the input pin is in a floating condition, the output is held in the low state. This is achieved using GND pull-down resistors on the input pin. Figure 7 illustrates an input signal to the 1ED44173N01B, its input threshold values, and the logic state of the IC as a result of the input signal. Figure 7 5.4 IN input thresholds Undervoltage lockout (VCC) The 1ED44173N01B has internal UVLO protection feature on the VCC pin supply circuit blocks. When VCC bias voltage keeps lower than the VCCUV- threshold more than UVLO filter time (tVCCUV), the VCC UVLO feature holds the output low, regardless of the status of the IN input. At the same time, the internal MOSFET QFLT turns on and the EN/FLT pin is internally pulled down to COM. The EN/FLT output stays in the low state until the UVLO has been removed; once the UVLO is removed, the internal MOSFET QFLT turns off, and the voltage on the EN/FLT pin is charged up by external voltage Vdd. The length of the fault clear time period (t FLTC) is determined by exponential charging characteristics of the capacitor where the time constant is set by RFLTC and CFLTC. And when VCC is higher than VCCUV+ and longer than fault clear time (tFLTC), the OUT still keeps low until next input signal IN is high. (See Figure 8) The filter time (tVCCUV) of about 2μs helps to suppress noise from the UVLO circuit, so that negative going voltage spikes at the supply pin will avoid parasitic UVLO events. Datasheet www.infineon.com/gdLowSide 10 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection Vcc VCCUV+ VCCUV- IN tVCCUV OUT tFLTC QFLT off EN/FLT VENH QFLT off QFLT on Figure 8 5.5 VCC under voltage protection waveform definitions Over current protection (OCP) The 1ED44173N01B has a function of over current protection with a threshold VCSTH at the OCP pin input. The voltage at this pin is the negative voltage drop sensed across the system current sense resistor. It is up to minus 10 VDC negative input capability of OCP pin. To avoid false tripping due to the fast high current switch on transient that occurs at the switch on of a MOSFET resulting from the circuit parasitic capacitors, there is blanking interval which disables over current detection for the period of t BLK (Additional RC filter is recommended, if internal tBLK is not enough in the very noisy circuit.). After tBLK and the voltage of OCP pin is over VCSTH, the 1ED44173N01B causes fault logic to initiate a fault shutdown sequence. This sequence starts with the generation of a fault signal and internal MOSFET QFLT is turned on and EN/FLT pin is pulled down. At the same time the 1ED44173N01B terminates the present cycle, and the gate output is immediately pulled down with internal propagation delay (tOCPDEL), see the Figure 9 and Figure 10. Figure 9 is the diagram of 1ED44173N01B in boost application. And Figure 10 is the typical waveforms of the application.If the OCP fault condition is removed, the internal pull down NMOS of EN/FLT is released and EN/FLT will be pull up again with Vdd, but the output still keeps low until the next input signal IN is high. Vout AC RCS Vcc Vdd RFLTC µC 4 I/O2 5 I/O1 6 Vcc EN/FLT OUT 3 COM 2 OCP 1 RFLT Gnd Figure 9 1ED44173N01B IN CFLTC CFLT 1ED44173N01B in Boost application Datasheet www.infineon.com/gdLowSide 11 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection IN 50% OUT tOCPDEL OCP vOCTH tFLTC tOCPFLT EN/FLT QFLT off vENH 50% QFLT on Figure 10 5.6 OCP fault detection and fault clear waveforms Fault reporting and programmable fault clear timer The 1ED44173N01B provides an integrated fault reporting output and an adjustable fault clear timer. There are two situations that would cause the driver to report a fault via the EN/FLT pin. The first is an under voltage condition of VCC and the second is if the OCP pin recognizes a fault. Once the fault condition occurs, the EN/FLT pin is internally pulled to COM. The EN/FLT output stays in the low state until the fault condition has been removed and the internal pull down NMOS QFLT turns off, the voltage on the EN/FLT pin is charged up with external pull-up voltage. The length of the fault clear time period (tFLTC) is determined by exponential charging characteristics of the capacitor where the time constant is set by RFLTC and CFLTC. Figure 9 shows that RFLTC is connected between the external supply (Vdd) and the EN/FLT pin, while CFLTC is placed between the EN/FLT and COM pins. EN/FLT is weakly pulled up to 3.3 V reference voltage with 2.15 M resistor internally. So the length of the fault clear time period can be determined by using the formula below (If Vdd = 3.3 V). tFLTC = - ( 5.7 RFLTC x 2.15M VENH ) ) x CFLTC x In(1RFLTC + 2.15M Vdd Enable input 1ED44173N01B provides an enable functionality that allows to shutdown or to enable the output. When EN/FLT is pulled up (the enable voltage is higher than VENH) the output is able to operate normally, pulling EN/FLT low (the enable voltage is lower than VENL) the output is disable. The relationships between the input, output, and enable signals of the 1ED44173N01B are illustrated below in Figure 11~13. From these figures, we can see the definitions of several timing parameters and threshold voltages (i.e. tDISA, VENH and VENL) associated with this device. Datasheet www.infineon.com/gdLowSide 12 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection High IN IN VEN 50% EN/FLT OUT tDISA 90% OUT Figure 11 Input/output/enable pins timing diagram Figure 12 Figure 13 EN input thresholds Datasheet www.infineon.com/gdLowSide 13 of 20 EN pin switching time waveform 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection 6 Package outline: PG-SOT23-6-3 Outline dimensions Footprint dimensions Figure 14 Package outline Datasheet www.infineon.com/gdLowSide 14 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection 7 Tape and reel details Figure 15 Tape and reel dimensions Notes: For further details, please visit www.infineon.com/packages Datasheet www.infineon.com/gdLowSide 15 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection 8 Part marking information TOP MARKING Note: New part marking implementation beginning in 2021. Refer to Information Note 001/21 for details. Figure 16 Part marking information Datasheet www.infineon.com/gdLowSide 16 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection 9 Channels Similar products Typ. gate drive (Io+/Io-) Part number A 1 Max UVLO supply (on/off) voltage Typ. Logic and features prop. delay (on/off) V V ns 1.5 / 1.5 IRS44273L 25 10.2 / 9.2 50 / 50 0.8/1.75 1ED44176 25 11.9/11.4 50 / 50 2.6/2.6 1ED44175 25 11.9/11.4 50 / 50 IRS4426S 25 IRS44262S 20 IRS4427S Package options Single non-inverting channel SOT23-5L Dual OUT pins Single positive current sense PG-DSO-8 OCP, fault out and ENABLE Single negative current sense SOT23-6-3 OCP, fault out and ENABLE 50 / 50 Dual inverting channels SOIC-8L 50 / 50 Dual inverting channels SOIC-8L 25 50 / 50 Dual non-inverting channels SOIC-8L IRS4428S 25 50 / 50 2ED24427 24 10.2 / 9.2 2.3 / 3.3 2 10/10 Datasheet www.infineon.com/gdLowSide 11.5/10 17 of 20 40 / 55 Single inverting channel Single non-inverting channel Dual non-inverting channels with ENABLE SOIC-8L Power Pad DSO-8 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection 10 Related documents 1. AN2020-09 Low-side MOSFET driver with fast over current protection and fault/enable (negative current sense) 2. Datasheets of 1ED44175N01B and 1ED44176N01B Datasheet www.infineon.com/gdLowSide 18 of 20 1.1 2021-07-22 1ED44173N01B Single-channel low-side gate driver IC with over-current protection Revision history Document version 1.0 1.1 Date of release Description of changes Apr. 1, 2020 Jul. 22, 2021 Final Datasheet Updated the marking, adding a line for lot code to improve traceability. Updated the table of similar products (Deleted Gen.7 parts and added 2ED24427). Datasheet www.infineon.com/gdLowSide 19 of 20 1.1 2021-07-22 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2021-07-2222 Published by Infineon Technologies AG 81726 Munich, Germany © 2021 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? Email: erratum@infineon.com Document reference IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office (www.infineon.com). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application.