E i c e D R I V E R ™ 1E D B x 2 7 5 F
Single-channel isolated gate-dri ver ICs in 150 mil DSO package
Description
EiceDRIVER™ 1EDBx275F is a family of single-channel isolated gate-driver ICs, designed to drive Si, SiC and GaN
power switches.
1EDBx275F is available in an 8-pin DSO package with 4 mm input-to-output creepage distance; it provides
isolation by means of on-chip coreless transformer (CT) technology.
With tight timing specifications, 1EDBx275F is designed for fast-switching medium-to-high power systems.
Excellent common-mode rejection, low part-to-part skew, fast signal propagation and small package size make
1EDBx275F a superior alternative to high-side driving solutions using optocouplers or pulse transformers.
Features
• Single-channel isolated gate-driver
• 45 ns input-to-output propagation delay with excellent accuracy (+4/-6 ns)
• Separate low impedance source and sink outputs
• Fast clamping of parasitics-induced output overshoots under UVLO conditions
• Fast start-up times and fast recovery after supply glitches
• Optimized UVLO levels (4 V, 8 V, 12 V, 15 V) for Si, SiC and GaN transistors
• High common mode transient immunity (CMTI > 300 V/ns)
• Available in 8-pin 150mil DSO package
• Fully qualified according JEDEC for industrial grade applications
Isolation and safety certificates
•
UL 1577 with VISO = 3000 VRMS
Table 1
EiceDRIVER™ 1EDBx275F Portfolio
Part number
Peak source / sink current
UVLO ON / OFF
1EDB7275F
Isolation certification
Package
UL 1577
(VISO = 3000 VRMS)
PG-DSO-8
4.2 V / 3.9 V
1EDB8275F
8.0 V / 7.0 V
5.4 A / 9.8 A
(for VDDO = 15 V)
1EDB6275F
12.2 V / 11.5 V
1EDB9275F
14.9 V / 14.4 V
Controller VDDI
VDD
EiceDRIVER™ 1EDBx275F
VDDI
VDDO
High-side
MOSFET
VDDO
Rgon
PWM
IN+
OUT_SRC
IN-
OUT_SNK
CVDDI
CVDDO
Rgoff
GNDI
GND
GNDO
Input-to-output
isolation
Figure 1
Typical application
Final Data Sheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Potential Applications
•
•
•
Server, telecom and industrial Switch-Mode Power Supplies (SMPS)
EV power modules, motor drives and power tools
Solar power inverters and Uninterruptable Power Supplies (UPS)
Final Data Sheet
2
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Table of Contents
1
Pin configuration and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.3
2.4
2.5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power supply and Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output active clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CT communication and input to output data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3.1
3.2
3.3
3.4
3.5
Electrical characteristics and parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Isolation specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
Layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
6.1
6.2
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Driving 600 V CoolGaNTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Driving 650 V CoolSiCTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8
8.1
8.2
Package outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Device numbers and markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Final Data Sheet
3
5
5
5
5
6
6
6
7
7
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Pin configuration and description
1
Pin configuration and description
VDDI
1
8
GNDO
IN+
2
7
OUT_SNK
1EDBx275F
IN-
3
6
OUT_SRC
GNDI
4
5
VDDO
Figure 2
Pin configuration (top side view)
Table 2
Pin description
Pin Symbol
Description
1
VDDI
Input-side supply voltage (3 V to 15 V)
2
IN+
Non-inverting driver input (active high); if IN+ is low or left open, OUT_SNK is low
3
IN-
Inverting driver input (active low); if IN- is high or left open, OUT_SNK is low
4
GNDI
Input-side ground reference
5
VDDO
Output-side supply voltage (up to 20 V)
6
OUT_SRC
Driver output source, low-impedance switch to VDDO
7
OUT_SNK
Driver output sink, low-impedance switch to GNDO
8
GNDO
Output-side ground reference
For package drawing details see Chapter 8 Package outline dimensions.
Final Data Sheet
4
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Functional description
2
Functional description
2.1
Block diagram
A simplified functional block diagram for the EiceDRIVER™ 1EDBx275F is given in Figure 3.
1
UVLO
UVLO
IN+ 2
6 OUT_SRC
GNDI
Logic
TX
RX
VDDI
GNDI
Logic
VDDO
Input-to-output
isolation
IN- 3
GNDI 4
5 VDDO
Figure 3
Block diagram
2.2
Power supply and Undervoltage Lockout (UVLO)
7 OUT_SNK
Active
Clamp
8 GNDO
Due to the isolation between input and output side, two power domains with independent power management
are required. Undervoltage Lockout (UVLO) functions for both input and output supplies ensure a defined startup
and robust functionality under all operating conditions.
2.2.1
Input supply voltage
The input die is powered via VDDI and supports a wide supply voltage range from 3 V to 15 V. A ceramic bypass
capacitor must be placed between VDDI and GNDI in close proximity to the device; a minimum capacitance of
100 nF is recommended.
Power consumption to some extent depends on switching frequency, as the input signal is converted into a train
of repetitive current pulses to drive the coreless transformer. Due to the chosen robust encoding scheme the
average repetition rate of these pulses and thus the average supply current depends on the
switching frequency, fsw. However, for fsw < 500 kHz this effect is very small.
The Undervoltage Lockout function for the input supply VDDI ensures that, as long as VDDI is below UVLO (e.g. in
startup), no data is transferred to the output side and the gate driver output is held low (Safety Lock-down at
startup). When VDDI exceeds the UVLO level, the PWM input signal is transferred to the output side. If the output
side is ready (not in UVLO condition), the output reacts according to the logic input.
Final Data Sheet
5
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Functional description
2.2.2
Output supply voltage
The output die is powered via VDDO (up to 20 V). A ceramic bypass capacitor must be placed between VDDO and
GNDO in close proximity to the device. A minimum capacitance of 20 x Ciss (MOSFET input capacitance) is
recommended to ensure an acceptable ripple (5% of VDDO) on the supply pin.
The minimum supply voltage is set by the Undervoltage Lockout (UVLO) function. The gate-driver output can be
switched only, if the output supply voltage (VDDO) exceeds the output-side UVLO. Thus it can be guaranteed that
the switch transistor is not operated, if the driving voltage is too low to achieve a complete and fast transition to
the "on" state. Low driving voltage in fact could cause the power MOSFET to enter its saturation (ohmic) region
with potentially destructive power dissipation; the output UVLO ensures that the switch transistor always stays
within its Safe Operating Area (SOA). Versions with 4 V, 8 V, 12 V, 15 V UVLO thresholds for the output supply are
currently available; Table 3 shows the recommended UVLO levels for different Infineon power switch families.
Table 3
Recommended 1EDBx275F UVLO levels for typical use-cases
Switch family
TM
Logic level OptiMOS
TM
Normal level OptiMOS
CoolMOS
TM
650 V CoolSiCTM
600 V CoolGaN
2.2.3
TM
Switch part number example
Recommended 1EDBx275F
BSC010N04LS6, BSZ070N08LS5, ..
1EDB7275F (4 V UVLO)
BSC040N10NS5, BSZ084N08NS5, ..
1EDB8275F (8 V UVLO)
IPP60R099C7, IPB60R600P6, ..
1EDB8275F (8 V UVLO)
IMZA65R027M1H, IMW65R107M1H, ..
1EDB6275F (12 V UVLO for 15V VGS driving)
IGOT60R070D1, IGLD60R070D1, ..
1EDB9275F (15 V UVLO for 18V VGS driving)
1EDB7275F (4V UVLO)
Input stage
The logic driver output state is equal to the non-inverted or inverted input signal state at pins IN+ or IN-,
respectively. The non-inverting input IN+ is internally pulled down to a logic low voltage and the inverting input
is internally pulled up to a logic high voltage. This prevents any switching-on during power-up or in other
situations with insufficient supply voltage.
The input is compatible with LV-TTL levels and provide a hysteresis of typically 0.9 V. This hysteresis is
independent of the supply voltage VDDI.
Table 4 shows the IN+, IN- driver logic in case of sufficiently high supply voltage. Otherwise the outputs of the
driver are determined by the Undervoltage Lockout (UVLO) and Output Active Clamping functionalities as shown
in Table 5.
Table 4
Logic table in case of sufficient bias power
Inputs
2.3
IN+
IN-
H
L
x
H
L
x
Supplies
Outputs
VDDI, VDDO
OUT
H
>UVLOVDDx,on (active)
Note
–
L
The output is disabled via IN- (active low)
L
The output is disabled via IN+ (active high)
Driver output
The rail-to-rail output stage realized with complementary MOS transistors is able to provide a typical 5.4 A
sourcing and 9.8 A sinking peak current for a 15 V supply. The low on-resistance coming together with high driving
current is particularly beneficial for fast switching of very large MOSFETs. With a Ron of 0.95 Ω for the sourcing
pMOS and 0.48 Ω for the sinking nMOS transistor the driver can in most applications be considered as a nearly
Final Data Sheet
6
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Functional description
ideal switch. The p-channel sourcing transistor enables real rail-to-rail behavior without suffering from the
voltage drop unavoidably associated with nMOS source follower stages.
In case of floating inputs or insufficient supply voltage not exceeding the UVLO thresholds, the driver output is
actively clamped to the "low" level (GNDO).
2.4
Output active clamping
The Undervoltage Lockout (UVLO) ensures no driver operation for supplies below the UVLO thresholds. However,
this is not sufficient to guarantee that the output of the driver is kept low. Transient-induced current on the
MOSFETs side may pull-up the output node of the driver and the gate voltage causing an unwanted turn-on of the
switch; this is particularly critical in systems using bootstrapping since, during start-up, the supply of the highside channel is delayed, while the low-side MOSFETs is already switching. In resonant topologies (as LLC), the
half-bridge switching node may be pulled up after the turn-off of the low-side switch. When this is turned on
again, the dv/dt induced increase of the high-side gate voltage cannot be clamped by the drivers RDSON,sink if the
the boostrap supply is not yet available.
With a fast active clamping circuit in the output stage, EiceDRIVER™ 1EDBx275F ensures safe operation in all
UVLO situations. This structure allows fast reaction and effective clamping of the output pins (OUT). The exact
reaction time depends on the output supply (VDDO) and on the output voltage levels; however, already for very low
supply levels (~1 V), the active clamping is able to react in some tens of ns.
Undervoltage Lockout together with the Output Active Clamping ensure that the output is actively held low in
case of unsufficient output-side supply voltage.
Table 5
Logic table in case of insufficient supply voltages
Inputs
2.5
Supplies
Output
INx
VDDI
VDDO
OUT
x
> UVLOVDDI,on
1.2 V < VDDO< UVLOVDDO,on
L
CT communication and input to output data transmission
A coreless transformer (CT) based communication module is used for PWM signal transfer between input and
output. A proven high-resolution pulse repetition scheme in the transmitter combined with a watchdog timeout
at the receiver side enables recovery from communication fails and ensures safe system shutdown in failure
cases.
Final Data Sheet
7
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Electrical characteristics and parameters
3
Electrical characteristics and parameters
The absolute maximum ratings are listed in Table 6. Stresses beyond these values may cause permanent damage
to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
3.1
Absolute maximum ratings
Table 6
Absolute maximum ratings
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Note or Test Condition
Input supply voltage
VDDI
-0.3
–
17
V
–
Output supply voltage
VDDO
-0.3
–
22
V
–
Voltage at pins IN+, IN-
VIN
-0.3
–
17
V
–
-5
–
–
V
transient for 50 ns
VDDO-24
–
VDDO+0.3
V
OUT = low, DC
VDDO-24
–
VDDO+2
V
OUT = low,
transient for 200 ns
-0.3
–
24
V
OUT = high, DC
-2
–
24
V
OUT = high,
transient for 200 ns
Voltage at pin OUT_SRC
Voltage at pin OUT_SNK
VOUT_SRC
VOUT_SNK
Reverse current peak at pin
OUT_SRC
ISRC_rev
-5
–
–
Apk
transient for 500 ns
Reverse current peak at pin
OUT_SNK
ISNK_rev
–
–
5
Apk
transient for 500 ns
Junction temperature
TJ
-40
–
150
°C
–
Storage temperature
TSTG
-55
–
150
°C
–
Soldering temperature
TSOL
–
–
260
°C
reflow / wave soldering 1)
VESD_CDM
–
–
0.5
kV
Charged Device Model
(CDM) 2)
VESD_HBM
–
–
2
kV
Human Body Model
(HBM) 3)
ESD capability
1) according to JESD22A111
2) according to ESD-CDM: ANSI/ESDA/JEDEC JS-002
3) according to ESD-HBM: ANSI/ ESDA/JEDEC JS-001 (discharging 100 pF capacitor through 1.5 kΩ resistor)
Final Data Sheet
8
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Electrical characteristics and parameters
3.2
Thermal characteristics
Table 7
Thermal characteristics at TA= 25°C
Parameter
Symbol
Values
Unit Note or Test Condition
Min.
Typ.
Max.
Thermal resistance junctionambient 1)
RthJA25
–
116
–
K/W
Thermal resistance junctioncase (top) 2)
RthJC25
–
54
–
K/W
Thermal resistance junctionboard 3)
RthJB25
–
45
–
K/W
Characterization parameter
junction-top 4)
ΨthJT25
–
9
–
K/W
Characterization parameter
junction-board 4)
ΨthJB25
–
36
–
K/W
200mW output power
1) obtained by simulating a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in
JESD51-2a
2) obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close
description can be found in the ANSI SEMI standard G30-88
3) obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in
JESD51-8
4) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining
Rth, using a procedure described in JESD51-2a (sections 6 and 7)
3.3
Operating range
Table 8
Operating range
Parameter
Symbol
Values
Unit Note or Test Condition
Min.
Typ.
Max.
Input supply voltage
VDDI
3.0
–
15
V
Min. defined by UVLO
Output supply voltage
VDDO
4.5
–
20
V
for 1EDB7275F
8.5
–
20
V
for 1EDB8275F
12.8
–
20
V
for 1EDB6275F
15.5
–
20
V
for 1EDB9275F
Logic input voltage at pins IN+,
IN-
VIN
-0.3
–
15
V
–
Junction temperature
TJ
-40
–
150
°C
1)
Ambient temperature
TA
-40
–
125
°C
–
1) continuous operation above 125°C may reduce lifetime
Final Data Sheet
9
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Electrical characteristics and parameters
3.4
Electrical characteristics
Unless otherwise noted the electrical characteristics are given for VDDI = 3.3 V, VDDO = 12 V (VDDO = 18 V for
1EDB6275F, 1EDB9275F) and no load.
Typical values are given at TJ = 25°C. Min. and max. values are the lower and upper limits valid within the full
operating temperature range.
Table 9
Power supply
Parameter
Symbol
IVDDI quiescent current
IVDDO quiescent current
Table 10
Values
Unit
Note or Test Condition
1
mA
no switching
0.65
0.85
mA
OUT = low, no switching,
VDDO = 12 V
–
0.72
1.0
mA
OUT = low, no switching,
VDDO = 18 V
-
0.84
1.0
mA
OUT = high, no switching,
VDDO = 12 V
Min.
Typ.
Max.
–
0.85
–
IVDDIq
IVDDOq
Undervoltage Lockout VDDI
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Undervoltage Lockout (UVLO)
turn-on threshold VDDI
UVLOVDDI,on
2.7
2.85
3.0
V
–
Undervoltage Lockout (UVLO)
turn-off threshold VDDI
UVLOVDDI,off
–
2.65
–
V
–
UVLO threshold hysteresis VDDI
UVLOVDDI, hys
0.15
0.2
0.25
V
–
Table 11
Undervoltage Lockout VDDO for 1EDB7275F (4 V UVLO option)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Undervoltage Lockout (UVLO)
turn on threshold VDDO
UVLOVDDO, on
4.0
4.2
4.4
V
–
Undervoltage Lockout (UVLO)
turn off threshold VDDO
UVLOVDDO, off
–
3.9
–
V
–
UVLO threshold hysteresis
VDDO
UVLOVDDO, hys
0.2
0.3
0.4
V
–
Final Data Sheet
10
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Electrical characteristics and parameters
Table 12
Undervoltage Lockout VDDO for 1EDB8275F (8 V UVLO option)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Undervoltage Lockout (UVLO)
turn on threshold VDDO
UVLOVDDO, on
7.6
8.0
8.4
V
–
Undervoltage Lockout (UVLO)
turn off threshold VDDO
UVLOVDDO, off
–
7.0
–
V
–
UVLO threshold hysteresis
VDDO
UVLOVDDO, hys
0.7
1
1.3
V
–
Table 13
Undervoltage Lockout VDDO for 1EDB6275F (12 V UVLO option)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Undervoltage Lockout (UVLO)
turn on threshold VDDO
UVLOVDDO, on
11.7
12.2
12.7
V
–
Undervoltage Lockout (UVLO)
turn off threshold VDDO
UVLOVDDO, off
–
11.5
–
V
–
UVLO threshold hysteresis
VDDO
UVLOVDDO, hys
0.5
0.7
0.9
V
–
Table 14
Undervoltage Lockout VDDO for 1EDB9275F (15 V UVLO option)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Undervoltage Lockout (UVLO)
turn on threshold VDDO
UVLOVDDO, on
14.4
14.9
15.4
V
–
Undervoltage Lockout (UVLO)
turn off threshold VDDO
UVLOVDDO, off
–
14.4
–
V
–
UVLO threshold hysteresis
VDDO
UVLOVDDO, hys
0.3
0.5
0.7
V
–
Table 15
Logic inputs IN+, IN-
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Input voltage threshold for
transition LH
VINH
1.9
2.2
2.5
V
–
Input voltage threshold for
transition HL
VINL
1
1.3
1.6
V
–
Input voltage threshold
hysteresis
VIN_hys
–
0.9
–
V
–
High-level input leakage
current at pin IN+
IIN+,H
–
40
70
µA
Final Data Sheet
11
IN+ tied to VDDI
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Electrical characteristics and parameters
Table 15
Logic inputs IN+, IN- (cont’d)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Low-level input leakage
current at pin IN-
IIN-,L
-55
-40
–
µA
IN- tied to GNDI
Input pull-down resistor
RIN,PD
–
75
–
kΩ
–
Input pull-up resistor
RIN,PU
–
75
–
kΩ
–
Table 16
Static output characteristics
Parameter
Symbol
High-level (sourcing) output
resistance
Ron_SRC
Peak sourcing output current 1)
Low-level (sinking) output
resistance
Peak sinking output current 1)
Values
Min.
Typ.
Max.
0.52
0.95
1.70
Unit
Ω
ISNK = 50 mA
–
5.2
–
A
VDDO = 12 V, VOUT = 0 V;
see Figure 23,
Figure 24
–
5.6
–
A
VDDO = 18 V, VOUT = 0 V;
see Figure 23,
Figure 24
0.31
0.48
0.88
Ω
ISRC = 50 mA
–
-9.2
–
A
VOUT = VDDO = 12 V; see
Figure 23, Figure 24
–
-10.2
–
A
VOUT = VDDO = 18 V; see
Figure 23, Figure 24
ISRC_pk
Ron_SNK
Note or
Test Condition
ISNK_pk
1) parameter not subject to production test - verified by design / characterization
Table 17
Dynamic characteristics
Parameter
IN+ /IN- to output propagation
delay
Part-to-part skew
Pulse width distortion
|tPDoff - tPDon| 2)
Rise time 3)
Final Data Sheet
Symbol
Values
Unit
Note or
Test Condition
Min.
Typ.
Max.
tPDon, tPDoff
41
45
51
ns
see Figure 4
∆tPDon,p-p
–
–
2
ns
1)
∆tPDoff,p-p
–
–
2
ns
1)
tPWD
–
–
2
ns
see Figure 5
–
6.5
12
ns
VDDO = 12 V, CLOAD =
1.8 nF, see Figure 6
–
8.3
16
ns
VDDO = 18 V, CLOAD =
1.8 nF, see Figure 6
trise
12
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Electrical characteristics and parameters
Table 17
Dynamic characteristics (cont’d)
Parameter
Symbol
Values
Unit
Note or
Test Condition
Min.
Typ.
Max.
–
4.5
8
ns
VDDO = 12 V, CLOAD =
1.8 nF, see Figure 6
–
5
9
ns
VDDO = 18 V, CLOAD =
1.8 nF, see Figure 6
tPW
15
19
23
ns
see Figure 7
tSTART,VDDI
–
3
–
µs
see Figure 8
tSTOP,VDDI
–
300
–
ns
see Figure 8
tSTART,VDDO
–
5
–
µs
see Figure 9
3)
tSTOP,VDDO
–
125
–
ns
see Figure 9
Activation time of output
clamping in UVLO condition 3)
tCLAMP,OUT
–
20
–
ns
see Figure 10
Fall time 3)
tfall
Minimum input pulse width
that changes output state
Input-side start-up time 3)
Input-side deactivation time
3)
Output-side start-up time 3)
Output-side deactivation time
1) The parameter gives the difference in propagation delay between different samples switching in the same direction
under same conditions, including same ambient temperature
2) The parameter gives the maximum difference between on and off propagation delay shown from the same sample over
the operating temperature range
3) parameter not subject to production test - verified by design / characterization
Table 18
Common Mode Transient Immunity (CMTI)
Parameter
Symbol
Values
Unit
Note or Test Condition
–
V/ns
VCM = 1500 V; IN- tied to GNDI,
IN+ tied to VDDI (logic high inputs)
–
–
V/ns
VCM = 1500 V; IN- tied to GNDI, IN+
tied to GNDI (logic low inputs)
–
–
V/ns
VCM = 1500 V; IN- tied to GNDI,
dynamic IN+ (10 MHz square wave)
Min.
Typ.
Max.
|CMStatic,H|
300
–
|CMStatic,L|
300
Dynamic Common Mode
|CMDynamic|
Transient Immunity 1) 3)
300
Static Common Mode
Transient Immunity 1) 2)
1) minimum slew rate of a common mode voltage that is able to cause a wrong output signal
2) verified by characterization according to VDE0884-11 standard definitions and test-methods
3) verified by characterization with ground reference for the common mode pulse generator connected to the coupler
input-side ground to reflect real applications requirements
Final Data Sheet
13
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Electrical characteristics and parameters
3.5
Isolation specifications
This coupler is suitable for rated insulation only within the given safety limiting values. Compliance with the
safety limiting values shall be ensured by means of suitable protective circuits.
Table 19
Input-to-output isolation specifications
Parameter
UL1577
Unit
Note or Test Condition
Nominal input-to-output
clearance 1)
CLR
4.0
mm
Shortest distance in air between any
input pin and any output pin
Nominal input-to-output
creepage 1)
CRP
4.0
mm
Shortest distance over package surface
between any input pin and any output
pin
Comparative tracking index
CTI
> 400
< 600
V
According to DIN EN 60112 (VDE 030311)
Material group
–
II
–
According to IEC 60112
Pollution degree
–
2
–
According to IEC 60664-1
Overvoltage category per
IEC 60664-1
–
I -IV
–
Rated mains voltage ≤ 150 VRMS
–
I -III
–
Rated mains voltage ≤ 300 VRMS
–
I -II
–
Rated mains voltage ≤ 600 VRMS
–
40/125
/21
–
–
Climatic category
2)
Symbol Value
Input-to-output isolation
voltage
VISO
3000
VRMS
VTEST = VISO for t = 60 s (qualification);
VTEST = 1.2 x VISO for t = 1 s (100%
productive tests)
Maximum rated transient
isolation voltage
VIOTM
4242
Vpk
VTEST = 1.2 x VIOTM for tini = 1 s
qPD
tPWmin
tPW < tPWmin
OUT
Figure 7
Minimum pulse that changes the output state
Figure 8 illustrates the input supply UVLO behavior. It depicts the reaction time to UVLO events when VDDI crosses
the UVLO thresholds during rising or falling transitions (power-up, power-down, supply noise).
IN+ high
IN- low
VDDO > UVLOVDDO,on
UVLOVDDI,on
UVLOVDDI,off
VDDI
OUT
tSTART,VDDI
Figure 8
tSTOP,VDDI
VDDI UVLO behavior, start-up and deactivation time (unloaded output)
Figure 9 illustrates the output supply UVLO behavior. It depicts the reaction time to UVLO events when VDDO
crosses the UVLO thresholds during rising or falling transitions (power-up, power-down, supply noise).
IN+ high
IN- low
VDDI > UVLOVDDI,on
UVLOVDDO,on
UVLOVDDO,off
VDDO
OUT
tSTART,VDDO
Figure 9
tSTOP,VDDO
VDDO UVLO behavior, start-up and deactivation time (unloaded output)
Final Data Sheet
17
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Timing diagrams
Figure 10 illustrates tCLAMP,OUT, the time required to clamp potential output induced overshoots in UVLO
condition (VDDO < UVLOVDDO,on).
VDDO
1.2V
OUT
tCLAMP,OUT
Figure 10
Activation time of output clamping in UVLO conditions (unloaded output)
Final Data Sheet
18
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Layout recommendation
5
Layout recommendation
For any fast-switching power system the PCB layout is crucial to achieve optimum performance. Among the many
existing rules, recommendations, guidelines, tips and tricks, the ones of highest importance are listed as follow.
•
Use low-ESR decoupling capacitances (CVDDI, CVDDO) and place them as close as possible to the driver to
support high peak currents during switching and to ensure stable supply voltages for the driver. The use of
PCB planes at ground potential is also recommended to further reduce the inductance to ground.
•
Minimize the gate loop inductance by placing the driver as close as possible to the driven transistor and by
ensuring that the gate traces are always placed on top of a PCB plane at ground (GNDO) potential. Minimizing
the power loop inductance is the key measure to limit voltage overshoots and enable fast switching.
•
In case of boostrapping, minimize the boostrap loop inductance to ensure reliable operation and fast
bootstrap charge. The boostrap capacitor is, in fact, charged every cycle through the bootstrap diode and the
turned-on low-side transistor and the loop is subject to potential high peak charging currents. When this is not
possible, use a split bootstrap capacitor with one part placed in some distance of the driver to avoid induced
noise; if big enough, this acts as a stable supply for the high-side driver decoupling capacitance (placed close
to the driver).
•
Pay attention to keep any source of noise (like half-bridge high-current switching traces) away from the driver
to avoid any coupling capacitance.
•
According to the application requirements, pay attention to keep the needed input-to-output clearance and
creepage on PCB level. To fully benefits from the isolation capabilities of the driver, any trace or plane below
the device must be strictly avoided.
•
Connect the driver ground pin to proper PCB planes to reduce the junction-to-board resistance and support
the spread of heat outside the driver
A layout recommendation for EiceDRIVER™ 1EDBx275F is given in Figure 11.
9 22
2
22
0123
1
3456789
1
345671
012
223
8789
345
871
9 223
Figure 11
Layout recommendation
Final Data Sheet
19
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Application notes
6
Application notes
Note: The following information is given as a hint for the implementation of the device only and shall not be regarded
as a description or warranty of a certain functionality, condition or quality of the device.
Due to the input-to-output isolation, EiceDRIVER™ 1EDBx275F is best suited for use as high-side driver. In
particular, the combination with EiceDRIVER™ 1EDNx550B (single-channel gate driver with true differential
inputs), is best suited for half-bridge driving due to perfect matching in timing performances and output
capability.
By making use of the drivers inverting and non-inverting inputs, shoot-through protection can be implemented
as depicted in Figure 12; any undesired overlap of low-side and high-side PWM signals is not propagated at the
transistors input.
This solution is preferable compared to dual-channel gate drivers in case of high-power or high-frequency
designs; here minimizing the gate loop may become a critical requirement that can be more easily fulfilled by
using single-channel solutions.
Controller
VBUS
EiceDRIVER™ 1EDBx275F
VDD
VDD
VDDI
PWM1
CVDDI
GND
VDDO
IN+
OUT_SRC
IN-
OUT_SNK
Rgon
Rgoff
Cboot
GNDO
GNDI
Q1
Dboot
Rboot
Rin1
PWM2
Rin2
EiceDRIVER™ 1EDNx550B
IN+
VDD
IN-
OUT_SRC
GND
OUT_SNK
Rgoff
Q2
CVDDO
Rc
Figure 12
Rgon
Typical application circuit for half-bridge driving
The high CMTI of 300 V/ns, in conjunction with the ability to drive 4-pin Kelvin source transistors, makes the
combination 1EDBx275F, 1EDNx550B ideal to drive GaN and SiC power switches.
6.1
Driving 600 V CoolGaNTM
Figure 13 depicts a 1EDB7275F typical use case driving Infineon´s 600V GaN power switches (CoolGaNTM). The
example shows a soft-switching topology; here, due to acceptable switching speed, unipolar driving is possible
without risk of false triggering of the devices due to switching induced overshoots.
Details of component dimensioning can be found in the EiceDRIVER™ 1EDi-GaN product family datasheet.
Final Data Sheet
20
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Application notes
400V
Controller
D
EiceDRIVER™ 1EDB7275F
8V
VDDI
VDD
PWM1
100n
GND
560
VDDO
IN+
OUT_SRC
IN-
OUT_SNK
GNDI
10
2
33k
33k
IN+
VDD
IN-
OUT_SRC
GND
OUT_SNK
IGT60R070
G
SS
220n
GNDO
S
D
2.2
EiceDRIVER™ 1EDN7550B
PWM2
1.8n
560
10
2
1.8n
IGT60R070
G
SS
2.2μ
10
S
Figure 13
Typical application circuit for 600 V CoolGaNTM driving
6.2
Driving 650 V CoolSiCTM
Figure 14 depicts a typical use case for 600V Infineon´s SiC power switches (CoolSiCTM) in a so-called “totempole” PFC. It consists of a 48mΩ SiC half-bridge controlled by two 1EDB9275F EiceDRIVERTM; the diode functions
indicated in the power path are usually realized with low-RDSON MOSFETs operating as synchronous rectifiers.
3.3 kW of power can be handled at very high efficiency (above 99%).
Considering a typical 18 V gate-to-source voltage driving, EiceDRIVERTM 1EDB9275F offers an output UVLO level
fitting for 650 V CoolSiCTM. With a typical UVLOVDDO,off of 14.4 V, 1EDB9275F ensures that even in an unsupplied
case the transistor (e.g. IMZA65R048M1H in a 3.3 kW totem-pole PFC) stays within the Safe Operating Area (SOA)
with acceptable power dissipation.
In Figure 14 a Schottky diode at the CoolSiCTM gate is recommended to clamp switching induced undershoots on
the gate terminal which may cause a potential drift in the gate threshold voltage Vgs,th over lifetime.
Controller
3.3V
EiceDRIVER™ 1EDB9275F
VDDI
VDD
PWM1
100n
GND
VDDO
IN+
OUT_SRC
IN-
OUT_SNK
GNDI
6.8
6.8
220n
GNDO
IMZA65R048M1
AC
3.3V
EiceDRIVER™ 1EDB9275F
VDDI
PWM2
100n
OUT_SRC
IN-
OUT_SNK
GNDI
Figure 14
2.2
18V
VDDO
IN+
GNDO
Vin
6.8
2.2μ
6.8
IMZA65R048M1
Typical application circuit for 650 V CoolSiCTM driving
Final Data Sheet
21
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Typical characteristics
7
Typical characteristics
VDDI = 3.3 V, VDDO = 12 V, TA = 25°C, fsw= 1MHz, no load unless otherwise noted.
1.00
4.0
VDDI = 3.3V
VDDI = 5V
fsw = 100 KHz
fsw = 1MHz
fsw = 3MHz
3.0
square wave input
IVDDI [mA]
IVDDI [mA]
0.90
0.80
2.0
1.0
0.70
0.0
-50
0
50
100
Tj [°C]
150
-50
Typical IVDDIq quiescient
current vs. temperature
Figure 15
150
Typical IVDDI switching
current vs. temperature
Input-side supply current IVDDIq (quiescent and switching current)
1.2
1.0
VDDO = 4.5 V
VDDO = 12 V
VDDO = 20 V
OUT LOW
VDDO = 12 V
OUT HIGH
1.0
IVDDOq [mA]
0.8
IVDDOq [mA]
50
Tj [°C]
0.6
0.8
0.6
0.4
-50
-50
50
100
150
Tj [°C]
Typical IVDDOq quiescient
current(OUT low) vs. temperature
Figure 16
0
0
50
100
Tj [°C]
150
Typical IVDDOq quiescient
current(OUT high) vs. temperature
Output-side supply current IVDDOq (quiescent current)
Final Data Sheet
22
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Typical characteristics
14
fsw = 100KHz
fsw = 1MHz
fsw = 3MHz
12
no load, VDDO = 12V,
square wave input
40
IVDDO [mA]
10
IVDDO [mA]
VDDO = 4.5V
VDDO = 8V
VDDO = 12V
VDDO = 20V
50
8
6
4
30
20
10
2
0
0
-50
50
Tj [°C]
0
150
Typical IVDDO switching current vs.
temperature
Figure 17
2
4
6
fsw [MHz]
8
10
Typical IVDDO switching current vs.
frequency
Output-side supply current IVDDO (switching current without load)
2.0
40
VDDO = 5V
VDDO = 12V
VDDO = 20V
1.0
0.5
VDDO = 5V
VDDO = 12V
VDDO = 20V
30
IVDDO [mA]
1.5
IVDDO [mA]
no load, TA = 25°C,
square wave input
square wave input,
TA = 25°C, fsw = 1KHz,
series resistance RS = 0 Ω
0.0
square wave input,
TA = 25°C, fsw = 100KHz,
series resistance RS = 0 Ω
20
10
0
0
Figure 18
5
Cload [nF]
Typical IVDDO current vs. capacitive
load (1 KHz frequency)
10
0
5
10
Cload [nF]
Typical IVDDO current vs. capacitive
load (100 KHz frequency)
Output-side supply current IVDDO (switching current with load)
Final Data Sheet
23
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Typical characteristics
3.0
ON threshold
OFF threshold
2.9
2.0
UVLOVDDI [V]
Vin [V]
2.5
UVLO on
UVLO off
2.7
1.5
1.0
2.5
0.5
-50
0
50
100
Tj [°C]
-50
150
50
100
Tj [°C]
150
Typical Undervoltage Lockout
thresholds VDDI vs. temperature
Typical input voltage thresholds vs.
temperature
Figure 19
0
Logic input thresholds and VDDI UVLO thresholds
4.5
8.8
UVLO on
UVLO off
UVLO on
UVLO off
8.4
4.3
UVLOVDDO [V]
UVLOVDDO [V]
8.0
4.1
7.6
7.2
3.9
6.8
3.7
6.4
-50
0
50
100
Tj [°C]
150
-50
50
100
150
Tj [°C]
Typical Under Voltage Lockout VDDO
thresholds vs. temperature (8 V version)
Typical Under Voltage Lockout VDDO
thresholds vs. temperature (4 V version)
Figure 20
0
VDDO UVLO thresholds (4 V, 8 V options)
Final Data Sheet
24
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Typical characteristics
Figure 21
VDDO UVLO thresholds (12 V, 15 V options)
2.0
50
Ron_src
Ron_snk
ON
OFF
48
tPDon,off [ns]
Ron [Ω]
1.5
1.0
0.5
0.0
45
43
40
-50
Figure 22
0
50
100
150
Tj [°C]
Typical output resistance vs.
temperature
-50
0
50
100
Tj [°C]
Typical propagation
delay vs. temperature
150
Output resistance and propagation delay
Final Data Sheet
25
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Typical characteristics
16
VDDO = 5 V
VDDO = 12 V
VDDO = 20 V
8
TA = 25°C,
CLOAD =150nF,
RS = 0.1 Ω
12
6
10
ISNK [A]
ISRC [A]
VDDO = 5 V
VDDO = 12 V
VDDO = 20 V
14
4
8
6
4
2
TA = 25°C, CLOAD =150nF,
series resistance RS = 0.1 Ω
2
0
0
0
Figure 23
5
10
15
20
VOUT [V]
Typical sourcing output
current vs. output voltage
0
5
10
15
VOUT [V]
20
Typical sinking output
current vs. output voltage
Source and sink current with output voltage
12
ISRC_pk
ISNK_PK
10
ISRC_pk , ISNK_pk [A]
8
6
4
VDDO = 12V, TA = 25°C,
CLOAD =150nF,
series resistance RS = 0.1 Ω
2
0
4
Figure 24
8
12
16
20
VDDO [V]
Typical peak output current
vs. supply voltage
Peak source and sink current with supply voltage
Final Data Sheet
26
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Typical characteristics
10
14
VDDO = 5 V
VDDO = 12 V
VDDO = 20 V
8
12
10
ISNK_pk [A]
ISRC_pk [A]
6
4
2
8
6
4
CLOAD =150nF,
series resistance RS = 0.1 Ω
0
CLOAD =150nF,
series resistance RS = 0.1 Ω
2
-50
Figure 25
0
50
100
150
Tj [°C]
Typical peak sourcing output
current vs. temperature
-50
0
50
100
150
Tj [°C]
Typical peak sinking output
current vs. temperature
Peak source and sink current with temperature
50
30
VDDO = 5V
VDDO = 12V
VDDO = 20V
40
VDDO = 5V
VDDO = 12V
VDDO =20V
20
30
tfall [ns]
trise [ns]
VDDO = 5 V
VDDO = 12 V
VDDO = 20 V
20
10
10
TA = 25°C,
series resistance Rs = 0 Ω
0
0
3
5
8
Cload [nF]
0
0
10
Typical rise time vs.
capacitive load
Figure 26
TA = 25°C,
series resistance Rs = 0 Ω
3
5
8
Cload [nF]
10
Typical fall time vs.
capacitive load
Rise and fall times with capacitive load
Final Data Sheet
27
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Typical characteristics
2.5
Rise time
Fall time
trise/fall [ns]
2.0
1.5
1.0
0.5
VDDO = 12V,
no load
0.0
-50
0
50
100
TJ [°C]
150
Typical rise and fall times
vs. temperature (no load)
Figure 27
Rise and fall times with temperature
Final Data Sheet
28
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Package outline dimensions
8
Package outline dimensions
8.1
Device numbers and markings
Table 21
Device numbers and markings
Part number
Orderable part number (OPN)
Device marking
1EDB6275F
1EDB6275FXUMA1
1B6275A
1EDB7275F
1EDB7275FXUMA1
1B7275A
1EDB8275F
1EDB8275FXUMA1
1B8275A
1EDB9275F
1EDB9275FXUMA1
1B9275A
+0.08 2)
0.41 -0.06
5
1
4
5 -0.21)
.01
+0.45
0.8 -0.4
4 -0.21)
0.25 M D C 8x
8
+0.05
0.2 -0
+0.1
1.75 MAX.
C
0.1 8x
3 x 1.27 = 3.81
+0.17
0.33 -0.08 x 45°
7° MAX.
1.27
0.15 -0.05
STAND OFF
Package PG-DSO-8
1.25 MIN.
8.2
6 ±0.2
A
0.25 M A
D
Index Marking
1) Does not include plastic or metal protrusion
2) Does not include dambar protrusion of 0.127 max. in excess of the lead width dimension
PG-DSO-8-41, -42, -51, -53, -58-PO V06
Figure 28
PG-DSO-8 outline1)
1) Dimensions in mm
Final Data Sheet
29
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Package outline dimensions
0.65
1.27
2.765
2.765
1.47
2.765
1.27
1.47
2.765
0.65
Copper
Stencil apertures
Solder mask
PG-DSO-8-41, -42, -51, -53, -58-FP V01
Figure 29
PG-DSO-8 footprint
8
5.2
Index
Marking
6.4
12
0.3
1.75
2.1
PG-DSO-8-41, -42, -51, -53, -58-TP V09
Figure 30
PG-DSO-8 packaging
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pbfree finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Further information on packages
https://www.infineon.com/packages
Final Data Sheet
30
Rev. 2.1
2021-04-21
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate-driver ICs in 150 mil DSO package
Revision history
Page or Item
Subjects (major changes since previous revision)
Rev. 2.1, 2021-04-21
Whole document
Removed “UL1577 certification pending” because certification has been
issued
Table 1, Table 3, Table 21
Added 1EDB6275F 12 V UVLO variant
Table 1, Table 21
Modified UVLO values for 1EDB9275F
Table 7
Fixed typo in RthJB25
Table 17
Increased propagation delay max (49ns → 51ns)
Table 19
Added pollution degree, climatic category and emulated VDE0884-11
parameters
Table 20
Added safety limiting values table
Table 21
Updated VDDO UVLO vs. temperature graph for 1EDB9275F, added graph for
1EDB6275F
Rev. 2.0, 2020-04-08
Final datasheet created
Final Data Sheet
31
Rev. 2.1
2021-04-21
Please read the Important Notice and Warnings at the end of this document
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Edition 2021-04-21
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2021 Infineon Technologies AG.
All Rights Reserved.
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Email: erratum@infineon.com
Document reference
EiceDRIVER™ 1EDBx275F
IMPORTANT NOTICE
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