1EDI2002ASXUMA2

EiceDRIVER™ SIL 1EDI2002AS Features Functional Features • Single Channel IGBT Driver. • On-chip galvanic insulation (up to 6 kV). • Support of 600 V and 1200 V IGBT technologies. • Low propagation delay and minimal PWM distortion. • Support of 5 V logic levels (primary side). • 16-bit Standard SPI interface (up to 2 MBaud) with daisy chain support (primary side). • Enable input pin (primary side). • Pseudo-differential inputs for critical signals (primary side). • Power-On Reset pin (primary side). • Debug mode. • Pulse Suppressor. • Fully Programmable Active Clamping Inhibit signal (secondary side). • Fully programmable Two-Level Turn On (TTON). • Low latency digital channel. • Optimal support of EiceBoost functions. • 36-pin PG-DSO-36 green package. • Automotive qualified (as per AEC Q100). Safety Relevant Features • Programmable Desaturation monitoring. • Overcurrent protection. • Fully programmable Two-Level Turn-Off. • Automatic Emergency Turn-Off in failure case. • Automatic or externally triggered disabling of the output stage (tristate). • Under- and over-voltage supervision of all the power supplies (both primary and secondary sides). • NFLTA and NFLTB notification pins for fast system response time (primary side). • Safe internal state machine. • Weak Turn-On functionality. • Internal overtemperature sensor (secondary side). • Internal clock monitoring. Datasheet www.infineon.com 1 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS • Gate signal monitoring. • IGBT state monitoring. • Individual error and status flags readable via SPI. • Support for Active Short Circuit strategies. • Full diagnosticability. • In-application testability of safety critical functions. • Suitable for systems up to ASIL D requirements (as per ISO 26262). Potential applications • Inverters for automotive Hybrid Electric Vehicles (HEV) and Electric Vehicles (EV). • High Voltage DC/DC converter. • Industrial Drive. Product validation Qualified for Automotive Applications. Product Validation according to AEC-Q100/101. Description Type Package Ordering Code Marking 1EDI2002AS PG-DSO-36 SP001362894 1EDI2002AS Datasheet 2 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Table of Contents 1 1.1 Product Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 2.1 2.2 2.2.1 2.2.2 2.2.2.1 2.2.2.2 2.2.2.3 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.4.1 2.4.4.2 2.4.4.3 2.4.4.4 2.4.4.5 2.4.5 2.4.5.1 2.4.5.2 2.4.5.3 2.4.5.4 2.4.5.5 2.4.5.6 2.4.6 2.4.6.1 2.4.6.2 2.4.6.3 2.4.6.4 2.4.7 2.4.8 2.4.9 2.4.10 2.4.10.1 2.4.10.2 2.4.10.3 2.4.11 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Primary Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pull Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Data Integrity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Modes Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activating the device after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activating the device after an Event Class A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Sequence Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disabling the output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Passive Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Notifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EN Signal Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation in Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delay Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Latency Digital Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 11 13 13 14 16 17 18 18 18 19 21 21 22 24 26 27 31 31 32 34 36 36 36 37 37 42 43 44 45 46 46 49 49 53 53 54 3 3.1 3.2 3.2.1 3.2.2 Protection and Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervision Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions: Category A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 55 57 57 59 Datasheet 3 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS 3.2.3 3.2.4 3.3 3.3.1 3.3.2 3.3.2.1 3.3.2.2 3.3.2.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.5.9 3.5.10 External Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Stage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions: Category B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lifesign watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions: Category C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shoot Through Protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Short Circuit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGBT State Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions: Category D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation in Verification Mode and Weak Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Weak Turn On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DESAT Supervision Level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DESAT Supervision Level 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DESAT Supervision Level 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCP Supervision Level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCP Supervision Level 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Monitoring Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Clock Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIO Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 4.2 4.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Primary Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Secondary Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Read / Write Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5 5.1 5.2 5.3 5.4 5.5 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 5.5.9 5.5.10 5.5.11 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Primary I/O Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary I/O Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Latency Digital Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over temperature Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Detection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Datasheet 4 61 62 63 63 64 65 65 65 66 66 67 68 68 69 70 71 71 71 72 73 74 74 75 75 77 77 126 126 129 130 130 131 131 132 133 135 137 139 139 140 140 140 141 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS 5.5.12 5.5.13 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Insulation Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Datasheet 5 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Datasheet Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Internal pull devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI Command Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Word Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ENTER_CMODE request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ENTER_VMODE request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 EXIT_CMODE request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 NOP request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 READ request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 WRITEH request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 WRITEL request and answer messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Failure Notification Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Reset Events Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Pin behavior (primary side) in case of reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Pin behavior (secondary side) in case of reset condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Safety Related Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 DESAT Protection Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 OCP Function Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 External Enable Function Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Output Stage Monitoring Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Power Supply Voltage Monitoring Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 System Supervision Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 STP Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Gate Monitoring Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Temperature Monitoring Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 SPI Error Detection Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Active Short Circuit Support Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 IGBT State Monitoring Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DESAT Supervision Level 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 DESAT Supervision Level 2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 DESAT Supervision Level 3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 OCP Supervision Level 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 OCP Supervision Level 3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Power Supply Monitoring Supervision Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Primary Clock Supervision Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 DIO Supervision Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Bit Access Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Read Access Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Write Access Validity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Power Supplies Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Internal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Datasheet Electrical Characteristics for Pins: INP, INSTP, EN/FEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Electrical Characteristics for Pins: NRST/RDY, SCLK, SDI, NCS, DIO1 (input) . . . . . . . . . . . . . . . 133 Electrical Characteristics for Pins: SDO, DOUT, DIO1 (output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Electrical Characteristics for Pins: NFLTA, NFLTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Electrical Characteristics for Pins: TON, TOFF & GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Electrical Characteristics for Pins: OSD, DEBUG, DIO2 (input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Electrical Characteristics for Pin: NUV2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Electrical Characteristics for Pins: DACLP, DIO2 (output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Electrical Characteristics for Pin: VREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 DESAT characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 OCP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Digital channel characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Data Out characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Over temperature Warning Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Error Detection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SPI Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Insulation Characteristics in compliance with DIN V VDE 0884 - 10 : 2006-12, expired on December 31st, 2019 143 Isolation Characteristics referring to UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Datasheet Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PWM Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STP: Inhibition Time Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STP: Example of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI Regular Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI Daisy Chain Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Response Answer Principle - Daisy Chain Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Response Answer Principle - Regular Topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI Commands Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating Modes State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Output Stage Diagram of Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TTOFF: Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TTON: Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 TTOFF: pulse suppressor aborting a turn-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Idealized Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Output Stage Disable: Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Low Latency Digital Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 DESAT Function: Diagram of Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 DESAT Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DESAT Operation with DESAT clamping enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 OCP Function: Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Power Supply Supervision Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Shoot Through Protection: Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Gate Monitoring Function: Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ASC Strategy Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Idealized Weak Turn-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Typical Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Recommended Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Product Definition 1 Product Definition 1.1 Overview The 1EDI2002AS is a high-voltage IGBT gate driver designed for automotive motor drives above 5 kW. The 1EDI2002AS is based on Infineon’s Coreless Transformer (CLT) technology, providing galvanic insulation between low voltage and high voltage domains. The device has been designed to support 400 V, 600 V and 1200 V IGBT technologies. The 1EDI2002AS can be connected on the low voltage side (“primary” side) to 5 V logic. A standard SPI interface allows the logic to configure and to control the advanced functions implemented in the driver. On the high voltage side (“secondary” side), the 1EDI2002AS is dimensioned to drive an external booster stage. Short propagation delays and controlled internal tolerances lead to minimal distortion of the PWM signal. A large panel of safety-related functions has been implemented in the 1EDI2002AS, in order to support functional safety requirements at system level (as per ISO 26262). Besides, those integrated features ease the implementation of Active Short Circuit (ASC) strategies. The 1EDI2002AS can be used optimally with Infineon’s 1EBN100XAE “EiceDRIVER™ Boost” booster stage family. Datasheet 9 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description 2 Functional Description 2.1 Introduction The 1EDI2002AS is an advanced single channel IGBT driver that can also be used for driving power MOS devices. The device has been developed in order to optimize the design of high performance safety relevant automotive systems. The device is based on Infineon’s Coreless Transformer Technology and consist of two chips separated by a galvanic isolation. The low voltage (primary) side can be connected to a standard 5 V logic. The high voltage (secondary) side is in the DC-link voltage domain. Internally, the data transfers are ensured by two independent communication channels. One channel is dedicated to transferring the ON and OFF information of the PWM input signal only. This channel is unidirectional (from primary to secondary). Because this channel is dedicated to the PWM information, latency time and PWM distortion are minimized. The second channel is bidirectional and is used for all the other data transfers (e.g. status information, etc). The 1EDI2002AS supports advanced functions in order to optimize the switching behavior of the IGBT. Furthermore, it supports several monitoring and protection functions, making it suitable for systems having to fulfill ASIL requirements (as per ISO 26262). Datasheet 10 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description 2.2 Pin Configuration and Functionality 2.2.1 Pin Configuration 1 VEE2 GND1 36 2 TON IREF1 35 3 VCC2 VCC1 34 4 TOFF INSTP 33 5 DESAT INP 32 6 GATE REF0 31 7 GND2 EN/FEN 30 8 IREF2 NRST /RDY 29 9 VEE2 GND1 28 10 VREG NFLTA 27 11 OCP NFLTB 26 12 OCPG DOUT 25 13 DEBUG SDO 24 14 DACLP NCS 23 15 OSD SDI 22 16 DIO2 SCLK 21 17 NUV2 DIO1 20 18 VEE2 GND1 19 Figure 1 Pin Configuration Table 1 Pin Configuration Pin Number Symbol I/O Voltage Class Function 1,9,18 VEE2 Supply Supply Negative Power Supply1). 2 TON Output 15V Secondary Turn-On Output. 3 VCC2 Supply Supply 4 TOFF Output 15V Secondary Turn-Off Output. 5 DESAT Input 15V Secondary Desaturation Protection Input. 6 GATE Input 15V Secondary Gate Monitoring Input. 7 GND2 Ground Ground Ground. 8 IREF2 Input 5V Secondary External Reference Input. 10 VREG Output 5V Secondary Reference Output Voltage. 11 OCP Input 5V Secondary Over Current Protection. 12 OCPG Ground Ground Ground for the OCP function, 13 DEBUG Input 5V Secondary Debug Input. Datasheet Positive Power Supply. 11 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description Table 1 Pin Configuration (cont’d) Pin Number Symbol I/O Voltage Class Function 14 DACLP Output 5V Secondary Active Clamping Disable Output. 15 OSD Input 5V Secondary Output Stage Disable Input. 16 DIO2 Input / Output 5V Secondary Digital I/O. 17 NUV2 Output 5V Secondary VCC2 not valid notification output. 19, 28, 36 GND1 Ground Ground Ground2). 20 DIO1 Input / Output 5V Primary Digital I/O. 21 SCLK Input 5V Primary SPI Serial Clock Input. 22 SDI Input 5V Primary SPI Serial Data Input. 23 NCS Input 5V Primary SPI Chip Select Input (low active). 24 SDO Output 5V Primary SPI Serial Data Output. 25 DOUT Output 5V Primary DESAT comparator output. 26 NFLTB Output 5V Primary Fault B Output (low active, open drain). 27 NFLTA Output 5V Primary Fault A Output (low active, open drain). 29 NRST/RDY Input/Output 5V Primary Reset Input (low active, open drain). This signal notifies that the device is “ready”. 30 EN/FEN Input 5V Primary Enable Input. 31 REF0 Ref. Ground Ground Reference Ground for signals INP, INSTP, EN/FEN. 32 INP Input 5V Primary Positive PWM Input. 33 INSTP Input 5V Primary Monitoring PWM Input. 34 VCC1 Supply Input Supply Positive Power Supply. 35 IREF1 Input 5V Primary External Reference Input. 1) All VEE2 pins must be connected together. 2) All GND1 pins must be connected together. Datasheet 12 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description 2.2.2 Pin Functionality 2.2.2.1 Primary Side GND1 Ground connection for the primary side. VCC1 5 V power supply for the primary side (referring to GND1). INP Non-inverting PWM input of the driver. The internal structure of the pad makes the IC robust against glitches. An internal weak pull-down resistor to VREF0 drives this input to Low state in case the pin is floating. INSTP Monitoring PWM input for shoot through protection. The internal structure of the pad makes the IC robust against glitches. An internal weak pull-down resistor to VREF0 drives this input to Low state in case the pin is floating. REF0 Reference Ground signal for the signals INP, INSTP, EN/FEN. This pin should be connected to the ground signal of the logic issuing those signals. EN/FEN Enable Input Signal. This signal allows the logic on the primary side to turn-off and deactivate the device. An internal weak pull-down resistor to VREF0 drives this input to Low state in case the pin is floating. This pin reacts on logic levelsor on a periodic signal, depending on the device’s configuration. NFLTA Open-Drain Output signal used to report major failure events (Event Class A). In case of an error event, NFLTA is driven to Low state. This pin shall be connected externally to VCC1 with a pull-up resistance. NFLTB Open-Drain Output signal used to report major failure events (Event Class B). In case of an error event, NFLTB is driven to Low state. This pin shall be connected externally to VCC1 with a pull-up resistance. SCLK Serial Clock Input for the SPI interface. An internal weak pull-up device to VCC1 drives this input to high state in case the pin is floating. SDO Serial Data Output (push-pull) or the SPI interface. Datasheet 13 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description SDI Serial Data Input for the SPI interface. An internal weak pull-up device to VCC1 drives this input to high state in case the pin is floating. NCS Chip Select input for the SPI interface. This signal is low active. An internal weak pull-up device to VCC1 drives this input to High state in case the pin is floating. IREF1 Reference input of the primary chip. This pin shall be connected to VGND1 via an external resistor. NRST/RDY Open drain reset input. This signal is low-active. When a valid signal is received on this pin, the device is brought in its default state. This signal is also used as a “ready notification”. A high level on this pin indicates that the primary chip is functional. DOUT Enhanced DESAT functionality comparator status output. This signal allows real-time monitoring of the IGBT state. DIO1 I/O for the digital channel. Depending of the chosen configuration of the device, this pin can be an input or an output (push-pull). An internal weak pull-down resistor to VGND1 drives this input to Low state in case the pin is floating. 2.2.2.2 Secondary Side VEE2 Negative power supply for the secondary side, referring to VGND2. VCC2 Positive power supply for the secondary side, referring to VGND2. GND2 Reference ground for the secondary side. DESAT Desaturation Protection input pin. The function associated with this pin monitors the VCE voltage of the IGBT. The detection threshold is programmable. An internal pull-up resistor to VCC2 drives this signal to High level in case it is floating. Datasheet 14 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description OCP Over Current Protection input pin. The function associated with this pin monitors the voltage across a sensing resistance located on the auxiliary path of a Current Sense IGBT. An internal weak pull-up resistor to the internal 5V reference drives this input to High state in case the pin is floating. OCPG Over Current Protection Ground. TON Output pin for turning on the IGBT. TOFF Output pin for turning off the IGBT. GATE Input pin used to monitor the IGBT gate voltage. OSD Output Stage Disable input. A High Level on this pin tristates the output stage. An internal weak pull-down resistor to VGND2 drives this input to Low state in case the pin is floating. DACLP Output pin used to disable the active clamping function of the booster. DEBUG Debug input pin. This pin is latched at power-up. When a High level is detected on this pin, the device enters a special mode where it can be operated without SPI interface. This feature is for development purpose only. This pin should normally be tied to VGND2. An internal weak pull-down resistor to VGND2 drives this input to Low state in case the pin is floating. IREF2 Reference input of the secondary chip. This pin shall be connected to VGND2 via an external resistor. VREG Reference Output voltage. This pin shall be connected to an external capacitance to VGND2. NUV2 VCC2 not valid notification signal (Open Drain). This signal drives a low level when VCC2 is not valid or when the internal 5V digital supply is not valid. When both supplies are valid, this pin is in high impedance state. This pin shall be connected externally to a 5 V reference with a pull-up resistance. DIO2 I/O for the digital channel. Depending of the chosen configuration of the device, this pin can be an input or an output (push-pull). An internal weak pull-down resistor to VGND2 drives this input to Low state in case the pin is floating. Datasheet 15 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description 2.2.2.3 Pull Devices Some of the pins are connected internally to pull-up or pull-down devices. This is summarized in Table 2. Table 2 Internal pull devices Signal Device INP Weak pull down to VREF0 INSTP Weak pull down to VREF0 EN/FEN Weak pull down to VREF0 SCLK Weak pull up to VCC1 SDI Weak pull up to VCC1 NCS Weak pull up to VCC1 DIO1 Weak pull down to VGND1 DESAT Weak pull up to VCC2 DIO2 Weak pull down to VGND2 OSD Weak pull down to VGND2 OCP Weak pull up to 5 V internal reference DEBUG Weak pull down to VGND2 Datasheet 16 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description 2.3 Block Diagram IREF1 OSC 1 WDG WDG OSC2 IREF2 Vcc1 GND2 P-Supply Vee2 GND1 INP EN/FEN INSTP P-Supply NUV2 PWM Input Stage VREG Start-Stop Osc REF0 NCS SDI SPI Interface SDO Vcc2 Secondary Primary Logic OSD Output Stage Switching Control TON GATE TOFF Logic SCLK DACLP NFLTA OCP OCP NFLTB OCPG NRST/RDY DESAT DOUT DESAT DEBUG DIO1 DIO2 T sensor Figure 2 Datasheet Block Diagram 17 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description 2.4 Functional Block Description 2.4.1 Power Supplies On the primary side, the 1EDI2002AS needs a single 5 Vsupply source VCC1 for proper operation. This makes the device compatible to most of the microcontrollers available for automotive applications. On the secondary side, the 1EDI2002AS needs two power supplies for proper operation. • The positive power supply VCC2 is typically set to 15 V (referring to VGND2). • The negative supply VEE2 is typically set to -8 V (referring to VGND2). Under- and over-voltage monitoring is performed continuously during operation of the device (see Chapter 3.3.1). A 5 V supply for the digital domain on the secondary side is generated internally (present at pin VREG). 2.4.2 Clock Domains The clock system of the 1EDI2002AS is based on three oscillators defining each a clock domain: • One RC oscillator (OSC1) for the primary chip. • One RC oscillator (OSC2) for the secondary chip excepting the output stage. • One Start-Stop oscillator (SSOSC2) for the output stage on the secondary side. The two RC oscillators are running constantly. They are also monitored constantly, and large deviations from the nominal frequency are identified as a system failure (Event Class B, see Chapter 3.3.2.2). The Start Stop oscillator is controlled by the PWM command. Datasheet 18 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description 2.4.3 PWM Input Stage The PWM input stage generates from the external signals INP, INSTP and EN/FEN the turn-on and turn-off commands to the secondary side. The general structure of the PWM input block is shown Figure 3. VCC1 EN inhibit_act. en_valid LOGIC Inhibit Time Generation INSTP Validity Check INP pwm_cmd REF0 Figure 3 PWM Input Stage Signals INP, INSTP and EN/FEN are pseudo-differential, in the sense that they are not referenced to the common ground GND1 but to signal REF0. This is intended to make the device more robust against ground bouncing effects. Note: Glitches shorter than tINPR1 occurring at signal INP are filtered internally. Note: Pulses at INP below tINPPD might be distorted or suppressed. The 1EDI2002AS supports non-inverted PWM signals only. When a High level on pin INP is detected while signals INSTP and EN/FEN are valid, a turn-on command is issued to the secondary chip. A Low level at pin INP issues a turn-off command to the secondary chip. Signal EN/FEN can inhibit turn-on commands received at pin INP. A valid signal EN/FEN is required in order to have turn-on commands issued to the secondary chip. If an invalid signal is provided, the PWM input stage issues constantly turn-off commands to the secondary chip. The functionality of signal EN/FEN is detailed in Chapter 2.4.8. Note: After an invalid-to valid-transition of signal EN/FEN, a minimum delay of tINPEN should be inserted before turning INP on. As shown in Figure 4, signal INSTP provides a Shoot-Through Protection (STP) to the system. When signal at pin INSTP is at High level, the internal signal inhibit_act is activated. The inhibition time is defined as the pulse duration of signal inhibit_act. It corresponds to the pulse duration of signal INSTP to which a minimum dead time is added. During the inhibition time, rising edges of signal INP are inhibited. Bit PSTAT2.STP is set for the duration of the inhibition time. The deadtime is programmable with bit field PCFG2.STPDEL. Datasheet 19 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description INSTP dead time inhibit_act INP Inhibition time pwm_cmd Figure 4 STP: Inhibition Time Definition It shall be noted that during the inhibition time, signal pwm_cmd is not forced to Low. It means that if the device is already turned-on when INSTP is High, it stays turned-on until the signal at pin INP goes Low. This is depicted in Figure 5. INSTP dead time inhibit_act Inhibited edge INP pwm_cmd Inhibition time Figure 5 STP: Example of Operation When a condition occurs where a rising edge of signal INP is inhibited, an error notification is issued. See Chapter 3.4.1 for more details. Datasheet 20 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description 2.4.4 SPI Interface This chapter describes the functionality of the SPI block. 2.4.4.1 Overview The standard SPI interface implemented on the 1EDI2002AS is compatible with most of the microcontrollers available for automotive and industrial applications. The following features are supported by the SPI interface: • Full-duplex bidirectional communication link. • SPI Slave mode (only). • 16-bit frame format. • Daisy chain capability. • MSB first. • Parity Check (optional) and Parity Bit generation (LSB). The SPI interface of the 1EDI2002AS provides a standardized bidirectional communication interface to the main microcontroller. From the architectural point of view, it fulfills the following functions: • Initialization of the device. • Configuration of the device (static and runtime). • Reading of the status of the device (static and runtime). • Operation of the verification modes of the device. The purpose of the SPI interface is to exchange data which have relaxed timing constraints compared to the PWM signals (from the point of view of the motor control algorithm). The IGBT switching behavior is for example controlled directly by the PWM input. Similarly, critical application failures requiring fast reaction are notified on the primary side via the feedback signals NFLTA, NFLTB and NRST/RDY. In order to minimize the complexity of the end-application and to optimize the microcontroller’s resources, the implemented interface has daisy chain capability. Several (typically 6) 1EDI2002AS devices can be combined into a single SPI bus. Datasheet 21 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description 2.4.4.2 General Operation The SPI interface of the 1EDI2002AS supports full duplex operation. The interface relies on four communication signals: • NCS: (Not) Chip Select. • SCLK: Serial Clock. • SDI: Serial Data In. • SDO: Serial Data Out. The SPI interface of the 1EDI2002AS supports slave operation only. An SPI master (typically, the main microcontroller) is connected to one or several 1EDI2002AS devices, forming an SPI bus. Several bus topologies are supported. A regular SPI bus topology can be used where each of the slaves is controlled by an individual chip select signal (Figure 6). In this case, the number of slaves on the bus is only limited by the application’s constraints. SCLK Master SCLK SDO SDI SDI SDO NCS1 NCS Slave 1 NCS2 SCLK ... SDI NCSn Slave 2 ... SDO NCS ... ... ... SCLK SDI Slave n SDO NCS Figure 6 SPI Regular Bus Topology In order to simplify the layout of the PCB and to reduce the number of pins used on the microcontroller’s side, a daisy chain topology can also be used. The chain’s depth is not limited by the 1EDI2002AS itself. A possible topology is shown Figure 7. Datasheet 22 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description SCLK Master SCLK SDO SDI SDI SDO NCS NCS Slave 1 SCLK SDI Slave 2 ... SDO NCS ... ... SCLK ... SDI Slave n SDO NCS Figure 7 SPI Daisy Chain Bus Topology Physical Layer The SPI interface relies on two shift registers: • A shift output register, reacting on the rising edges of SCLK. • A shift input register, reacting on the falling edges of SCLK. When signal NCS is inactive, the signals at pins SCLK and SDI are ignored. The output SDO is in tristate. When NCS is activated, the shift output register is updated internally with the value requested by the previous SPI access. At each rising edge of the SCLK signal (while NCS is active), the shift output register is serially shifted out by one bit on the SDO pin (MSB first). At each falling edge of the clock pulse, the data bit available at the input SDI is latched and serially shifted into the shift input register. At the deactivation of NCS, the SPI logic checks how many rising and falling edges of the SCLK signal have been received. In case both counts differ and / or are not a multiple of 16, an SPI Error is generated. The SPI block then checks the validity of the received 16-bit word. In case of a non valid data, an SPI error is generated. In case no error is detected, the data is decoded by the internal logic. The NCS signal is active low. Input Debouncing Filters The input stages of signals SDI, SCLK, and NCS include each a Debouncing Filter. The input signals are that way filtered from glitches and noise. The input signals SDI and SCLK are analyzed at each edge of the internal clock derived from OSC1. If the same external signal value is sampled three times consecutively, the signal is considered as valid and is processed by the SPI logic. Otherwise, the transition is considered as a glitch and is discarded. Datasheet 23 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description The input signal NCS is sampled at a rate corresponding to the period of the internal clock derived from OSC1. If the same external signal value is sampled two times consecutively, the signal is considered as valid and is processed by the SPI logic. Otherwise, the transition is considered as a glitch and is discarded. 2.4.4.3 Definitions Command A command is a high-level command issued by the SPI master which aims at generating a specific reaction in the addressed slave. The command is physically translated into a Request Message by the SPI master. The correct reception of the Request Message by the SPI slave leads to a specific action inside the slave and to the emission of an Answer Message by the slave. Example: the READ command leads to the transfer of the value of the specified register from the device to the SPI master. Word A word is a 16-bit sequence of shifted data bits. Transfer A transfer is defined as the SPI data transfers (in both directions) occurring between a falling edge of NCS and the next consecutive rising edge of NCS. Request Message A request message is a word issued by the SPI master and addressing a single slave. A request message relates to a specific command. Answer Message An answer message is a well-defined word issued by a single SPI slave as a response to a request message. Transmit Frame A transmit frame is a sequence of one or several words sent by the SPI Master within one SPI transfer. In regular SPI topologies, a transmit frame is in practice identical to a data word. In daisy chain topologies, a transmit frame is a sequence of data words belonging to different request messages. Receive Frame A receive frame is a sequence of one or several words received by the SPI Master within one SPI transfer. In regular SPI topologies, a receive frame is in practice identical to a data word. In daisy chain topologies, a receive frame is a sequence of data words belonging to different Answer Messages. The SPI protocol supported by the 1EDI2002AS is based on the Request / Answer principle. The master sends a defined request message to which the slave answers with the corresponding answer message (Figure 8, Figure 9). Due to the nature of the SPI interface, the Answer Message is shifted, compared to the Request Message, by one SPI transfer. It means, for example, that the last word of answer message n is transmitted by the slave while the master sends the first word of request message n+1. Datasheet 24 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description Transfer ... inactive Chip Select NCS active Word i Transmit Frame Master Serial Output (seen at SDI) ... RM1 ... ... RM2 ... ... ... RMn Wn ... ... AM2 ... ... ... ... ... AMn ... Request Message for Slave i Receive Frame Master Serial Input (seen at SDO) ... ... ... ... AM1 ... ... Answer Message of Slave i Figure 8 Response Answer Principle - Daisy Chain Topology Transfer ... inactive Chip Select NCS for Slave i Master Serial Output (seen at SDI) active Transmit Frame Request Message RM1 RM2 ... ... RMn Word Master Serial Input (seen at SDO) ... AM1 AM2 AMn Answer Meassage Receive Frame Figure 9 ... Response Answer Principle - Regular Topology The first word transmitted by the device after power-up is the content of register PSTAT. Datasheet 25 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description 2.4.4.4 2.4.4.4.1 SPI Data Integrity Support Parity Bit By default, the SPI link relies on an odd parity protection scheme for each transmitted or received 16-bit word of the SPI message. The parity bit corresponds to the LSB of the 16-bit word. Therefore, the effective payload of a 16-bit word is 15 data bit (plus one parity bit). The parity bit check (on the received data) can be disabled by clearing bit PCFG.PAREN. In this case, the parity bit is considered as “don’t care”. The generation of the parity bit by the driver for transmitted words can not be disabled (but can be considered as “don’t care” by the SPI master). Note: 2.4.4.4.2 For fixed value commands (ENTER_CMODE, ENTER_VMODE, EXIT_CMODE, NOP), it has to be ensured that the value of the parity bit is correct even if parity check is disabled. Otherwise, an SPI error will be generated. SPI Error When the device is not able to process an incoming request message, an SPI error is generated: the received message is discarded by the driver, bit PER.SPIERis set and the erroneous message is answered with an error notification (bit LMI set). Several failures generate an SPI error: • A parity error is detected on the received word. • An invalid data word format is received (e.g. not a 16 bit word). • A word is received, which does not corresponding to a valid Request Message. • A command is received which can not be processed. For example, the driver receives in Active Mode a command which is only valid in other operating modes. Another typical example is a read access to the secondary while the previous read access is not yet completed (device “busy”). • An SPI access to an invalid address. Note: the content of a frame with LMI bit set is the value of register PSTAT. Note: In case of permanent LMI error induced by system failures, it is recommended to apply a reset via pin NRST/RDY. Datasheet 26 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description 2.4.4.5 Protocol Description 2.4.4.5.1 Command Catalog Table 3 gives an overview of the command catalog supported by the device. The full description of the commands and of the corresponding request and answer messages is provided in the following sections. Table 3 SPI Command Catalog Acronym Short Description Valid in Mode ENTER_CMODE Enters into Configuration Mode. OPM0, OPM1 ENTER_VMODE Enters into Verification Mode. OPM2 EXIT_CMODE Leaves Configuration Mode to enter into Configured Mode. OPM2 READ Reads the register value at the specified address. All NOP Triggers no action in the device (equivalent to a “nop”). All WRITEH Update the most significant byte of the internal write buffer. All WRITEL Updates the least significant byte of the internal write buffer, All (with restrictions) and copies the contents of the complete buffer into the addressed register. The write buffer is cleared afterwards. An overview of the commands is given Figure 10. Message ENTER_CMODE ENTER_VMODE EXIT_CMODE NOP READ WRITEH WRITEL Figure 10 2.4.4.5.2 0 0 0 0 0 0 1 Command 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 0 0 0 A4 0 A4 0 0 0 1 A3 1 A3 0 0 1 0 A2 0 A2 0 1 0 0 A1 D15 A1 1 0 0 0 A0 D14 A0 Data 0 1 0 0 0 D13 D7 0 0 1 0 1 D12 D6 0 0 0 1 0 D11 D5 0 0 0 0 1 D10 D4 0 0 0 0 0 D9 D3 P 0 0 0 0 X X X 0 0 0 0 1 D8 D2 SPI Commands Overview Word Convention In order to simplify the description of the SPI commands, the following conventions are used (Table 4). Datasheet 27 Rev. 3.3 2021-01-10 EiceDRIVER™ SIL 1EDI2002AS Functional Description Table 4 Word Convention Acronym Value Va(REGISTER) Value of register REGISTER PB Parity Bit