1EDI20I12MF

1EDIxxI12MF (1ED-MF) EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Features • • • • • • • • • Single channel isolated gate driver For 600 V/650 V/1200 V IGBTs, MOSFETs, and SiC MOSFETs Up to 6 A typical peak current at rail-to-rail output Active Miller clamp Galvanically isolated coreless transformer driver Wide input voltage operating range Suitable for operation at high ambient temperature and in fast switching applications Small and cost optimized DSO-8 150 mil package with 4 mm creepage 20 V absolute maximum output supply voltage Potential applications • • • • • • • AC and brushless DC motor drives High voltage DC/DC-converter and DC/AC-inverter Induction heating resonant application UPS-systems Commercial air-conditioning (CAC) Server and telecom switched mode power supplies (SMPS) Solar Product type Typical output current and configuration UVLO Propagation delay Package marking 1EDI10I12MF 2.3 A with 1.0 A Miller clamp 12 V 300 ns 1I10I12M 1EDI20I12MF 4.4 A with 2.0 A Miller clamp 12 V 300 ns 1I20I12M 1EDI30I12MF 6.2 A with 3.0 A Miller clamp 12 V 300 ns 1I30I12M Product validation Qualified for industrial applications according to the relevant tests of JEDEC47/20/22. Datasheet Please read the sections "Important notice" and "Warnings" at the end of this document www.infineon.com/gdisolated 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Description Description The 1EDIxxI12MF are galvanically isolated single channel gate driver in a DSO-8 narrow body package that provide output currents up to 6.2 A and an integrated active Miller clamp circuit with the same current rating to protect against parasitic turn on. The input logic pins operate on a wide input voltage range from 3 V to 15 V using scaled CMOS threshold levels to support even 3.3 V microcontrollers. Data transfer across the isolation barrier is realized by the coreless transformer technology. Every driver family member comes with logic input and driver output undervoltage lockout (UVLO) and active shutdown. VCC1 VCC2,H OUT IN+ IN- EiceDRIVERTM Single channel with CLAMP CLAMP GND1 GND2,H VCC1 VCC2,L Control OUT IN+ IN- EiceDRIVERTM Single channel with CLAMP CLAMP GND1 Figure 1 Datasheet GND2,L Typical application 2 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Table of contents Table of contents Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 2.1 2.2 Pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.3 3.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Undervoltage lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Active shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Short circuit clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Active Miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Non-inverting and inverting inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Voltage supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Short circuit clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Active Miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Active shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 6.1 6.2 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reference layout for thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Printed circuit board guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Datasheet 3 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Block diagram 1 Block diagram VCC1 1 UVLO UVLO 5 VCC2 6 OUT 7 CLAMP 8 GND2 & IN+ 2 input filter GND1 & active filter TX RX GND2 VCC1 IN- 3 VCC2 input filter 2V & GND1 Figure 2 Datasheet 4 Block diagram 4 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Pin configuration and functionality 2 Pin configuration and functionality 2.1 Pin configuration Table 1 Pin configuration Pin No. Name Function 1 VCC1 Positive logic supply 2 IN+ Non-inverted driver input (active high) 3 IN- Inverted driver input (active low) 4 GND1 Logic ground 5 VCC2 Positive power supply voltage 6 OUT Driver output 7 CLAMP Active Miller clamp 8 GND2 Power ground 1 VCC1 GND2 8 2 IN+ CLAMP 7 3 IN- OUT 6 4 GND1 VCC2 5 Figure 3 DSO-8 narrow body (top view) 2.2 Pin functionality VCC1 Logic input supply voltage of 3.3 V up to 15 V wide operating range. IN+ non inverting driver input IN+ non-inverted control signal for driver output if IN- is set to low. (Output sourcing active at IN+ = high and IN- = low) Due to internal filtering a minimum pulse width is defined to ensure robustness against noise at IN+. An internal weak pull-down-resistor favors off-state. IN- inverting driver input IN- inverted control signal for driver output if IN+ is set to high. (Output sourcing active at IN- = low and IN+ = high) Due to internal filtering a minimum pulse width is defined to ensure robustness against noise at IN-. An internal weak pull-up-resistor favors off-state. Datasheet 5 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Pin configuration and functionality GND1 Ground connection of input circuit. GND2 reference ground Reference ground of the output driving circuit. VCC2 Positive power supply pin of output driving circuit. A proper blocking capacitor has to be placed close to this supply pin. OUT driver output Combined source and sink output pin to external IGBT. The output voltage will be switched between VCC2 and GND2 and is controlled by IN+ and IN-. In case of an UVLO event this output will be switched off and an active shut down keeps the output voltage at a low level. CLAMP active Miller clamp Connect gate of external IGBT directly to this pin. As soon as the gate voltage has dropped below 2 V referred to GND2 during turn off state the Miller clamp function ties its output to GND2 to avoid parasitic turn on of the connected IGBT. Datasheet 6 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Functional description 3 Functional description The 1EDIxxI12MF is a general purpose isolated gate driver. Basic control and protection features support fast and easy design of highly reliable systems. The integrated galvanic isolation between control input logic and driving output stage grants additional safety. Its wide input voltage supply range supports the direct connection of various signal sources like DSPs and microcontrollers. With the rail-to-rail output and the additional active Miller clamp, dynamic turn on due to Miller capacitance is suppressed. 3.1 Supply The driver can operate over a wide supply voltage range. +5 V VCC1 SGND IN Figure 4 +15 V VCC2 1µ 100n 10R OUT GND1 IN+ CLAMP IN- GND2 Application example The typical positive supply voltage for the driver is 15 V at VCC2. Erratical dynamic turn on of the IGBT can be prevented with the active Miller clamp function, in which the CLAMP output is directly connected to the IGBT gate. Datasheet 7 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Functional description 3.2 Protection features 3.2.1 Undervoltage lockout (UVLO) IN+ VUVLOH1 VUVLOL1 VCC1 VUVLOH2 VUVLOL2 VCC2 OUT Figure 5 UVLO behavior To ensure correct switching of IGBTs the device is equipped with an undervoltage lockout for input and output independently. Operation starts only after both VCC levels have increased beyond the respective VUVLOH levels If the power supply voltage VVCC1 of the input chip drops below VUVLOL1 a turn-off signal is sent to the output chip before power-down. The IGBT is switched off and the signals at IN+ and IN- are ignored until VVCC1 reaches the power-up voltage VUVLOH1 again. If the power supply voltage VVCC2 of the output chip goes down below VUVLOL2 the IGBT is switched off and signals from the input chip are ignored until VVCC2 reaches the power-up voltage VUVLOH2 again. 3.2.2 Active shut-down The active shut-down feature ensures a safe IGBT off-state if the output chip is not connected to the power supply or an undervoltage lockout is in effect. The IGBT gate is clamped at OUT to GND2. 3.2.3 Short circuit clamping During short circuit the IGBT’s gate voltage tends to rise because of the feedback via the Miller capacitance. An additional protection circuit connected to OUT and CLAMP limits this voltage to a value slightly higher than the supply voltage. A maximum current of 500 mA may be fed back to the supply through one of these paths for 10 μs. If higher currents are expected or tighter clamping is desired external Schottky diodes may be added. 3.2.4 Active Miller clamp In a half bridge configuration the switched off IGBT tends to dynamically turn on during turn on phase of the opposite IGBT. A Miller clamp allows sinking the Miller current across a low impedance path in this high dV/dt situation. Therefore in many applications, the use of a negative supply voltage can be avoided. During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage drops below typical 2 V (referred to GND2). The clamp is designed for a Miller current in the same range as the nominal output current. Datasheet 8 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Functional description 3.3 Non-inverting and inverting inputs IN+ IN- OUT Figure 6 Logic input to output switching behavior There are two possible input modes to control the IGBT. At non-inverting mode IN+ controls the driver output while IN- is set to low. At inverting mode IN- controls the driver output while IN+ is set to high. A minimum input pulse width is defined to filter occasional glitches. 3.4 Driver output The output driver section uses MOSFETs to provide a rail-to-rail output. This feature permits that tight control of gate voltage during on-state and short circuit can be maintained as long as the driver’s supply is stable. Due to the low internal voltage drop, switching behavior of the IGBT is predominantly governed by the gate resistor. Furthermore, it reduces the power to be dissipated by the driver. Datasheet 9 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Electrical parameters 4 Electrical parameters 4.1 Absolute maximum ratings Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. Unless otherwise noted all parameters refer to GND1 Table 2 Absolute maximum ratings Parameter Symbol Values Min. Max. 201) Unit Note or Test Condition Power supply output side VVCC2 -0.3 V 2) Gate driver output VOUT VGND2-0.3 VVCC2+0.3 V 2) Maximum short circuit clamping time tCLP – 10 ICLAMP/OUT = 500 mA Positive power supply input side VVCC1 -0.3 Logic input voltages (IN+,IN-) VLogicIN Pin CLAMP voltage 18.0 μs V – -0.3 18.0 V – VCLAMP -0.3 VVCC2 +0.31) V 2) Input to output isolation voltage (GND2) VGND2 -1200 1200 V GND2 - GND1 Junction temperature TJ -40 150 °C – Storage temperature TS -55 150 °C – Comparative tracking index CTI 600 –   IEC 60601-1: Material group II Power dissipation (Input side) PD, IN – 25 mW 3) @T A = 25°C Power dissipation (Output side) PD, OUT – 400 mW 3) @T Thermal resistance (Input side) RTHJA,IN – 145 K/W 3) @T Thermal resistance (Output side) RTHJA,OUT – 165 K/W 3) @T ESD capability VESD,HBM – 2 kV Human body model4) VESD,CDM – 1 kV Charged device model5) 1 2 3 4 5 A = 25°C A = 85°C A = 85°C May be exceeded during short circuit clamping. With respect to GND2. See Figure 10 for reference layouts for these thermal data. Thermal performance may change significantly with layout and heat dissipation of components in close proximity. According to ANSI/ESDA/JEDEC-JS-001-2017 (discharging a 100 pF capacitor through a 1.5 kΩ series resistor). According to ANSI/ESDA/JEDEC-JS-002-2014 (TC = test condition in volt) Datasheet 10 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Electrical parameters 4.2 Operating parameters Note: Within the operating range the IC operates as described in the functional description. Unless otherwise noted all parameters refer to GND1. Table 3 Operating parameters Parameter Symbol Values Min. Max. Unit Note or Test Condition Power supply output side VVCC2 13 18 V 6) Power supply input side VVCC1 3.1 17 V – Logic input voltages (IN+,IN-) VLogicIN -0.3 17 V – Pin CLAMP voltage VCLAMP VGND2-0.3 VVCC27) V 6) Switching frequency fsw – 1.0 MHz 8)9) Ambient temperature TA -40 125 °C – – 4.8 K/W 9)@T – 100 kV/μs 9) @ 1000 V Thermal coefficient, junction-top Common mode transient immunity 4.3 Ψth,jt |dVISO/dt| Electrical characteristics Note: The electrical characteristics include the spread of values in supply voltages, load and junction temperatures given below. Typical values represent the median values at TA = 25°C. Unless otherwise noted all voltages are given with respect to their respective GND (GND1 for pins 1 to 3, GND2 for pins 5 to 7). 4.3.1 Voltage supply Table 4 Voltage supply Parameter Symbol Values Min. UVLO threshold input chip UVLO hysteresis input chip (VUVLOH1 - VUVLOL1) 6 8 9 10 Typ. Unit Note or Test Condition Max. VUVLOH1 – 2.85 3.1 V – VUVLOL1 2.55 2.75 – V – VHYS1 0.09 0.10 – V – – 11.9 12.7 V 10) 10.5 11.0 – V 10) UVLO threshold output chip (IGBT VUVLOH2 supply) VUVLOL2 (table continues...) 7 A = 85°C With respect to GND2. May be exceeded during short circuit clamping. do not exceed max. power dissipation Parameter is not subject to production test - verified by design/characterization With respect to GND2. Datasheet 11 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Electrical parameters Table 4 (continued) Voltage supply Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. UVLO hysteresis output chip (VUVLOH1 - VUVLOL1) VHYS2 0.7 0.85 – V – Quiescent current input chip IQ1 – 0.6 1 mA VVCC1 = 5 V IN+ = High, IN- = Low =>OUT = High Quiescent current output chip IQ2 – 1.2 2 mA VVCC2 = 15 V IN+ = High, IN- = Low =>OUT = High 4.3.2 Logic input VIN+L ,VIN-L VIN+H ,VIN-H in 0.7×15 V 10 ig -H ,IN hI np m e, ag t l o tV u + IN 5 VVCC1,max UVLO No driver operation 0.3×15 V 0.7×5 V IN+, 0.7×3.3 V IN- L x , ma tage Vol nput ow I 0.3×5 V 0.3×3.3 V 3.3 Figure 7 15 10 5 VVCC1 VCC1 scaled input threshold voltage of IN+ and IN- Beginning from the input undervoltage lockout level, threshold levels for IN+ and IN- are scaled to VVCC1. The high input threshold is 70% of VVCC1 and the low input threshold is at 30% of VVCC1. Table 5 Logic input Parameter Symbol Values Min. Typ. Unit Note or Test Condition 11)3.1 V ≤ V Max. IN+,IN- low input voltage VIN+L, VIN-L – – 0.3 × VVCC1   IN+,IN- high input voltage VIN+H, VIN-H 0.7 × VVCC1 – –   (table continues...) 11 VCC1 ≤ 17 V Parameter is not subject to production test - verified by design/characterization Datasheet 12 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Electrical parameters Table 5 (continued) Logic input Parameter Symbol Values Min. Typ. Unit Note or Test Condition VVCC1 = 5.0 V Max. IN+,IN- low input voltage VIN+L, VIN-L – – 1.5 V IN+,IN- high input voltage VIN+H, VIN-H 3.5 – – V IN- input current IIN- – 70 200 μA IN+ input current IIN+ – 70 200 4.3.3 Note: Table 6 minimum Peak current rating valid over temperature range! Gate driver Symbol Values Min. High level output peak current (source) 1EDI10I12MF 1EDI20I12MF 1EDI30I12MF IOUT,H,PEAK Low level output peak current (sink) 1EDI10I12MF 1EDI20I12MF 1EDI30I12MF IOUT,L,PEAK 13 VVCC1 = 5.0 V, VIN+ = VVCC1 Gate driver Parameter 12 μA VVCC1 = 5.0 V, VIN- = GND1 Typ. Note or Test Condition A 12) 13) Max. – 1.0 2.0 3.0 Unit IN+ = High, IN- = Low, VVCC2 = 15 V 2.2 4.4 5.9 – 1.0 2.0 3.0 A 2.3 4.1 6.2 12) 13) IN+ = Low, IN- = Low, VVCC2 = 15 V specified min. output current is forced; voltage across the device V(VCC2 - OUT) or V(OUT - GND2) < VVCC2. Parameter is not subject to production test - verified by design/characterization Datasheet 13 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Electrical parameters 4.3.4 Short circuit clamping Table 7 Short circuit clamping Parameter Symbol Values Min. Typ. Unit Note or Test Condition 14)IN+ = High, IN- = Max. Clamping voltage (OUT) (VOUT - VVCC2) VCLPout – 0.9 1.3 V Clamping voltage (CLAMP) (VVCLAMP - VVCC2) VCLPclamp1 – 1.3 – V Clamping voltage (CLAMP) VCLPclamp2 – 0.7 1.1 V 4.3.5 Active Miller clamp Table 8 Active Miller clamp Parameter Symbol Values Min. Typ. ICLAMP,PEAK Low level clamp current 1EDI10I12MF 1EDI20I12MF 1EDI30I12MF Clamp threshold voltage 14 15 16 – Low, ICLAMP = 500 mA (pulse test tCLPmax = 10 μs) 14)IN+ = High, IN- = Low, ICLAMP = 20 mA Note or Test Condition A 15) IN+ = Low, IN- = Low, VCLAMP = 15 V pulsed tpulse = 2 μs 1.0 2.0 3.0 VCLAMP 14)IN+ = High, IN- = Unit Max. – Low, IOUT = 500 mA (pulse test tCLPmax = 10 μs) 1.6 2.0 2.4 V 16) With respect to GND2. Parameter is not subject to production test - verified by design/characterization With respect to GND2. Datasheet 14 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Electrical parameters 4.3.6 Dynamic characteristics Dynamic characteristics are measured with VVCC1 = 5 V and VVCC2 = 15 V. 50% IN+ 80% 50% 20% OUT tPDON tRISE tPDOFF Figure 8 Propagation delay, rise and fall time Table 9 Dynamic characteristics Parameter Symbol Values Min. Typ. tFALL Unit Note or Test Condition CLOAD = 100 pF VIN+ = 50%, VOUT = 50% @ 25°C Max. Input IN to output propagation delay ON tPDON 270 300 330 ns Input IN to output propagation delay OFF tPDOFF 270 300 330 ns Input IN to output propagation delay distortion (tPDOFF - tPDON) tPDISTO -30 5 40 ns Input pulse suppression time IN+, tMININ+, INtMININ- 230 240 – ns IN input to output propagation delay ON variation due to temp tPDONt – – 14 ns 17)C LOAD = 100 pF IN input to output propagation delay OFF variation due to temp tPDOFFt – – 14 ns VIN+ = 50%, VOUT=50% IN input to output propagation delay distortion variation due to temp (tPDOFF-tPDON) tPDISTOt – – 8 ns Rise time tRISE – 10 20 ns Fall time tFALL – 9 19 ns 4.3.7 Active shut down Table 10 Active shut down Parameter Symbol Values Min. Active shut down voltage VACTSD Typ. – 2.0 Unit Note or Test Condition V 18)I Max. 2.3 CLOAD = 1 nF VL 20%, VH 80% OUT-/IOUT-,PEAK=0.1, VCC2 open 17 18 Parameter is not subject to production test - verified by design/characterization With respect to GND2. Datasheet 15 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Package outline 5 Package outline Figure 9 DSO-8 narrow body (Plastic (green) dual small outline package) Datasheet 16 1.10 2023-06-23 EiceDRIVER™ 1EDI Compact (1ED-MF) Single channel isolated gate driver IC with clamp Application notes 6 Application notes 6.1 Reference layout for thermal data Figure 10 Reference layout for thermal data (Copper thickness 35 μm) This PCB layout represents the reference layout used for the thermal characterization. Pin 4 (GND1) and pin 8 (GND2) require each a ground plane of 100 mm² for achieving maximum power dissipation. The package is built to dissipate most of the heat generated through these pins. The thermal coefficient junction-top (Ψth,jt) can be used to calculate the junction temperature at a given top case temperature and driver power dissipation: Tj = Ψth,jt ⋅ PD + Ttop 6.2 Printed circuit board guidelines The following factors should be taken into account for an optimum PCB layout. • Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits. • The same minimum distance between two adjacent high-side isolated parts of the PCB should be maintained to increase the effective isolation and to reduce parasitic coupling. • In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be kept as short as possible. Revision history Document version Date of release Description of changes 1.10 2023-06-23 Change of template, general layout, and version numbering system minimum value of tRISE and tFALL removed Added footnote for gate driver output current 2.0 2014-11-10 Parameter finalized, editorial changes 1.02 2014-10-14 Parameter list completed Datasheet 17 1.10 2023-06-23 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2023-06-23 Published by Infineon Technologies AG 81726 Munich, Germany   © 2023 Infineon Technologies AG All Rights Reserved.   Do you have a question about any aspect of this document? Email: erratum@infineon.com   Document reference IFX-rat1468407400815 Important notice The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. Warnings Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.