2ED2182S06FXUMA1

2ED2182 (4) S06F (J) 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode Features Product summary • • • • • • • • • • • • • • VS_OFFSET = 650 V max Io+pk / Io- pk(typ.) =+ 2.5 A/ - 2.5 A VCC = 10 V to 20 V Delay matching = 35 ns max. Deadtime (typ.) = 400 ns tON / tOFF (typ.) = 200 ns/ 200 ns • • • Unique Infineon Thin-Film-Silicon on Insulator (SOI)-Technology Negative VS transient immunity of 100 V Floating channel designed for bootstrap operation Operating voltages (VS node) upto + 650 V Maximum bootstrap voltage (VB node) of + 675 V Integrated ultra-fast, low resistance bootstrap diode Logic Operational up to –11 V on VS Pin Negative Voltage Tolerance on Inputs of –5 V Independent under voltage lockout for both channels Schmitt trigger inputs with hysteresis 3.3 V, 5 V and 15 V input logic compatible Maximum supply voltage of 25 V Dual package options of DSO-8 and DSO-14 High and Low Voltage Pins Separated for Maximum Creepage and Clearance (2ED21824S06J version) Separate logic and power ground with the 2ED21824S06J version Interlocking function with internal 400 ns dead time and programmable up to 5 us with external resistor (2ED21824S06J only) RoHS compliant Packages DSO-8 DSO-14 Potential applications Driving IGBTs, enhancement mode N-Channel MOSFETs in various power electronic applications. Typical Infineon recommendations are as below: • Motor drives, general purpose inverters having TRENCHSTOP™ IGBT6 or 600 V EasyPACK™ modules • Refrigeration compressors, induction cookers, other major home appliances having RCD series IGBTs or TRENCHSTOP™ family IGBTs or their equivalent power stages • Battery operated small home appliances such as power tools, vaccum cleaners using low voltage OptiMOS™ MOSFETs or their equivalent power stages • Totem pole, half-bridge and full-bridge converters in offline AC-DC power supplies for industrial SMPS having high voltage CoolMOS™ super junction MOSFETs or TRENCHSTOP™ H3 and WR5 IGBT series or their equivalent • High power LED and HID lighting having CoolMOS™ super junction MOSFETs • Electric vehicle (EV) charging stations and battery management systems • Driving 650 V SiC MOSFETs in above applications Product validation Qualified for industrial applications according to the relevant tests of JEDEC47/20/22 Ordering information Base part number 2ED2182S06F 2ED21824S06J Datasheet www.infineon.com/soi Package type DSO-8 DSO -14 Standard pack Form Tape and Reel Tape and Reel Quantity 2500 2500 Orderable part number 2ED2182S06FXUMA1 2ED21824S06JXUMA1 Please read the Important Notice and Warnings at the end of this document Page 1 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode Description The 2ED2182(4)S06F(J) is a half-bridge high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Based on Infineon’s SOI-technology there is an excellent ruggedness and noise immunity with capability to maintain operational logic at negative voltages of up to - 11 VDC on VS pin (VCC = 15 V) on transient voltages. There are not any parasitic thyristor structures present in the device, hence no parasitic latch up may occur at all temperature and voltage conditions. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET, SiC MOSFET or IGBT in the high side configuration, which operate up to 650 V. Up to 650V Up to 650V 2ED21824S06J 2ED2182S06F 14 HIN 1 HIN HIN 1 HIN VB 8 LIN 2 LIN VB 13 LIN 2 LIN HO 7 VSS 3 VSS HO 12 3 COM VS 6 4 DT VS 11 VCC 5 5 COM 10 6 LO 9 7 VCC 8 RDT 4 LO VCC TO LOAD VCC TO LOAD *Bootstrap diode is monolithically integrated This diagram shows electrical connections only. Please refer to our application notes and design tips for proper circuit board layout. Figure 1 Typical application block diagram Summary of feature comparison of the 2ED218x family Table 1 Part No. Package Drive current source / sink 2ED2181S06F DSO – 8 + 2.5 A / - 2.5 A 2ED21814S06J DSO – 14 HIN, + 2.5 A / - 2.5 A LIN 2ED2182S06F DSO – 8 + 2.5 A / - 2.5 A 2ED21824S06J DSO – 14 HIN, + 2.5 A / - 2.5 A LIN 2ED2183S06F DSO – 8 + 2.5 A / - 2.5 A 2ED21834S06J DSO – 14 HIN, + 2.5 A / - 2.5 A LIN 2ED2184S06F DSO – 8 + 2.5 A / - 2.5 A 2ED21844S06J DSO – 14 Datasheet www.infineon.com/soi Input logic Cross conduction Deadtime prevention logic Ground tON / tOFF pins COM No Yes Yes + 2.5 A / - 2.5 A IN, SD 2 of 26 Yes None VSS / COM Internal 400 ns COM Programmable 400 ns - 5000 ns VSS / COM Internal 400 ns COM Programmable 400 ns - 5000 ns VSS / COM Internal 400 ns COM Programmable 400 ns - 5000 ns VSS / COM 200 ns / 200 ns 600 ns / 200 ns V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V Half-Bridge gate driver with integrated bootstrap diode 1 Table of contents Product summary ........................................................................................................................................................ 1 Product validation ....................................................................................................................................................... 1 Description………………………………………………………………………………………………………………….2 Summary of feature comparison of the 2ED218x family ............................................................................................ 2 1 Table of contents ................................................................................................................... 3 2 Block diagram........................................................................................................................ 4 3 3.1 3.2 Pin configuration and functionality .......................................................................................... 5 Pin configuration ..................................................................................................................................... 5 Pin functionality ...................................................................................................................................... 5 4 4.1 4.2 4.3 4.4 Electrical parameters ............................................................................................................. 6 Absolute maximum ratings ..................................................................................................................... 6 Recommended operating conditions..................................................................................................... 6 Static electrical characteristics ............................................................................................................... 7 Dynamic electrical characteristics .......................................................................................................... 8 5 Application information and additional details .......................................................................... 9 5.1 IGBT / MOSFET gate drive ....................................................................................................................... 9 5.2 Switching and timing relationships ........................................................................................................ 9 5.3 Deadtime and matched propagation delays ....................................................................................... 10 5.4 Input logic compatibility ....................................................................................................................... 12 5.5 Undervoltage lockout ........................................................................................................................... 12 5.6 Bootstrap diode..................................................................................................................................... 13 5.7 Calculating the bootstrap capacitance CBS .......................................................................................... 13 5.8 Tolerant to negative tranisents on input pins ...................................................................................... 15 5.9 Negative voltage transient tolerance of VS pin .................................................................................... 15 5.10 NTSOA – Negative Transient Safe Operating Area ............................................................................... 17 5.11 Higher headroom for input to output signal transmission with logic operation upto -11 V .............. 18 5.12 Maximum switching frequency ............................................................................................................. 18 5.13 PCB layout tips ...................................................................................................................................... 19 6 Qualification information....................................................................................................... 21 7 Related products................................................................................................................... 21 8 Package details ..................................................................................................................... 22 9 Part marking information ...................................................................................................... 23 10 Additional documentation and resources................................................................................. 24 10.1 Infineon online forum resources .......................................................................................................... 24 11 Revision history .................................................................................................................... 25 Datasheet www.infineon.com/soi 3 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 2 Block diagram LIN 1 R Deadtime VCC UV DETECT VCC VSS/COM LEVEL SHIFT 4 LIN 2 VSS 3 Figure 2 5 VCC 4 LO 3 COM 13 VB R Deadtime VCC UV DETECT Q 12 HO 11 VS 7 VCC 6 LO 5 COM S Pulse Generator DT VS R Pulse Filter DT 6 UV DETECT 2ED21824S06J 1 HO BS diode Delay Match HIN Q S Pulse Generator 2 7 R Pulse Filter DT VB UV DETECT 2ED2182S06F HIN 8 BS diode VCC VSS/COM LEVEL SHIFT Delay Match Block diagrams Datasheet www.infineon.com/soi 4 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 3 Pin configuration and functionality 3.1 Pin configuration 1 HIN VB 8 2 LIN HO 7 3 COM VS 6 4 LO VCC 5 8-Lead DSO-8 (150 mil) 2ED2182S06F Figure 3 3.2 14 1 HIN 2 LIN VB 13 3 VSS HO 12 4 DT VS 11 5 COM 10 6 LO 9 7 VCC 8 14-Lead DSO-14 (150 mil) 2ED21824S06J 2ED2182(4)S06F(J) pin assignments (top view) Pin functionality Table 2 Symbol Description HIN Logic input for high side gate driver output (HO), in phase with HO LIN Logic input for low side gate driver output (LO), in phase with LO VSS Logic ground ( 2ED21824S06J only) DT Programmable dead-time, referenced to VSS.( 2ED21824S06J only) COM Low-side gate drive return LO Low-side driver output VCC Low-side and logic supply voltage VS High voltage floating supply return HO High-side driver output VB High-side gate drive floating supply Datasheet www.infineon.com/soi 5 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 4 Electrical parameters 4.1 Absolute maximum ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM unless otherwise stated in the table. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Table 3 Symbol VB VS VHO VCC VLO VIN Vss DT dVS/dt PD RthJA TJ TS TL Absolute maximum ratings Definition High-side floating well supply voltage (Note 1) High-side floating well supply return voltage Floating gate drive output voltage Low side supply voltage Low-side output voltage Logic input voltage (HIN & LIN) Logic ground (2ED21824S06J only) Programmable dead time pin voltage (2ED21824S06J only) Allowable VS offset supply transient relative to COM Package power dissipation 8-Lead DSO-8 14-Lead DSO-14 @ TA +25ºC Thermal resistance, junction 8-Lead DSO-8 to ambient 14-Lead DSO-14 Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) Min. VCC – 5 VCC – VBS– 5 Max. VS – 0.5 -1 –0.5 -5/ (VSS – 5) VCC – 25 675 650 VB + 0.5 25 VCC + 0.5 VCC + 0.5 VCC + 0.5 VSS – 5 VCC + 0.5 — — — — — — -55 — 50 0.625 1 200 120 150 150 300 Units V V/ns W ºC/W ºC Note 1: In case VCC > VB there is an additional power dissipation in the internal bootstrap diode between pins VCC and VB. 4.2 Recommended operating conditions For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to COM unless otherwise stated in the table. The offset rating is tested with supplies of (VCC – COM) = (VB – VS) = 15 V. Table 4 Recommended operating conditions Symbol Definition VB Bootstrap voltage VBS High-side floating well supply voltage VS High-side floating well supply offset voltage VHO Floating gate drive output voltage VCC Low-side supply voltage VLO Low-side output voltage VIN Logic input voltage(HIN & LIN) Logic ground (2ED21824S06J only) with respect to VSS COM Programmable dead time pin voltage DT (2ED21824S06J only) TA Ambient temperature Note 2: Logic operation for VS of – 10 V to +650 V. Datasheet www.infineon.com/soi 6 of 26 Min Max VS + 10 10 VCC – VBS– 1 VS 10 COM -4 / (VSS – 4) VS + 20 20 650 VB 20 VCC 5 / (VSS + 5) -5 +5 VSS – 4 5 -40 125 Units V ºC V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 4.3 Static electrical characteristics (VCC– COM) = (VB – VS) = 15 V, VSS = COM and TA = 25 °C unless otherwise specified. The VIL, VIH and IIN parameters are referenced to Vss / COM and are applicable to the respective input leads: HIN and LIN. The VO and IO parameters are referenced to VS / COM and are applicable to the respective output leads HO or LO. The V CCUV parameters are referenced to COM. The VBSUV parameters are referenced to VS. Table 5 Static electrical characteristics Symbol Min. Typ. Max. 7.6 8.2 8.9 6.7 7.2 8.1 — 1.0 — 8.4 9.1 9.8 7.5 8.2 8.9 — — — — — — 1.65 0.9 1 170 550 0.05 0.02 2.2 — 12.5 — — 0.2 0.1 — Peak output current turn-on1 — 2.5 — Io-mean Mean output current from 12 V to 9 V 1.65 2.2 — VBSUV+ VBSUVVBSUVHY VCCUV+ VCCUVVCCUVHY ILK IQBS IQCC VOH VOL Io+mean Io+ Units Test Conditions V uA VB = VS = 650 V All inputs are in the off state V IO = 20 mA A CL = 22 nF VO = 0 V PW ≤ 10 µs CL = 22 nF VO = 15 V PW ≤ 10 µs V Vcc=10 V to 20 V µA VIN = 5 V VIN = 0 V Io- Peak output current turn-off1 — 2.5 — VIH VIL IIN+ IIN- Logic “1” input voltage Logic “0” input voltage Input bias current (Output = High) Input bias current (Output = Low) Bootstrap diode forward voltage between Vcc and VB Bootstrap diode forward current between Vcc and VB Bootstrap diode resistance Allowable Negative VS pin voltage for IN Signal propagation to HO 1.7 0.7 — — 2.1 0.9 25 — 2.4 1.1 50 1 — 1 1.2 V IF=0.3 mA 55 100 145 mA VCC-VB=4 V 15 25 40 Ω VF1=4V,VF2=5 V — -11 -10 V Vcc=15 V VFBSD IFBSD RBSD VS 1 Definition VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VBS supply undervoltage hysteresis VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold VCC supply undervoltage hysteresis High-side floating well offset supply leakage Quiescent VBS supply current Quiescent VCC supply current High level output voltage drop, Vcc- VLO , VB- VHO Low level output voltage drop, VO Mean output current from 3 V to 6 V Not subjected to production test, verified by characterization. Datasheet www.infineon.com/soi 7 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 4.4 Dynamic electrical characteristics VCC = VBS= 15 V, VSS = COM, TA = 25 oC and CL = 1000 pF unless otherwise specified. Table 6 Symbol tON tOFF tR tF MT Dynamic electrical characteristics Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time Delay matching time (HS & LS turnon/off) DT Deadtime: LO Turn-off to HO Turn-on & HO Turn-off to LO turn-on MDT Deadtime matching= I DTLO-HO – DTHO-LO I Datasheet www.infineon.com/soi Min. Typ. Max. — — — — 200 200 15 15 300 300 30 30 — — 35 260 400 540 4 5 6 — — 60 — — 600 8 of 26 Units Test Conditions VS = 0 V or 650 V ns us ns VS = 0 V RDT=0 Ω RDT=200 kΩ (2ED21824S06J) RDT=0 Ω RDT=200 kΩ (2ED21824S06J) V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 5 Application information and additional details 5.1 IGBT / MOSFET gate drive The 2ED2182 (4) S06F (J) HVIC is designed to drive MOSFET or IGBT power devices. Figures 4 and 5 illustrate several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the high-side power switch and VLO for the low-side power switch; this parameter is sometimes generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage. VB (or VCC) VB (or VCC) IO+ HO (or LO) HO (or LO) + IO- VHO (or VLO) VS (or COM) Figure 4 - VS (or COM) HVIC Sourcing current 5.2 Figure 5 HVIC Sinking current Switching and timing relationships The relationships between the input and output signals of the 2ED2182 (4) S06F (J) are illustrated below in Figure 6 and Figure 7. From these figures, we can see the definitions of several timing parameters (i.e. tON, tOFF, tR, and tF) associated with this device. 50% 50% HIN LIN tON tR tOFF 90% HO LO Figure 6 10% Switching timing diagram Datasheet www.infineon.com/soi tF 90% 10% Figure 7 9 of 26 Input/output logic diagram V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 5.3 Deadtime and matched propagation delays This 2ED2182 (4) S06F (J) features integrated deadtime protection circuitry. The deadtime is fixed for 2ED2182S06F; is programmable for 2ED2182S06J, it provides greater design flexibility. The deadtime feature inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserter whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified by the gate driver. Figure 8 illustrates the deadtime period and the relationship between the output gate signals. The deadtime circuitry of 2ED2182 (4) S06F (J) is matched with respect to the high- and low-side outputs. Figure 9 defines the two deadtime parameters (i.e., DTLO-HO and DTHO-LO); the deadtime matching parameter (MDT) associated with the 2ED2182S06F (J) specifies the maximum difference between DTLO-HO and DTHO-LO. LIN 1 .65 V 1. 65 V HIN 12 V 3V HO DT DT LO 12 V 3V Figure 8 Dead Time Definitions Figure 9 Delay Matching Waveform Definitions The 2ED2182 (4) S06F (J) is designed with propagation delay matching circuitry. With this feature, the IC’s response at the output to a signal at the input requires approximately the same time duration (i.e., t ON, tOFF) for both the low-side channels and the high-side channels; the maximum difference is specified by the delay matching parameter (MT). The propagation turn-on delay (tON) of the 2ED2182 (4) S06F (J) is matched to the propagation turn-on delay (tOFF). The 14-pin variant (2ED21824S06J) provides greater design flexibility with a programmable dead-time feature using an external resistor (RDT) connected between the DT pin and VSS pin as shown in figure 10. A decoupling ceramic capacitor (CDT > 1 nF) is recommended which is parallel with RDT. Datasheet www.infineon.com/soi 10 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode Up to 650V 2ED21824S06J 14 HIN 1 HIN LIN 2 LIN VB 13 3 VSS HO 12 4 DT VS 11 5 COM 10 6 LO 9 7 VCC 8 VSS RDT CDT VCC Figure 10 TO LOAD 14-pin half-bridge variants having adjustable dead-time feature settable with a resistor Figure 11 shows the linear relationship between the resistor (RDT) and dead time. Based on the end application, designers can choose to add the external resistor to increase the dead time. In case the DT pin is left open, the gate driver enters protection mode switching off the output stages. Hence this pin has to be connected to VSS pin with a 0 ohm to 200 k resistor based on application requirements. A 0 ohm (or shorted) provides a minimum deadtime of 400 ns and 200 k ohm provides a maximum deadtime of 5 us. Programmable dead time in 2ED21824S06J 6 Deadtime in us 5 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 External Resistor in kΩ Figure 11 Variation of dead time vs. external resistor Datasheet www.infineon.com/soi 11 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 5.4 Input logic compatibility The input pins of are based on a TTL and CMOS compatible input-threshold logic that is independent of the Vcc supply voltage. With typical high threshold (VIH) of 2.1 V and typical low threshold (VIL) of 0.9 V, along with very little temperature variation as summarized in Figure 12, the input pins are conveniently driven with logic level PWM control signals derived from 3.3 V and 5 V digital power-controller devices. Wider hysteresis (typically 0.9 V) offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. 2ED218x family also features tight control of the input pin threshold voltage levels which eases system design considerations and ensures stable operation across temperature. The 2ED218x features floating input protection wherein if any of the input pin is left floating, the output of the corresponding stage is held in the low state. This is achieved using pull-down resistors on all the input pins (HIN, LIN) as shown in the block diagram. The 2ED218x family has input pins that are capable of sustaining voltages higher than the bias voltage applied on the Vcc pin of the device. Input Signal (IRS23364D) VIH Input Logic Level VIL High Low Figure 12 5.5 Low HIN & LIN input thresholds Undervoltage lockout This IC provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and the VBS (high-side circuitry) power supply. Figure 13 is used to illustrate this concept; VCC (or VBS) is plotted over time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or disabled. Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC won’t turn-on. Additionally, if the VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault condition and shutdown the high and low-side gate drive outputs. Upon power-up, should the VBS voltage fail to reach the VBSUV+ threshold, the IC won’t turn-on. Additionally, if the VBS voltage decreases below the VBSUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the IC. The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high conduction losses within the power device and could lead to power device failure. Datasheet www.infineon.com/soi 12 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode VCC (or VBS) VCCUV(or VBSUV-) VCCUV+ (or VBSUV+) Time UVLO Protection (Gate Drive Outputs Disabled) Normal Operation Figure 13 5.6 Normal Operation UVLO protection Bootstrap diode An ultra-fast bootstrap diode is monolithically integrated for establishing the high side supply. The differential resistor of the diode helps to avoid extremely high inrush currents when initially charging the bootstrap capacitor. The integrated diode with its resistrance helps save cost and improve reliability by reducing external components as shown below figures 14 and 15. Figure 14 2ED218x with integrated components Figure 15 Standard bootstrap gate driver The low ohmic current limiting resistor provides essential advantages over other competitor devices with high ohmic bootstrap structures. A low ohmic resistor such as in the 2ED218x family allows faster recharching of the bootstrap capacitor during periods of small duty cycles on the low side transistor. The bootstrap diode is usable for all kind power electronic converters. The bootstrap diode is a real pn-diode and is temperature robust. It can be used at high temperatures with a low duty cycle of the low side transistor. The bootstrap diode of the 2ED218x family works with all control algorithms of modern power electronics, such as trapezoidal or sinusoidal motor drives control. 5.7 Calculating the bootstrap capacitance CBS Bootstrapping is a common method of pumping charges from a low potential to a higher one. With this technique a supply voltage for the floating high side sections of the gate drive can be easily established according to Figure 16. This method has the advantage of being simple and low cost but may force some limitations on duty-cycle 1 and on-time since they are limited by the requirement to refresh the charge in the bootstrap capacitor.Proper capacitor choice can reduce drastically these limitations. Datasheet www.infineon.com/soi 13 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode Figure 16 Half bridge bootstrap circuit in 2ED218x When the low side MOSFET turns on, it will force the potential of pin VS to GND. The existing difference between the voltage of the bootstrap capacitor VCBS and VCC results in a charging current IBS into the capacitor CBS. The current IBS is a pulse current and therefore the ESR of the capacitor CBS must be very small in order to avoid losses in the capacitor that result in lower lifetime of the capacitor. This pin is on high potential again after low side is turned off and high side is conducting current. But now the bootstrap diode DBS blocks a reverse current, so that the charges on the capacitor cannot flow back to the capacitor CVCC. The bootstrap diode DBS also takes over the blocking voltage between pin VB and VCC. The voltage of the bootstrap capacitor can now supply the high side gate drive sections. It is a general design rule for the location of bootstrap capacitors CBS, that they must be placed as close as possible to the IC. Otherwise, parasitic resistors and inductances may lead to voltage spikes, which may trigger the undervoltage lockout threshold of the individual high side driver section. The current limiting resistor RBS according to Figure 16 reduces the peak of the pulse current during the low side MOSFET turn-on. The pulse current will occur at each turn-on of the low side MOSFET, so that with increasing switching frequency the capacitor CBS is charged more frequently. Therefore a smaller capacitor is suitable at higher switching frequencies. The bootstrap capacitor is mainly discharged by two effects: The high side quiescent current and the gate charge of the high side MOSFET to be turned on. The minimum size of the bootstrap capacitor is given by 𝐶𝐵𝑆 = 𝑄𝐺𝑇𝑂𝑇 ∆𝑉𝐵𝑆 VBS is the maximum allowable voltage drop at the bootstrap capacitor within a switching period, typically 1 V. It is recommended to keep the voltage drop below the undervoltage lockout (UVLO) of the high side and limit VBS ≤ (VCC – VF– VGSmin– VDSon) VGSmin > VBSUV- , VGSmin is the minimum gate source voltage we want to maintain and VBSUV- is the high-side supply undervoltage negative threshold. VCC is the IC voltage supply, VF is bootstrapdiode forward voltage and VDSon is drain-source voltage of low side MOSFET. Please note, that the value QGTOT may vary to a maximum value based on different factors as explained below and the capacitor shows voltage dependent derating behavior of its capacitance. The influencing factors contributing VBS to decrease are: Datasheet www.infineon.com/soi 14 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode - MOSFET turn on required Gate charge (QG) - MOSFET gate-source leakage current (ILK_GS) - Floating section quiescent current (IQBS) - Floating section leakage current (ILK) - Bootstrap diode leakage current (ILK_DIODE) - Charge required by the internal level shifters (𝑄𝐿𝑆 ): typical 1nC - Bootstrap capacitor leakage current (ILK_CAP) - High side on time (THON) Considering the above, 𝑄𝐺𝑇𝑂𝑇 = 𝑄𝐺 + 𝑄𝐿𝑆 + (𝐼𝑄𝐵𝑆 + 𝐼𝐿𝐾𝐺𝑆 + 𝐼𝐿𝐾 + 𝐼𝐿𝐾𝐷𝐼𝑂𝐷𝐸 + 𝐼𝐿𝐾𝐶𝐴𝑃 ) ∗ 𝑇𝐻𝑂𝑁 ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor (paralleling electrolytic capacitor and low ESR ceramic capacitor may result in an efficient solution). The above CBS equation is valid for pulse by pulse considerations. It is easy to see, that higher capacitance values are needed, when operating continuously at small duty cycles of low side. The recommended bootstrap capacitance is therefore in the range up to 4.7 μF for most switching frequencies. The performance of the integrated bootstrap diode supports the requirement for small bootstrap capacitances. 5.8 Tolerant to negative tranisents on input pins Typically the driver's ground pin is connected close to the source pin of the MOSFET or IGBT. The microcontroller which sends the HIN and LIN PWM signals refers to the same ground and in most cases there will be an offset voltage between the microcontroller ground pin and driver ground because of ground bounce. The 2ED218x family can handle negative voltage spikes up to 5 V. The recommended operating level is at negative 4 V with absolute maximum of negative 5 V. Standard half bridge or high-side/low-side drivers only allow negative voltage levels down to -0.3 V. The 2ED218x family has much better noise immunity capability on the input pins. Figure 17 5.9 Negative voltage tolerance on inputs of upto –5 V Negative voltage transient tolerance of VS pin A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage as the power switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit is shown in Figure 18, here we define the power switches and diodes of the inverter. Datasheet www.infineon.com/soi 15 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode If the high-side switch (e.g., the IGBT Q1 in Figures 19 and 20) switches from on to off, while the U phase current is flowing to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC bus voltage to the negative DC bus voltage. DC+ BUS D1 Q1 Input Voltage VS1 Q2 D3 Q3 VS2 U D2 Q4 D5 Q5 VS3 V D4 W To Load D6 Q6 DC- BUS Figure 18 Three phase inverter Also when the V phase current flows from the inductive load back to the inverter (see Figures 19 C) and D)), and Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2, swings from the positive DC bus voltage to the negative DC bus voltage. However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient” DC+ BUS Q1 ON Q1 OFF DC+ BUS DC+ BUS DC+ BUS D1 Q3 OFF D3 IU Q3 OFF D3 IV VS1 VS2 VS2 VS1 IV IU Q2 OFF D2 A) DC- BUS Figure 19 Q2 OFF D2 DC- BUS A) Q1 conducting B) D2 conducting Q4 OFF B) D4 DC- BUS C) D3 conducting Q4 ON C) DC- BUS D) D) Q4 conducting The circuit shown in Figure 20-A depicts one leg of the three phase inverter; Figures 20-B and 20-C show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the PCB tracks are lumped together in L C and LE for each IGBT. When the high-side switch is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS pin). Datasheet www.infineon.com/soi 16 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode DC+ BUS DC+ BUS DC+ BUS + LC1 VLC1 - D1 Q1 + LE1 VLE1 VS1 VS1 LC2 D1 Q1 OFF Q1 ON IU - VS1 - VLC2 IU + Q2 D2 Q2 OFF D2 - Q2 OFF VD2 + - LE2 VLE2 + DC- BUS Figure 20 5.10 A DC- BUS B DC- BUS C Figure A shows the Parasitic Elements. Figure B shows the generation of VS positive. Figure C shows the generation of VS negative NTSOA – Negative Transient Safe Operating Area In a typical motor drive system, dV/dt is typically designed to be in the range of 3 – 5 V / ns. The negative VS transient voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in normal operation. Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications. An indication of the 2ED2182’s robustness can be seen in Figure 21, where the 2ED2182’s Safe Operating Area is shown at VBS=15 V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area (outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC do not appear if negative Vs transients fall inside the SOA. Recommended safe operating area Figure 21 Negative VS transient SOA for 2ED2182(4)S06F(J) @ VBS=15 V Even though the 2ED2182S06F(J) has been shown able to handle these large negative VS transient conditions, it is highly recommended that the circuit designer always limit the negative VS transients as much as possible by careful PCB layout and component use. Datasheet www.infineon.com/soi 17 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 5.11 Higher headroom for input to output signal transmission with logic operation upto -11 V If there is not enough voltage for the level shifter to transmit a valid signal to the high side.High side driver doesn’t turn on. The level shifter circuit is with respect to COM (refer to Block Diagram on page 4), the voltage from VB to COM is the supply voltage of level shifter. Under the condition of VS is negative voltage with respect to COM, the voltage of VS - COM is decreased, as shown in Figure 22. There is a minimum operational supply voltage of level shifter, if the supply voltage of level shifter is too low, the level shifter cannot pass through HIN signal to HO. If VB – VS voltage is different, the minimum VS voltage changes accordingly. VS COM - 11 V Figure 22 5.12 Headroom for HV level shifter data transmission Maximum switching frequency The 2ED218x family is capable of switching at higher frequencies as compared to standard half-bridge or high side / low side gate drivers. They are available in two packages, the PG-DSO-8 and the PG-DSO-14. It is essential to ensure that the component is not thermally overloaded when operating at higher frequencies. This can be checked by means of the thermal resistance junction to ambient and the calculation or measurement of the dissipated power. The thermal resistance is given in the datasheet (section 4) and refers to a specific layout. Changes of this layout may lead to an increased thermal resistance, which will reduce the total dissipated power of the driver IC. One should therefore do temperature measurements in order to avoid thermal overload under application relevant conditions of ambient temperature and housing. The maximum chip temperature TJ can be calculated with 𝑇𝐽 = Pd ∙ 𝑅𝑡ℎ𝐽𝐴 + 𝑇𝐴_𝑚𝑎𝑥 , where TA_max is the maximum ambient temperature. The dissipated power Pd by the driver IC is a combination of several sources. These are explained in detail in the application note “Advantages of Infineon’s Silicon on Insulator (SOI) technology based High Voltage Gate Driver ICs (HVICs)” From above, we arrive at the below figure 23 which estimates the gate driver IC temperature rise when switching a given MOSFET at different switching frequencies. Datasheet www.infineon.com/soi 18 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 140 120 100 80 60 40 20 10.00 100.00 Switching Frequency (kHz) IPW60R037P7 2ED218x4S06J family gate drivers temperature rise Driver IC Junction Temperature (°C) Driver IC Junction Temperature (°C) 2ED218x4S06F family gate drivers temperature rise IPP60R180P7 140 120 100 80 60 40 20 10.00 100.00 Switching Frequency (kHz) IPW60R037P7 IPP60R360P7 IPP60R180P7 IPP60R360P7 *Assumptions for above curves: Ta = 25 °C, VBUS = 400 V, VCC = 12 V, Rgon = 10 Ω, Rgoff = 5Ω. P7 CoolMOS™ super junction MOSFET power disspation has to be verified on lab bench for >300 kHz switching frequencies. Figure 23 5.13 Estimated temperature rise in the 2ED218x family gate drivers for different switching frequencies when switching CoolMOSTM SJ MOSFETs PCB layout tips Distance between high and low voltage components: It’s strongly recommended to place the components tied to the floating voltage pins (VB and VS) near the respective high voltage portions of the device. Please see the Case Outline information in this datasheet for the details. Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating side. Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 24). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect. Figure 24 Avoid antenna loops Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and COM pins. A ceramic 1μF ceramic capacitor is suitable for most applications. This component should be placed as close as possible to the pins in order to reduce parasitic elements. Datasheet www.infineon.com/soi 19 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the VS pin and the switch node (see Figure 25), and in some cases using a clamping diode between COM and VS (see Figure 26). See DT04-4 at www.infineon.com for more detailed explanations. Figure 25 Resistor between the VS pin and the switch node Datasheet www.infineon.com/soi Figure 26 20 of 26 Clamping diode between COM and VS V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 6 Table 7 Qualification information1 Qualification information Qualification level Moisture sensitivity level Charged device model ESD Human body model IC latch-up test RoHS compliant 7 Industrial2 Note: This family of ICs has passed JEDEC’s Industrial qualification. Consumer qualification level is granted by extension of the higher Industrial level. MSL2, 260°C DSO-8 (per IPC/JEDEC J-STD-020) MSL33, 260°C DSO-14 (per IPC/JEDEC J-STD-020) Class C3 (1.0 kV) (per JEDEC standard JS-002) Class 2 (2 kV) (per JEDEC standard JS-001) Class II Level A (per JESD78) Yes Related products Table 8 Product Description Gate Driver ICs 6EDL04I06 / 6EDL04N06 2EDL23I06 / 2EDL23N06 Power Switches IKD04N60R / RF IKD06N65ET6 IPD65R950CFD IPN50R950CE 600 V, 3 phase level shift thin-film SOI gate driver with integrated high speed, low RDS(ON) bootstrap diodes with over-current protection (OCP), 240/420 mA source/sink current drive, Fault reporting, and Enable for MOSFET or IGBT switches. 600 V, Half-bridge thin-film SOI level shift gate driver with integrated high speed, low RDSON bootstrap diode, with over-current protection (OCP), 2.3/2.8 A source/sink current driver, and one pin Enable/Fault function for MOSFET or IGBT switches. 600 V TRENCHSTOP™ IGBT with integrated diode in PG-TO252-3 package 650 V TRENCHSTOP™ IGBT with integrated diode in DPAK 650 V CoolMOS CFD2 with integrated fast body diode in DPAK 500 V CoolMOS CE Superjunction MOSFET in PG-SOT223 package iMOTION™ Controllers IRMCK099 iMOTION™ Motor control IC for variable speed drives utilizing sensor-less Field Oriented Control (FOC) for Permanent Magnet Synchronous Motors (PMSM). IMC101T High performance Motor Control IC for variable speed drives based on field oriented control (FOC) of permanent magnet synchronous motors (PMSM). Qualification standards can be found at Infineon’s web site www.infineon.com Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales representative for further information. 3 DSO-14 package with MSL2 rating is available if required. Please contact your Infineon sales representative for further information. Datasheet 21 of 26 V 2.31 www.infineon.com/soi 2021-10-11 1 2 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 8 Package details Figure 27 8 - Lead DSO (2ED2182S06F) Figure 28 14- Lead DSO (2ED21824S06J) Datasheet www.infineon.com/soi 22 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 9 Part marking information Front Side Back Side 2ED2182 Part number XXX Infineon logo XXXX Lot code H YYWW Pin 1 identifier XXXX X Date code Assembly site code (may vary) Figure 29 Marking information PG-DSO-8 Front Side Infineon logo Date code Pin 1 identifier Figure 30 2D21824S06J Part number H YYWW XXX Assembly site code XXXXXXXXXXX Lot code Marking information PG-DSO-14 Datasheet www.infineon.com/soi 23 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 10 Additional documentation and resources Several technical documents related to the use of HVICs are available at www.infineon.com; use the Site Search function and the document number to quickly locate them. Below is a short list of some of these documents. Application Notes: Understanding HVIC Datasheet Specifications HV Floating MOS-Gate Driver ICs Use Gate Charge to Design the Gate Drive Circuit for Power MOSFETs and IGBTs Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality Design Tips: Using Monolithic High Voltage Gate Drivers Alleviating High Side Latch on Problem at Power Up Keeping the Bootstrap Capacitor Charged in Buck Converters Managing Transients in Control IC Driven Power Stages Simple High Side Drive Provides Fast Switching and Continuous On-Time 10.1 Infineon online forum resources The Gate Driver Forum is live at Infineon Forums (www.infineonforums.com). This online forum is where the Infineon gate driver IC community comes to the assistance of our customers to provide technical guidance – how to use gate drivers ICs, existing and new gate driver information, application information, availability of demo boards, online training materials for over 500 gate driver ICs. The Gate Driver Forum also serves as a repository of FAQs where the user can review solutions to common or specific issues faced in similar applications. Register online at the Gate Driver Forum and learn the nuances of efficiently driving a power switch in any given power electronic application. Datasheet www.infineon.com/soi 24 of 26 V 2.31 2021-10-11 2ED2182 (4) S06F (J) 650 V half-bridge gate driver with integrated bootstrap diode 11 Document version 2.00 2.10 2.20 2.21 2.30 2.31 Revision history Date of release Description of changes July 30, 2019 Final Datasheet September 12, 2019 Revised parameter values in Tables 5 & 7 to match the test conditions. Updated figure 1 to include 14 pin variant typical connection diagram. January 14, 2020 Revised parameter values in Table 7 to match the test conditions. Added deadtime settings section in page 10-11, revised DSO-14 pin package marking July 07, 2020 IC latch-up test per JESD78 June 1, 2021 Added the recommended CDT capacitor on deadtime pin as shown in figure 10. Updated block diagrams in Figure 2. Oct. 11, 2021 Merge V2.21 and V2.30. Added interlocking function under Features section on page 1. Datasheet www.infineon.com/soi 25 of 26 V 2.31 2021-10-11 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2021-10-11 Published by Infineon Technologies AG 81726 Munich, Germany © 2021 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? 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