2EDL05I06PF

2EDL05 family 2EDL05x06xx family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD) Features • • • • • • • • • • • • Infineon thin-film-SOI-technology Fully operational to +600 V Floating channel designed for bootstrap operation Output source/sink current capability +0.36 A/-0.7 A Integrated Ultra-fast, low RDS(ON) Bootstrap Diode Tolerant to negative transient voltage up to -100 V (Pulse width is up 300 ns) given by SOI-technology 10 ns typ., 60 ns max. propagation delay matching dV/dt immune ±50 V Gate drive supply range from 10 V to 20 V Undervoltage lockout for both channels 3.3 V, 5 V and 15 V input logic compatible RoHS compliant Product summary VOFFSET IO+/- (typ.) VOUT Delay Matching tf/tr (typ.) = 620 V max. = 0.36 A/0.7 A = 10 V - 17.5 V = 60 ns max. = 24 ns/48 ns Package DSO-14 DSO-8 Potential applications • • • Motor drives, General purpose inverters Refrigeration compressors, home appliance Half-bridge and full-bridge converters in offline AC-DC power supplies for telecom and lighting Product validation Qualified for industrial applications according to the relevant tests of JEDEC47/20/22. Description The 2ED05 is a 600-V half-bridge gate driver family. Its Infineon thin-film-SOI technology provides excellent ruggedness and noise immunity. The Schmitt trigger logic inputs are compatible with standard CMOS or LSTTL logic down to 3.3 V. The output drivers features a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 V. Additionally, the offline clamping function provides an inherent protection of the parasitic turn-on by floating gate conditions when IC is not supplied. DC-Bus VCC +5V µC VB HO 2EDL05x06yy VS VCC PWM_H HIN PWM_L LIN GND GND LO To Load To Opamp / Comparator Refer to lead assignments for correct pin configuration. This diagram show electrical connections only. Please refer to our application notes and design tips for proper circuit board layout. - DC-Bus Figure 1 Typical application diagram 2EDL05 family Datasheet Please read the Important Notice and Warnings at the end of this document www.infineon.com/gdHalfBridge 1 of 21 Version 2.9 2019-01-24 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD) Ordering information Ordering information Special output Target typ. LS UVLO- Bootstrap function current transistor thresholds diode 2EDL05I06PF deadtime, 2EDL05I06PJ interlock IGBT 12.5 V / 11.6 V 2EDL05I06BF – 0.5 A Yes 2EDL05N06PF deadtime, MOSFET 9.1 V / 8.3 V 2EDL05N06PJ interlock Sales Name Package Evaluation board DSO-8 DSO-14 DSO-8 DSO-8 DSO-14 EVAL-2EDL05I06PF Table of contents Features ........................................................................................................................................ 1 Product summary ........................................................................................................................... 1 Package ......................................................................................................................................... 1 Potential applications ..................................................................................................................... 1 Product validation .......................................................................................................................... 1 Description .................................................................................................................................... 1 Ordering information ...................................................................................................................... 2 Table of contents ............................................................................................................................ 2 1 Block diagram........................................................................................................................ 3 2 Lead definitions ..................................................................................................................... 3 3 Functional description ............................................................................................................ 4 3.1 Low Side and High Side Control Pins (LIN, HIN)..................................................................................... 4 3.1.1 Input voltage range ............................................................................................................................ 4 3.1.2 Switching levels.................................................................................................................................. 4 3.1.3 Input filter time .................................................................................................................................. 4 3.2 VDD and GND ........................................................................................................................................... 4 3.3 VB and VS (High Side Supplies) ............................................................................................................... 5 3.4 LO and HO (Low and High Side Outputs) ............................................................................................... 5 3.5 Undervoltage lockout (UVLO) ................................................................................................................. 5 3.6 Bootstrap diode....................................................................................................................................... 5 3.7 Deadtime and interlock function............................................................................................................ 6 3.8 Tolerant to negative transient voltage on VS pin (-VS) .......................................................................... 6 4 4.1 4.2 4.3 4.4 4.5 4.6 Electrical parameters ............................................................................................................. 9 Absolute maximum ratings ..................................................................................................................... 9 Required operation conditions............................................................................................................. 10 Operating Range ................................................................................................................................... 10 Static logic function table ..................................................................................................................... 11 Static parameters .................................................................................................................................. 11 Dynamic parameters ............................................................................................................................. 13 5 Timing diagrams ................................................................................................................... 14 6 Package information ............................................................................................................. 17 7 Qualification information....................................................................................................... 19 8 Related products................................................................................................................... 19 Revision history............................................................................................................................. 20 2EDL05 family Datasheet www.infineon.com/gdHalfBridge 2 of 21 Version 2.9 2019-01-24 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode 1 Block diagram VDD VDD LIN HV LEVEL-SHIFTER + REVERSE-DIODE LATCH UVDETECT GateDrive HO VS VDD UVDETECT GateDrive DELAY LO Functional block diagram 2 Lead definitions 2EDL05 family lead definitions Name VDD 2 HIN 3 LIN 4 5 6 7 8 GND LO VS HO VB Function Low-side and logic supply voltage Logic input for high-side gate driver output (HO), in phase. Schmitt trigger inputs with hysteresis and pull down Logic input for low-side gate driver output (LO), in phase. Schmitt trigger inputs with hysteresis and pull down Low-side gate drive return Low-side driver output High voltage floating supply return High-side driver output High-side gate drive floating supply 2EDL (SO8) Figure 3 COMPA RATOR SO8, 2EDL05x06yF: 500 mA, Figure 2 Pin no. 1 GND / PGND LEVELSHIFTER Functional options depending on type: Interlock, Deadtime, Filter times, Propagation delay VDD Table 1 VB BIAS NETWORK - VB HIN GND Boostrap diode 2EDL (0.5A, SO14) 1 VDD VB 8 1 nc nc 14 2 HIN HO 7 2 VDD nc 13 3 LIN VS 6 3 HIN VB 12 4 GND LO 5 4 LIN HO 11 5 GND VS 10 6 LO nc 9 7 nc nc 8 2EDL05 family lead assignments (top view) 2EDL05 family Datasheet www.infineon.com/gdHalfBridge 3 of 21 Version 2.9 2019-01-24 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode 3 Functional description 3.1 Low Side and High Side Control Pins (LIN, HIN) 3.1.1 Input voltage range All input pins have the capability to process input voltages up to the supply voltage of the IC. The inputs are therefore internally clamped to VDD and GND by diodes. An internal pull-down resistor is high ohmic, so that it can keep the IC in a safe state in case of PCB crack. 3.1.2 Switching levels The Schmitt trigger input threshold is such to guarantee LSTTL and CMOS compatibility down to 3.3 V controller outputs. The input Schmitt trigger and noise filter provide beneficial noise rejection to short input pulses according to Figure 4 and Figure 5. Please note, that the switching levels of the input structures remain constant even though they can accept amplitudes up to the IC supply level. ILIN IHIN HINx LINx 2EDL-family Vcc V ; V IH IL INPUT NOISE FILTER VZ=5.25 V Figure 4 3.1.3 Input pin structure Input filter time a) Figure 5 tFILIN b) tFILIN LIN HIN LIN LO HO LO low high Input filter timing diagram Short pulses are suppressed by means of an input filter. All IC, which have undervoltage lockout (UVLO) thresholds for MOSFET, have an input filter time of tFILIN = 75 ns typ. and 150 ns max. All IC having UVLO thresholds for IGBT have filter times of tFILIN = 150 ns min and 200 ns typ. 3.2 VDD and GND VDD is the low side supply and it provides power to both the input logic and the low side output power stage. The input logic is referenced to GND ground as well as the under-voltage detection circuit. Output power stage is also referenced to GND ground. The undervoltage lockout circuit enables the device to operate at power on when a typical supply voltage higher than VDDUV+ is present. Please see section 3.5 “Undervoltage lockout” for further information. 2EDL05 family Datasheet www.infineon.com/gdHalfBridge 4 of 21 Version 2.9 2019-01-24 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode A filter time of typ. 1.8µs 1 helps to suppress noise from the UVLO circuit, so that negative going voltage spikes at the supply pins will avoid parasitic UVLO events. 3.3 VB and VS (High Side Supplies) VB to VS is the high side supply voltage. The high side circuit can float with respect to GND following the external high side power device emitter/source voltage. Due to the low power consumption, the floating driver stage can be supplied by bootstrap topology connected to VDD. A filter time of typ. 1.8µs1 helps to suppress noise from the UVLO circuit, so that negative going voltage spikes at the supply pins will avoid parasitic UVLO events. The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than VDDUV+ is present. Please see section 3.5 “Undervoltage lockout” for further information. Details on bootstrap supply section and transient immunity can be found in application note EiceDRIVER™ 2EDL family: Technical description. 3.4 LO and HO (Low and High Side Outputs) Low side and high side power outputs are specifically designed for pulse operation such as gate drive for IGBT and MOSFET devices. Low side output is state triggered by the respective input, while high side output is edge triggered by the respective input. In particular, after an undervoltage condition of the VBS supply, a new turn-on signal (edge) is necessary to activate the high side output. In contrast, the low side outputs switch to the state of their respective inputs after an undervoltage condition of the VDD supply. The output current specification IO+ and IO- is defined in a way, which considers the power transistors miller voltage.This helps to design the gate drive better in terms of the application needs. Nevertheless, the devices are also characterised for the value of the pulse short circuit value IOpk+ and IOpk–. 3.5 Undervoltage lockout (UVLO) Two different UVLO options are required for IGBT and MOSFET. The types 2EDL05I06Px and 2EDL05I06BF are designed to drive IGBT. There are higher levels of undervoltage lockout for the low side UVLO than for the high side. This supports an improved start up of the IC, when bootstrapping is used. The thresholds for the low side are typically VDDUV+ = 12.5 V (positive going) and VDDUV– = 11.6 V (negative going). The thresholds for the high side are typically VBSUV+ = 11.6 V (positive going) and VBSUV– = 10.7 V (negative going). The types 2EDL05N06Px are designed to drive power MOSFET. A similar distinction for the high side and low side UVLO threshold as for IGBT is not realised here. The IC shuts down all the gate drivers power outputs, when the supply voltage is below typ. VDDUV- = 8.3 V (min. / max. = 7.5 V / 9 V). The turn-on threshold is typ. VDDUV+ = 9.1 V (min. / max. = 8.3 V / 9.9 V) 3.6 Bootstrap diode An ultra fast bootstrap diode is monolithically integrated for establishing the high side supply. The differential resistor of the diode helps to avoid extremely high inrush currents when charging the bootstrap capacitor initially. Not subject of production test, verified by characterisation 2EDL05 family Datasheet www.infineon.com/gdHalfBridge 1 5 of 21 Version 2.9 2019-01-24 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode 3.7 Deadtime and interlock function The IC provides a hardware fixed deadtime. The deadtime is different for the two MOSFET types (2EDL05N06Px) and for the two IGBT types (2EDL05I06Px). The deadtimes are particularly typ. 380 ns for IGBT and typ. 75 ns for MOSFET. An additional interlock function prevents the two outputs from being activated simultaneously. The part 2EDL05I06BF does not have the deadtime feature and also not the interlock function. Here, the two outpus can be activated simultaneously. 3.8 Tolerant to negative transient voltage on VS pin (-VS) A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage as the power switches transition on and off quickly while carrying a large current. A typical three phase inverter circuit is shown in Figure 6; here we define the power switches and diodes of the inverter. If the high-side switch (e.g., the IGBT Q1 in Figures 7 and 8) switches off, while the U phase current is flowing to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC bus voltage to the negative DC bus voltage. DC+ BUS D1 Q1 Input Voltage VS1 Q2 D3 Q3 VS2 U D2 Q4 D5 Q5 VS3 V D4 Q6 W To Load D6 DC- BUS Figure 6 Three phase inverter DC+ BUS DC+ BUS Q1 ON Q1 OFF D1 IU VS1 Q2 OFF VS1 D2 Q2 OFF DC- BUS Figure 7 IU D2 DC- BUS Q1 conducting Figure 8 D2 conducting Also when the V phase current flows from the inductive load back to the inverter (see Figures 9 and 10), and Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2, swings from the positive DC bus voltage to the negative DC bus voltage. 2EDL05 family Datasheet www.infineon.com/gdHalfBridge 6 of 21 Version 2.9 2019-01-24 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode DC+ BUS DC+ BUS Q3 OFF D3 IV VS2 Q4 OFF Q3 OFF VS2 D4 IV Q4 ON DC- BUS Figure 9 D3 DC- BUS D3 conducting Figure 10 Q4 conducting However, in a real inverter circuit the VS voltage swing does not stop at the level of the negative DC bus but instead swings below the level of the negative DC bus. This undershoot voltage is called “negative transient voltage”. The circuit shown in Figure 11 depicts one leg of the three phase inverter; Figures 12 and 13 show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS pin). DC+ BUS DC+ BUS + LC1 D1 Q1 VLC1 - Q1 ON LC2 D2 Q2 VS1 IU VLE1 - VS1 Figure 11 Parasitic Elements - IU VLC2 + D2 Q2 OFF - Q2 OFF VD2 + - LE2 DC- BUS D1 Q1 OFF + LE1 VS1 DC+ BUS VLE2 + DC- BUS DC- BUS Figure 12 VS positive Figure 13 VS negative In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in normal operation. Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications. An indication of the 2EDL05 family’s robustness can be seen in Figure 14, where the 2EDL05 Safe Operating Area is shown at VBS=15 V based on repetitive negative VS spikes. A negative transient voltage falling in the grey area 2EDL05 family Datasheet www.infineon.com/gdHalfBridge 7 of 21 Version 2.9 2019-01-24 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC do not appear if negative VS transients fall inside the SOA. Figure 14 Negative transient voltage SOA on VS pin for 2EDL05 family @ VBS=15 V Even though the 2EDL05 family has been shown to be able to handle these large negative transient voltage conditions, it is highly recommended that the circuit designer always limit the negative transient voltage on VS pin as much as possible by careful PCB layout and component use. 2EDL05 family Datasheet www.infineon.com/gdHalfBridge 8 of 21 Version 2.9 2019-01-24 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode 4 Electrical parameters 4.1 Absolute maximum ratings All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta=25°C). Table 2 Absolute maximum ratings Parameter High side offset voltage Symbol VS 1 High side offset voltage (tp 7.0 V. All input pins (HIN, LIN) are internally clamped (see abs. maximum ratings). 3 The input pulse may not be transmitted properly in case of input pulse width at LIN and HIN below 0.8µs (IGBT types) or 0.3 µs (MOSFET) respectively. 2EDL05 family Datasheet 10 of 21 Version 2.9 www.infineon.com/gdHalfBridge 2019-01-24 1 2 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode 4.4 Static logic function table VDD VBS LO HO tFILIN tIN > tFILIN HO/LO HO/LO Figure 15 Timing of short pulse suppression LIN1,2,3 1.65V 1.65V HIN1,2,3 12V HO1,2,3 3V DT DT 12 V LO1,2,3 3V Figure 16 Timing of of internal deadtime LIN HIN 1.65V 1.65V PWIN ton tr 80% HO LO 20% Figure 17 toff tf 80% PWOUT 20% Input to output propagation delay times and switching times definition 2EDL05 family Datasheet www.infineon.com/gdHalfBridge 14 of 21 Version 2.9 2019-01-24 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode Figure 18 Operating areas (IGBT UVLO levels) Figure 19 Operating areas (MOSFET UVLO levels) HIN/LIN PWIN PM = PWIN - PWOUT PWOUT HO/LO HIN/LIN PWIN PM = PWIN - PWOUT HO/LO Figure 20 MTon MToff PWOUT Output pulse width timing and matching delay timing diagram for positive logic 2EDL05 family Datasheet www.infineon.com/gdHalfBridge 15 of 21 Version 2.9 2019-01-24 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode HIN DT LIN DT HO LO Figure 21 Deadtime and interlock 2EDL05 family Datasheet www.infineon.com/gdHalfBridge 16 of 21 Version 2.9 2019-01-24 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode 6 Package information Max. reflow solder temperature: Max. wave solder temperature: 265°C acc. JEDEC 245°C acc. JEDEC Figure 22 Package outline PG-DSO-8 Figure 23 PCB reference layout left: Reference layout right: detail of footprint The thermal coefficient is used to calculate the junction temperature, when the IC surface temperature is measured. The junction temperature is 𝑇𝑇j = Ψth(j-top) ∙ 𝑃𝑃𝑑𝑑 + 𝑇𝑇top Table 7 Data of reference layout Dimensions Material Metal (Copper) 76.2 × 114.3 × 1.5 mm³ FR4 (λtherm = 0.3 W/mK) 70µm (λtherm = 388 W/mK) 2EDL05 family Datasheet www.infineon.com/gdHalfBridge 17 of 21 Version 2.9 2019-01-24 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode Max. reflow solder temperature: Max. wave solder temperature: 265°C acc. JEDEC 245°C acc. JEDEC Figure 24 Package outline PG-DSO-14 Figure 25 PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint The thermal coefficient is used to calculate the junction temperature, when the IC surface temperature is measured. The junction temperature is 𝑇𝑇j = Ψth(j-top) ∙ 𝑃𝑃𝑑𝑑 + 𝑇𝑇top Table 8 Data of reference layout Dimensions Material Metal (Copper) 76.2 × 114.3 × 1.5 mm³ FR4 (λtherm = 0.3 W/mK) 70µm (λtherm = 388 W/mK) 2EDL05 family Datasheet www.infineon.com/gdHalfBridge 18 of 21 Version 2.9 2019-01-24 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode 7 Table 9 Qualification information 1 Qualification information Qualification level Moisture sensitivity level Charged device model ESD Human body model IC latch-up test RoHS compliant 8 Industrial 2 Note: This family of ICs has passed JEDEC’s Industrial qualification. Consumer qualification level is granted by extension of the higher Industrial level. MSL3 3, 260°C DSO-8/-14 (per IPC/JEDEC J-STD-020) Class C3 (> 1.0 kV) (per JESD22-C101) Class 2 (per JEDEC standard JESD22-A114) Class II Level A (per JESD85) Yes Related products Table 10 Product Description Gate Driver ICs 6EDL04I06 / 6EDL04N06 2EDL23I06 / 2EDL23N06 Power Switches IKD04N60R / RF IKD06N65ET6 IPD65R950CFD IPN50R950CE 600 V, 3 phase level shift thin-film SOI gate driver with integrated high speed, low RDS(ON) bootstrap diodes with over-current protection (OCP), 240/420 mA source/sink current drive, Fault reporting, and Enable for MOSFET or IGBT switches. 600 V, Half-bridge thin-film SOI level shift gate driver with integrated high speed, low RDSON bootstrap diode, with over-current protection (OCP), 2.3/2.8 A source/sink current driver, and one pin Enable/Fault function for MOSFET or IGBT switches. 600 V TRENCHSTOP™ IGBT with integrated diode in PG-TO252-3 package 650 V TRENCHSTOP™ IGBT with integrated diode in DPAK 650 V CoolMOS CFD2 with integrated fast body diode in DPAK 500 V CoolMOS CE Superjunction MOSFET in PG-SOT223 package iMOTION™ Controllers IRMCK099 iMOTION™ Motor control IC for variable speed drives utilizing sensor-less Field Oriented Control (FOC) for Permanent Magnet Synchronous Motors (PMSM). IMC101T High performance Motor Control IC for variable speed drives based on field oriented control (FOC) of permanent magnet synchronous motors (PMSM). Qualification standards can be found at Infineon’s web site www.infineon.com Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales representative for further information. 3 Higher MSL ratings may be available for the specific package types listed here. Please contact your Infineon sales representative for further information. 2EDL05 family Datasheet 19 of 21 Version 2.9 www.infineon.com/gdHalfBridge 2019-01-24 1 2 2EDL05 family 600 V Half Bridge Gate Driver with Integrated Bootstrap Diode Revision history Document version Date of release Description of changes 0.85 2013‐04‐16 Change term VCC in VDD 2.6 2016-06-01 Update maximum Ta from 95oC to 105oC in Table 3 2.7 2016‐08‐18 Updated disclaimer, trademarks. Upated parameter VHO 2.8 2018‐11‐19 Updated ESD HBM information 2.9 2019-01-24 Updated Chapter 3.8 Tolerant to negative transient voltage on VS pin 2EDL05 family Datasheet www.infineon.com/gdHalfBridge 20 of 21 Version 2.9 2019-01-24 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2019-01-24 Published by Infineon Technologies AG 81726 Munich, Germany © 2019 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? Email: erratum@infineon.com Document reference IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology delivery terms and conditions and prices please contact your nearest Infineon Technologies office (www.infineon.com). Please note that this product is not qualified according to the AEC Q100 or AEC Q101 documents of the Automotive Electronics Council. WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.