2EDL23 family
2EDL23x06PJ family
600 V Half Bridge Gate Driver with OCP and Integrated Bootstrap Diode
Features
Infineon thin-film-SOI-technology
Fully operational to +600 V
Integrated Ultra-fast, low RDS(ON) Bootstrap Diode
Floating channel designed for bootstrap operation
Output source/sink current capability +1.8 A/-2.5 A
Tolerant to negative transient voltage up to -100 V
(Pulse width is up 300 ns) given by SOI-technology
Interlock, Enable, Fault, and over current protection
10 ns typ., 60 ns max. propagation delay matching
dV/dt immune ±50 V
Undervoltage lockout for both channels
3.3 V, 5 V and 15 V input logic compatible
RoHS compliant
Product summary
VOFFSET
IO+/- (typ.)
VOUT
Delay Matching
tf/tr (typ. CL=4.9 nF)
= 620 V max.
= 1.8 A/2.5 A
= 10 V - 17.5 V
= 60 ns max.
= 37 ns/48 ns
Package
DSO-14
Potential applications
Motor drives, general purpose inverters
Refrigeration compressors, home appliance
Half-bridge and full-bridge converters in offline AC-DC power supplies for telecom and lighting
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22.
Description
The 2EDL family contains devices, which control power devices like MOS-transistors or IGBTs with a maximum blocking
voltage of +600 V in half bridge configurations. Based on the used SOI-technology there is an excellent ruggedness on
transient voltages. No parasitic thyristor structures are present in the device. Hence, no parasitic latch up may occur at all
temperature and voltage conditions.
The two independent driver outputs are controlled at the low-side using two different CMOS resp. LSTTL compatible
signals, down up to 3.3 V logic. The device includes an under-voltage detection unit with hysteresis characteristic which
are optimised either for IGBT or MOSFET.
Those parts, which are designed for IGBT have asymmetric undervoltage lockout levels, which support strongly the
integrated ultra-fast bootstrap diode. Additionally, the offline gate clamping function provides an inherent protection of
the transistors for parasitic turn-on by floating gate conditions, when the IC is not supplied via VDD.
+ DC-Bus
+5 V
VDD
PWM_H
HIN
PWM_L
LIN
VS
To
Load
EN/FLT
EN
/CTRAP
2EDL23x06PJ
LO
GND
GND
Figure 1
VB
HO
GND
To Opamp /
Comparator
PGND
Refer to lead assignments for
correct pin configuration. This
diagram show electrical
connections only. Please refer to
our application notes and design
tips for proper circuit board
layout.
- DC-Bus
Typical application diagram
2EDL23 family Datasheet
Please read the Important Notice and Warnings at the end of this document
www.infineon.com/gdHalfBridge
1 of 21
Version 2.9
2019-01-252
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
Ordering information
Ordering information
Sales Name
2EDL23I06PJ
2EDL23N06PJ
Special function
output Target
typ. Level Shift Bootstrap Package Evaluation board
current transistor UVLO thresholds diode
Deadtime, Interlock, 2.3 A
Enable, Fault, Over
Current Protection
2.3 A
IGBT
12.5 V / 11.6 V
Yes
DSO-14
EVAL-2EDL23I06PJ
MOSFET
9.1 V / 8.3 V
Yes
DSO-14
EVAL-2EDL23N06PJ
Table of contents
Features ........................................................................................................................................ 1
Product summary ........................................................................................................................... 1
Package ......................................................................................................................................... 1
Potential applications ..................................................................................................................... 1
Product validation .......................................................................................................................... 1
Description .................................................................................................................................... 1
Ordering information ...................................................................................................................... 2
Table of contents ............................................................................................................................ 2
1
Block diagram........................................................................................................................ 3
2
Lead definitions ..................................................................................................................... 3
3
Functional description ............................................................................................................ 4
3.1
Low Side and High Side Control Pins (LIN, HIN) ..................................................................................... 4
3.1.1
Input voltage range ............................................................................................................................ 4
3.1.2
Switching levels.................................................................................................................................. 4
3.1.3
Input filter time .................................................................................................................................. 4
3.2
VDD, GND and PGND (Low Side Supply) ................................................................................................. 4
3.3
VB and VS (High Side Supplies) ............................................................................................................... 5
3.4
LO and HO (Low and High Side Outputs) ............................................................................................... 5
3.5
Undervoltage lockout (UVLO) ................................................................................................................. 5
3.6
Bootstrap diode (BSD) ............................................................................................................................ 5
3.7
Deadtime and interlock function ............................................................................................................ 6
3.8
EN-/FLT (fault indication and enable function) ..................................................................................... 6
3.9
Power ground / over current protection ................................................................................................ 6
3.10
Tolerant to negative transient voltage on VS pin (-VS) .......................................................................... 7
4
4.1
4.2
4.3
4.4
4.5
4.6
Electrical parameters ............................................................................................................ 10
Absolute maximum ratings ................................................................................................................... 10
Required operation conditions ............................................................................................................. 11
Operating Range.................................................................................................................................... 11
Static logic function table ..................................................................................................................... 12
Static parameters .................................................................................................................................. 12
Dynamic parameters ............................................................................................................................. 14
5
Timing diagrams ................................................................................................................... 15
6
Package information ............................................................................................................. 18
7
Qualification information....................................................................................................... 19
8
Related products................................................................................................................... 19
Revision history............................................................................................................................. 20
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
2 of 21
Version 2.9
2019-01-2512
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
1
Block diagram
VDD
VDD
Boostrap diode
VB
BIAS NETWORK - VB
Functional options depending on type:
Interlock, Deadtime, Filter times, Shut
down, UVLO, Propagation delay
LATCH
HIN
VDD
LIN
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPA
RATOR
GateDrive
UVDETECT
HO
VS
VDD
UVDETECT
DELAY
GND / PGND
LEVELSHIFTER
GateDrive
LO
PGND
GND
VDD
OR
VITRIP,TH+
VITRIP,TH,hys
EN/FLT
OR
Latch
230µs
-
SO14, 2EDL23x06PJ: 2.3 A
Figure 2
2
+
Filter (1.8µs)
0.46
V
Functional block diagram
Lead definitions
Table 1
2EDL23 family lead definitions
Pin no.
1
Name
VDD
2
HIN
3
LIN
4
5
6
7
8,9,13,14
10
11
12
EN-/FLT
GND
PGND
LO
nc
VS
HO
VB
2EDL (SO8)
Function
Low-side and logic supply voltage
Logic input for high-side gate driver output (HO), in phase. Schmitt trigger inputs
with hysteresis and pull down
Logic input for low-side gate driver output (LO), in phase. Schmitt trigger inputs
with hysteresis and pull down
Enable input and Fault indication output
Logic ground
Low-side gate drive return
Low-side driver output
Not connected
High voltage floating supply return
High-side driver output
High-side gate drive floating supply
2EDL (0.5A, SO14)
2EDL (2.3A, SO14)
VDD
VB
8
1
nc
nc 14
1
VDD
nc
14
HIN
HO
7
2
VDD
nc 13
2
HIN
nc
13
LIN
VS
6
3
HIN
VB 12
3
LIN
VB
12
GND
LO
5
4
LIN
HO 11
4
EN-/FLT
HO
11
5
GND
VS 10
5
GND
VS
10
6
LO
nc
9
6
PGND
nc
9
7
nc
nc
8
7
nc
8
Figure 3
LO
2EDL23 family lead assignments (top view)
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
3 of 21
Version 2.9
2019-01-2512
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
3
Functional description
3.1
Low Side and High Side Control Pins (LIN, HIN)
3.1.1
Input voltage range
All input pins have the capability to process input voltages up to the supply voltage of the IC. The inputs are
therefore internally clamped to VDD and GND by diodes. An internal pull-down resistor is high ohmic, so that it
can keep the IC in a safe state in case of PCB crack.
3.1.2
Switching levels
The Schmitt trigger input threshold is such to guarantee LSTTL and CMOS compatibility down to 3.3 V
controller outputs. The input Schmitt trigger and noise filter provide beneficial noise rejection to short input
pulses according to Figure 4 and Figure 5. Please note, that the switching levels of the input structures remain
constant even though they can accept amplitudes up to the IC supply level.
2EDL-family
ILIN
IHIN
HINx
LINx
Vcc V ; V
IH
IL
INPUT
NOISE
FILTER
VZ=5.25 V
Figure 4
3.1.3
Input pin structure
Input filter time
a)
tFILIN
b)
tFILIN
LIN
HIN
LIN
LO
HO
LO
high
Figure 5
low
Input filter timing diagram
Short pulses are suppressed by means of an input filter. The MOSFET version (2EDL23N06PJ) has an input filter
time of tFILIN = 100 ns typ. for high side and 150 ns typ. for low side. The IGBT version (2EDL23I06PJ) has filter
times of 190 ns typ.
3.2
VDD, GND and PGND (Low Side Supply)
VDD is the low side supply and it provides power to both the input logic and the low side output power stage.
The input logic is referenced to GND ground as well as the under-voltage detection circuit. Output power stage
is referenced to PGND ground. PGND ground is floating respect to GND ground with an absolute maximum
range of operation of +/-5.7 V. A back-to-back zener structure protects grounds from noise spikes.
The undervoltage lockout circuit enables the device to operate at power on when a typical supply voltage
higher than VDDUV+ is present. Please see section 3.5 “Undervoltage lockout”” for further information.
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
4 of 21
Version 2.9
2019-01-2512
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
A filter time of typ. 1.5 µs1 helps to suppress noise from the UVLO circuit, so that negative going voltage spikes
at the supply pins will avoid parasitic UVLO events.
3.3
VB and VS (High Side Supplies)
VB to VS is the high side supply voltage. The high side circuit can float with respect to GND following the
external high side power device emitter/source voltage. Due to the low power consumption, the floating driver
stage can be supplied by bootstrap topology connected to VDD. A filter time of typ. 1.3 µs helps to suppress
noise from the UVLO circuit, so that negative going voltage spikes at the supply pins will avoid parasitic UVLO
events.
The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than
VDDUV+ is present. Please see section 3.5 “Undervoltage lockout” for further information. Details on bootstrap
supply section and transient immunity can be found in application note EiceDRIVER™ 2EDL family: Technical
description.
3.4
LO and HO (Low and High Side Outputs)
Low side and high side power outputs are specifically designed for pulse operation such as gate drive for IGBT
and MOSFET devices. Low side output is state triggered by the respective inputs, while high side output is edge
triggered by the respective inputs. In particular, after an undervoltage condition of the VBS supply, a new turnon signal (edge) is necessary to activate the high side output. In contrast, the low side outputs switch to the
state of their respective inputs after an undervoltage condition of the VDD supply.
The output current specification IO+ and IO- is defined in a way, which considers the power transistors miller
voltage.This helps to design the gate drive better in terms of the application needs. Nevertheless, the devices
are also characterised for the value of the pulse short circuit value IOpk+ and IOpk–.
3.5
Undervoltage lockout (UVLO)
Two different UVLO options are required for IGBT and MOSFET. The types 2EDL23I06PJ are designed to drive
IGBT. There are higher levels of undervoltage lockout for the low side UVLO than for the high side. This supports
an improved start up of the IC, when bootstrapping is used. The thresholds for the low side are typically VDDUV+ =
12.5 V (positive going) and VDDUV– = 11.6 V (negative going). The thresholds for the high side are typically VBSUV+ =
11.6 V (positive going) and VBSUV– = 10.7 V (negative going).
The types 2EDL23N06PJ are designed to drive power MOSFET. A similar distinction for the high side and low
side UVLO threshold as for IGBT is not realised here. The IC shuts down all the gate drivers power outputs, when
the supply voltage is below typ. VDDUV- = 8.3 V (min. / max. = 7.5 V / 9 V). The turn-on threshold is typ. VDDUV+ = 9.1 V
(min. / max. = 8.3 V / 9.9 V)
3.6
Bootstrap diode (BSD)
An ultra fast bootstrap diode is monolithically integrated for establishing the high side supply. The differential
resistor of the diode helps to avoid extremely high inrush currents when charging the bootstrap capacitor
initially.
Not subject of production test, verified by characterisation
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
1
5 of 21
Version 2.9
2019-01-2512
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
3.7
Deadtime and interlock function
The IC provides a hardware fixed deadtime. The deadtime is different for the MOSFET type (2EDL23N06PJ) and
for the IGBT type (2EDL23I06PJ). The deadtimes are particularly typ. 380 ns for IGBT and typ. 75 ns for MOSFET.
An additional interlock function prevents the two outputs from being activated simultaneously.
3.8
EN-/FLT (fault indication and enable function)
The types 2EDL23x06PJ provide a pin, which can either be used to shut down the IC or to read out a failure
status of the IC. The signal applied to pin EN controls directly the output stages. All outputs are set to LOW, if EN
is at LOW logic level. An integrated pull down resistor shuts down the IC in case of a floating input. The internal
structure of the pin is given in Figure 6. The switching levels of the Schmitt-Trigger are here VEN,TH+ = 2.1 V and
VEN,TH- = 0.9 V. The typical propagation delay time is tEN = 550 ns. The input is clamped by diodes to VDD and GND.
The input voltage range is the same as the input control pins with a max. of 20 V.
The /FAULT function is an active low open-drain output indicating the status of the gate driver (see Figure 6).
The pin is active (i.e. forces LOW voltage level) when one of the following conditions occur:
Under-voltage condition of VDD supply: In this case the fault condition is released as soon as the supply
voltage condition returns in the normal operation range (please refer to VDD pin description for more
details). The fault signal is activate as long as UVLO is given during power up.
Overcurrent detection (ITRIP): The fault condition is latched until the overcurrent trigger condition is
finished and additional typ. 230 µs are elapsed.
The interface to the microcontroller can be realised by using an open collector / drain configured output pin for
enabling the driver IC and a GPIO pin for monitoring the /FAULT. The external pull-up resistor will pull-up the
voltage to +5V, when the IC is set for operation.
2EDL23x
+5V
To logic
µC
Rpu
EN
GPIO
Figure 6
3.9
EN/FLT
CFLT
Ron,FLT≈
35W
From
UVLO
OR
73kW
Latch
230µs
GND
From
ITRIPfilter
EN-/FLT pin structures and interface to microcontroller (µC)
Power ground / over current protection
A power ground (PGND) connects directly the emitter or source of the low side transistor with the gate drive IC.
No other components, such as shunts, etc., are between this connection and the emitter or source. This
enables the routing of smallest gate circuit loops and therefore smallest gate inductances.
A potential shunt resistor is between the power ground (PGND) connection and the gound connection (GND),
which leads to a voltage drop between these two pins.
The voltage drop between PGND and GND can be seen sensed by means of a comparator with a threshold of
Vth,ITRIP = 0.46 V. If the voltage drop is larger than Vth,ITRIP , then the output of the comparator is triggered and the
/FLT output is activated. Simultaneously, the IC shuts down both gate outputs for the period of the fault
indication, which is 230 µs.
Several influences, such as reverse recovery currents, parasitic inductances and other noise sources, make the
need of a signal filter necessary. The filter has a time constant of typically 1.8 µs to ensure good noise quality.
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
6 of 21
Version 2.9
2019-01-2512
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
3.10
Tolerant to negative transient voltage on VS pin (-VS)
A common problem in today’s high-power switching converters is the transient response of the switch node’s
voltage as the power switches transition on and off quickly while carrying a large current. A typical three phase
inverter circuit is shown in Figure 7; here we define the power switches and diodes of the inverter.
If the high-side switch (e.g., the IGBT Q1 in Figures 8 and 9) switches off, while the U phase current is flowing to
an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the
low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC
bus voltage to the negative DC bus voltage.
DC+ BUS
D1
Q1
Input
Voltage
VS1
Q2
D3
Q3
VS2
U
D2
Q4
D5
Q5
VS3
V
D4
Q6
W
To
Load
D6
DC- BUS
Figure 7
Three phase inverter
DC+ BUS
DC+ BUS
Q1
ON
Q1
OFF
D1
IU
VS1
VS1
IU
Q2
OFF
D2
Q2
OFF
DC- BUS
Figure 8
D2
DC- BUS
Q1 conducting
Figure 9
D2 conducting
Also when the V phase current flows from the inductive load back to the inverter (see Figures 10 and 11), and Q4
IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, V S2,
swings from the positive DC bus voltage to the negative DC bus voltage.
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
7 of 21
Version 2.9
2019-01-2512
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
DC+ BUS
DC+ BUS
Q3
OFF
D3
Q3
OFF
D3
IV
VS2
VS2
IV
Q4
OFF
D4
Q4
ON
DC- BUS
DC- BUS
Figure 10
D3 conducting
Figure 11
Q4 conducting
However, in a real inverter circuit the VS voltage swing does not stop at the level of the negative DC bus but instead
swings below the level of the negative DC bus. This undershoot voltage is called “negative transient voltage”.
The circuit shown in Figure 12 depicts one leg of the three phase inverter; Figures 13 and 14 show a simplified
illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit
from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch
is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic
elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in the
low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these figures).
This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative
voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS
pin).
DC+ BUS
DC+ BUS
LC1
D1
Q1
VLC1
-
Q1
ON
IU
VLE1
VS1
-
VS1
LC2
D2
Q2
Figure 12
Parasitic Elements
-
IU
VLC2
+
D2
Q2
OFF
-
Q2
OFF
VD2
+
-
LE2
DC- BUS
D1
Q1
OFF
+
LE1
VS1
DC+ BUS
+
VLE2
+
DC- BUS
DC- BUS
Figure 13
VS positive
Figure 14
VS negative
In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient
voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt
is greater than in normal operation.
Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications. An
indication of the 2EDL23 family’s robustness can be seen in Figure 15, where the 2EDL23 Safe Operating Area is
shown at VBS=15 V based on repetitive negative voltage spikes. A negative transient voltage falling in the grey area
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
8 of 21
Version 2.9
2019-01-2512
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
(outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent
damage to the IC do not appear if negative VS transients fall inside the SOA.
Figure 15
Negative transient voltage SOA on VS pin for 2EDL23 family @ VBS=15 V
Even though the 2EDL23 family has been shown to be able to handle these large negative transient voltage
conditions, it is highly recommended that the circuit designer always limit the negative transient voltage on VS
pin as much as possible by careful PCB layout and component use.
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
9 of 21
Version 2.9
2019-01-2512
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
4
Electrical parameters
4.1
Absolute maximum ratings
All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta=25°C).
Table 2
Absolute maximum ratings
Parameter
High side offset voltage
1
Symbol
VS
High side offset voltage (tp 7.0 V.
All input pins (HIN, LIN, EN) are internally clamped (see abs. maximum ratings).
3
The input pulse may not be transmitted properly in case of input pulse width at LIN and HIN below 0.8µs (IGBT types) or 0.3 µs
(MOSFET) respectively.
2EDL23 family Datasheet
11 of 21
Version 2.9
www.infineon.com/gdHalfBridge
2019-01-2512
1
2
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
4.4
Static logic function table
VDD
VBS
ENABLE
FAULT
PGND
LO
HO
1 µs
–
20
70
IGBT types
MOSFET types
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
14 of 21
Version 2.9
2019-01-2512
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
5
Timing diagrams
tFILIN
HIN/LIN
tFILIN
tIN
tIN
HIN/LIN
tIN < tFILIN
tIN < tFILIN
high
HO/LO
HO/LO
low
HIN/LIN
tIN
HIN/LIN
tIN
tIN > tFILIN
tIN > tFILIN
HO/LO
HO/LO
Figure 16
Timing of short pulse suppression
LIN1,2,3
1.65V
1.65V
HIN1,2,3
12V
HO1,2,3
3V
DT
DT
12 V
LO1,2,3
3V
Figure 17
Timing of of internal deadtime
EN
HO1,2,3
LO1,2,3
Figure 18
tEN
3V
Timing of of internal deadtime
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
15 of 21
Version 2.9
2019-01-2512
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
LIN
1.65V
1.65V
HIN
PWIN
ton
tr
toff
80%
tf
80%
HO
LO
20%
PWOUT
20%
Figure 19
Input to output propagation delay times and switching times definition
Figure 20
Operating areas (IGBT UVLO levels)
Figure 21
Operating areas (MOSFET UVLO levels)
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
16 of 21
Version 2.9
2019-01-2512
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
PGND
1V
0.1V
FAULT
2.1V
0.5V
tFLT
tFLTCLR
Any
output
Figure 22
3V
tITRIP
ITRIP-Timing
HIN/LIN
PWIN
PM = PWIN - PWOUT
PWOUT
HO/LO
HIN/LIN
PWIN
PM = PWIN - PWOUT
HO/LO
Figure 23
MTon
MToff
PWOUT
Output pulse width timing and matching delay timing diagram for positive logic
HIN
DT
LIN
DT
HO
LO
Figure 24
Deadtime and interlock
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
17 of 21
Version 2.9
2019-01-2512
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
6
Package information
Max. reflow solder temperature:
Max. wave solder temperature:
265°C acc. JEDEC
245°C acc. JEDEC
Figure 25
Package outline PG-DSO-14
Figure 26
PCB reference layout (according to JEDEC 1s0P)
left: Reference layout
right: detail of footprint
The thermal coefficient is used to calculate the junction temperature, when the IC surface temperature is
measured. The junction temperature is
𝑇j = Ψth(j-top) ∙ 𝑃𝑑 + 𝑇top
Table 7
Data of reference layout
Dimensions
Material
Metal (Copper)
76.2 114.3 1.5 mm³
FR4 (therm = 0.3 W/mK)
70µm (therm = 388 W/mK)
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
18 of 21
Version 2.9
2019-01-2512
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
7
Table 8
Qualification information1
Qualification information
Qualification level
Moisture sensitivity level
Charged device model
ESD
Human body model
IC latch-up test
RoHS compliant
8
Industrial2
Note: This family of ICs has passed JEDEC’s Industrial
qualification. Consumer qualification level is granted by
extension of the higher Industrial level.
MSL33, 260°C
DSO-8/-14
(per IPC/JEDEC J-STD-020)
Class C3 (> 1.0 kV)
(per JESD22-C101)
Class 2
(per JEDEC standard JESD22-A114)
Class II Level A
(per JESD78)
Yes
Related products
Table 9
Product
Description
Gate Driver ICs
6EDL04I06 /
6EDL04N06
2EDL05I06 /
2EDL05N06
Power Switches
IKD04N60R / RF
IKD06N65ET6
IPD65R950CFD
IPN50R950CE
600 V, 3 phase level shift thin-film SOI gate driver with integrated high speed, low RDS(ON) bootstrap
diodes with over-current protection (OCP), 240/420 mA source/sink current drive, Fault reporting,
and Enable for MOSFET or IGBT switches.
600 V, Half-bridge thin-film SOI level shift gate driver with integrated high speed, low
RDS(ON) bootstrap diode, 0.36/0.7 A source/sink current driver, 8pins/14pins package, for MOSFET or
IGBT switches.
600 V TRENCHSTOP™ IGBT with integrated diode in PG-TO252-3 package
650 V TRENCHSTOP™ IGBT with integrated diode in DPAK
650 V CoolMOS™ CFD2 with integrated fast body diode in DPAK
500 V CoolMOS™ CE Superjunction MOSFET in PG-SOT223 package
iMOTION™ Controllers
IRMCK099
iMOTION™ Motor control IC for variable speed drives utilizing sensor-less Field Oriented Control
(FOC) for Permanent Magnet Synchronous Motors (PMSM).
IMC101T
High performance Motor Control IC for variable speed drives based on field oriented control (FOC)
of permanent magnet synchronous motors (PMSM).
Qualification standards can be found at Infineon’s web site www.infineon.com
Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales
representative for further information.
3
Higher MSL ratings may be available for the specific package types listed here. Please contact your Infineon sales representative for
further information.
2EDL23 family Datasheet
19 of 21
Version 2.9
www.infineon.com/gdHalfBridge
2019-01-2512
1
2
2EDL23 family
600 V Half Bridge Gate Driver with Integrated Bootstrap Diode (BSD)
Revision history
Document version Date of release
Description of changes
0.86
2014-05-15
Change term VCC in VDD
2.2
2016-06-01
Update maximum Ta from 95oC to 105oC in Table 3
2.3
2016-08-18
Updated disclaimer, trademarks. Upated parameter VHO
2.4
2017-11-28
th(j-top) change to junction to top
2.5
2018-11-20
Updated ESD HBM information
2.6
2019-01-25
Updated Charpter 3.10 Tolerant to negative transient voltage on VS pin
2.7
2020-07-07
IC latch-up test per JESD78
2.8
2021-07-19
Modified ambient temperature max. rating in Table 4 on page 11
2.9
2022-05-12
Remove IF,BSD maximum spec
2EDL23 family Datasheet
www.infineon.com/gdHalfBridge
20 of 21
Version 2.9
2019-01-2512
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2019-01-2507
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2022 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
Email: erratum@infineon.com
Document reference
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
Please note that this product is not qualified
according to the AEC Q100 or AEC Q101 documents
of the Automotive Electronics Council.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of the
product or any consequences of the use thereof can
reasonably be expected to result in personal injury.
