2EDN7424F

EiceDRIVER™ 2EDN7424 Fast Dual Channel 4 A Low-Side Gate Driver Fast, precise, strong and compatible • Highly efficient SMPS enabled by 6 ns fast slew rates and 19 ns propagation delay precision for fast MOSFET and GaN switching • 1 ns channel-to-channel propagation delay accuracy enables safe use of two channels in parallel • Two independent 4 A channels enable numerous deployment options • Industry standard packages and pinout enable ease system-design upgrades • Qualified for industrial grade applications according to JEDEC (JESD47, J-STD20 and JESD22) The new Reference in Ruggedness • 4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant MOSFET protection under abnormal conditions • -10 V control and enable input robustness delivers crucial safety margin when driving pulse-transformers or driving MOSFETs in through hole packaging • 5 A reverse current robustness eliminates the need for output protection circuitry. Typical Applications • Server SMPS • TeleCom SMPS • DC-to-DC Converter • Bricks • Power Tools • Industrial SMPS • Motor Control • Solar SMPS Example Topologies • Single and interleaved PFC • LLC, ZVS with pulse transformer • Synchronous Rectification Description The 2EDN7424 is an advanced dual-channel driver. It is suited to drive logic and normal level MOSFETs and supports OptiMOSTM, CoolMOSTM, Standard Level MOSFETs, Superjunction MOSFETs, as well as IGBTs and GaN Power devices. Data Sheet www.infineon.com Please read the Important Notice and Warnings at the end of this document Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Fast Dual Channel 4 A Low-Side Gate Driver The control and enable inputs are LV-TTL compatible (CMOS 3.3 V) with an input voltage range up to +22V. 4.2 V (Under Voltage Lock Out) options ensure instant MOSFET and GaN protection under abnormal conditions. Under such circumstances, this UVLO mechanism provides crucial independence from whether and when other supervisors circuitries detect abnormal conditions. Each of the two outputs is able to sink and source 4 A currents utilizing a true rail-to-rail stage. This ensures very low on resistance of 0.84 Ω up to the positive and 0.66 Ω down to the negative rail respectively. Very tight channel to channel delay matching, typ. 2 ns, permits parallel use of two channels, leading to a source and sink capability of 8 A. Industry leading reverse current robustness eliminates the need for Schottky diodes at the outputs and reduces the bill-of-material. The pinout of the 2EDN family is compatible with the industry standard. Two package variants, DSO 8-pin and TSSOP 8-pin, allow optimization of PCB board space usage and thermal characteristics. Load1 From Controller VDD Load2 2EDN7424 1 ENA ENB 88 2 INA OUTA 77 33 GND VDD 66 4 INB M1 Rg1 Rg2 M2 OUTB 55 CVDD Data Sheet 2 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Table of Contents Table of Contents Fast Dual Channel 4 A Low-Side Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 1.1 1.2 1.3 Product Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Configuration and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 4.1 4.2 4.3 4.4 4.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Driver Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 5.1 5.2 5.3 5.4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 8.1 8.2 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PG-DSO-8-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PG-TSSOP-8-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data Sheet 3 4 4 4 5 11 11 11 12 12 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Product Versions 1 Product Versions The 2EDN7424 are available in 2 package versions. Table 1 Product Versions Package Type. UVLO Control Input Part Number IC Topside Marking Code 4.2V direct 2EDN7424F 2N7424AF EiceDRIV XXHYYWW 4.2V direct 2EDN7424R 2N7424 AR_XXX HYYWW PG-DSO-8-60 PG-TSSOP-8-1 1.1 Undervoltage Lockout The Undervoltage Lockout enables robust start-up and shutdown behavior. Please refer to the functional description section for more details in Chapter 4 (Undervoltage Lockout (UVLO)). 1.2 Logic Version The logic relations between inputs, enable pins and outputs are given in Table 2. The state of the driving output is defined by the state of the respective input, if the enable inputs ENA and ENB are high (or left open). A logic “low” at an enable input or an undervoltage lockout event, due to low voltage at VDD, causes the respective output to be low too, regardless of the input signal. Functional description is shown in Chapter 3 ( Block Diagram) and Chapter 4 (Input Configuration). Data Sheet 4 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Product Versions Table 2 Logic Table Inputs Output 1) ENA ENB INA INB UVLO OUTA OUTB x x x x active L L L L x x inactive L L H L L x inactive L L H L H x inactive H L L H x L inactive L L L H x H inactive L H H H L L inactive L L H H H L inactive H L H H L H inactive L H H H H H inactive H H 1) Inactive means that VDD is above UVLO threshold voltage and release logic to control output stage. Active means that UVLO disable active the output stages. 1.3 Package Versions The logic and UVLO versions are available in2 different packages. • a standard PG-DSO-8-60 (designated by “F”) • a small PG-TSSOP-8-1 (designated by “R”) Drawings can be viewed in Chapter 8 (Outline Dimensions). Data Sheet 5 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Pin Configuration and Description 2 Pin Configuration and Description The pin configuration for 2EDN7424F in the PG-DSO-8-60 package is shown in Figure 1. Drawings can be viewed in Chapter 8 (PG-DSO-8-60). 1 ENA 2 INA 3 GND 4 INB ENB 8 OUTA 7 VDD 6 OUTB 5 Figure 1 Pin Configuration PG-DSO-8-60, Top View Table 3 Pin Configuration 2EDN7424F in the PG-DSO-8-60 Package Pin Symbol Description 1 ENA Enable input channel A Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low 2 INA Input signal channel A Logic input, controlling OUTA 3 GND Ground 4 INB Input signal channel B Logic input, controlling OUTB 5 OUTB Driver output channel B Low-impedance output with source and sink capability 6 VDD Positive supply voltage Operating range 4.5 V to 20 V 7 OUTA Driver output channel A Low-impedance output with source and sink capability 8 ENB Enable input channel B Logic Input; if ENB is high or left open, OUTB is controlled by INB; ENB low causes OUTB low Data Sheet 6 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Pin Configuration and Description The pin configuration for 2EDN7424R in the PG-TSSOP-8-1 package is shown in Figure 2. Drawings can be viewed in Chapter 8 (PG-TSSOP-8-1). 1 ENA 2 INA 3 GND 4 INB Exposed Pad ENB 8 OUTA 7 VDD 6 OUTB 5 Figure 2 Pin Configuration PG-TSSOP-8-1, Top View Table 4 Pin Configuration 2EDN7424R in the PG-TSSOP-8-1 Package Pin Symbol Description 1 ENA Enable input channel A Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low 2 INA Input signal channel A Logic input, controlling OUTA 3 GND Ground1) 4 INB Input signal channel B Logic input, controlling OUTB 5 OUTB Driver output channel B Low-impedance output with source and sink capability 6 VDD Positive supply voltage Operating range 4.5 V to 20 V 7 OUTA Driver output channel A Low-impedance output with source and sink capability 8 ENB Enable input channel B Logic Input; if ENB is high or left open, OUTB is controlled by INB; ENB low causes OUTB low 1) Exposed Pad sink of PG-TSSOP-8-1 packages has to be connected to GND pin. Data Sheet 7 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Block Diagram 3 Block Diagram A simplified functional block diagram is given in Figure 3. Please refer to the functional description section for more details in Chapter 4. VDD VDD 6 UVLO VDD 400k ENA 1 Logic A INA 7 OUTA 5 OUTB 2 100k GND GND VDD VDD 400k ENB 8 Logic B INB 4 100k GND GND 3 GND Figure 3 Data Sheet Block Diagram,pull-up/pull-down resistor configuration 8 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Functional Description 4 Functional Description 4.1 Introduction The 2EDN7424 is a fast dual-channel driver for low-side switches. Two true rail-to-rail output stages with very low output impedance and high current capability are chosen to ensure highest flexibility and cover a high variety of applications. All inputs are compatible with LV-TTL signal levels. The threshold voltages with a typical hysteresis of 1.1 V are kept constant over the supply voltage range. Since the 2EDN7424 aims particularly at fast-switching applications, signal delays and rise/fall times have been minimized. Special effort has been made towards minimizing delay differences between the 2 channels to very low values of typically 2 ns. 4.2 Supply Voltage The maximum supply voltage is 20 V. This high voltage can be valuable in order to exploit the full current capability of 2EDN7424 when driving very large MOSFETs. The minimum operating supply voltage is set by the undervoltage lockout function to a typical default value of 4.2 V. This lockout function protects power MOSFETs from running into linear mode with subsequent high power dissipation. 4.3 Input Configuration As described in Chapter 1, 2EDN7424 is available with respect to the logic configuration of the 4 input pins (input plus enable). The enable inputs are internally pulled up to a logic high voltage, i.e. the driver is enabled with these pins left open. The direct PWM inputs are internally pulled down to a logic low voltage. This prevents a switch-on event during power up and a not driven input condition. Version with inverted PWM input have an internal pull up resistor to prevent unwanted switch-on. All inputs are compatible with LV-TTL levels and provide a hysteresis of 1.1 V typ. This hysteresis is independent of the supply voltage. All input pins have a negative extended voltage range. This prevents cross current over single wires during GND shifts between signal source (controller) and driver input. 4.4 Driver Outputs The two rail-to-rail output stages realized with complementary MOS transistors are able to provide a typical 4 A of sourcing and sinking current. This driver output stage has a shoot through protection and current limiting behavior. After a switching event, current limitation is raised up to achieve the typical current peak for an excellent fast reaction time of the following power MOS transistor. The output impedance is very low with a typical value below 0.84 Ω for the sourcing p-channel MOS and 0.66 Ω for the sinking n-channel MOS transistor. The use of a p-channel sourcing transistor is crucial for achieving true rail-to-rail behaviour and avoiding a source follower’s voltage drop. Gate Drive Outputs held active low in case of floating inputs ENx, INx or during startup or power down once UVLO is not exceeded. Under any situation, startup, UVLO or shutdown, outputs are held under defined conditions. Data Sheet 9 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Functional Description 4.5 Undervoltage Lockout (UVLO) The Undervoltage Lockout function ensures that the output can be switched to its high level only if the supply voltage exceeds the UVLO threshold voltage. Thus it can be guaranteed, that the switch transistor is not switched on if the driving voltage is too low to completely switch it on, thereby avoiding excessive power dissipation. The UVLO level is set to a typical value of 4.2 V (with hysteresis). Data Sheet 10 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Characteristics 5 Characteristics The absolute maximum ratings are listed in Table 5. Stresses beyond these values may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5.1 Absolute Maximum Ratings Table 5 Absolute Maximum Ratings Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Positive supply voltage VVDD -0.3 22 V Voltage at pins INA, INB, ENA, ENB VIN -10 22 V Voltage at pins OUTA, OUTB VOUT -0.3 VVDD+0.3 V Note 1) Reverse current peak at pins OUTA and OUTB ISRCREV 5 Apk < 500ns ISNKREV -5 Apk Junction temperature TJ -40 150 °C Storage temperature TS -55 150 °C ESD capability VESD 1.5 kV Charged Device Mode (CDM) 2) ESD capability VESD 2.5 kV Human Body Model (HBM) 3) 1) Voltage spikes resulting from reverse current peaks are allowed. 2) According to JESD22-C101 3) According to JESD22-A114 5.2 Thermal Characteristics Table 6 Thermal Characteristics for PG-DSO-8-60 (Tamb=25°C) Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Thermal resistance junctionambient 1) RthJA25 125 K/W Thermal resistance junctioncase (top) 2) RthJC25 66 K/W Thermal resistance junctionboard 3) RthJB25 62 K/W Characterization parameter junction-top 4) ΨthJC25 16 K/W Characterization parameter junction-board 5) ΨthJB25 55 K/W 1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDECstandard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Data Sheet 11 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Characteristics 3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 4) The characterization parameter junction-top, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7). 5) The characterization parameter junction-board, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7). Table 7 Thermal Characteristics for PG-TSSOP-8-1 (Tamb=25°C) Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Thermal resistance junctionambient 1) RthJA25 64 K/W Thermal resistance junctioncase (top) 2) RthJP25 56 K/W Thermal resistance junctionboard 3) RthJB25 55 K/W Characterization parameter junction-top 4) ΨthJC25 9 K/W Characterization parameter junction-board 5) ΨthJB25 13 K/W 1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDECstandard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 4) The characterization parameter junction-top, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7). 5) The characterization parameter junction-board, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7). 5.3 Operating Range Table 8 Operating Range Parameter Symbol Values Min. Typ. Unit Note or Test Condition Min. defined by UVLO Max. Supply voltage VVDD 4.5 20 V Logic input voltage VIN -5 20 V Junction temperature TJ -40 150 °C 1) 1) Continuous operation above 125 °C may reduce life time. 5.4 Electrical Characteristics Unless otherwise noted, min./max. values of characteristics are the lower and upper limits respectively. They are valid within the full operating range. The supply voltage is VVDD= 12 V. Typical values are given at TJ=25°C. Data Sheet 12 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Characteristics Table 9 Power Supply Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition VDD quiescent current IVDDQU1 0.5 0.7 1.2 mA OUT = high, VVDD= 12 V VDD quiescent current IVDDQU2 0.3 0.48 0.7 mA OUT = low, VVDD= 12 V Unit Note or Test Condition Table 10 Undervoltage Lockout Parameter Symbol Values Min. Typ. Max. Undervoltage Lockout (UVLO) UVLOON turn on threshold 3.9 4.2 4.5 V Undervoltage Lockout (UVLO) UVLOOFF turn off threshold 3.6 3.9 4.2 V UVLO threshold hysteresis Table 11 0.3 UVLOHYS V Logic Inputs INA, INB, ENA, ENB Parameter Symbol Values Unit Min. Typ. Max. Input voltage threshold for transition LH VINH 1.9 2.1 2.3 V Input voltage threshold for transition HL VINL 0.8 1.0 1.2 V Input pull up resistor1) RINH 400 kΩ Input pull down resistor2) RINL 100 kΩ Note or Test Condition 1) Inputs with initial high logic level 2) Inputs with initial low logic level Table 12 Static Output Caracteristics (see Figure 4) Parameter Symbol High Level (Sourcing) Output Resistance RONSRC High Level (Sourcing) Output Current ISRCPEAK Low Level (Sinking) Output Resistance RONSNK Low Level (Sinking) Output Current ISNKPEAK Values Unit Note or Test Condition ISRC = 50mA Min. Typ. Max. 0.35 0.84 1.2 Ω 4.0 1) A 0.66 1.0 Ω -4.0 2) A 0.28 ISNK = 50mA 1) Active limited by design at approx. 6.5Apk, parameter is not subject to production test - verified by design / characterization, max. power dissipation must be observed 2) Active limited by design at approx. -6.5Apk, parameter is not subject to production test - verified by design / characterization, max. power dissipation must be observed Data Sheet 13 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Characteristics Table 13 Dynamic Characteristics (see Figure 4, Figure 5 and Figure 6) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Input/Enable to output propagation delay TPDlh 15 19 25 ns CLOAD= 1.8 nF, VVDD= 12 V; low to high transition at Input/Enable Input/Enable to output propagation delay TPDhl 15 19 25 ns CLOAD= 1.8 nF, VVDD= 12 V high to low transition at Input/Enable 2 ns Input/Enable to output delta tPD propagation delay mismatch between the two channels on the same IC Rise Time TRISE — 6.4 10 1) ns CLOAD= 1.8 nF, VVDD= 12 V Fall Time TFAll — 5.4 10 1) ns CLOAD= 1.8 nF, VVDD= 12 V 1) ns CLOAD= 1.8 nF, VVDD= 12 V Minimum input pulse width that changes output state TPW — 10 20 1) Parameter verified by design, not 100% tested in production. Data Sheet 14 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Timing Diagrams 6 Timing Diagrams Figure 4 shows the definition of rise, fall and delay times for the inputs of the non-inverting / direct version (with Enable pin high or open). ENx (constant high) V INH VIN L INx 90% OUT 10% TPDON Figure 4 TRISE TPDOFF TFALL Propagation delay, rise and fall time, non-inverted Figure 5 illustrates the undervoltage lockout function. UVLOON UVLOOFF VDD OUT Figure 5 UVLO behaviour, input ENx and INx drives OUTx normally high Figure 6 illustrates the minimum input pulse width that changes output state. ENx (high) VIN H VINL VIN H INx VINL TPW 90% OUTx Figure 6 Data Sheet TPW, minimum input pulse width that changes output state 15 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Typical Characteristics 7 Typical Characteristics UVLO ON/OFF vs TEMPERATURE 4.5 UVLO HYSTERESIS vs TEMPERATURE 0.4 on value off value 0.35 VDD delta [V] VDD [V] 4.3 4.1 3.9 0.3 0.25 Inx, ENx high Indication Outx Inx, ENx high Indication Outx 3.7 0.2 -50 Figure 7 0 50 100 T junction [°C] 150 -50 0 50 100 T junction [°C] 150 Undervoltage lockout (4.2V) INPUT THRESHOLD INx to OUTx vs TEMPERATURE INx HYSTERESIS vs TEMPERATURE 1.2 typ ON threshold typ OFF threshold 1.1 2 VINx delta [V] VINx [V] 2.5 1.5 1 1 VDD=12V VDD=12V 0.9 0.5 -50 Figure 8 Data Sheet 0 50 100 T junction [°C] -50 150 0 50 100 T junction [°C] 150 Input (INx) characteristic 16 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Typical Characteristics INPUT THRESHOLD ENx to OUTx vs TEMPERATURE ENx HYSTERESIS vs TEMPERATURE 1.2 typ ON threshold typ OFF threshold 1.1 2 VENx delta [V] VENx [V] 2.5 1.5 1 1 VDD=12V VDD=12V 0.9 0.5 -50 Figure 9 0 50 100 T junction [°C] -50 150 50 100 T junction [°C] 150 Input (ENx) characteristic VINx to OUTx PROPAGATION DELAY vs TEMPERATURE 25 VINx to OUTx PROPAGATION DELAY vs TEMPERATURE 25 typ input rise-up typ input rise-up typ input fall-down 22.5 typ input fall-down 22.5 TPD [ns] TPD [ns] 0 20 20 17.5 17.5 15 VDD=12V Input 5V VDD=12V Input 3.3V 15 12.5 -50 Figure 10 Data Sheet 0 50 100 T junction [°C] -50 150 0 50 100 T junction [°C] 150 Propagation delay (INx) on different input logic levels (see Figure 4) 17 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Typical Characteristics VENx to OUTx PROPAGATION DELAY vs TEMPERATURE 25 VENx to OUTx PROPAGATION DELAY vs TEMPERATURE 25 typ input rise-up typ input fall-down typ input fall-down 22.5 TPD [ns] 22.5 TPD [ns] typ input rise-up 20 17.5 20 17.5 VDD=12V Enable 5V VDD=12V Enable 3.3V 15 -50 Figure 11 0 50 100 T junction [°C] 15 150 -50 0 50 100 T junction [°C] 150 Propagation delay (ENx) on different input logic levels (see Figure 4) OUTx RISE/FALL TIME 10% - 90% vs TEMPERATURE 8.00 typ turn-on typ turn-off Time [ns] 7.00 6.00 5.00 VDD=12V OUTx with 1.8nF load 4.00 -50 Figure 12 Data Sheet 0 50 100 T junction [°C] 150 Rise / fall times with load on output (see Figure 4) 18 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Typical Characteristics CURRENT CONSUMPTION vs OPERATING SUPPLY VDD CURRENT CONSUMPTION vs TEMPERATURE 0.80 OUTx High 0.70 OUTx Low IDD [mA] IDD [mA] 0.8 0.6 0.60 0.50 0.4 OUTx Low 0.2 VDD=12V ENx NC 0.30 0 10 VDD [V] 20 -50 0 50 100 T junction [°C] 150 CURRENT CONSUMPTION vs FREQUENCY 50 Tamb 25°C Input 50%@3.3V Device self-heating Load 1.8nF serial 40 I DD [mA] OUTx High 0.40 Tj=25°C ENx floating (VDD) VDD 4,5V 30 VDD 12V VDD 20V 20 10 0 0 Figure 13 Data Sheet 250 500 750 Frequency [kHz] 1000 Power consumption related to temperature, supply voltage and frequency 19 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Outline Dimensions 8 Outline Dimensions Notes 1. For further information on package types, recommendation for board assembly, please go to: http://www.infineon.com/cms/en/product/technology/packages/. 8.1 PG-DSO-8-60 Figure 8-1 PG-DSO-8-60 outline Figure 8-2 PG-DSO-8-60 footprint Data Sheet 20 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Outline Dimensions 0.3 12 ±0.3 5.2 8 1.75 6.4 2.1 Figure 8-3 PG-DSO-8-60 packaging 8.2 PG-TSSOP-8-1 Figure 8-4 PG-TSSOP-8-1 outline Data Sheet 21 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Outline Dimensions Figure 8-5 PG-TSSOP-8-1 footprint Figure 8-6 PG-TSSOP-8-1 packaging Data Sheet 22 Revision 2.0 2016-11-09 EiceDRIVER™ 2EDN7424 Revision History 9 Revision History Revision 2.0, 2016-11-09 Page/ Item Subjects (major changes since previous revision) Responsible Date first version Tobias Gerber 2016/11/09 Data Sheet 23 Revision 2.0 2016-11-09 Please read the Important Notice and Warnings at the end of this document Trademarks of Infineon Technologies AG µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™. 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