2EDN8524RXTMA1

EiceDRIVER™ 2EDN752x / 2EDN852x Features Fast, precise, strong and compatible • Highly efficient SMPS enabled by 5 ns fast slew rates and 17 ns propagation delay precision for fast MOSFET and GaN switching • 1 ns channel-to-channel propagation delay accuracy enables safe use of two channels in parallel • Two independent 5 A channels enable numerous deployment options • Industry standard packages and pinout ease system-design upgrades The new Reference in Ruggedness • 4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant MOSFET protection under abnormal conditions • -10 V control and enable input robustness delivers crucial safety margin when driving pulse-transformers or driving MOSFETs in through hole packaging • 5 A reverse current robustness eliminates the need for output protection circuitry. Typical Applications • Server SMPS • TeleCom SMPS • DC-to-DC Converter • Bricks • Power Tools • Industrial SMPS • Motor Control • Solar SMPS Example Topologies • Single and interleaved PFC • LLC, ZVS with pulse transformer • Synchronous Rectification Description The 2EDN752x/2EDN852x is an advanced dual-channel driver. It is suited to drive logic and normal level MOSFETs and supports OptiMOSTM, CoolMOSTM, Standard Level MOSFETs, Superjunction MOSFETs, as well as IGBTs and GaN Power devices. Data Sheet www.infineon.com Please read the Important Notice and Warnings at the end of this document Rev. 2.6 2021-07-23 EiceDRIVER™ 2EDN752x / 2EDN852x Features The control and enable inputs are LV-TTL compatible (CMOS 3.3 V) with an input voltage range from -5 V to +20 V. -10 V input pin robustness protects the driver against latch-up or electrical overstress which can be induced by parasitic ground inductances. This greatly enhances system stability. 4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant MOSFET and GaN protection under abnormal conditions. Under such circumstances, this UVLO mechanism provides crucial independence from whether and when other supervisors circuitries detect abnormal conditions. Each of the two outputs is able to sink and source 5 A currents utilizing a true rail-to-rail stage. This ensures very low on resistance of 0.7 Ω up to the positive and 0.55 Ω down to the negative rail respectively. Very tight channel to channel delay matching, typ. 1 ns, permits parallel use of two channels, leading to a source and sink capability of 10 A. Industry leading reverse current robustness eliminates the need for Schottky diodes at the outputs and reduces the bill-of-material. From Controller The pinout of the 2EDN family is compatible with the industry standard. Two different control input options, direct and inverted, offer high flexibility. Three package variants, DSO 8-pin, TSSOP 8-pin, WSON 8-pin, allow optimization of PCB board space usage and thermal characteristics. VDD 2EDN752x / 2EDN852x 1 ENA ENB 88 2 INA OUTA 7 33 GND VDD 6 44 INB Load1 Load2 M1 Rg1 Rg2 M2 OUTB 55 CVDD Data Sheet 2 Rev. 2.6 2021-07-23 EiceDRIVER™ 2EDN752x / 2EDN852x Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 1.1 1.2 Product Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Logic Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin Configuration and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 4.1 4.2 4.3 4.4 4.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 11 11 12 5 5.1 5.2 5.3 5.4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 13 14 15 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 8.1 8.2 8.3 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG-DSO-8-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG-TSSOP-8-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG-WSON-8-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Data Sheet 3 25 25 26 28 Rev. 2.6 2021-07-23 EiceDRIVER™ 2EDN752x / 2EDN852x Product Versions 1 Product Versions The 2EDN752x / 2EDN852x are available in 2 different logic, 2 different undervoltage lockout and 3 package versions. Table 1 Product Versions Package Type. UVLO Control Input Part Number IC Topside Marking Code 4.2V direct 2EDN7524F 2N7524AF EiceDRIV XXHYYWW inverted 2EDN7523F 2N7523AF EiceDRIV XXHYYWW direct 2EDN8524F 2N8524AF EiceDRIV XXHYYWW inverted 2EDN8523F 2N8523AF EiceDRIV XXHYYWW direct 2EDN7524R 2N7524 AR_XXX HYYWW inverted 2EDN7523R 2N7523 AR_XXX HYYWW direct 2EDN8524R 2N8524 AR_XXX HYYWW inverted 2EDN8523R 2N8523 AR_XXX HYYWW direct 2EDN7524G 2N7524 AG_XXX HYYWW inverted 2EDN7523G 2N7523 AG_XXX HYYWW PG-DSO-8-60 8V PG-TSSOP-8-1 4.2V 8V PG-WSON-8-4 4.2V Data Sheet 4 Rev. 2.6 2021-07-23 EiceDRIVER™ 2EDN752x / 2EDN852x Product Versions 1.1 Logic Versions The 2 logic versions are indicated by the variable x in the product version 2EDNy52x: • x=3: inverting input logic • x=4: non-inverting / direct input logic The logic relations between inputs, enable pins and outputs are given in Table 2 for the inverting and noninverting version 2EDNx523 and 2EDNx524. The state of the driving output is defined by the state of the respective input, if the enable inputs ENA and ENB are high (or left open). A logic “low” at an enable input or an undervoltage lockout event, due to low voltage at VDD, causes the respective output to be low too, regardless of the input signal. Functional description is shown in Chapter 3 ( Block Diagram) and Chapter 4 (Input Configurations). Table 2 Logic Table Inputs Output Inverting Output Standard ENA ENB INA INB UVLO1) OUTA OUTB OUTA OUTB x x x x active L L L L L L x x inactive L L L L H L L x inactive H L L L H L H x inactive L L H L L H x L inactive L H L L L H x H inactive L L L H H H L L inactive H H L L H H H L inactive L H H L H H L H inactive H L L H H H H H inactive L L H H 1) Inactive means that VDD is above UVLO threshold voltage and release logic to control output stage. Active means that UVLO disable active the output stages. 1.2 Package Versions The logic and UVLO versions are available in 3 different packages. • a standard PG-DSO-8-60 (designated by “F”) • a small PG-TSSOP-8-1 (designated by “R”) • a leadless PG-WSON-8-4 (designated by “G”) Drawings can be viewed in Chapter 8 (Outline Dimensions). Data Sheet 5 Rev. 2.6 2021-07-23 EiceDRIVER™ 2EDN752x / 2EDN852x Pin Configuration and Description 2 Pin Configuration and Description The pin configuration for all input versions of 2EDN7524F, 2EDN7523F, 2EDN8524F and 2EDN8523F in the PGDSO-8-60 package is shown in Figure 1. Drawings can be viewed in Chapter 8 (PG-DSO-8-60). 1 ENA 2 INA 3 GND 4 INB ENB 8 OUTA 7 VDD 6 OUTB 5 Figure 1 Pin Configuration PG-DSO-8-60, Top View Table 3 Pin Configuration 2EDN7524F, 2EDN7523F, 2EDN8524F and 2EDN8523F in the PG-DSO-8-60 Package Pin Symbol Description 1 ENA Enable input channel A Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low 2 INA Input signal channel A Logic input, controlling OUTA (inverting or non-inverting) 3 GND Ground 4 INB Input signal channel B Logic input, controlling OUTB (inverting or non-inverting) 5 OUTB Driver output channel B Low-impedance output with source and sink capability 6 VDD Positive supply voltage Operating range 4.5 V/8.6V to 20 V 7 OUTA Driver output channel A Low-impedance output with source and sink capability 8 ENB Enable input channel B Logic Input; if ENB is high or left open, OUTB is controlled by INB; ENB low causes OUTB low Data Sheet 6 Rev. 2.6 2021-07-23 EiceDRIVER™ 2EDN752x / 2EDN852x Pin Configuration and Description The pin configuration for all input versions of 2EDN7524R, 2EDN7523R, 2EDN8524R and 2EDN8523R in the PGTSSOP-8-1 package is shown in Figure 2. Drawings can be viewed in Chapter 8 (PG-TSSOP-8-1). 1 ENA 2 INA 3 GND 4 INB Exposed Pad ENB 8 OUTA 7 VDD 6 OUTB 5 Figure 2 Pin Configuration PG-TSSOP-8-1, Top View Table 4 Pin Configuration 2EDN7524R, 2EDN7523R, 2EDN8524R and 2EDN8523R in the PG-TSSOP-8-1 Package Pin Symbol Description 1 ENA Enable input channel A Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low 2 INA Input signal channel A Logic input, controlling OUTA (non-inverting) 3 GND Ground1) 4 INB Input signal channel B Logic input, controlling OUTB (non-inverting) 5 OUTB Driver output channel B Low-impedance output with source and sink capability 6 VDD Positive supply voltage Operating range 4.5 V/8.6V to 20 V 7 OUTA Driver output channel A Low-impedance output with source and sink capability 8 ENB Enable input channel B Logic Input; if ENB is high or left open, OUTB is controlled by INB; ENB low causes OUTB low 1) Exposed Pad sink of PG-TSSOP-8-1 packages has to be connected to GND pin. Data Sheet 7 Rev. 2.6 2021-07-23 EiceDRIVER™ 2EDN752x / 2EDN852x Pin Configuration and Description The pin configuration for direct input versions of 2EDN7524G and 2EDN7523G in the PG-WSON-8-4 package is shown in Figure 3. Drawings can be viewed in Chapter 8 (PG-WSON-8-4). ENA 1 INA 2 GND INB 8 ENB 7 OUTA 3 6 VDD 4 5 OUTB Exposed Pad Figure 3 Pin Configuration PG-WSON-8-4, Top View Table 5 Pin Configuration 2EDN7524G and 2EDN7523G in the PG-WSON-8-4 Package Pin Symbol Description 1 ENA Enable input channel A Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low 2 INA Input signal channel A Logic input, controlling OUTA (non-inverting) 3 GND Ground1) 4 INB Input signal channel B Logic input, controlling OUTB (non-inverting) 5 OUTB Driver output channel B Low-impedance output with source and sink capability 6 VDD Positive supply voltage Operating range 4.5 V/8.6V to 20 V 7 OUTA Driver output channel A Low-impedance output with source and sink capability 8 ENB Enable input channel B Logic Input; if ENB is high or left open, OUTB is controlled by INB; ENB low causes OUTB low 1) Exposed Pad of PG-WSON-8-4 packages has to be connected to GND pin. Data Sheet 8 Rev. 2.6 2021-07-23 EiceDRIVER™ 2EDN752x / 2EDN852x Block Diagram 3 Block Diagram A simplified functional block diagram for the non-inverted / direct version is given in Figure 4. Please refer to the functional description section for more details in Chapter 4. VDD VDD 6 UVLO VDD 400k ENA 1 Logic A INA 7 OUTA 5 OUTB 2 100k GND GND VDD VDD 400k ENB 8 Logic B INB 4 100k GND GND 3 GND Figure 4 Data Sheet Block Diagram, direct input, pull-up/pull-down resistor configuration 9 Rev. 2.6 2021-07-23 EiceDRIVER™ 2EDN752x / 2EDN852x Block Diagram A simplified functional block diagram for the inverted version is given in Figure 5. Please refer to the functional description section for more details in Chapter 4. VDD VDD 6 UVLO VDD 400k ENA 1 VDD Logic A 7 OUTA 5 OUTB 400k INA 2 GND VDD VDD VDD 400k 400k ENB 8 Logic B INB 4 GND GND 3 GND Figure 5 Data Sheet Block Diagram, inverting input, pull-up/pull-down resistor configuration 10 Rev. 2.6 2021-07-23 EiceDRIVER™ 2EDN752x / 2EDN852x Functional Description 4 Functional Description 4.1 Introduction The 2EDN752x / 2EDN852x is a fast dual-channel driver for low-side switches. Two true rail-to-rail output stages with very low output impedance and high current capability are chosen to ensure highest flexibility and cover a high variety of applications. The focus on robustness at the input and output side additionally gives this device a safety margin in critical abnormal situations. An extended negative voltage range protects input pins against ground shifts. No current flows over the ESD structure in the IC during a negative input level. All outputs are robust against reverse current. The interaction with the power MOSFET, even reverse reflected power will be handled by the strong internal output stage. All inputs are compatible with LV-TTL signal levels. The threshold voltages with a typical hysteresis of 1.1 V are kept constant over the supply voltage range. Since the 2EDN752x / 2EDN852x aims particularly at fast-switching applications, signal delays and rise/fall times have been minimized. Special effort has been made towards minimizing delay differences between the 2 channels to very low values of typically 1 ns. 4.2 Supply Voltage The maximum supply voltage is 20 V. This high voltage can be valuable in order to exploit the full current capability of 2EDN752x / 2EDN852x when driving very large MOSFETs. The minimum operating supply voltage is set by the undervoltage lockout function to a typical default value of 4.2 V or of 8 V. This lockout function protects power MOSFETs from running into linear mode with subsequent high power dissipation. 4.3 Input Configurations As described in Chapter 1, 2EDN752x / 2EDN852x is available in 2 different configurations with respect to the logic configuration of the 4 input pins (input plus enable). The enable inputs are internally pulled up to a logic high voltage, i.e. the driver is enabled with these pins left open. The direct PWM inputs are internally pulled down to a logic low voltage. This prevents a switch-on event during power up and a not driven input condition. Version with inverted PWM input have an internal pull up resistor to prevent unwanted switch-on. All inputs are compatible with LV-TTL levels and provide a hysteresis of 1.1 V typ. This hysteresis is independent of the supply voltage. All input pins have a negative extended voltage range. This prevents cross current over single wires during GND shifts between signal source (controller) and driver input. 4.4 Driver Outputs The two rail-to-rail output stages realized with complementary MOS transistors are able to provide a typical 5 A of sourcing and sinking current. This driver output stage has a shoot through protection and current limiting behavior. After a switching event, current limitation is raised up to achieve the typical current peak for an excellent fast reaction time of the following power MOS transistor. The output impedance is very low with a typical value below 0.7 Ω for the sourcing p-channel MOS and 0.5 Ω for the sinking n-channel MOS transistor. The use of a p-channel sourcing transistor is crucial for achieving true railto-rail behaviour and avoiding a source follower’s voltage drop. Data Sheet 11 Rev. 2.6 2021-07-23 EiceDRIVER™ 2EDN752x / 2EDN852x Functional Description Gate Drive Outputs held active low in case of floating inputs ENx, INx or during startup or power down once UVLO is not exceeded. Under any situation, startup, UVLO or shutdown, outputs are held under defined conditions. 4.5 Undervoltage Lockout (UVLO) The Undervoltage Lockout function ensures that the output can be switched to its high level only if the supply voltage exceeds the UVLO threshold voltage. Thus it can be guaranteed, that the switch transistor is not switched on if the driving voltage is too low to completely switch it on, thereby avoiding excessive power dissipation. The UVLO level is set to a typical value of 4.2 V / 8 V (with hysteresis). UVLO of 4.2 V is normally used for logic level based MOSFETs. For higher level, like standard and high voltage superjunction MOSFETS, an UVLO voltage of typical 8 V is available. Data Sheet 12 Rev. 2.6 2021-07-23 EiceDRIVER™ 2EDN752x / 2EDN852x Characteristics 5 Characteristics The absolute maximum ratings are listed in Table 6. Stresses beyond these values may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5.1 Absolute Maximum Ratings Table 6 Absolute Maximum Ratings Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Positive supply voltage VVDD -0.3 22 V Voltage at pins INA, INB, ENA, ENB VIN -10 22 V Voltage at pins OUTA, OUTB VOUT -0.3 VVDD+0.3 V Note1) -2 VVDD+0.3 V Repetitive pulse