6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Features
•
•
•
•
•
Infineon Thin-Film-SOI technology
Fully operational to +1200 V
Integrated Ultra‐fast Bootstrap Diode
Floating channel designed for bootstrap operation
Output source/sink current capability +0.35 A/‐0.65 A
•
Tolerant to negative transient voltage up to -100 V
(Pulse width is up 700 ns) given by SOI-technology
Undervoltage lockout for both channels
3.3 V, 5 V, and 15 V input logic compatible
Over current protection with ±5% ITRIP threshold
Fault reporting, automatic Fault clear and
Enable function on the same pin (RFE)
Matched propagation delay for all channels
Integrated 460 ns deadtime protection
Shoot-through (cross-conduction) protection
•
•
•
•
•
•
•
Product summary
•
•
•
•
•
VOFFSET
VCC
IO+/- (typ.)
ton/off (typ.)
Deadtime (typ.)
≤ 1200 V
= 13 V - 20 V
= 0.35 A/0.65 A
= 700 ns/650 ns
= 460 ns
Package
DSO-24 (DSO-28 with 4 pins removed)
Typical applications
•
•
•
Industrial Drives
Embedded inverters for Motor Control in Pumps, Fans.
Commercial and Lite Commercial Air Conditioning
Description
The 6ED2230S12T is a high voltage, high speed IGBT with three independent high side and low side referenced
output channels for three phase applications. Proprietary HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The logic input is compatible with standard CMOS or TTL outputs, down to
3.3 V logic. An over‐current protection (OCP) function which terminates all six outputs can also be derived from
this resistor. An open drain FAULT signal is provided to indicate that an over-current or undervoltage shutdown
has occurred. Fault conditions are cleared automatically after a delay programmed externally via an RC network.
The output drivers feature a high-pulse current buffer stage designed for minimum driver cross-conduction. The
floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration which
operates up to 1200 V. Propagation delays are matched to simplify the HVIC’s use in high frequency applications.
DC BUS +
Vcc
Hin1,2,3
Lin1,2,3
RFE
ITRIP
(Refer to Lead Assignments for
correct pin configuration).
This diagram shows electrical
connections only. Please refer to
Application Notes & Design Tips
for proper circuit board layout.
VB1,2,3
HO1,2,3
VS1,2,3
To load
LO1,2,3
Vss
COM
DC BUS -
Figure 1
Datasheet
Typical connection diagram
Please read the Important Notice and Warnings at the end of this document
www.infineon.com/SOI
2020‐03‐10
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Device information
Device information
Base part number
6ED2230S12T
1
1)
Package type
DSO-24
Standard pack
Orderable part pumber
Form
Quantity
Tape and Reel
1000
6ED2230S12TXUMA1
Also available for die sales as ‘Sawn Wafer on Film’ with part number 6ED2230S12C. Please contact Infineon for
more information.
Datasheet
2
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Table of contents
Table of contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Lead configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
5.1
5.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6
6.1
6.2
6.2.1
6.2.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
Application information and additional details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IGBT/MOSFET gate drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Switching and timing relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Matched propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Input logic compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Undervoltage lockout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Shoot-Through protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Enable input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Fault reporting and programmable fault clear timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Over-Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Truth table: Undervoltage lockout, ITRIP, and ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Advanced input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Short-Pulse / Noise rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Integrated bootstrap diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Tolerant to negative VS transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PCB layout tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Additional documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
7.1
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package information DSO-24 (DSO-28 4 pins removed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
9
Qualification Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Related Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Datasheet
3
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Block diagram
1
Block diagram
VB1
S
HIN1
LIN1
Input
Noise
filter
Deadtime &
Shoot-Through
Prevention
VSS/COM
Level
Shifter
Latch
&
UV Detect
HV Level
Shifter
Driver
HO1
R
Input
Noise
filter
VS1
VB2
S
HIN2
Input
Noise
filter
Deadtime &
Shoot-Through
Prevention
LIN2
VSS/COM
Level
Shifter
Latch
&
UV Detect
HV Level
Shifter
Driver
HO2
R
Input
Noise
filter
VS2
VB3
S
HIN3
Input
Noise
filter
Deadtime &
Shoot-Through
Prevention
LIN3
RFE
Latch
&
UV Detect
HV Level
Shifter
Driver
HO3
R
Input
Noise
filter
VSS
ITRIP
VSS/COM
Level
Shifter
VS3
UV
Detect
ITRIP
Noise
filter
VCC
VSS/COM
Level
Shifter
Delay
Driver
LO1
VSS/COM
Level
Shifter
Delay
Driver
LO2
VSS/COM
Level
Shifter
Delay
Driver
LO3
Noise
filter
COM
Figure 2
Datasheet
Functional block diagram
4
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Lead configuration
2
Lead configuration
Table 1
Lead definitions
Symbol
Description
HIN1,2,3
Logic input for high side gate driver output (HO), in phase
LIN1,2,3
Logic input for low side gate driver output (LO), in phase
VB1,2,3
High side floating supply
HO1,2,3
High side gate drive output
VS1,2,3
High side floating supply return
VCC
Low side and logic fixed supply
LO
Low side gate drive output
COM
Low side return
VSS
Logic ground
ITRIP
Analog input for over-current shutdown. When active, ITRIP shuts down outputs and activates RFE
low. When ITRIP becomes inactive, RFE stays active low for an externally set time tFLTCLR, then
automatically becomes inactive (open-drain high impedance).
RFE
Integrated fault reporting function like over-current (ITRIP), or low-side undervoltage lockout and
the fault clear timer. This pin has negative logic and an open-drain output. The use of over-current
protection requires the use of external components.
Figure 3
Datasheet
HIN1
1
28
VB1
HIN2
2
27
HO1
HIN3
3
26
VS1
LIN1
4
25
LIN2
5
24
LIN3
6
23
VB2
ITRIP
7
22
HO2
RFE
8
21
VS2
VCC
9
20
VSS
10
19
COM
11
18
VB3
LO1
12
17
HO3
LO2
13
16
VS3
LO3
14
15
NC
Lead Assignments
5
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Absolute maximum ratings
3
Table 2
Absolute maximum ratings
Absolute maximum ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM unless otherwise stated in the table. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.
Parameter
Symbol
Values
Min.
Unit
Note or Test
Condition
Max.
Low side supply voltage
VCC
-0.3
25
V
—
Logic input voltage (LIN, HIN, RFE, ITRIP)
VIN
VSS - 5
VCC + 0.3 V
—
High-side floating well supply voltage
VB1,2,3
-0.3
1225
V
—
High-side floating well supply return
voltage
VS1,2,3
VB1,2,3 25
VB1,2,3
+ 0.3
V
—
Floating gate drive output voltage
VHO1,2,3
VS1,2,3 0.3
VB1,2,3
+ 0.3
V
—
Low-side output voltage
VLO1,2,3
- 0.3
VCC + 0.3 V
—
Logic ground
VSS
VCC - 25
VCC + 0.3 V
—
Allowable VS offset supply transient
relative to COM
dVS/dt
—
50
V/ns
—
Package power dissipation
PD
—
1.3
W
TA +25ºC
Thermal resistance, junction to ambient
RthJA
—
75
°C/W
—
Junction temperature
TJ
—
150
°C
—
Storage temperature
TS
-55
150
°C
—
Lead temperature (soldering, 10 seconds)
TL
—
300
°C
—
Datasheet
6
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Recommended operating conditions
4
Recommended operating conditions
Table 3
Recommended operating conditions
For proper operation, the device should be used within the recommended conditions. All voltage parameters
are absolute voltages referenced to COM unless otherwise stated in the table. The offset rating is tested with
supplies of (VCC - COM) = (VB - VS) = 15 V.
Parameter
Symbol
Values
Min.
Unit
Note or Test
Condition
Max.
Low-side supply voltage
VCC
1ϯ
20
V
—
Logic input voltage (LIN, HIN, ITRIP)
VIN
VSS
VSS + 5
V
—
RFE logic input voltage
VRFE
VSS
VCC
V
—
High-side floating well supply voltage
VB1,2,3
VS1,2,3
+ 12
VS1,2,3
+ 20
V
—
High-side floating well supply offset
voltage
VS1,2,3
COM – 8 900
V
1)
Transient High-side floating well supply
offset voltage
VSt
-100
1000
V
2)
Floating gate drive output voltage
VHO1,2,3
VS1,2,3
VB1,2,3
V
—
Low-side output voltage
VLO1,2,3
0
VCC
V
—
Logic ground
VSS
-5
5
V
—
Ambient temperature
TA
-40
125
°C
—
1
2
Logic operation for VS of –8 V to 1200 V. Logic state held for Vs of –8 V to –VBS
In case VCC > VB there is an additional power dissipation in the internal bootstrap diode between pins VCC
and VBx. Insensitivity of bridge output to negative transient voltage up to –100 V is not subject to production
test – verified by design / characterization.
Datasheet
7
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Electrical characteristics
5
Electrical characteristics
5.1
Static electrical characteristics
Table 4
Static electrical characteristics
(VCC - COM) = (VB - VS) = 15 V. TA = 25 °C unless otherwise specified. The VIN and IIN parameters are referenced
to COM. The VO and IO parameters are referenced to respective VS and COM and are applicable to the respective
output leads HO or LO. The VCCUV parameters are referenced to COM. The VBSUV parameters are referenced to
VS.
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or Test
Condition
Max.
VBS supply under voltage positive
threshold
VBSUV+
9.2
10.4
11.6
V
—
VBS supply under voltage negative
threshold
VBSUV-
8.3
9.4
10.5
V
—
VBS supply under voltage hysteresis
VBSUVHY
—
1
—
V
—
VCC supply under voltage positive
threshold
VCCUV+
10.2
11.4
12.6
V
—
VCC supply under voltage negative
threshold
VCCUV-
9.3
10.4
11.5
V
—
VCC supply under voltage hysteresis
VCCUVHY
—
1
—
V
—
High level output voltage drop, VBIAS- VOH
VO
—
0.35
—
V
Io = 20 mA
Low level output voltage drop, VO
VOL
—
0.15
—
V
Io = 20 mA
Logic “1” input voltage
VIH
2.3
—
—
V
—
Logic “0” input voltage
VIL
—
—
0.7
V
—
RFE positive going threshold
VRFE+
1.7
1.9
2.3
V
—
RFE negative going threshold
VRFE-
0.7
0.9
1.1
V
—
ITRIP positive going threshold
VITRIP+
0.475
0.500
0.525 V
—
ITRIP negative going threshold
VITRIP-
0.425
0.450
0.475 V
—
ITRIP hysteresis
VITRIP HYS
—
0.050
—
V
—
High-side floating well offset supply
leakage
ILK
—
—
50
µA
VB = VS = 1200
V
Quiescent VBS supply current
IQBS
—
175
250
µA
VIN = 0 V or 5 V
Quiescent VCC supply current
IQCC
—
1000
1500
µA
VIN = 0 V or 5 V
200
300
—
mA
C = 22 nF
Mean output current for load capacity IO+ mean
charging from 3 V (20%) to 6 V (40%)
Datasheet
8
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Electrical characteristics
Table 4
Static electrical characteristics (continued)
(VCC - COM) = (VB - VS) = 15 V. TA = 25 °C unless otherwise specified. The VIN and IIN parameters are referenced
to COM. The VO and IO parameters are referenced to respective VS and COM and are applicable to the respective
output leads HO or LO. The VCCUV parameters are referenced to COM. The VBSUV parameters are referenced to
VS.
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or Test
Condition
Max.
Mean output current
for load capacity discharging from
10.5 V (70%) to 7.5 V (50%)Mean
Output current for load capacity
charging from 3V (20%) to 6 V (40%)
supply current
IO- mean
400
600
—
mA
C = 22 nF
Output high short circuit pulsed
current
IO+
—
350
—
mA
VO = 0 V
PW ≤ 1 µs
Output low short circuit pulsed
current
IO-
—
650
—
mA
VO = 15 V
PW ≤ 1 µs
Logic “1” Input bias current (RFE)
IRFE+
—
0
1
µA
VRFE = 3.3 V
Logic “0” Input bias current (RFE)
IRFE-
1
0
—
µA
VRFE = 0 V
Logic “1” Input bias current (LIN,
HIN)
IIN+
—
1000
1250
µA
VIN = 5 V
Logic “0” Input bias current (LIN,
HIN)
IIN-
—
—
1
µA
VIN = 0 V
Logic “1” Input bias current (ITRIP)
IITRIP+
—
15
25
µA
VIN = 1 V
Logic “0” Input bias current (ITRIP)
IITRIP-
—
—
1
µA
VIN = 0 V
Bootstrap diode on resistance
RBS
—
120
150
Ω
—
Bootstrap diode forward voltage
drop
VFBSD
—
0.9
—
V
Io = 0.3 mA
RFE mos resistance
RON, RFE
—
40
60
Ω
—
Please refer to Application Section for integrated bootstrap diode description.
5.2
Table 5
Dynamic electrical characteristics
Dynamic electrical characteristics
VCC = VB = 15 V, VS = COM, TA = 25 oC, and CL = 1000 pF unless otherwise specified.
Parameter
Symbol
Values
Min.
Typ.
Unit
Max.
Turn-on propagation delay
tON
500
700
900
ns
Turn-off propagation delay
tOFF
450
650
850
ns
Turn-on rise time
tR
—
35
—
ns
Datasheet
9
Note or Test
Condition
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Electrical characteristics
Table 5
Dynamic electrical characteristics (continued)
VCC = VB = 15 V, VS = COM, TA = 25 oC, and CL = 1000 pF unless otherwise specified.
Parameter
Symbol
Values
Min.
Typ.
Unit
Max.
Note or Test
Condition
Turn-off fall time
tF
—
20
—
ns
Dead time, LO turn-off to HO turn-on &
HO turn-off to LO turn-on
DT
300
460
700
ns
Delay matching time (tON, tOFF)
MT
—
—
130
ns
Enable low to output shutdown
propagation delay
tEN
—
600
—
ns
Input filter time (LIN, HIN, EN)
TFIL,IN
200
350
500
ns
FAULT clear time
(R = 2 MΩ, C = 1 nF)
TFLTCLR
—
1.9
—
ms
VDD = 3.3V
ITRIP to output shutdown propagation TITRIP
delay
—
750
1250
ns
VITRIP = 1 V
ITRIP blanking time
TBL
—
500
—
ns
ITRIP to FAULT propagation delay
TFLT
450
650
900
ns
Datasheet
10
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Application information and additional details
6
Application information and additional details
Information regarding the following topics are included as subsections within this section of the datasheet.
•
IGBT/MOSFET gate drive
•
Switching and timing relationships
•
Deadtime
•
Matched propagation delays
•
Input logic compatibility
•
Undervoltage lockout protection
•
Shoot-Through protection
•
Enable input
•
Fault reporting and programmable fault clear timer
•
Over-Current protection
•
Truth table: Undervoltage lockout, ITRIP, and ENABLE
•
Advanced input filter
•
Short-Pulse / Noise rejection
•
Integrated bootstrap diodes
•
Negative VS transient SOA
•
PCB layout tips
•
Additional documentation
6.1
IGBT/MOSFET gate drive
The 6ED2230S12T HVICs are designed to drive MOSFET or IGBT power devices. Figure 4 and Figure 5 illustrate
several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC,
used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external
power switch is defined as VHO for the high-side power switch and VLO for the low-side power switch; this
parameter is sometimes generically called VOUT and in this case does not differentiate between the high-side
or low-side output voltage.
VB
(or V CC )
IO+
HO
(or LO)
+
VHO (or VLO)
VS
(or COM)
Figure 4
Datasheet
-
HVIC sourcing current
11
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Application information and additional details
VB
(or V CC )
HO
(or LO)
IO-
VS
(or COM)
Figure 5
6.2
HVIC sinking current
Switching and timing relationships
The relationships between the input and output signals of the 6ED2230S12T are illustrated below in Figure 6.
From these figures, we can see the definitions of several timing parameters (i.e., PWIN, PWOUT, tON, tOFF, tR,
and tF) associated with this device.
PW IN
LIN, HIN
50%
ton
50%
toff
tr
90%
90%
LO, HO
Figure 6
tf
PWOUT
10%
10%
Switching time waveformsInput/output timing diagram
Figure 7 an Figure 8 illustrate the timing relationships of some of the functionality of the 6ED2230S12T; this
functionality is described in further detail later in this document.
During interval A of Figure 7, the HVIC has received the command to turn-on both the high- and low-side
switches at the same time; as a result, the shoot-through protection of the HVIC has prevented this condition.
HVIC is keeping on output channel that is already on ignoring the 2nd input signal.
Interval B of Figure 7 an Figure 8 shows that the signal on the ITRIP input pin has gone from a low to a high
state; as a result, all of the gate drive outputs have been disabled (i.e., see that HO has returned to the low state;
LO is also held low), and a fault condition is reported on the RFE pin, which goes 0V. Once the ITRIP input has
returned to the low state, the output will remain disabled and the fault condition reported until the voltage on
the RFE pin charges up to VRFE+ threshold; the charging characteristics are dictated by the RC network attached
to the RFE pin. After fault clear time HVIC is waiting for a new input signal on LIN/HIN before activate the output
stage (LO/HO).
During interval C of Figure 7 an Figure 9, we can see that the RFE pin has been pulled low (as is the case when
the driver IC has received a command from the control IC to shutdown); these results in the outputs (HO and
LO) being held in the low state until the RFE pin is pulled high. After an enable event HVIC will wait for a new
input signal on LIN/HIN before activate the output stage (LO/HO).
Datasheet
12
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Application information and additional details
A
Figure 7
A
B
C
B
C
Input/output timing diagram
VIT,TH+
VIT,TH-
ITRIP
RFE
VRFE+
50%
tFLT
tFLTCLR
tTRIP
HO, LO
Figure 8
90%
Detailed view of B interval
RFE
VRFEtEN
90%
LO, HO
Figure 9
6.2.1
Detailed view of C interval
Deadtime
This HVIC features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within
Infineon’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature
inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off;
this is done to ensure that the power switch being turned off has fully turned off before the second power
Datasheet
13
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Application information and additional details
switch is turned on. This minimum deadtime is automatically inserted whenever the external deadtime is
shorter than DT; external deadtimes larger than DT are not modified by the gate driver.
6.2.2
Matched propagation delays
The 6ED2230S12T HVIC is designed with propagation delay matching circuitry. With this feature, the IC’s
response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF)
for both the low-side channels and the high-side channels; the maximum difference is specified by the delay
matching parameter (MT). The propagation turn-on delay (tON) of the 6ED2230S12T is matched to the
propagation turn-on delay (tOFF).
50%
HIN
LIN
50%
LO
HO
10%
MT
MT
90%
LO
Figure 10
6.3
HO
Delay Matching Waveform Definition
Input logic compatibility
The inputs of this IC are compatible with standard CMOS and TTL outputs. The 6ED2230S12T has been designed
to be compatible with 3.3 V and 5 V logic-level signals. Figure 11 illustrates an input signal to the 6ED2230S12T,
its input threshold values, and the logic state of the IC as a result of the input signal.
Input Logic
Level
Input Signal
(IRS23364D)
V IH
Figure 11
6.4
VIL
High
Low
Low
HIN & LIN input thresholds
Undervoltage lockout protection
This HVIC provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply
and the VBS (high-side circuitry) power supply. Figure 12 is used to illustrate this concept; VCC (or VBS) is
plotted over time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage
protection is enabled or disabled.
Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally,
if the VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry
Datasheet
14
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Application information and additional details
will recognize a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will
transition to the low state to inform the controller of the fault condition.
Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if
the VBS voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will
recognize a fault condition, and shutdown the high-side gate drive outputs of the IC.
The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is
sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could
be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is
high; this could result in very high conduction losses within the power device and could lead to power device
failure.
VCC
(or V BS )
V CCUV+
(or V BSUV+)
VCCUV (or V BSUV- )
Time
UVLO Protection
(Gate Drive Outputs Disabled)
Normal
Operation
Figure 12
6.5
Normal
Operation
UVLO protection
Shoot-Through protection
The 6ED2230S12T is equipped with shoot-through protection circuitry (also known as cross-conduction
prevention circuitry). Figure 13 shows how this protection circuitry prevents both the high- and low-side
switches from conducting at the same time.
Shoot-through
protection enabled
Figure 13
6.6
Shoot-through
protection enabled
HIN
HIN
LIN
LIN
HO
HO
LO
LO
Illustration of shoot-through protection circuitry
Enable input
The 6ED2230S12T provides an enable functionality that allows it to shutdown or enable the HVIC. When the RFE
pin is in the high state the HVIC is able to operate normally (assuming no other under voltage fault conditions
on Vcc). When the RFE pin is in a low state, the gate drive outputs are pulled low until the enable condition is
Datasheet
15
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Application information and additional details
restored. The enable circuitry of the 6ED2230S12T features an input filter; the minimum input duration is
specified by tFIL, IN. Please refer to the RFE pin parameters VRFE+, VRFE-, and IRFE for the details of its use.
6.7
Fault reporting and programmable fault clear timer
The 6ED2230S12T provides an integrated fault reporting output and an adjustable fault clear timer. There are
two situations that would cause the HVIC to report a fault via the RFE pin. The first is an undervoltage condition
of VCC and the second is if the ITRIP pin recognizes a fault. Once the fault condition occurs, the RFE pin is
internally pulled to Vss and the fault clear timer is activated. The RFE output stays in the low state until the fault
condition has been removed and the fault clear timer expires; once the fault clear timer expires, the voltage on
the RFE pin will return to its external pull-up voltage.
The length of the fault clear time period (tFLTCLR) is determined by a fix time constant added to exponential
charging characteristics of the capacitor where the time constant is set by RRFE and CRFE. Figure 14 shows that
RRFE is connected between the external supply (VDD) and the RFE pin, while CRFE is placed between the RFE
and Vss pins.
uC
VCC
HIN
LIN
HIN U
LIN U
HIN V
LIN V
HIN W
LIN W
VDD
HO
GK
RRFE
VS
RFE
LO
CRFE
Vss
ITRIP
DC - BUS
Figure 14
R
Programming the fault clear timer
The design guidelines for this network are shown in Table 6.
Table 6
CRFE
Design guidelines
≤1 nF
Ceramic
RRFE
0.5 MΩ to 2 MΩ
>> RON,REF
The length of the fault clear time period can be determined by using the formula below.
uC(t) = Vf*(1-e-t/RC)
tFLTCLR = -(RRFE*CRFE)*ln(1-VRFE+ /VDD) + 160 µs
The voltage on the RFE pin should not exceed the VDD of the uC power supply.
Datasheet
16
6ED2230S12T
1200 V Three Phase Gate Driver with Integrated Bootstrap Diode and OCP
Application information and additional details
6.8
Over-Current protection
The 6ED2230S12T HVICs are equipped with an ITRIP input pin. This functionality can be used to detect overcurrent events in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs
are shutdown, and RFE is pulled to Vss.
The level of current at which the over-current protection is initiated is determined by the resistor network (i.e.,
R0, R1, and R2) connected to ITRIP as shown in Figure 15, and the ITRIP threshold (VITRIP+). The circuit designer
will need to determine the maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that
the voltage at node VX reaches the over-current threshold (VITRIP+) at that current level.
VITRIP+ = R0*IDC-(R1/(R1+R2))
DC BUS +
Vcc
Hin
Lin
RFE
ITRIP
VB
HO
VS
To load
LO
COM
VSS
R2
R1
Vx
DC BUS -
R0
Figure 15
IDC-
Programming the over-current protection
For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed
to exceed 5 V; if necessary, an external voltage clamp may be used.
6.9
Truth table: Undervoltage lockout, ITRIP, and ENABLE
Table 7 provides the truth table for the 6ED2230S12T. The first line shows that the UVLO for VCC has been
tripped; the RFE output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in
this case and when VCC is greater than VCCUV, the FAULT output returns the driver is functional.
The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have
been disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new
rising transition of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that
the ITRIP trip threshold has been reached and that the gate drive outputs have been disabled. This condition is
stored in the external RC network waiting for fault clear time. The last case shows when the HVIC has received
an enable command through the RFE input to shutdown; as a result, the gate drive outputs have been disabled.
Table 7
UVLO VCC
Datasheet
Truth table
VCC
VBS
ITRIP
RFE
LO
HO
