AUTOMOTIVE GRADE
HEXFET® Power MOSFET
Features
Optimized for Logic Level Drive
Advanced Process Technology
Ultra Low On-Resistance
Logic Level Gate Drive
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
Package Type
AUIRLS4030-7P
D2Pak 7 Pin
VDSS
100V
RDS(on) typ.
3.2m
max.
3.9m
190A
ID
Description
Specifically designed for Automotive applications, this HEXFET®
Power MOSFET utilizes the latest processing techniques to achieve
extremely low on-resistance per silicon area. Additional features of
this design are a 175°C junction operating temperature, fast
switching speed and improved repetitive avalanche rating . These
features combine to make this design an extremely efficient and
reliable device for use in Automotive applications and a wide variety
of other applications.
Base Part Number
AUIRLS4030-7P
D2Pak 7 Pin
AUIRLS4030-7P
G
D
S
Gate
Drain
Source
Standard Pack
Form
Quantity
Tube
50
Tape and Reel Left
800
Orderable Part Number
AUIRLS4030-7P
AUIRLS4030-7TRL
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless
otherwise specified.
Symbol
Parameter
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
190
ID @ TC = 100°C
IDM
PD @TC = 25°C
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Maximum Power Dissipation
130
750
370
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy (Thermally Limited)
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
Thermal Resistance
Symbol
RJC
RJA
Parameter
Junction-to-Case
Junction-to-Ambient
Max.
Units
A
W
2.5
± 16
320
See Fig.14,15, 22a, 22b
W/°C
V
mJ
A
mJ
V/ns
13
-55 to + 175
300
°C
Typ.
Max.
Units
–––
–––
0.40
40
°C/W
HEXFET® is a registered trademark of Infineon.
*Qualification standards can be found at www.infineon.com
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AUIRLS4030-7P
Static @ TJ = 25°C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Trans conductance
IDSS
Drain-to-Source Leakage Current
IGSS
RG
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
Min.
100
–––
–––
–––
1.0
Typ. Max. Units
Conditions
––– –––
V VGS = 0V, ID = 250µA
0.10 ––– V/°C Reference to 25°C, ID = 5mA
3.2
3.9
VGS = 10V, ID = 110A
m
3.3
4.1
VGS = 4.5V, ID = 94A
–––
2.5
V VDS = VGS, ID = 250µA
250
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
2.0
–––
S
20
µA
250
100
nA
-100
–––
VDS = 25V, ID = 110A
VDS = 100V, VGS = 0V
VDS = 100V,VGS = 0V,TJ =125°C
VGS = 16V
VGS = -16V
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
–––
93
140
–––
27
–––
–––
43
–––
–––
50
–––
–––
53
–––
––– 160 –––
––– 110 –––
–––
87
–––
––– 11490 –––
––– 680 –––
Crss
Coss eff.(ER)
Coss eff.(TR)
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
–––
–––
–––
300
760
1170
Min.
Typ. Max. Units
–––
–––
190
–––
–––
750
–––
–––
–––
–––
–––
–––
–––
53
63
99
155
3.3
1.3
–––
–––
–––
–––
–––
Diode Characteristics
Parameter
Continuous Source Current
IS
(Body Diode)
Pulsed Source Current
ISM
(Body Diode)
VSD
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
–––
–––
–––
ID = 110A
VDS = 50V
nC
VGS = 4.5V
VDD = 65V
ID = 110A
ns
RG= 2.7
VGS = 4.5V
VGS = 0V
VDS = 50V
pF ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 80V
VGS = 0V, VDS = 0V to 80V
Conditions
MOSFET symbol
showing the
A
integral reverse
p-n junction diode.
V TJ = 25°C,IS = 110A,VGS = 0V
TJ = 25°C
VDD = 85V
ns
TJ = 125°C
IF = 110A,
TJ = 25°C di/dt = 100A/µs
nC
TJ = 125°C
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.05mH, RG = 25, IAS = 110A, VGS =10V. Part not recommended for use above this value.
ISD 110A, di/dt 1520A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994
R is measured at TJ approximately 90°C.
RJC value shown is at time zero.
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AUIRLS4030-7P
1000
1000
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.7V
2.5V
BOTTOM
100
10
2.5V
2.5V
60µs PULSE WIDTH
60µs PULSE WIDTH
Tj = 25°C
1
Tj = 175°C
10
0.1
1
10
100
1000
0.1
V DS, Drain-to-Source Voltage (V)
100
1000
3.0
R DS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
Fig. 2 Typical Output Characteristics
1000
T J = 175°C
100
10
T J = 25°C
1
VDS = 25V
60µs PULSE WIDTH
0.1
1
2
3
4
ID = 110A
VGS = 10V
2.5
2.0
1.5
1.0
0.5
5
-60 -40 -20 0 20 40 60 80 100 120 140160 180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig. 4 Normalized On-Resistance vs. Temperature
Fig. 3 Typical Transfer Characteristics
100000
5.0
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = C gd
VGS, Gate-to-Source Voltage (V)
ID = 110A
Coss = Cds + Cgd
C, Capacitance (pF)
1
V DS, Drain-to-Source Voltage (V)
Fig. 1 Typical Output Characteristics
C iss
10000
C oss
1000
C rss
100
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
3
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.7V
2.5V
4.0
VDS = 80V
VDS = 50V
3.0
2.0
1.0
0.0
0
20
40
60
80
100
120
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
2017-10-10
AUIRLS4030-7P
10000
T J = 175°C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
100
T J = 25°C
10
1
OPERATION IN THIS AREA
LIMITED BY R DS (on)
1000
100µsec
100
1msec
10msec
10
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
0.1
0.0
0.5
1.0
1.5
1
2.0
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
200
180
ID, Drain Current (A)
160
140
120
100
80
60
40
20
0
75
100
125
150
125
Id = 5mA
120
115
110
105
100
95
-60 -40 -20 0 20 40 60 80 100 120 140160 180
175
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs. Case Temperature
EAS , Single Pulse Avalanche Energy (mJ)
3.5
ID
TOP
12A
16A
BOTTOM 110A
1200
3.0
Energy (µJ)
Fig 10. Drain-to-Source Breakdown Voltage
1400
4.0
1000
2.5
2.0
1.5
1.0
0.5
0.0
-20
0
20
40
60
80
100
800
600
400
200
0
120
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
Fig 12. Maximum Avalanche Energy vs. Drain Current
Fig 11. Typical COSS Stored Energy
4
1000
Fig 8. Maximum Safe Operating Area
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
50
100
VDS , Drain-to-Source Voltage (V)
VSD , Source-to-Drain Voltage (V)
25
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AUIRLS4030-7P
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.1
0.20
0.10
0.05
J
0.02
0.01
0.01
R1
R1
J
1
R2
R2
C
2
1
Ri (°C/W)
C
2
C i= i R i
Ci = iRi
I (sec)
0.176
0.000343
0.227
0.006073
0.001
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
1E-005
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Avalanche Current vs. Pulse width
EAR , Avalanche Energy (mJ)
400
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 110A
300
200
100
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
5
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.infineon.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 18a, 18b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 13, 14).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
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AUIRLS4030-7P
30
2.5
2.0
1.5
IRRM (A)
VGS(th) , Gate threshold Voltage (V)
3.0
ID = 250µA
ID = 1.0mA
ID = 1.0A
1.0
25
IF = 75A
V R = 85V
20
TJ = 25°C
TJ = 125°C
15
10
0.5
5
0.0
0
-75 -50 -25
0
25 50 75 100 125 150 175
0
200
T J , Temperature ( °C )
1000
1400
1200
IF = 75A
VR = 85V
1000
TJ = 25°C
TJ = 125°C
QRR (nC)
IRRM (A)
20
TJ = 25°C
TJ = 125°C
800
Fig. 17 - Typical Recovery Current vs. dif/dt
30
25
600
diF /dt (A/µs)
Fig 16. Threshold Voltage vs. Temperature
IF = 110A
V R = 85V
400
15
10
800
600
400
5
200
0
0
200
400
600
800
0
1000
0
diF /dt (A/µs)
200
400
600
800
1000
diF /dt (A/µs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
1600
IF = 110A
VR = 85V
1400
TJ = 25°C
TJ = 125°C
1200
QRR (nC)
1000
800
600
400
200
0
0
200
400
600
800
1000
diF /dt (A/µs)
Fig. 20 - Typical Stored Charge vs. dif/dt
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AUIRLS4030-7P
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
15V
tp
L
VDS
D.U.T
RG
IAS
20V
tp
DRIVER
+
V
- DD
A
0.01
Fig 22a. Unclamped Inductive Test Circuit
Fig 23a. Switching Time Test Circuit
I AS
Fig 22b. Unclamped Inductive Waveforms
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Fig 24a. Gate Charge Test Circuit
7
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
2017-10-10
AUIRLS4030-7P
D2Pak - 7 Pin Package Outline (Dimensions are shown in millimeters (inches))
D2Pak - 7 Pin Part Marking Information
Part Number
AULS4030-7P
YWWA
IR Logo
XX
Date Code
Y= Year
WW= Work Week
XX
Lot Code
8
2017-10-10
AUIRLS4030-7P
D2Pak - 7 Pin Tape and Reel
9
2017-10-10
AUIRLS4030-7P
Qualification Information
Automotive
(per AEC-Q101)
Comments: This part number(s) passed Automotive qualification. Infineon’s
Industrial and Consumer qualification level is granted by extension of the higher
Automotive level.
Qualification Level
Moisture Sensitivity Level
D2-Pak 7 Pin
MSL1
Class M4 (+/- 800V)†
AEC-Q101-002
Class H3A (+/- 6000V)†
AEC-Q101-001
Class C5 (+/- 2000V)†
AEC-Q101-005
Yes
Machine Model
ESD
Human Body Model
Charged Device Model
RoHS Compliant
† Highest passing voltage.
Revision History
Date
03/03/2014
04/02/2014
11/06/2015
10/10/2017
Comments
Added "Logic Level Gate Drive" bullet in the features section on page 1
Updated data sheet with new IR corporate template
Updated package outline and part marking on page 8 & 9
Updated typo on the fig.19 and fig.20, unit of y-axis from "A" to "nC" on page 6.
Corrected typo error on part marking on page 8.
Updated datasheet with corporate template
Corrected ordering table on page 1.
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
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