AUIRS20302S

May 2nd, 2014 Automotive Grade AUIRS20302S Pre-regulated Three Phase Gate Driver Product Summary Features • • • • • • • • • • • • • • • • Topology 3 phase gate driver for 24V & higher drives Under-voltage lockout for all channels Cross-conduction prevention logic High voltage pre-regulator MOSFET Power-on reset architecture FAULT detection and Reset Current sense comparator Over-current blanking time 3.3V logic compatible Matched propagation delay for all channels Fully operational up to +200V Floating channels for bootstrap operation High negative transients immunity Pre-regulated supply line for uP Automotive qualified Leadfree, RoSH Compliant 3-phase gate driver VOFFSET 200 V VOUT 8.0 V – 17 V Io+ & I o- (typical) 0.20 A & 0.35 A tON & tOFF 530 ns / 530 ns (typical) Deadtime (typical) 0.7 us Package Typical Applications SOIC 28WB 24V to 150V – 3 Phase Motor Drives Automotive & Truck HVAC, PUMP BLDC Motor Drives Typical Connection Diagram + Bat VCP VPR 5V Reg Vb1 Vb2 Vb3 Ho1 Ho2 Ho3 Vs1 Vs2 Vs3 AUIRS20302S ASIC or uP Flt Frst EN Hin3 Lin3 Hin2 Lin2 Hin1 Lin1 Vss Cap Can Lo1 Lo2 Lo3 Com U V W Ref - Bat 1 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Table of Contents Page Typical Connection Diagram 1 Description/Feature Comparison 3 Qualification Information 4 Absolute Maximum Ratings 5 Recommended Operating Conditions 5 Static Electrical Characteristics 6 Dynamic Electrical Characteristics 7 Functional Block Diagram 8 Input/Output Pin Equivalent Circuit Diagram 9 Lead Definitions 10 Lead Assignments 10 Application Information and Additional Details 11 Parameter Temperature Trends 16 Package Details 21 Tape and Reel Details 22 Part Marking Information & Ordering Information 23 2 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Description The AUIRS20302S is a three phase gate driver dedicated to BLDC motor drive up to 600W. Proprietary HVIC technology enables this rugged monolithic design with enforced Automotive ESD & Latch-up grades. Primarily designed for 24V battery application, its drive capability goes from 12v to 200V which cover all the abnormal conditions of the vehicle. The gate drive circuitry features cross-conduction preventive and minimum dead-time blocks. It is powered by a constant voltage so that the gate drives never exceed 17V including during Load Dump condition. An external MOSFET is acting as a pre-regulator. The inner charge pump and voltage control loop drives its gate in order to keep the VPR pin constant when the battery voltage varies. The AUIRS20302S also features an overcurrent protection that definitively shuts down all gates in case of short-circuit. The fault condition is reset by cycling the FRST pin while the I.C is disabled. A blanking time, synchronized with each high side switch command, avoids any premature triggering of the protection. The logic control block of the AUIRS20302S is developed in order to support a fast and reliable 3 phase BLDC design. For example, its inputs are compatible with the 3.3V logic processors and feature a short-pulse/noise rejection filter. The 6 commands include matched propagation delays, shoot-through protections and minimum dead-time. The bootstrap capacitor voltage of each phase is monitored independently (UVLO). Also, the maximum gate voltage is controlled by the pre-regulator in all conditions. No linear or abnormal gate drive is possible. The VPR pin can also supply the surrounding system components if the total consumption doesn’t exceed 0.1A. 3 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Qualification Information† Automotive (per AEC-Q100††) Qualification Level Comments: This family of ICs has passed an Automotive qualification. IR’s Industrial and Consumer qualification level is granted by extension of the higher Automotive level. SOIC28 Moisture Sensitivity Level Machine Model Human Body Model ESD Charged Device Model IC Latch-Up Test RoHS Compliant MSL3††† 260°C (per IPC/JEDEC J-STD-020) M1 (+/-200V) (per AEC-Q100-003) H1B (+/-2000V) (per AEC-Q100-002) C3B (+/-500 V) (per AEC-Q100-011) Class II Level A (per AEC-Q100-004) Yes Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ † †† Exceptions to AEC-Q100 requirements are noted in the qualification report. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. 4 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSS, all currents are defined positive into any lead. An operation above the absolute maximum limit is not implied and could damage the part. The thermal resistance and power dissipation ratings are measured under board mounted and free air conditions Symbol Definition VB1,2,3 VHO1,2,3 VS1,2,3 VPR VCP COM High side floating supply voltage High side floating output voltage High side offset voltage Low side supply voltage Charge pump output voltage Power ground VLO1,2,3, / FLT VIN Can/Cap EN/Frst dV/dt RthJA TJ TS TReflow Units Min. Max. -0.3 VS1,2,3 - 0.3 VB 1,2,3 - 20 -0.3 -0.3 -5 220 VB 1,2,3 + 0.3 VB 1,2,3 + 0.3 17 17 5 Low side output voltage LO#; FLT pin -0.3 VPR + 0.3 Input pin voltage (LIN#, HIN#,) Over-current comparator inputs Enable & Fault Reset inputs High side floating voltage slew rate Junction to ambient thermal resistance Maximum operating junction temperature Maximum storage temperature Reflow max. temperature (60 sec.) -0.3 -0.3 -0.3 — — VPR + 0.3 VPR + 0.3 VPR + 0.3 50 80 150 150 260 -55 — V V/ns °C/W °C Recommended Operating Conditions The Input/Output timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are referenced to VSS. The VS & COM offset rating are tested with all supplies biased at 15V differential. Symbol VB1,2,3 VHO 1,2,3 VS 1,2,3 VPR VLO1,2,3 COM VHO1,2,3 VLO1,2,3 VIN Vcan/cap VCP Definition High side floating supply voltage High side output voltage HO# High side floating supply voltage Low side supply voltage Low side output voltage LO# Power ground High side output voltage Low side output voltage Logic input voltage LIN, HIN, EN, CAp, CAn, FRST Common mode voltage on the CAN & CAP inputs Charge Pump Output Voltage Min. Max. Units VS1,2,3 +6 VS1,2,3-0.3 VS1,2,3 +19 VB1,2,3+0.3 200 17 VPR+0.3 5 VB1,2,3 VPR VPR 5 15 V (Note 1) 6 -0.3 -5 VS1,2,3 COM VSS-0.3 0 - Note 1: Logic operational for VS between COM -5V to COM +200V. Logic state held for VS of COM -5 to COM – VBS. (Please refer to the Design Tip DT97 -3 for more details). 5 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Static Electrical Characteristics Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj ≤ 125°C with bias conditions of VBIAS (VPR,VBS 1,2,3) = 15V. The VIN , VTH and IN parameters are referenced to VSS and are applicable to all six channels (HS 1,2,3 and LS 1,2,3). The VO and IO parameters are referenced to COM and VS 1,2,3 and are applicable to the respective output leads: LO1,2,3 and HO1,2,3. Symbol VIN,th+ Definition Input positive going threshold (Hin#, Lin#, EN, FRST) Min - VIN,th- Input negative going threshold (Hin#, Lin#, EN, FRST) 0,7 Typ Max Units Test Conditions 1.9 2.5 V 1 - Iin+ Input bias current (Lin#, Hin#, EN, FRST) 15 100 220 Iin- Input bias current (Lin#, Hin#, EN, FRST) -1 0 1 VPR,UVth+ VPR supply undervoltage positive going threshold (note 2) 6.4 7.2 8,2 VPR,UVth- VPR supply undervoltage negative going threshold (note 2) 6 6.7 7.6 VPR,UVhys VPR supply undervoltage hysteresis (note 2) 0.4 0.5 0.7 VBS, UVth+ VBS supply undervoltage positive going threshold 6.4 7.2 8,2 VBS, UVth- VBS supply undervoltage negative going threshold 6 6.7 7.6 VBS, UVhys VBS supply undervoltage hysteresis 0.4 0.5 0.7 ILK Offset supply leakage current - 5 50 Iqbs Quiescent VBS supply current 20 45 120 Iqpr Quiescent VPR supply current 1 2,5 5 VOH High level output voltage, VPR – VO, HO# 0,2 0.9 1.4 VOL Low level output voltage, VO, HO# 0,05 0.2 0.6 Io+ Output high short circuit pulsed current, HO#,LO# 105 200 450 210 350 650 6 13 15 15 200 500 5 7,5 15 17 17 400 1000 10 Io- Output low short circuit pulsed current, HO#,LO# VCP Charge pump output voltage Vin=5V Vin=0V V µA VB=VS=200V mA VPR=14V V Io =20mA mA mA ICP+ Charge Pump source current ICP- Charge Pump sink current 5 10 13 13 100 200 - Vcl_Vcp Vcp pin Active Clamp 17 18.6 21 VFLT FLT low output voltage - - 0.8 Ican1 Comparator input high bias current - - 7 Ican0 Comparator input low bias current - - 7 Voff Comparator input offset -33 - 33 mV Tfrst Minimum FAULT RESET time 20 - - us Minimum ENABLE time 20 - - us Ton_EN VPR=4V VPR=8V VPR=9V VPR=14V VPR=6V VPR=14V µA V Vo =0V, PW ≤10 µs Vo =15V, PW ≤10 µs Rext=100kΩ µA mA Icp=10mA V µA IFLT = 10mA Can=5V Can=0V Vcap= 5V (note 2):. UVPR is latched; when VPR>UVPR, FAULT remains pulled down. This leads to have the FAULT active and latched at VPR ramp up if no fault reset occurs. 6 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Dynamic Electrical Characteristics Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj ≤ 125°C with bias conditions of VPR = VBS = 15V, VS1,2,3 = VSS = COM, and CL = 1000 pF. Symbol Ton Toff LOtr , HOtr LOtf , HOtr TOC TFLT tblank tFILIN DT Definition Min Typ Max Units Turn-on propagation delay, LO#, HO# Turn-off propagation delay, LO#, HO# Turn-on rise time LO#, HO# Turn-off fall time LO#, HO# Over-current to output shutdown response time Over-current FLT response time Current limit blanking time Input filter time (HIN, LIN) Dead-time 350 350 10 5 5 200 420 550 850 600 850 100 300 35 75 1 1.7 0.7 1.2 6 7.5 270 510 700 1000 Test Conditions nS VIN = 0 & 5V uS V(Can)-V(Cap)=1V nS VIN = 0 & 5V VPR=15V Truth Table This table is valid for voltages ranges defined in the recommended operating conditions section. ENABLE FRST 0 CAN>CA P 0 LO#/HO# FLT 0 LIN#/HIN # X 0 Comments 0 No Change 1 0 X 0 Vss 0 0 1 X 0 Open 0 1 1 X 0 Vss 1 0 X LIN#/HIN# LO#/HO# Open 1 1 0 LIN#/HIN# 0 Vss Normal Operation: An anti-shoot-through logic prevents each channel from turning on simultaneously the HS and LS switches Over-current detection (FLT) 1* 1* 1* LIN#/HIN# * LO#/HO# * Open* * Not recommended (cycling on default) FLT keeps showing same status FLT Reset Sequence (Note3) Note 3: The proper sequence to reset the Fault latch is to first set EN at 0V and then cycle the FRST pin. The gate drives return to normal operation when EN is set again at 5V. 7 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Functional Block Diagram VCP VPR PreRegulation Control VB1 Vcc Hin1 HV level shifter Latch & Undervoltage detection Driver Deadtime & shoot-through protection HO1 VS1 Lin1 Driver Hin2 LO1 VB2 Lin2 HV level shifter Logic Hin3 Control Latch & Undervoltage detection Driver Deadtime & shoot-through protection HO2 VS2 Lin3 Driver LO2 VB3 EN HV level shifter FRST Latch & Undervoltage detection Driver Deadtime & shoot-through protection HO3 VS3 FLT Driver LO3 R Fault Q latch VSS S Over-current Blanking time + _ CAp CAn COM 8 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Input/Output Pin Equivalent Circuit Diagram 9 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Lead Definitions Symbol HIN# LIN# VSS VCP VPR LO# COM CAP CAN VS# HO# VB# EN FAULT FRST Description Input for high side gate drive – Active high Input for low side gate drive – active high Logic Ground Pre-regulated MOSFET gate output – Analog gate drive Power supply pin of the I.C (equivalent to Vcc) Low side gate driver outputs (1,2 & 3) Common low side gate drive return pin & Power Ground Non inverting input of the over-current comparator Inverting input of the over-current comparator High side floating supply return (1, 2 & 3) High side gate driver outputs (1, 2 & 3) High side floating supply (1, 2 & 3) Enable input – Active high Fault output pin – Open collector Fault Reset input pin – Active high Lead Assignments 10 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Application Information and Additional Details Input Short-Pulse / Noise Rejection Filter The inputs of this I.C are compatible with CMOS and TTL standards. The AUIRS20302S has been designed in order to also interface the 3.3V logic signals. The VIN th+ and VIN th- thresholds of the input Schmitt trigger were set to 1.9V and 1V (typical). Figure #1 shows the inner logic signal versus the input profile. Figure 1: Input Thresholds Figure 2: Input Filter A filter is then implemented just after the Schmitt trigger on every input pin. HIN & LIN feature a 270 ns filter (typical) while FRST & EN have a 50 ns one. Its principle greatly improves the input/output pulse symmetry as well as helps reject noise spikes. The behaviour of the input filters is presented in the Figure #2. The parameter tFILIN represents the minimum pulse duration to pass the filter. Logic Control Block This block centralizes all the logic signals in order to: Generate the proper Outputs drives with minimum dead-time insertion, prevent shoot-through sequences, blank premature triggering of the short-circuit comparator and reset the FAULT flag. The enable pin (EN) switches off all outputs immediately in case of an urgent system request. It actually can be used to cycle the gates. The figure #3 shows all the signals timing. Figure 3: Input/Output Timing Diagram 11 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S The AUIRS20302S features an embedded dead-time circuitry. It inserts a minimum time period in which both the high and low side switches are forced OFF. By this mean and for each leg, each power switch is fully off before the next one turns on. This dead-time is automatically inserted by the AUIRS20302S including when the command sequence does include a shorter DT. Sequences with larger dead-time are not affected by the driver. Figures #4 & 5 show the deadtime principle and timing on the outputs. The dead-times are matched not only for each leg (high side / low side matching) but also among the three legs. Figure 4: Dead-time Principle Figure 5: Output Timing (dead-time) Protection Blanking time & Fault Reset Sequence The CAN and CAP pins are intended to interface a shunt. In case of over-current protection (CAN>CAP), the FLT pin and all the gates are pulled down. There is a blanking time circuitry on the over-current protection. The comparator output is ignored for (tblank) µS after each HINx rising edge. The fault reset is achieved by the following sequence: a) force EN pin to Gnd and b) cycle the FRST pin for the recommended minimum time (tfrst). Then, pulling-up again the EN pin resumes normal operation. Figure #6 shows the fault and output sequences while figure #7 emphasizes the reset sequence. Figure 6: Fault/Output after SC Figure 7: Fault Reset Sequence Pre-regulated VPR voltage The AUIRS20302S features a pre-regulated supply in order to maintain reasonable gate voltages in all conditions. This circuitry is composed of a VCO controlled charge pump, a comparator and a protective active clamp. Those three blocks were specifically designed in order to minimize their EMI contribution to the whole system. The MOSFET gate is regulated at 15V. Depending on the MOSFET gate threshold, VPR is then stabilized at ‘’ VCP – Vt ‘’ which usually ends up between 12V and 13.5 V. A higher VPR voltage is achievable by using a logic level MOSFET. The gate voltage and the charge pump output are protected by a 17V clamp. The figure #8 presents the block diagram of the preregulator circuitry with the 100K resistor needed between the Gate and the Drain of the MOSFET. 12 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S + Bat 100k VCP Voltage Control Loop Active Clamp VCP Vcc VPR Charge Pump VCO 2.2M VCP comparator System Intelligence + Ref 1.1M Vss Figure 8: Pre-regulator Block Diagram During the power-up sequence, the gate is biased thanks to the 100k resistor connected to its drain. When Vbat exceeds 4V, the charge pump output is already close to the MOSFET gate threshold. At 6V, VCP is typically higher than 9V (see VCP values – page 5 – Static Electrical Characteristics). So, during Vbat ramp-up, the MOSFET is first biased by the resistor until the charge pump overcomes the gate voltage and turns it fully on. As Vbat keeps increasing, the MOSFET remains fully on until the voltage closed loop enters the linear mode to control and stabilize VCP at 15V. Pre-regulator MOSFET drive The stabilized VPR voltage supplies the I.C and the bootstrap diodes thus the MOSFET power dissipation is quite low. It can also supply the system components. In that case, the power MOSFET dissipation has to be evaluated carefully and the implementation of an extra heat-sink considered. In some applications, it may be necessary to know at what exact voltage the charge pump overcomes the resistive bias of the pre-regulator MOSFET. This voltage depends on the total MOSEFT drain current (Iqpr + system consumption). For example, the system intelligence may include a regulator whose voltage drop influences the minimum operation voltage. If we consider the voltage drop of a 5V regulator at 0.8V, what is the status of the pre-regulator MOSFET when Vbat passes 5,8V (already fully on or still in the source follower mode)? Figure #9 summarizes the procedure to evaluate the exact Vbat voltage at which the pre-regulator MOSFET is turned fully on by the charge pump. It is a 4 steps procedure where ‘’ I load ‘’ represents the quiescent current of the I.C plus the system consumption (in the voltage range considered). Looking to the MOSFET characteristic at the specific ‘’ I load ‘’ drain current point gives the corresponding Vgs value. The MOSFET will be fully on when the VCP pin exceeds this Vgs value. The charge pump characterization is then used to determine the exact VPR voltage at which the quantity ‘’VCP-VPR’’ exactly equals the identified Vgs. Finally, from the VPR value, the corresponding VCP voltage 13 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S is extracted again from the charge pump characterization. At this point of operation, the VCP voltage equals the Vbat potential at which the MOSFET becomes fully on (no voltage drop across the biasing resistor in this mode). Figure 9: The 4 Step Procedure PCB recommendations The PCB is designed in order to minimize the gate drive wires, make the power topology up to 15A continuous capable and have the shunt interface as short as possible. Also, ground star connection is located at the bottom of the shunt. Figure 10: Component Face Layout 14 www.irf.com © 2014 International Rectifier Figure 11: Solder Face Layout Submit Datasheet Feedback May 28, 2014 AUIRS20302S The following schematic is an example of the AUIRS20302S application. It is a 100W-24V BLDC motor drive for an actuator. The power MOSFETs and the pre-regulator are designed in order to pass the 60V truck load dump condition. The system intelligence is powered via a 5V regulator connected to the VPR pin. 3 4 5 6 7 8 External drive 1 2 J8P1 Tp5 on 100k R2 100k R3 100k R4 100k R5 100k R6 100k R7 100k D1 D2 D3 BAV21 BAV21 BAV21 R10 R11 R12 R13 10k 10 10 10 Ld1 C1 Bt2 470n 1 Vcc5V CompPWM 3 1 0 R1 1 Tp4 1 Tp3 2 ENABLE 2 Bt1 1 1 0 3 Vcc5V 2 Sw1 Forward R8 1k Tp6 Vcc Hall Sensor R14 R15 logicCPLD R16 R17 Vcc 4k7 4k7 A 1 B B Hlv Hall C C C Hlw R18 1k R19 1k R20 1k 1 2 3 4 R21 1k R22 1k R23 1k 5 6 7 8 9 10 LIv Tp2 D M1 IRFS3607 F R26 10k 1 10k R27 HIN1 HIN2 HIN3 Masse Logic VB1 HO1 VS1 LIN1 LIN2 LIN3 VB2 HO2 VS2 VSS VCP VPR VB3 HO3 VS3 LO1 LO2 LO3 CAp CAn nc COM 28 27 Tp8 1 C2 26 25 24 HO1 23 22 21 HO2 20 19 18 HO3 U 1 V 1 Tp10 100n C4 R28 17 16 100n W 22k Vcc5V R29 15 1k2 IRS20302S 0 0 100k Tp9 100n C3 2.2u CPLD 0 FRST FLT EN C5 10k Tp1 14 Vss R25 Frequency 20Khz 11 12 13 LO1 LO2 LO3 LIw P R24 ComS U1 0 1 MC7805CD GND 1 LIu PWM Tp7 1 U2 0 1k Hlu A Hall B Gnd Hall Sensor 6k8 0 4k7 Hall A R9 Vcc5V Vcc5V OUT IN 3 Vcc5V C7 2 C6 100n 100n 0 Vbusp Tp11 C10100n/100V C9 100n/100V C8 100n/100V Tp15 Tp13 HO1 0 M4 R34 R38 0 HO3 1 HO2 M6 0 0 R39 R35 R31 IRFS3607 IRFS3607 IRFS3607 100k 100k 100k 0 1 0 1 M2 R30 Power Supply D4 Phase U V Phase V W 0 R36 LO1 0 R40 Phase W LO2 LO3 IRFS3607 IRFS3607 IRFS3607 100k R41 R37 R33 0 1 R32 M7 M5 M3 470µF /63V 1 1 U Tp16 + SMCJ54A Tp14 Tp12 Cp1 1 2 24V to 60V 100k 100k ComS R42 2k2 R43 Shunt C11 Modif.: R30; R32; R34; R36; R38; R40 =0 1n Title AUIRS20302SDemoboard GND Size A3 0 Date: Document Number Thursday , May 06, 2010 Rev Sheet 1 of 1 Figure 12: 100W – 24V BLDC Application Schematic 15 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Figure 13: Component Implementation 16 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Parameter Temperature Trends Figures illustrated in this chapter provide information on the experimental performance of the AUIRS20302S HVIC. The line plotted in each figure is generated from actual lab data. A large number of individual samples were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) with supply voltage of 15V in order to generate the experimental curve. The line consists of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood trend. The individual data points on the Typ. curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). Figure 14. Turn-On Propagation Delay vs. Temperature Figure 15. Turn-Off Propagation Delay vs. Temperature Figure 16. Turn-On Rise Time vs. Temperature Figure 17. Turn-Off Fall Time vs. Temperature 17 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Figure 18. Input Filter Time vs. Temperature Figure 19. Current Limit Blanking Time vs. Temperature Figure 20. Over Current Response Time vs. Temperature Figure 21. Over Current Shutdown Time vs. Temperature 18 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Figure 22. Dead Time vs. Temperature Figure 23. Offset Leakage Current vs. Temperature Figure 24. Quiescent VPR Current vs. Temperature Figure 25. Quiescent VBS Current vs. Temperature 19 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Figure 26. Output High Pulse Current vs. Temperature Figure 27. Output Low Pulse Current vs. Temperature Figure 28. Charge Pump Source Current vs. Temperature VPR = 6V Figure 29. Charge Pump Source Current vs. Temperature VPR = 14V Figure 30. Comparator Input High Current vs. Temperature Figure 31. Comparator Input Low Current vs. Temperature 20 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Figure 32. VPR UV+ Going Threshold vs. Temperature Figure 33. VPR UV- Going Threshold vs. Temperature Figure 34. VBS UV+ Going Threshold vs. Temperature Figure 35. VBS UV- Going Threshold vs. Temperature 21 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Figure 36. High Level Output Voltage vs. Temperature Io = 20mA Figure 37. Low Level Output Voltage vs. Temperature Io = 20mA Figure 38. FLT Low Output Voltage vs. Temperature Figure 39. Charge Pump Output Voltage vs. Temperature VPR = 4V Figure 40. Charge Pump Output Voltage vs. Temperature VPR = 8V Figure 41. Charge Pump Output Voltage vs. Temperature VPR = 14V 22 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Package Details: 23 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Tape and Reel Information 24 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S 25 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S Part Marking Information AUIRS20302S Part number AYWW ? Date code Pin 1 Identifier IR logo ? XXXX ? MARKING CODE P Lead Free Released Lot Code (Prod mode – 4 digit SPN code) Assembly site code Per SCOP 200-002 Non-Lead Free Released Ordering Information Standard Pack Base Part Number AUIRS20302S 26 www.irf.com Package Type SOIC28W Complete Part Number Form Quantity Tube/Bulk 25 AUIRS20302S Tape and Reel 1000 AUIRS20302STR © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S IMPORTANT NOTICE Unless specifically designated for the automotive market, International Rectifier Corporation and its subsidiaries (IR) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or services without notice. Part numbers designated with the “AU” prefix follow automotive industry and / or customer specific requirements with regards to product discontinuance and process change notification. All products are sold subject to IR’s terms and conditions of sale supplied at the time of order acknowledgment. IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with IR’s standard warranty. Testing and other quality control techniques are used to the extent IR deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. IR assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using IR components. To minimize the risks with customer products and applications, customers should provide adequate design and operating safeguards. Reproduction of IR information in IR data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. 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Should Buyer purchase or use IR products for any such unintended or unauthorized application, Buyer shall indemnify and hold International Rectifier and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that IR was negligent regarding the design or manufacture of the product. Only products certified as military grade by the Defense Logistics Agency (DLA) of the US Department of Defense, are designed and manufactured to meet DLA military specifications required by certain military, aerospace or other applications. Buyers acknowledge and agree that any use of IR products not certified by DLA as military-grade, in applications requiring military grade products, is solely at the Buyer’s own risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. IR products are neither designed nor intended for use in automotive applications or environments unless the specific IR products are designated by IR as compliant with ISO/TS 16949 requirements and bear a part number including the designation “AU”. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, IR will not be responsible for any failure to meet such requirements. 27 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 AUIRS20302S For technical support, please contact IR’s Technical Assistance Center http://www.irf.com/technical-info/ WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245 Tel: (310) 252-7105 Revision History Date Comment DR2 format and revision (Preliminary) Note 2 at page 5 modified (“UVPR is latched”) and moved under st el char table. Added AU qualified, Leadfree, RoSH; revised Qualification level table; added tri-temp graphs; August 31, 2011 modified part marking graph; revise Notice page to the latest version. Abs Max Rat: COM limits set to -5V..5V; Max Oper Junc temp=150^C; static El Char: Voffset min=th Sep 13 , 2011 33mV. Fig4 and Fig5 and Fig6 change. th Sep 14 , 2011 Added AU qualified, leadfree RoSH; removed preliminary; revised DT condition VPR=15V nd May 2 , 2014 Update ESD protection scheme on page 9, pins CAn and CAp Nov 20th, 2010 March 14th 2011 28 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014