Automotive Grade
AUIRS2184(4)S
HALF-BRIDGE DRIVER
Features
Product Summary
Floating channel designed for bootstrap operation
Fully operational to + 600 V
Tolerant to negative transient voltage, dV/dt
immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for both channels
3.3 V and 5 V input logic compatible
Matched propagation delay for both channels
Logic and power ground +/- 5 V offset
Lower di/dt gate driver for better noise immunity
Output source/sink current capability
(typical) 1.9 A/2.3 A
Lead free, RoHS compliant
Automotive Qualified*
Topology
Half-Bridge
VOFFSET
600 V
10 V – 20 V
VOUT
Io+ & I o- (typical)
1.9 A & 2.3 A
ton & toff (typical)
600 ns & 230 ns
400 ns (RDT = 0 Ω)
Deadtime (typical)
5 µs (RDT = 200 kΩ)
Package Options
Typical Applications
DC/DC converter
pump and compressor
piezo injection
Starter/ alternator
8-Lead SOIC
AUIRS2184S
14-Lead SOIC
Narrow Body
AUIRS21844S
Typical Connection
Up to 600 V
Vcc
VB
Vcc
IN
SD
IN
HO
SD
COM
VS
LO
TO
LOAD
AUIRS2184
Up to 600 V
AUIRS21844
Vcc
IN
SD
Vcc
IN
SD
HO
VB
VS
TO
LOAD
DT
(Refer to Lead Assignments for correct pin
configuration). This/These diagram(s) show
electrical connections only. Please refer to our
Application Notes and Design Tips for proper
circuit board layout.
1
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Vss
RDT
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Vss
COM
LO
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AUIRS2184(4)S
Table of Contents
Page
Description
3
Feature Comparison
3
Qualification Information
4
Absolute Maximum Ratings
5
Recommended Operating Conditions
6
Dynamic Electrical Characteristics
6
Static Electrical Characteristics
7
Functional Block Diagram
8
Input/Output Pin Equivalent Circuit Diagram
9-10
Lead Definitions
11
Lead Assignments
11
Application Information and Additional Details
12
Parameter Temperature Trends
13-17
Package Details
18
Tape and Reel Details
19-20
Part Marking Information
21
Ordering Information
22
Important Notice
23
2
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AUIRS2184(4)S
Description
The AUIRS2184(4)S are high voltage, high speed power MOSFET and IGBT drivers with dependent high
and low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output,
down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver
cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the
high-side configuration which operates up to 600 V.
Feature Comparison: AUIRS2181(4)/AUIRS2183(4)/AUIRS2184(4)
Part
2181
21814
2183
21834
2184
21844
3
Input
Logic
CrossConduction
Prevention
logic
HIN/LIN
no
HIN/LIN
yes
IN/SD
yes
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Dead-Time
none
Internal 500ns
Programmable 0.4 – 5 us
Internal 500ns
Programmable 0.4 – 5 us
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Ground
Pins
COM
VSS/COM
COM
VSS/COM
COM
VSS/COM
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Ton/Toff
160/200 ns
160/200 ns
600/230 ns
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AUIRS2184(4)S
Qualification Information
†
Automotive
(per AEC-Q100)
Comments: This family of ICs has passed an
Automotive qualification. IR’s Industrial and Consumer
qualification level is granted by extension of the higher
Automotive level.
Qualification Level
SOIC8
Moisture Sensitivity Level
SOIC14N
Machine Model
Human Body Model
ESD
Charged Device Model
IC Latch-Up Test
RoHS Compliant
†
††
†††
MSL3†† 260°C
(per IPC/JEDEC J-STD-020)
Class M1 (Pass +/-100V)
(per AEC-Q100-003)
Class H1C (Pass +/-1500V)
(per AEC-Q100-002)
Class C4 (Pass +/-1000V)
(per AEC-Q100-011)
Class II, Level A†††
(per AEC-Q100-004)
Yes
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
IN, SD, DT Class II Level B at 40mA per JESD78.
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AUIRS2184(4)S
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to COM lead. Stresses beyond those listed under "
Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only; and
functional operation of the device at these or any other condition beyond those indicated in the
“Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise
specified.
Symbol
Definition
Min
Max
Units
VB
High-side floating absolute voltage
-0.3
620
VS
High-side floating supply offset voltage
VB - 25
VB + 0.3
VHO
High-side floating output voltage
VS - 0.3
VB + 0.3
VCC
Low-side and logic fixed supply voltage
-0.3
VLO
Low-side output voltage
-0.3
20
VCC + 0.3
DT
Programmable deadtime pin voltage
VSS -0.3
VCC + 0.3
VIN
Logic input voltage (IN & SD )
Logic ground
VSS -0.3
VCC + 0.3
VCC - 20
VCC + 0.3
—
50
(8-lead SOIC)
—
0.625
(14-lead SOIC)
—
1.0
(8-lead SOIC)
—
200
(14-lead SOIC)
—
120
VSS
†
dVS/dt
Allowable offset supply voltage transient
PD
Package power dissipation @ TA ≤ 25°C
RthJA
Thermal resistance, junction to ambient
†
V
V/ns
W
°C/W
TJ
Junction temperature
—
150
TS
Storage temperature
-50
150
°C
TL
Lead temperature (soldering, 10 seconds)
—
300
All supplies are fully tested at 25 V and an internal 20 V clamp exists for each supply.
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AUIRS2184(4)S
Recommended Operating Conditions
The input/output logic timing diagram is shown in Figure 1. For proper operation the device should be used
within the recommended conditions. The VS and VSS offset rating are tested with all supplies biased at a 15 V
differential.
Symbol
Definition
Min
Max
Units
VB
High-side floating supply absolute voltage
VS + 10
VS + 20
VS
High-side floating supply offset voltage
(††)
600
VHO
High-side floating output voltage
VS
VB
VCC
Low-side and logic fixed supply voltage
10
20
V
VLO
Low-side output voltage
0
VCC
†††)
VIN
VSS
VCC
Logic input voltage (IN & SD ) (
DT
Programmable deadtime pin voltage
VSS
VCC
VSS
Logic ground
-5
5
TA
Ambient temperature
-40
125
°C
†† Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to –VBS. (Please refer to Design
Tip DT97-3 for more details).
††† HIN and LIN are internally clamped with a 5.2 V zener diode.
Dynamic Electrical Characteristics
Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj
≤ 125°C with bias conditions of VBIAS (VCC, VBS) = 15 V, VSS = COM, CL = 1000 pF.
Symbol
ton
toff
tsd
MTon
MToff
tr
tf
DT
MDT
6
Definition
Turn-on propagation delay
Turn-off propagation delay
Shut-down propagation delay
Delay matching, HS & LS turn-on
Delay matching , HS & LS turn-off
Turn-on rise time
Turn-off fall time
Deadtime: LO turn-off to HO turn-on (DTLO-HO) &
HO turn-off to LO turn-on (DTHO-LO)
Deadtime matching DTLO-HO - DTHO-LO
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Min
—
—
—
—
—
—
—
280
3.9
—
—
Typ
600
230
220
3
15
15
12
375
5
0
0
Max Units Test Conditions
900
VS = 0 V
400
VS = 0 V or 600 V
350
90
ns
40
60
VS = 0 V
35
520
RDT = 0 Ω
6
µs
RDT = 200 kΩ
50
RDT = 0 Ω
ns
600
RDT = 200 kΩ
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AUIRS2184(4)S
Static Electrical Characteristics
Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj
≤ 125°C with bias conditions of VBIAS (VCC, VBS) = 15 V, VSS = COM. The VIL, VIH and IIN parameters are
referenced to VSS/COM and are applicable to the respective input leads: IN and SD . The VO, IO and Ron
parameters are referenced to COM and are applicable to the respective output leads: HO and LO.
Symbol
VIH
VIL
VSD,TH+
VSD,THVOH
VOL
ILK
IQBS
IQCC
IIN+
IINVCCUV+
VBSUV+
VCCUVVBSUVVCCUVH
VBSUVH
IO25+ (
IO25-(
IO+ (
IO-(
†)
†)
†) (††)
†) (††)
Definition
Logic “1” input voltage for HO & logic “0” for LO
Logic “0” input voltage for HO & logic “1” for LO
SD input positive going threshold
SD input negative going threshold
High level output voltage, VBIAS - VO
Low level output voltage, VO
Offset supply leakage current
Quiescent VBS supply current
Quiescent VCC supply current
Logic “1” input bias current
Logic “0” input bias current
VCC and VBS supply undervoltage positive going
threshold
VCC and VBS supply undervoltage negative going
threshold
Min Typ Max
2.5 —
—
—
— 0.8
2.5 —
—
—
— 0.8
—
— 1.5
—
— 0.2
—
— 50
10 50 130
0.4 1.0 1.3
— 25 60
—
— 5.0
Units Test Conditions
VCC = 10 V to 20 V
V
µA
mA
µA
IO = 0 A
IO = 20 mA
VB = VS = 600 V
VIN = 0 V or 5 V
IN = 5 V, SD = 0 V
IN = 0 V, SD = 5 V
8.0
8.9
9.8
7.4
8.2
9.0
Hysteresis
0.3
0.7
—
Output high short circuit pulsed current
1.4
1.9
—
VO = 0V,
PW ≤ 10us,
TJ = 25°C
Output low short circuit pulsed current
1.8
2.3
—
VO = 15V,
PW ≤ 10us,
TJ = 25°C
Output high short circuit pulsed current
1.2
—
—
Output low short circuit pulsed current
1.5
—
—
V
A
VO = 0 V,
PW ≤ 10 µs
VO = 15 V,
PW ≤ 10 µs
(†) Guaranteed by design
(††) IO+ and IO- decrease with rising temperature
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AUIRS2184(4)S
Functional Block Diagram: AUIRS2184, AUIRS21844
VB
UV
DETECT
AUIRS2184
R
HV
LEVEL
SHIFTER
VSS/ COM
LEVEL
SHIFT
IN
HO
Q
R
PULSE
FILTER
S
PULSE
GENERATOR
VS
VCC
DEADTIME
UV
DETECT
LO
+5V
VSS/ COM
LEVEL
SHIFT
SD
DELAY
COM
VB
UV
DETECT
AUIRS21844
R
HV
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFT
IN
R
PULSE
FILTER
Q
HO
S
PULSE
GENERATOR
VS
VCC
DEADTIME
DT
UV
DETECT
LO
+5 V
VSS/COM
LEVEL
SHIFT
SD
DELAY
COM
VSS
8
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AUIRS2184(4)S
Input/Output Pin Equivalent Circuit Diagrams: AUIRS2184S
VB
ESD
Diode
20V
HO
VCC
ESD
Diode
+5V
RPU
ESD
Diode
VS
600V
SD
RESD
ESD
Diode
VCC
ESD
Diode
VSS
LO
20V
ESD
Diode
COM/VSS
VCC
VCC
ESD
Diode
ESD
Diode
DT
IN
RESD
RPD
VSS
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RESD
ESD
Diode
RDT(internal)
ESD
Diode
VSS
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AUIRS2184(4)S
Input/Output Pin Equivalent Circuit Diagrams: AUIRS21844S
VB
ESD
Diode
20V
HO
VCC
ESD
Diode
+5V
RPU
ESD
Diode
VS
600V
SD
RESD
VCC
ESD
Diode
ESD
Diode
LO
VSS
20V
20V
ESD
Diode
COM
VSS
VCC
VCC
ESD
Diode
ESD
Diode
DT
IN
RESD
RPD
VSS
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RESD
ESD
Diode
RDT(internal)
ESD
Diode
VSS
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AUIRS2184(4)S
Lead Definitions
Symbol
IN
SD
DT
VSS
VB
HO
VS
VCC
LO
COM
Description
Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO
(referenced to COM for AUIRS2184 and VSS for AUIRS21844)
Logic input for shutdown (referenced to COM for AUIRS2184 and VSS for AUIRS21844)
Programmable deadtime lead, referenced to VSS (AUIRS21844 only)
Logic ground (AUIRS21844 only)
High-side floating supply
High-side gate drive output
High-side floating supply return
Low-side and logic fixed supply
Low-side gate drive output
Low-side return
Lead Assignments: AUIRS2184(4)S
1
IN
VB
8
2
SD
HO
7
3
COM
VS
6
4
LO
VCC
5
1
IN
2
SD
VB
13
3
VSS
HO
12
4
DT
VS
11
5
COM
10
6
LO
9
7
VCC
8
8-Lead SOIC
14
14-Lead SOIC
Narrow Body
AUIRS2184(S)
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AUIRS21844(S)
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AUIRS2184(4)S
Application Information and Additional Details
IN (LO)
50%
IN
50%
IN (HO)
SD
tr
ton
toff
tf
90%
90%
HO
LO
HO
LO
Figure 1: Input/Output Timing Diagram
10%
10%
Figure 2: Switching Time Waveform Definitions
50%
50%
IN
90%
SD
50%
HO
DTLO-HO
10%
DTHO-LO
90%
LO
tsd
90%
HO
LO
10%
MDT =
Figure 3: Shutdown Waveform Definitions
DTLO-HO
DTHO-LO
Figure 4: Deadtime Waveform Definitions
IN (LO)
50%
50%
IN (HO)
LO
HO
10%
MT
MT
90%
LO
HO
Figure 5: Delay Matching Waveform Definitions
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AUIRS2184(4)S
Tolerability to Negative VS Transients
The AUIRS21844S has been seen to withstand negative VS transient conditions on the
order of -20V for a period of 400 ns.
An illustration of the AUIRS21844S performance can be seen in Figure 7, where points
above the lines represent pulses that the circuit can withstand (with VCC=VBS= 15V).
Two curves are present in figure 7: one refers to ambient temperature TA=25 °C, the other
refers to tests performed at TA=-40 °C, 25 °C and 125 °C.
Even though the AUIRS21844S has been shown able to handle these negative VS transient
conditions, it is highly recommended that the circuit designer always limit the negative VS
transients as much as possible by careful PCB layout and component use.
Figure 7: -Vs Transient results
13
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AUIRS2184(4)S
Parameter Trends vs. Temperature and vs. Supply Voltage
Figures of this chapter provide information on the experimental performance of the AUIRS2184(4)S HVIC.
The line plotted in each figure is generated from actual lab data.
A large number of individual samples were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order
to generate the experimental curve. The line consists of three data points (one data point at each of the
tested temperatures) that have been connected together to illustrate the understood trend. The individual
data points on the Typ. curve were determined by calculating the averaged experimental value of the
parameter (for a given temperature).
Turn-on Propagation Delay (ns)
Turn-on Propagation Delay (ns)
A different set of individual samples was used to generate curves of parameter trends vs. supply voltage.
700
650
M ax.
600
Typ.
M in.
550
500
-50
-25
0
25
50
75
100
1400
1200
M ax.
1000
125
800
T yp.
600
400
10
12
300
250
M ax.
Typ.
M in.
150
-25
0
25
50
75
100
125
Temperature (oC)
Figure 7A. Turn-off Propagation Delay vs.
Temperature
14
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18
20
Figure 6B. Turn-on Propagation Delay vs.
Figure6B. Turn-on
Propagation
Supply
Voltage Delay
vs. Supply Voltage
Turn-off Propagation Delay (ns)
Turn-off Propagation Delay (ns)
350
-50
16
Supply Voltage (V)
Temperature (oC)
Figure 6A. Turn-on Propagation Delay vs.
Temperature
200
14
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600
500
400
300
M ax.
T yp.
200
100
0
10
12
14
16
18
20
Supply Voltage (V)
Figure
7B.
Turn-off
Propagation
Delay
vs.
Figure
7B.
Turn-off
Propagation
Delay
vs.
Figure
7B.
Turn-off
Propagation
Delay
Supply
Voltage
Supply Voltage vs.
Supply
Voltage
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AUIRS2184(4)S
SD Propagation Delay (ns)
SD Propagation Delay (ns)
350
300
250
M ax.
200
Typ.
M in.
150
-50
-25
0
25
50
75
100
500
400
M ax.
300
T yp.
200
100
0
125
10
Temperature (oC)
12
14
16
18
20
Supply Voltage (V)
Figure 8A. SD Propagation Delay vs. Temperature
Figure 8B. SD Propagation Delay vs. Supply
Voltage
80
16
Turn-off Fall Time (ns)
Turn-Off fall Time (ns) -
18
M ax.
14
Typ.
12
10
M in.
8
6
60
Max.
40
Typ.
20
0
4
-50
-25
0
25
50
75
100
10
125
12
Temperature ( C)
16
18
20
Figure 10B. Turn-off Fall Time vs. Supply
Voltage
Figure 9A. Turn-off Fall Time vs. Temperature
7
20
6
18
Deadtime (us)
Turn-On Rise Time (ns)
14
Supply Voltage (V)
o
M ax.
16
Typ.
14
M in.
12
5
4
3
2
1
10
0
-50
-25
0
25
50
75
100
125
Temperature (oC)
Figure 10. Turn-on Rise Time vs. Temperature
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0
50
100
150
200
RDT (KW)
Figure 11. Deadtime vs RDT
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AUIRS2184(4)S
450
1100
M ax.
900
Deaduime (ns)
Typ.
M in.
350
300
700
Max.
500
Typ.
Min.
300
250
100
-50
-25
0
25
50
75
100
125
10
12
14
Temperature (oC)
M ax.
Low Level Output (mV)
High Level Output (V)
20
140
1.5
Typ.
1.0
M in.
0.5
120
100
M ax.
Typ.
80
M in.
0.0
60
-50
-25
0
25
50
75
100
-50
125
-25
0
Figure 13. High Level Output vs. Temperature
(IO = 0 mA)
Quiescent VBS Supply Current (uA)
30
M ax.
10
Typ.
0
-25
0
25
50
75
100
125
Temperature (oC)
Figure 15. Offset Supply Leakage Current vs.
Temperature
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75
100
125
Figure 14. Low Level Output vs. Temperature
40
-50
50
Temperature ( C)
Temperature ( C)
M in.
25
o
o
16
18
Figure 12B. Deadtim e vs. Supply Voltage
2.0
20
16
Supply Voltage (v)
Figure 12A. Deadtime vs Temperature
Offset Supply Leakage Current (uA)
Deadtime (ns)
400
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120
100
80
M ax.
60
Typ.
40
M in.
20
-50
-25
0
25
50
75
100
125
Temperature (oC)
Figure 16. VBS Supply Current vs. Temperature
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1100
VCC Supply Current (uA)
Quiescent VCC Supply Current (uA)
AUIRS2184(4)S
M ax.
1050
Typ.
1000
M in.
950
500
400
300
Max.
200
Typ.
100
Min.
0
900
-50
-25
0
25
50
75
100
10
125
12
14
18
20
VCC Supply Voltage (V)
Temperature (oC)
Figure 17A. Vcc Supply Current vs. Temperature
Figure 17B. VCC Supply Current vs. VCC Supply
Voltage (V)
40
0.00
Logic "0" Input Bias Current (uA).
Logic "1" Input Bias Current (uA)
16
30
M ax.
20
Typ.
M in.
10
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
-0.02
M ax.
-0.04
Typ.
M in.
-0.06
-0.08
-0.10
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Figure 18. Logic “1” Input Bias Current vs. Temperature
VCC and VBS UV- Threshold (V)
VCC and VBS UV+ Threshold (V)
10.0
9.5
M ax.
9.0
Typ.
8.5
M in.
8.0
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Figure 20. VCC and VBS Undervoltage Threshold (+) vs.
Temperature
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Figure 19. Logic “0” Input Bias Current vs.
Temperature
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9.0
8.5
M ax
.
8.0 Typ.
M in.
7.5
7.0
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Figure 21. VCC and VBS Undervoltage Threshold (-) vs.
Temperature
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AUIRS2184(4)S
5
Output Source Current (A)
Output Source Current (A)
5
4
3
Typ.
2
Min
.
1
4
3
2
Typ.
1
Min.
0
0
-50
-25
0
25
50
75
100
10
125
12
14
16
18
20
Temperature (°C)
Supply Voltage (V)
Figure 22. Output Source Current (A) vs. Temperature
Figure 22A. Output Source Current (A) vs. Supply
vs. Supply Voltage
Voltage (V)
Figure 25B. Output Source Current
5
Output Sink Current (A)
Output Sink Current (A)
5.0
4.0
3.0
Typ.
2.0
Min.
4
3
2
Typ.
1
Min.
0
1.0
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 23. Output Sink Current (A) vs. Temperature
10
12
14
16
18
20
Supply Voltage (V)
Figure 23A. Output Sink Current (A) vs. Supply
Figure 26B.
Output(V)
Sink Current
Voltage
vs. Supply Voltage
18
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AUIRS2184(4)S
Package Details: SOIC8
Package Details: SOIC14N
19
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AUIRS2184(4)S
Tape and Reel Details: SOIC8
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 8SOICN
Metric
Imperial
Code
Min
Max
Min
Max
A
7.90
8.10
0.311
0.318
B
3.90
4.10
0.153
0.161
C
11.70
12.30
0.46
0.484
D
5.45
5.55
0.214
0.218
E
6.30
6.50
0.248
0.255
F
5.10
5.30
0.200
0.208
G
1.50
n/a
0.059
n/a
H
1.50
1.60
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Code
Min
Max
A
329.60
330.25
B
20.95
21.45
C
12.80
13.20
D
1.95
2.45
E
98.00
102.00
F
n/a
18.40
G
14.50
17.10
H
12.40
14.40
20
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Imperial
Min
Max
12.976
13.001
0.824
0.844
0.503
0.519
0.767
0.096
3.858
4.015
n/a
0.724
0.570
0.673
0.488
0.566
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July 22, 2014
AUIRS2184(4)S
Tape and Reel Details: SOIC14N
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 14SOICN
Metric
Imperial
Code
Min
Max
Min
Max
A
7.90
8.10
0.311
0.318
B
3.90
4.10
0.153
0.161
C
15.70
16.30
0.618
0.641
D
7.40
7.60
0.291
0.299
E
6.40
6.60
0.252
0.260
F
9.40
9.60
0.370
0.378
G
1.50
n/a
0.059
n/a
H
1.50
1.60
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 14SOICN
Metric
Imperial
Code
Min
Max
Min
Max
A
329.60
330.25
12.976
13.001
B
20.95
21.45
0.824
0.844
C
12.80
13.20
0.503
0.519
D
1.95
2.45
0.767
0.096
E
98.00
102.00
3.858
4.015
F
n/a
22.40
n/a
0.881
G
18.50
21.10
0.728
0.830
H
16.40
18.40
0.645
0.724
21
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AUIRS2184(4)S
Part Marking Information
SOIC8:
Part number
AS2184
Date code
AYWW ?
Pin 1
Identifier
IR logo
? XXXX
?
MARKING CODE
P
Lead Free Released
Lot Code
(Prod mode –
4 digit SPN code)
Assembly site code
Per SCOP 200-002
Non-Lead Free Released
SOIC14N:
AUIRS21844S
Part number
AYWW ?
Date code
Pin 1
Identifier
? XXXX
?
MARKING CODE
P
Lead Free Released
Non-Lead Free Released
22
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IR logo
© 2014 International Rectifier
Lot Code
(Prod mode –
4 digit SPN code)
Assembly site code
Per SCOP 200-002
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July 22, 2014
AUIRS2184(4)S
Ordering Information
Standard Pack
Base Part Number
AUIRS2184S
AUIRS21844S
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Package Type
Complete Part Number
Form
Quantity
Tube/Bulk
55
AUIRS2184S
Tape and Reel
2500
AUIRS2184STR
Tube/Bulk
55
AUIRS21844S
Tape and Reel
2500
AUIRS21844STR
SOIC8
SOIC14N
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July 22, 2014
AUIRS2184(4)S
IMPORTANT NOTICE
Unless specifically designated for the automotive market, International Rectifier Corporation and its subsidiaries
(IR) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its
products and services at any time and to discontinue any product or services without notice. Part numbers
designated with the “AU” prefix follow automotive industry and / or customer specific requirements with regards
to product discontinuance and process change notification. All products are sold subject to IR’s terms and
conditions of sale supplied at the time of order acknowledgment.
IR warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with IR’s standard warranty. Testing and other quality control techniques are used to the extent IR
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
IR assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using IR components. To minimize the risks with customer products and
applications, customers should provide adequate design and operating safeguards.
Reproduction of IR information in IR data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of
this information with alterations is an unfair and deceptive business practice. IR is not responsible or liable for
such altered documentation. Information of third parties may be subject to additional restrictions.
Resale of IR products or serviced with statements different from or beyond the parameters stated by IR for that
product or service voids all express and any implied warranties for the associated IR product or service and is an
unfair and deceptive business practice. IR is not responsible or liable for any such statements.
IR products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or in other applications intended to support or sustain life, or in any other application in
which the failure of the IR product could create a situation where personal injury or death may occur. Should
Buyer purchase or use IR products for any such unintended or unauthorized application, Buyer shall indemnify
and hold International Rectifier and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if
such claim alleges that IR was negligent regarding the design or manufacture of the product.
IR products are neither designed nor intended for use in military/aerospace applications or environments unless
the IR products are specifically designated by IR as military-grade or “enhanced plastic.” Only products
designated by IR as military-grade meet military specifications. Buyers acknowledge and agree that any such
use of IR products which IR has not designated as military-grade is solely at the Buyer’s risk, and that they are
solely responsible for compliance with all legal and regulatory requirements in connection with such use.
IR products are neither designed nor intended for use in automotive applications or environments unless the
specific IR products are designated by IR as compliant with ISO/TS 16949 requirements and bear a part number
including the designation “AU”. Buyers acknowledge and agree that, if they use any non-designated products in
automotive applications, IR will not be responsible for any failure to meet such requirements.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
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AUIRS2184(4)S
Revision History
Date
Comment
04/29/08
5/6/08
Draft
Converted to automotive format
Corrected various formatting issues and typos (e.g. /SD)
5/13/08
Corrected typical application dwg
In
5/16/08
Inserted figures 1-5
5/22/08
Added graphs for parameter temperature trends
5/26/08
Added missing graphs, added note on PbF and auto qualification on features list
5/28/08
Added date
9/30/08 F Reviewed and updated various missing information
10/01/08 IIn Inserted Input/Output Pin Equivalent Circuit Diagram
th
Feb13 , 2009 Typ application changes
6/04/09 Up Updated package information, qualification information, and tri-temp waveforms
Updated qualification information; graphs 27-42 changed 2181(4) to 2184(4)
8/4/09
Removed characterization graphs 27-42.
8/6/09
Updated package type and marking info
8/11/09
Corrected chapter with Parameter Trends
SD max propagation delay changed from 270ns to 300ns
9/15/09
Turn on rise time typ value changed from 40nsec to 20nsec
Rearranged temperature characteristic graphs and added actual part number on marking
9/19/09
drawings
9/21/09
Added ESD passing voltages, updated table of contents.
Typ application section updated
9/22/09
Added note 1 for Vcc under Abs Max rating
9/23/09
Front page: changed ton/toff typ. to 600ns/230ns, Page6: changed Ton typ.=600ns; toff
typ.=230ns; tsd typ.=220ns, max=350ns; MTon typ.=3ns; MToff typ.=15ns; tr typ=15ns; tf
12/17/09
typ=12ns, DT (RDT@200Kohms) min=3.9uS; DT (0-ohm) typ=375ns; VOH max.=1.5V; iqbs
min.=10uA, typ=50uA, max=130uA; Iqcc max.=1.3mA; added Important Notice page
Corrected MSL level on qual info page to MSL3 and updated MM ESD passing voltage to
12/22/09
+/-100V instead of +/-150V.
Updated disclaimer under Abs. Max. Rating
02/24/2010
Page 6: Added IO25+ and IO25- specification and the note
Jul. 27, 2010
clamp diode values changed from 25V into 20V (in-out pin eq. circ. diagrams)
th
Aug 29 , 2011 AUIRS2184 Functional Block diagram: COM no more shorted to Vss.
nd
Dec 22 , 2012 Added paragraph “Tolerability to Negative VS Transients”
July 22, 2014 Page 4: Removed note II from AEC-Q100
25
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