AUIRS2332J

September 3rd, 2012 Automotive Grade AUIRS2332J 3-PHASE BRIDGE DRIVER IC Features • • • • • • • • • • • • • • Floating channel designed for bootstrap operation Fully operational to +600 V Tolerant to negative transient voltage – dV/dt immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for all channels Over-current shutdown turns off all six drivers Independent half-bridge drivers Matched propagation delay for all channels 3.3 V logic compatible Outputs out of phase with inputs Cross-conduction prevention logic Integrated Operational Amplifier RoHS Compliant Product Summary ≤ 600V VOFFSET VOUT 10 – 20V Io+ & I o- (typical) 250mA & 500mA tON & tOFF (typical) 540ns Deadtime (typical) 850ns Package Options Automotive qualified* Typical Applications • • • Automotive Body electronics 3 phase motor control Pumps and fans Typical Connection Diagram 44-Lead PLCC w/o 12 Leads AUIRS2332J Table of Contents Page Description 3 Qualification Information 4 Absolute Maximum Ratings 5 Recommended Operating Conditions 6 Dynamic Electrical Characteristics 6 Static Electrical Characteristics 7-8 Functional Block Diagram 8 Input/Output Pin Equivalent Circuit Diagram 9 Lead Definitions 10 Lead Assignments 10 Application Information and Additional Details 11 - 25 Parameter Temperature Trends 26 - 29 Package Details 30 - 31 Part Marking Information 32 Ordering Information 32 Important Notice 33 2 AUIRS2332J Description The AUIRS2332J is a high voltage, high speed power MOSFET and IGBT driver with three independent high and low side referenced output channels. Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3V logic. A ground-referenced operational amplifier provides analog feedback of bridge current via an external current sense resistor. A current trip function which terminates all six outputs is also derived from this resistor. An open drain FAULT signal indicates if an over-current or undervoltage shutdown has occurred. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use at high frequencies. The floating channel can be used to drive N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. 3 AUIRS2332J Qualification Information† Automotive †† (per AEC-Q100 ) Comments: This family of ICs has passed an Automotive qualification. IR’s Industrial and Consumer qualification level is granted by extension of the higher Automotive level. Qualification Level ††† MSL3 245°C (per IPC/JEDEC J-STD-020) Moisture Sensitivity Level Machine Model ESD Human Body Model Charged Device Model IC Latch-Up Test RoHS Compliant Class M2 (Pass +/-200V) (per AEC-Q100-003) Class H1C (Pass +/-1500V) (per AEC-Q100-002) Class C4 (+/-1000V) (per AEC-Q100-011) Class II, Level A (per AEC-Q100-004) Yes † Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ †† Exceptions (if any) to AEC-Q100 requirements are noted in the qualification report. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. 4 AUIRS2332J Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which permanent damage to the device may occur. These are stress ratings only, functional operation of the device at these or any other condition beyond those indicated in the “Recommended Operating Condition” is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. All voltage parameters are absolute voltages referenced to VSO unless otherwise stated in the table. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB1,2,3 Definition High Side Floating Supply Voltage Min. Max. -0.3 620 VS1,2,3 High Side Floating Offset Voltage VB1,2,3 - 20 VB1,2,3 + 0.3 VHO1,2,3 High Side Floating Output Voltage VS1,2,3 - 0.3 VB1,2,3 + 0.3 VCC Low Side and Logic Fixed Supply Voltage VSS Logic Ground VLO1,2,3 VIN VFLT VCAO VCA- Low Side Output Voltage _______ ______ Logic Input Voltage ( HIN1,2,3, LIN1,2,3 & ITRIP) FAULT Output Voltage Operational Amplifier Output Voltage Operational Amplifier Inverting Input Voltage -0.3 20 VCC - 20 VCC + 0.3 -0.3 VCC + 0.3 VSS -0.3 (VSS + 15) or (VCC + 0.3) Whichever is lower VSS -0.3 VSS -0.3 VCC +0.3 VCC +0.3 VSS -0.3 VCC +0.3 Units V dVS/dt Allowable Offset Supply Voltage Transient — 50 V/ns PD Package Power Dissipation @ TA ≤ +25 °C — 2.0 W RthJA Thermal Resistance, Junction to Ambient — 63 °C/W RthJC Thermal Resistance, Junction to Case --- 21.95 °C/ W TJ Junction Temperature — 150 TS Storage Temperature -55 150 TL Lead Temperature (soldering, 10 seconds) — 300 °C 5 AUIRS2332J Recommended Operating Conditions The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltage referenced to VSO. The VS offset rating is tested with all supplies biased at 15V differential. Symbol Definition VB1,2,3 High Side Floating Supply Voltage Min. Max. VS1,2,3 +10 VS1,2,3 +20 VSO-8 (Note1) 600 -50 (Note2) VS1,2,3 600 VB1,2,3 VS1,2,3 Static High side floating offset voltage VSt1,2,3 VHO1,2,3 Transient High side floating offset voltage VCC Low Side and Logic Fixed Supply Voltage 10 20 VSS Logic Ground -5 5 0 VSS VSS VCC VSS + 5 VCC VLO1,2,3 VIN VFLT High Side Floating Output Voltage Low Side Output Voltage Logic Input Voltage (HIN1,2,3, LIN1,2,3 & ITRIP) FAULT Output Voltage VCAO Operational Amplifier Output Voltage VSS VSS + 5 VCA- Operational Amplifier Inverting Input Voltage VSS VSS + 5 Units V TA Ambient temperature -40 125 °C Note 1: Logic operational for VS of (VSO -8 V) to (VSO +600 V). Logic state held for VS of (VSO -8 V) to (VSO – VBS). Note 2: Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to the Application Information section of this datasheet for more details. Note 3: CAO input pin is internally clamped with a 5.2 V zener diode. Dynamic Electrical Characteristics Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj ≤125°C with bias conditions VBIAS (VCC, VBS1,2,3) = 15 V, CL = 1000 pF. Symbol Definition Min Typ Max Units ton Turn-on propagation delay 400 540 700 toff Turn-off propagation delay 400 540 700 tr Turn-on rise time — 80 145 tf Turn-off fall time ITRIP to Output Shutdown Propagation delay ITRIP Blanking Time ITRIP to FAULT Indication Delay Input Filter Time (All Six Inputs) LIN1,2,3 to FAULT Clear Time — 40 55 400 625 920 — 350 — 400 550 325 — 870 — 5300 8500 13700 Deadtime: Deadtime matching: 500 — 850 — 1100 145 titrip tbl tflt tflt, in tfltclr DT MDT MT Delay matching time (t ON , t OFF) — — 50 PM Pulse width distortion — — 75 SR+ Operational Amplifier Slew Rate (+) 5 10 — SR- Operational Amplifier Slew Rate (-) 2.4 3.2 — Test Conditions VS1,2,3 = 0 V to 600 V VS1,2,3 = 0 V ns VIN = 0 V & 5 V without external deadtime VIN = 0 V & 5 V without external deadtime larger than DT PM input 10 µs V/µs 1 V input step 1 V input step 6 AUIRS2332J NOTE: For high side PWM, HIN pulse width must be > 1.5 usec Static Electrical Characteristics Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj ≤ 125°C with bias conditions of VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS . The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3. Symbol Definition VIH Logic “0” input Voltage (OUT = LO) VIL Min Typ Max Units Test Conditions — — 2.2 VIT,TH+ Logic “1” input Voltage (OUT = HI) ITRIP Input Positive Going Threshold 0.8 400 — 490 — 580 VOH High Level Output Voltage, VBIAS - VO — — 1150 VOL Low Level Output Voltage, VO — — 400 ILK Offset Supply Leakage Current — — 50 IQBS Quiescent VBS Supply Current — 37 50 IQCC Quiescent VCC Supply Current — 4.5 6.2 IIN+ IIN- Logic “1” Input Bias Current (OUT =HI) Logic “0” Input Bias Current (OUT = LO) “High” ITRIP Bias Current “LOW” ITRIP Bias Current VBS Supply Undervoltage Positive Going Threshold VBS Supply Undervoltage Negative Going Threshold VCC Supply Undervoltage Positive going Threshold VCC Supply Undervoltage Negative Going Threshold IITRIP+ IITRIPVBSUV+ VBSUVVCCUV+ VCCUV- -450 -300 -100 -350 -220 -100 — 5 10 — — 30 7.5 8.3 9.2 7.1 7.9 8.8 8.3 8.9 9.7 8 8.6 9.4 VCCUVH Hysteresis — 0.3 — VBSUVH Hysteresis FAULT Low On-Resistance — 0.4 — — 55 75 IO+ Output High Short Circuit Pulsed Current — IO- Output Low Short Circuit Pulsed Current 375 500 — — — — — 20 100 — 80 — Ron, FLT V mV VIN = 5 V, IO = 20 mA VB = VS = 600 V µA mA µA nA CMRR PSRR VOH,AMP VOL,AMP Operational Amplifier Input Offset Voltage CA- Input Bias Current Operational Amplifier Common Mode Rejection Ratio Operational Amplifier Power Supply Rejection Ratio Operational Amplifier High Level Output Voltage Operational Amplifier Low Level Output Voltage mV nA — 75 — 4.8 5.2 5.6 V — — 40 mV — -7 -4 ISNK,AMP Operational Amplifier Output Sink Current 1 2.1 — VIN = 0 V VIN = 4 V ITRIP = 4 V ITRIP = 0 V VO = 0 V, VIN = 0 V PW ≤ 10 us VO = 15 V, VIN = 5 V PW ≤ 10 us VSO = 0.2 V VCA- = 1 V VSO = 0.1 V & 5 V dB Operational Amplifier Output Source Current VIN = 0 V Ω -250 -180 ISRC,AMP VIN = 0 V or 4 V V mA VOS ICA- VIN = 0 V, IO = 20 mA mA VSO = 0.2 V VCC = 9.7 V & 20 V VCA- = 0 V, VSO =1 V VCA- = 1 V, VSO =0 V VCA- = 0 V, VSO =1 V VCAO = 4 V VCA- = 1 V, VSO =0 V VCAO = 2 V 7 AUIRS2332J IO+,AMP IO-,AMP Operational Amplifier Output High Short Circuit Current Operational Amplifier Output Low Short Circuit Current -30 -10 — — 4 — VCA- = 0 V, VSO =5 V VCAO = 0 V VCA- = 5 V, VSO =0 V VCAO = 5 V Functional Block Diagram 8 AUIRS2332J Input/Output Pin Equivalent Circuit Diagram: VCC ESD Diode HIN123 , LIN123 50 KOhm 250 Ohm 20V ESD Diode 5V VSS VCC ESD Diode 250 Ohm ITRIP ESD Diode 5V 1 MOhm VSS 9 AUIRS2332J VB123 ESD Diode 20V HO123 ESD Diode VS123 10 AUIRS2332J Lead Definitions Symbol HIN1,2,3 LIN1,2,3 FAULT VCC Description Logic input for high side gate driver outputs (HO1,2,3), out of phase Logic input for low side gate driver output (LO1,2,3), out of phase Indicates over-current or undervoltage lockout (low side) has occurred, negative logic Low side and logic fixed supply ITRIP Input for over-current shutdown CAO Output of current amplifier CA- Negative input of current amplifier VSS VB1,2,3 HO1,2,3 VS1,2,3 Logic Ground High side floating supply High side gate drive output High side floating supply return LO1,2,3 Low side gate drive output VSO Low side return and positive input of current amplifier #Leas7, #11, #13, #15, #17, #20, #21 are N.C. Lead Assignments Leads num. 7, 11, 13, 15, 17, 20 and 21 are N.C. 11 AUIRS2332J Application Information and Additional Details Information regarding the following topics are included as subsections within this section of the datasheet. • • • • • • • • • • • • • • • • • • • • IGBT/MOSFET Gate Drive Switching and Timing Relationships Deadtime Matched Propagation Delays Input Logic Compatibility Undervoltage Lockout Protection Shoot-Through Protection Fault Reporting Over-Current Protection Over-Temperature Shutdown Protection Truth Table: Undervoltage lockout, ITRIP Advanced Input Filter Short-Pulse / Noise Rejection Integrated Bootstrap Functionality Bootstrap Power Supply Design Separate Logic and Power Grounds Negative VS Transient SOA DC- bus Current Sensing PCB Layout Tips Additional Documentation IGBT/MOSFET Gate Drive The AUIRS2332J HVIC is designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the high-side power switch and VLO for the low-side power switch; this parameter is sometimes generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage. VB (or VCC) VB (or VCC) IO+ HO (or LO) + HO (or LO) IO- VHO (or VLO) VS (or COM) - Figure 1: HVIC sourcing current VS (or COM) Figure 2: HVIC sinking current 12 AUIRS2332J Switching and Timing Relationships The relationship between the input and output signals of the AUIRS2332J are illustrated below in Figures 3. From these figures, we can see the definitions of several timing parameters (i.e., PW IN, PW OUT, tON, tOFF, tR, and tF) associated with this device. LINx (or HINx) 50% 50% PWIN tON tOFF tR 90% LOx (or HOx) tF PWOUT 10% 90% 10% Figure 3: Switching time waveforms The following two figures illustrate the timing relationships of some of the functionalities of the AUIRS2332J. These functionalities are described in further detail later in this document. During interval A of Figure 4, the HVIC has received the command to turn-on both the high- and low-side switches at the same time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the high- and low-side output are held in the off state. Interval B of Figures 4 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a result, all of the gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also held low) and a fault is reported by the FAULT output transitioning to the low state. Once the ITRIP input has returned to the low state, the fault condition is latched until the all LINx become high. HIN1,2,3 A B LIN1, 2, 3 ITRIP FAULT HO1, 2, 3 LO1,2, 3 Figure 4: Input/output timing diagram 13 AUIRS2332J Deadtime This HVIC features integrated deadtime protection circuitry. The deadtime for this IC is fixed; other ICs within IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserted whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified by the gate driver. Figure 5 illustrates the deadtime period and the relationship between the output gate signals. The deadtime circuitry of the AUIRS2332J is matched with respect to the high- and low-side outputs of a given channel; additionally, the deadtimes of each of the three channels are matched. Figure 5: Illustration of deadtime Matched Propagation Delays The AUIRS2332J HVIC is designed with propagation delay matching circuitry. With this feature, the IC’s response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the low-side channels and the high-side channels. Additionally, the propagation delay for each low-side channel is matched when compared to the other low-side channels and the propagation delays of the high-side channels are matched with each other. The propagation turn-on delay (tON) of the AUIRS2332J is matched to the propagation turn-on delay (tOFF). Input Logic Compatibility The inputs of this IC are compatible with standard CMOS and TTL outputs. The AUIRS2332J has been designed to be compatible with 3.3 V and 5 V logic-level signals. The AUIRS2332J features an integrated 5.2 V Zener clamp on the HIN, LIN, and ITRIP pins. Figure 6 illustrates an input signal to the AUIRS2332J, its input threshold values, and the logic state of the IC as a result of the input signal. 14 AUIRS2332J Figure 6: HIN & LIN input thresholds Undervoltage Lockout Protection This IC provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and the VBS (high-side circuitry) power supply. Figure 7 is used to illustrate this concept; VCC (or VBS) is plotted over time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or disabled. Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to inform the controller of the fault condition. Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the VBS voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the IC. The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high conduction losses within the power device and could lead to power device failure. Figure 7: UVLO protection Shoot-Through Protection 15 AUIRS2332J The AUIRS2332J is equipped with shoot-through protection circuitry (also known as cross-conduction prevention circuitry). Figure 8 shows how this protection circuitry prevents both the high- and low-side switches from conducting at the same time. Table 1 illustrates the input/output relationship of the devices in the form of a truth table. Note that the AUIRS2332J has inverting inputs (the output is out-of-phase with its respective input). Figure 8: Illustration of shoot-through protection circuitry AUIRS2332J HIN LIN HO LO 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 Table 1: Input/output truth table Fault Reporting The AUIRS2332J provides an integrated fault reporting output. There are two situations that would cause the HVIC to report a fault via the FAULT pin. The first is an undervoltage condition of VCC and the second is if the ITRIP pin recognizes a fault. Once the fault condition occurs, the FAULT pin is internally pulled to VSS and the fault condition is latched. The fault output stays in the low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed, the voltage on the FAULT pin will return to VCC. Over-Current Protection The AUIRS2332J HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-current events in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are shutdown, a fault is reported through the FAULT pin. The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R0, R1, and R2) connected to ITRIP as shown in Figure 9, and the ITRIP threshold (VIT,TH+). The circuit designer will need to determine the maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that the voltage at node VX reaches the over-current threshold (VIT,TH+) at that current level. VIT,TH+ = R0IDC-(R1/(R1+R2)) 16 AUIRS2332J Vcc A U I R S 2 3 3 2 J HIN(x3) LIN(x3) FAULT ITRIP VSS R1 VB (x3) HO( x3) VS (x3) LO(x3) COM R2 R0 IDC- Figure 9: Programming the over-current protection For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to exceed 5 V; if necessary, an external voltage clamp may be used. Over-Temperature Shutdown Protection The ITRIP input of the AUIRS2332J can also be used to detect over-temperature events in the system and initiate a shutdown of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will need to design the resistor network as shown in Figure 10 and select the maximum allowable temperature. This network consists of a thermistor and two standard resistors R3 and R4. As the temperature changes, the resistance of the thermistor will change; this will result in a change of voltage at node VX. The resistor values should be selected such the voltage VX should reach the threshold voltage (VIT,TH+) of the ITRIP functionality by the time that the maximum allowable temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V. When using both the over-current protection and over-temperature protection with the ITRIP input, OR-ing diodes (e.g., DL4148) can be used. This network is shown in Figure 11; the OR-ing diodes have been labeled D1 and D2. Figure 10: Programming over-temperature protection Figure 11: Using over-current protection and over-temperature protection Truth Table: Undervoltage lockout and ITRIP 17 AUIRS2332J Table 2 provides the truth table for the AUIRS2332J. The first line shows that the UVLO for VCC has been tripped; the FAULT output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case and when VCC is greater than VCCUV, the FAULT output returns to the high impedance state. The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have been disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new falling transition of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been reached and that the gate drive outputs have been disabled and a fault has been reported through the fault pin. The fault output stays in the low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed, the voltage on the FAULT pin will return to VCC. UVLO VCC UVLO VBS Normal operation ITRIP fault VCC