BSZ009NE2LS5

BSZ009NE2LS5 MOSFET OptiMOSTM5Power-Transistor,25V TSDSON-8FL (enlarged source interconnection) Features •Optimizedfore-fuseandORingapplication •Verylowon-resistanceRDS(on) •100%avalanchetested •Superiorthermalresistance •N-channel •Pb-freeleadplating;RoHScompliant •Halogen-freeaccordingtoIEC61249-2-21 Productvalidation FullyqualifiedaccordingtoJEDECforIndustrialApplications Table1KeyPerformanceParameters S1 8D S2 7D Parameter Value Unit S3 6D VDS 25 V G4 5D RDS(on),max 0.9 mΩ ID 40 A Qoss 26 nC QG(0V..10V) 92 nC QG(0V..4.5V) 52 nC Type/OrderingCode Package Marking RelatedLinks BSZ009NE2LS5 PG-TSDSON-8 FL 09NE2L5 - Final Data Sheet 1 Rev.2.0,2019-02-04 OptiMOSTM5Power-Transistor,25V BSZ009NE2LS5 TableofContents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Final Data Sheet 2 Rev.2.0,2019-02-04 OptiMOSTM5Power-Transistor,25V BSZ009NE2LS5 1Maximumratings atTA=25°C,unlessotherwisespecified Table2Maximumratings Parameter Symbol Values Unit Note/TestCondition 40 40 40 40 39 A VGS=10V,TC=25°C VGS=10V,TC=100°C VGS=4.5V,TC=25°C VGS=4.5V,TC=100°C VGS=10V,TA=25°C, RTHJA=60°C/W1) - 160 A TC=25°C - - 160 mJ ID=20A,RGS=25Ω VGS -16 - 16 V - Power dissipation Ptot - - 69 2.1 W TC=25°C TA=25°C,RTHJA=60°C/W1) Operating and storage temperature Tj,Tstg -55 - 150 °C IEC climatic category; DIN IEC 68-1: 55/150/56 Unit Note/TestCondition Min. Typ. Max. ID - - ID,pulse - Avalanche energy, single pulse EAS Gate source voltage Continuous drain current Pulsed drain current2) 3) 2Thermalcharacteristics Table3Thermalcharacteristics Parameter Symbol Thermal resistance, junction - case, bottom Values Min. Typ. Max. RthJC - - 1.8 °C/W - Thermal resistance, junction - case, top RthJC - - 20 °C/W - Device on PCB, 6 cm² cooling area RthJA - - 60 °C/W - 1) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 2) See Diagram 3 for more detailed information 3) See Diagram 13 for more detailed information Final Data Sheet 3 Rev.2.0,2019-02-04 OptiMOSTM5Power-Transistor,25V BSZ009NE2LS5 3Electricalcharacteristics atTj=25°C,unlessotherwisespecified Table4Staticcharacteristics Parameter Symbol Drain-source breakdown voltage Values Unit Note/TestCondition - V VGS=0V,ID=1mA - 2 V VDS=VGS,ID=250µA - 0.1 10 1 100 µA VDS=20V,VGS=0V,Tj=25°C VDS=20V,VGS=0V,Tj=125°C IGSS - 10 100 nA VGS=16V,VDS=0V Drain-source on-state resistance RDS(on) - 0.70 0.96 0.9 1.2 mΩ VGS=10V,ID=20A VGS=4.5V,ID=20A Gate resistance RG - 0.7 1.2 Ω - Transconductance gfs 70 140 - S |VDS|≥2|ID|RDS(on)max,ID=20A Unit Note/TestCondition Min. Typ. Max. V(BR)DSS 25 - Gate threshold voltage VGS(th) 1.2 Zero gate voltage drain current IDSS Gate-source leakage current Table5Dynamiccharacteristics Parameter Symbol Input capacitance Values Min. Typ. Max. Ciss - 4200 5500 pF VGS=0V,VDS=12V,f=1MHz Output capacitance1) Coss - 1200 1600 pF VGS=0V,VDS=12V,f=1MHz Reverse transfer capacitance Crss - 1100 - pF VGS=0V,VDS=12V,f=1MHz Turn-on delay time td(on) - 7 - ns VDD=12V,VGS=10V,ID=20A, RG,ext=1.6Ω Rise time tr - 9 - ns VDD=12V,VGS=10V,ID=20A, RG,ext=1.6Ω Turn-off delay time td(off) - 31 - ns VDD=12V,VGS=10V,ID=20A, RG,ext=1.6Ω Fall time tf - 17 - ns VDD=12V,VGS=10V,ID=20A, RG,ext=1.6Ω Unit Note/TestCondition Table6Gatechargecharacteristics2) Parameter Symbol Gate to source charge Values Min. Typ. Max. Qgs - 10.6 - nC VDD=12V,ID=20A,VGS=0to4.5V Gate charge at threshold Qg(th) - 6.1 - nC VDD=12V,ID=20A,VGS=0to4.5V Gate to drain charge Qgd - 28 - nC VDD=12V,ID=20A,VGS=0to4.5V Switching charge Qsw - 32 - nC VDD=12V,ID=20A,VGS=0to4.5V Gate charge total Qg - 52 70 nC VDD=12V,ID=20A,VGS=0to4.5V Gate plateau voltage Vplateau - 2.5 - V VDD=12V,ID=20A,VGS=0to4.5V Gate charge total1) Qg - 92 124 nC VDD=12V,ID=20A,VGS=0to10V Gate charge total, sync. FET Qg(sync) - 33 - nC VDS=0.1V,VGS=0to4.5V Qoss - 26 35 nC VDD=12V,VGS=0V 1) 1) Output charge 1) 2) Defined by design. Not subject to production test See ″Gate charge waveforms″ for parameter definition Final Data Sheet 4 Rev.2.0,2019-02-04 OptiMOSTM5Power-Transistor,25V BSZ009NE2LS5 Table7Reversediode Parameter Symbol Diode continuous forward current Values Unit Note/TestCondition 40 A TC=25°C - 160 A TC=25°C - 0.76 1 V VGS=0V,IF=20A,Tj=25°C - 20 - nC VR=12V,IF=20A,diF/dt=400A/µs Min. Typ. Max. IS - - Diode pulse current IS,pulse - Diode forward voltage VSD Reverse recovery charge Qrr Final Data Sheet 5 Rev.2.0,2019-02-04 OptiMOSTM5Power-Transistor,25V BSZ009NE2LS5 4Electricalcharacteristicsdiagrams Diagram1:Powerdissipation Diagram2:Draincurrent 70 280 60 240 50 200 40 160 ID[A] Ptot[W] package limit silicon limit 30 120 20 80 10 40 0 0 20 40 60 80 100 120 140 0 160 0 20 40 60 TC[°C] 80 100 120 140 160 TC[°C] Ptot=f(TC) ID=f(TC);VGS≥10V Diagram3:Safeoperatingarea Diagram4:Max.transientthermalimpedance 3 101 10 single pulse 0.01 0.02 0.05 0.1 0.2 0.5 1 µs 102 10 µs 10 ms 100 µs DC 100 ZthJC[K/W] ID[A] 101 1 ms 0 10 10-1 10-1 10-2 10-1 100 101 102 10-2 10-5 10-4 VDS[V] 10-2 10-1 100 tp[s] ID=f(VDS);TC=25°C;D=0;parameter:tp Final Data Sheet 10-3 ZthJC=f(tp);parameter:D=tp/T 6 Rev.2.0,2019-02-04 OptiMOSTM5Power-Transistor,25V BSZ009NE2LS5 Diagram5:Typ.outputcharacteristics 160 Diagram6:Typ.drain-sourceonresistance 2.4 10 V 4.5 V 3V 140 2.0 4V 120 1.6 80 2.8 V 60 RDS(on)[mΩ] ID[A] 100 3.5 V 3.5 V 1.2 4V 4.5 V 0.8 5V 10 V 40 0.4 20 0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 3.0 0 10 20 VDS[V] 30 RDS(on)=f(ID),Tj=25°C;parameter:VGS Diagram7:Typ.transfercharacteristics Diagram8:Typ.drain-sourceonresistance 160 2.00 140 1.75 120 1.50 100 1.25 RDS(on)[mΩ] ID[A] ID=f(VDS),Tj=25°C;parameter:VGS 80 60 150 °C 1.00 0.75 40 0.50 20 0.25 150 °C 0 0 1 25 °C 2 3 4 5 VGS[V] 0.00 25 °C 0 2 4 6 8 10 VGS[V] ID=f(VGS),|VDS|>2|ID|RDS(on)max;parameter:Tj Final Data Sheet 40 ID[A] RDS(on)=f(VGS),ID=20A;parameter:Tj 7 Rev.2.0,2019-02-04 OptiMOSTM5Power-Transistor,25V BSZ009NE2LS5 Diagram10:Typ.gatethresholdvoltage 1.6 2.00 1.4 1.75 1.2 1.50 1.0 1.25 2500 µA VGS(th)[V] RDS(on)(normalizedto25°C) Diagram9:Normalizeddrain-sourceonresistance 0.8 1.00 250 µA 0.6 0.75 0.4 0.50 0.2 0.25 0.0 -80 -40 0 40 80 120 0.00 -80 160 -40 0 Tj[°C] 40 80 120 160 Tj[°C] RDS(on)=f(Tj),ID=20A,VGS=10V VGS(th)=f(Tj),VGS=VDS;parameter:ID Diagram11:Typ.capacitances Diagram12:Forwardcharacteristicsofreversediode 4 103 10 25 °C 25 °C, max 150 °C 150 °C, max Coss Ciss Crss IF[A] C[pF] 102 103 101 102 0 5 10 15 20 25 100 0.0 0.2 VDS[V] 0.6 0.8 1.0 1.2 1.4 VSD[V] C=f(VDS);VGS=0V;f=1MHz Final Data Sheet 0.4 IF=f(VSD);parameter:Tj 8 Rev.2.0,2019-02-04 OptiMOSTM5Power-Transistor,25V BSZ009NE2LS5 Diagram13:Avalanchecharacteristics Diagram14:Typ.gatecharge 2 10 10 5V 12 V 20 V 8 25 °C 101 6 IAV[A] VGS[V] 100 °C 125 °C 4 0 10 2 10-1 100 101 102 103 tAV[µs] 0 0 20 40 60 80 100 120 Qgate[nC] IAS=f(tAV);RGS=25Ω;parameter:Tj,start VGS=f(Qgate),ID=20Apulsed,Tj=25°C;parameter:VDD Diagram15:Drain-sourcebreakdownvoltage Diagram Gate charge waveforms 28 27 VBR(DSS)[V] 26 25 24 23 -80 -40 0 40 80 120 160 Tj[°C] VBR(DSS)=f(Tj);ID=1mA Final Data Sheet 9 Rev.2.0,2019-02-04 OptiMOSTM5Power-Transistor,25V BSZ009NE2LS5 5PackageOutlines Figure1OutlinePG-TSDSON-8FL,dimensionsinmm/inches Final Data Sheet 10 Rev.2.0,2019-02-04 OptiMOSTM5Power-Transistor,25V BSZ009NE2LS5 RevisionHistory BSZ009NE2LS5 Revision:2019-02-04,Rev.2.0 Previous Revision Revision Date Subjects (major changes since last revision) 2.0 2019-02-04 Release of final version Trademarks Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. 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TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. Final Data Sheet 11 Rev.2.0,2019-02-04