BSZ040N04LSGATMA1

BSZ040N04LSG MOSFET OptiMOSª3Power-Transistor,40V S3O8 Features •FastswitchingMOSFETforSMPS •OptimizedtechnologyforDC/DCconverters •QualifiedaccordingtoJEDEC1)fortargetapplications •N-channel;Logiclevel •ExcellentgatechargexRDS(on)product(FOM) •Verylowon-resistanceRDS(on) •Superiorthermalresistance •100%Avalanchetested •Pb-freeplating;RoHScompliant •Halogen-freeaccordingtoIEC61249-2-21 Table1KeyPerformanceParameters S1 8D S2 7D Parameter Value Unit S3 6D VDS 40 V G4 5D RDS(on),max 4.0 mΩ ID 105 A Type/OrderingCode Package Marking RelatedLinks BSZ040N04LS G PG-TSDSON-8 040N04L - 1) J-STD20 and JESD22 Final Data Sheet 1 Rev.2.0,2020-07-09 OptiMOSª3Power-Transistor,40V BSZ040N04LSG TableofContents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Final Data Sheet 2 Rev.2.0,2020-07-09 OptiMOSª3Power-Transistor,40V BSZ040N04LSG 1Maximumratings atTA=25°C,unlessotherwisespecified Table2Maximumratings Parameter Symbol Values Unit Note/TestCondition 105 66 90 57 18 A VGS=10V,TC=25°C VGS=10V,TC=100°C VGS=4.5V,TC=25°C VGS=4.5V,TC=100°C VGS=10V,TA=25°C,RthJA=60K/W2) - 420 A TC=25°C - - 20 A TC=25°C EAS - - 130 mJ ID=20A,RGS=25Ω Gate source voltage VGS -20 - 20 V - Power dissipation Ptot - - 69 2.1 W TC=25°C TA=25°C,RthJA=60K/W2) Operating and storage temperature Tj,Tstg -55 - 150 °C IEC climatic category; DIN IEC 68-1: 55/150/56 Unit Note/TestCondition Min. Typ. Max. ID - - ID,pulse - Avalanche current, single pulse IAS Avalanche energy, single pulse Continuous drain current1) Pulsed drain current3) 4) 2Thermalcharacteristics Table3Thermalcharacteristics Parameter Symbol Thermal resistance, junction - case Device on PCB, 6 cm2 cooling area2) Values Min. Typ. Max. RthJC - - 1.8 K/W - RthJA - - 60 K/W - 1) Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature at 25°C. For higher case temperature please refer to Diagram 2. De-rating will be required based on the actual environmental conditions. 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 3) See Diagram 3 for more detailed information 4) See Diagram 13 for more detailed information Final Data Sheet 3 Rev.2.0,2020-07-09 OptiMOSª3Power-Transistor,40V BSZ040N04LSG 3Electricalcharacteristics atTj=25°C,unlessotherwisespecified Table4Staticcharacteristics Parameter Symbol Drain-source breakdown voltage Values Unit Note/TestCondition - V VGS=0V,ID=1mA - 2 V VDS=VGS,ID=36µA - 0.1 10 1 100 µA VDS=40V,VGS=0V,Tj=25°C VDS=40V,VGS=0V,Tj=125°C IGSS - 10 100 nA VGS=20V,VDS=0V Drain-source on-state resistance RDS(on) - 4.5 3.3 5.6 4 mΩ VGS=4.5V,ID=20A VGS=10V,ID=20A Gate resistance RG - 1.8 - Ω - Transconductance gfs 40 79 - S |VDS|>2|ID|RDS(on)max,ID=20A Unit Note/TestCondition Min. Typ. Max. V(BR)DSS 40 - Gate threshold voltage VGS(th) 1.2 Zero gate voltage drain current IDSS Gate-source leakage current Table5Dynamiccharacteristics Parameter Symbol Input capacitance1) Values Min. Typ. Max. Ciss - 3800 5100 pF VGS=0V,VDS=20V,f=1MHz Output capacitance1) Coss - 830 1100 pF VGS=0V,VDS=20V,f=1MHz Reverse transfer capacitance Crss - 45 - pF VGS=0V,VDS=20V,f=1MHz Turn-on delay time td(on) - 8.5 - ns VDD=20V,VGS=10V,ID=20A, RG=1.6Ω Rise time tr - 4.8 - ns VDD=20V,VGS=10V,ID=20A, RG=1.6Ω Turn-off delay time td(off) - 33 - ns VDD=20V,VGS=10V,ID=20A, RG=1.6Ω Fall time tf - 5.4 - ns VDD=20V,VGS=10V,ID=20A, RG=1.6Ω Unit Note/TestCondition Table6Gatechargecharacteristics2) Parameter Symbol Gate to source charge Values Min. Typ. Max. Qgs - 11 - nC VDD=20V,ID=20A,VGS=0to10V Gate charge at threshold Qg(th) - 6.1 - nC VDD=20V,ID=20A,VGS=0to10V Gate to drain charge Qgd - 4.9 - nC VDD=20V,ID=20A,VGS=0to10V Switching charge Qsw - 10 - nC VDD=20V,ID=20A,VGS=0to10V Gate charge total Qg - 48 64 nC VDD=20V,ID=20A,VGS=0to10V Gate plateau voltage Vplateau - 3.0 - V VDD=20V,ID=20A,VGS=0to10V Gate charge total1) Qg - 23 31 - VDD=20V,ID=20A,VGS=0to4.5V Gate charge total, sync. FET Qg(sync) - 45 - nC VDS=0.1V,VGS=0to10V Output charge Qoss - 31 - - VDD=20V,VGS=0V 1) 1) 2) Defined by design. Not subject to production test See ″Gate charge waveforms″ for parameter definition Final Data Sheet 4 Rev.2.0,2020-07-09 OptiMOSª3Power-Transistor,40V BSZ040N04LSG Table7Reversediode Parameter Symbol Diode continuous forward current Values Unit Note/TestCondition 58 A TC=25°C - 420 A TC=25°C - 0.8 1.2 V VGS=0V,IF=20A,Tj=25°C - 26 - nC VR=20V,IF=IS,diF/dt=400A/µs Min. Typ. Max. IS - - Diode pulse current IS,pulse - Diode forward voltage VSD Reverse recovery charge Qrr Final Data Sheet 5 Rev.2.0,2020-07-09 OptiMOSª3Power-Transistor,40V BSZ040N04LSG 4Electricalcharacteristicsdiagrams Diagram1:Powerdissipation Diagram2:Draincurrent 80 120 100 60 ID[A] Ptot[W] 80 40 60 40 20 20 0 0 40 80 120 0 160 0 20 40 60 TC[°C] 80 100 120 140 160 TC[°C] Ptot=f(TC) ID=f(TC);VGS≥10V Diagram3:Safeoperatingarea Diagram4:Max.transientthermalimpedance 3 101 10 1 µs 10 µs 2 10 100 µs 100 0.5 ZthJC[K/W] ID[A] 1 ms 10 ms 101 DC 0.2 0.1 0.05 10-1 0.02 100 0.01 single pulse 10-1 10-1 100 101 102 10-2 10-6 10-5 10-4 VDS[V] 10-2 10-1 100 tp[s] ID=f(VDS);TC=25°C;D=0;parameter:tp Final Data Sheet 10-3 ZthJC=f(tp);parameter:D=tp/T 6 Rev.2.0,2020-07-09 OptiMOSª3Power-Transistor,40V BSZ040N04LSG Diagram5:Typ.outputcharacteristics Diagram6:Typ.drain-sourceonresistance 200 12 10 V 5V 10 160 3.2 V 4.5 V 8 4V ID[A] RDS(on)[mΩ] 120 80 3.5 V 6 4V 4.5 V 5V 4 3.5 V 10 V 40 2 3.2 V 0 3V 2.8 V 0 1 2 0 3 0 10 20 VDS[V] 30 40 50 ID[A] ID=f(VDS);Tj=25°C;parameter:VGS RDS(on)=f(ID);Tj=25°C;parameter:VGS Diagram7:Typ.transfercharacteristics Diagram8:Typ.forwardtransconductance 200 160 160 120 120 ID[A] gfs[S] 200 80 80 40 40 150 °C 25 °C 0 0 1 2 3 4 5 0 0 VGS[V] 80 120 160 ID[A] ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj Final Data Sheet 40 gfs=f(ID);Tj=25°C 7 Rev.2.0,2020-07-09 OptiMOSª3Power-Transistor,40V BSZ040N04LSG Diagram9:Drain-sourceon-stateresistance Diagram10:Typ.gatethresholdvoltage 8 2.5 2.0 6 VGS(th)[V] RDS(on)[mΩ] 1.5 98 % 4 typ 1.0 2 0.5 0 -60 -20 20 60 100 140 0.0 -60 180 -20 20 Tj[°C] 60 100 140 180 Tj[°C] RDS(on)=f(Tj);ID=20A;VGS=10V VGS(th)=f(Tj);VGS=VDS;ID=36µA Diagram11:Typ.capacitances Diagram12:Forwardcharacteristicsofreversediode 4 103 10 25 °C 25 °C, max 150 °C 150 °C, max Ciss 103 102 IF[A] C[pF] Coss 102 101 Crss 101 0 10 20 30 40 100 0.0 0.5 VDS[V] C=f(VDS);VGS=0V;f=1MHz Final Data Sheet 1.0 1.5 2.0 VSD[V] IF=f(VSD);parameter:Tj 8 Rev.2.0,2020-07-09 OptiMOSª3Power-Transistor,40V BSZ040N04LSG Diagram13:Avalanchecharacteristics Diagram14:Typ.gatecharge 2 10 12 20 V 10 VGS[V] IAV[A] 8 25 °C 101 100 °C 32 V 8V 6 125 °C 4 2 100 100 101 102 103 tAV[µs] 0 0 10 20 30 40 50 Qgate[nC] IAS=f(tAV);RGS=25Ω;parameter:Tj(start) VGS=f(Qgate);ID=20Apulsed;parameter:VDD Diagram15:Drain-sourcebreakdownvoltage Diagram Gate charge waveforms 45 40 VBR(DSS)[V] 35 30 25 20 -60 -20 20 60 100 140 180 Tj[°C] VBR(DSS)=f(Tj);ID=1mA Final Data Sheet 9 Rev.2.0,2020-07-09 OptiMOSª3Power-Transistor,40V BSZ040N04LSG 5PackageOutlines Figure1OutlinePG-TSDSON-8,dimensionsinmm/inches Final Data Sheet 10 Rev.2.0,2020-07-09 OptiMOSª3Power-Transistor,40V BSZ040N04LSG RevisionHistory BSZ040N04LS G Revision:2020-07-09,Rev.2.0 Previous Revision Revision Date Subjects (major changes since last revision) 2.0 2020-07-09 Update current rating and footnotes Trademarks Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. 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TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. Final Data Sheet 11 Rev.2.0,2020-07-09