PR OFET™ + 12V
BTS5030-2EKA
Smart High-Side Power Switch
Dual Channel, 30mΩ
Data Sheet
Rev. 2.1, 2011-09-01
Automotive Power
BTS5030-2EKA
Table of Contents
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage and Current Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4.1
4.2
4.3
4.3.1
4.3.2
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PCB set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
5.1
5.2
5.3
5.3.1
5.3.2
5.4
5.5
Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output ON-state Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Turn ON/OFF Characteristics with Resistive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Load Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inverse Current Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
16
16
17
17
19
6
6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.2
6.5.3
6.6
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss of Ground Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Limitation in the Power DMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Circuit Appearance with Channel in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics for the Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
22
23
23
23
24
25
26
7
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.3.1
7.3.3.2
7.3.3.3
7.3.4
7.3.5
7.3.6
7.4
Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SENSE Signal in Different Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SENSE Signal in the Nominal Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SENSE Signal Variation as a Function of Temperature and Load Current . . . . . . . . . . . . . . . . . . .
SENSE Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SENSE Signal in Open Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Load in ON Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Load in OFF Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Load Diagnostic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SENSE Signal with OUT in Short Circuit to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SENSE Signal in Case of Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SENSE Signal in Case of Inverse Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Diagnostic Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
27
28
29
29
30
31
31
31
32
33
33
33
34
8
8.1
Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Sheet
PROFET™+ 12V
2
7
7
7
8
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Table of Contents
8.2
8.3
8.4
DEN / DSEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Input Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.3
9.3.1
9.3.2
9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.5
9.5.1
9.5.2
9.5.3
9.5.4
Characterization Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimum Functional Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Consumption One Channel active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Consumption Two Channels active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby Current for Whole Device with Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Drop Limitation at Low Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drain to Source Clamp Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slew Rate at Turn ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slew Rate at Turn OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Turn ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Turn OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Turn ON / OFF matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch ON Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch OFF Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overload Condition in the Low Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overload Condition in the High Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense at no Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Load Detection Threshold in ON State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sense Signal Maximum Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sense Signal maximum Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage Threshold ON to OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage Threshold OFF to ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Current High Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10.1
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Data Sheet
PROFET™+ 12V
3
39
39
39
39
40
40
40
41
41
41
42
42
42
43
43
44
44
45
45
45
46
46
46
47
47
48
48
48
49
49
Rev. 2.1, 2011-09-01
Smart High-Side Power Switch
1
BTS5030-2EKA
Overview
Application
•
•
•
Suitable for resistive, inductive and capacitive loads
Replaces electromechanical relays, fuses and discrete circuits
Most suitable for loads with high inrush current, such as lamps
Basic Features
•
•
•
•
•
•
•
•
•
Two channel device
Very low stand-by current
3.3 V and 5 V compatible logic inputs
Electrostatic discharge protection (ESD)
Optimized electromagnetic compatibility
Logic ground independent from load ground
Very low power DMOS leakage current in OFF state
Green product (RoHS compliant)
AEC qualified
PG-DSO-14-40 EP
Description
The BTS5030-2EKA is a 30 mΩ dual channel Smart High-Side Power Switch, embedded in a PG-DSO-14-40 EP,
Exposed Pad package, providing protective functions and diagnosis. The power transistor is built by an N-channel
vertical power MOSFET with charge pump. The device is integrated in Smart6 technology. It is specially designed
to drive lamps up to 2 * P21W, as well as LEDs in the harsh automotive environment.
Table 1
Product Summary
Parameter
Symbol
Value
Operating voltage range
VS(OP)
VS(LD)
RDS(ON)
IL(NOM)1
IL(NOM)2
kILIS
IL5(SC)
IS(OFF)
5 V ... 28 V
Maximum supply voltage
Maximum ON state resistance at TJ = 150 °C per channel
Nominal load current (one channel active)
Nominal load current (both channels active)
Typical current sense ratio
Minimum current limitation
Maximum standby current with load at TJ = 25 °C
41 V
60 mΩ
6A
4A
2150
36 A
500 nA
Type
Package
Marking
BTS5030-2EKA
PG-DSO-14-40 EP
BTS5030-2EKA
Data Sheet
PROFET™+ 12V
4
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Overview
Diagnostic Functions
•
•
•
•
•
•
Proportional load current sense for both channels multiplexed
Open load in ON and OFF
Short circuit to battery and ground
Overtemperature
Stable diagnostic signal during short circuit
Enhanced kILIS dependency with temperature and load current
Protection Functions
•
•
•
•
•
•
•
Stable behavior during undervoltage
Reverse polarity protection with external components
Secure load turn-off during logic ground disconnect with external components
Overtemperature protection with restart
Overvoltage protection with external components
Voltage dependent current limitation
Enhanced short circuit operation
Data Sheet
PROFET™+ 12V
5
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Block Diagram
2
Block Diagram
Channel 0
VS
voltage sensor
internal
power
supply
IN0
over
temperature
driver
logic
DEN
ESD
protection
IS
gate control
&
charge pump
T
clamp for
inductive load
over current
switch limit
load current sense and
open load detection
OUT 0
forward voltage drop detection
VS
Channel 1
T
IN1
Control and protection circuit equivalent to channel 0
DSEL
OUT 1
GND
Figure 1
Block diagram DxS.vsd
Block Diagram for the BTS5030-2EKA
Data Sheet
PROFET™+ 12V
6
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
GND
1
14
OUT0
IN0
2
13
OUT0
DEN
3
12
OUT0
IS
4
11
NC
DSEL
5
10
OUT1
IN1
6
9
OUT1
NC
7
8
OUT1
Pinout dual SO14 .vsd
Figure 2
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
Function
1
GND
GrouND; Ground connection
2
IN0
INput channel 0; Input signal for channel 0 activation
3
DEN
Diagnostic ENable; Digital signal to enable/disable the diagnosis of the device
4
IS
Sense; Sense current of the selected channel
5
DSEL
Diagnostic SELection; Digital signal to select the channel to be diagnosed
6
IN1
INput channel 1; Input signal for channel 1 activation
7, 11
NC
Not Connected; No internal connection to the chip
8, 9, 10
OUT1
OUTput 1; Protected high side power output channel 11)
12, 13, 14
OUT0
OUTput 0; Protected high side power output channel 01)
Cooling Tab
VS
Voltage Supply; Battery voltage
1) All output pins of a given channel must be connected together on the PCB. All pins of an output are internally connected
together. PCB traces have to be designed to withstand the maximum current which can flow.
Data Sheet
PROFET™+ 12V
7
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Pin Configuration
3.3
Voltage and Current Definition
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.
IS
VS
VDS0
VS
I IN0
IN0
VIN0
I IN1
IN1
VOUT0
VIN1
I DEN
I OUT0
OUT0
VDS1
DEN
VDEN
IDSEL
OUT1
I OUT1
DSEL
VDSEL
IIS
IS
GND
VOUT1
VIS
IGND
voltage and current convention.vsd
Figure 3
Voltage and Current Definition
Data Sheet
PROFET™+ 12V
8
Rev. 2.1, 2011-09-01
BTS5030-2EKA
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 2
Absolute Maximum Ratings 1)
TJ = -40°C to +150°C; (unless otherwise specified)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
VS
-VS(REV)
-0.3
–
28
V
–
P_4.1.1
0
–
16
V
P_4.1.2
VBAT(SC)
0
–
24
V
t < 2 min
TA = 25 °C
RL ≥ 4 Ω
RGND = 150 Ω
2)
RECU = 20 mΩ
RCable= 16 mΩ/m
LCable= 1 μH/m,
l = 0 or 5 m
Supply Voltages
Supply voltage
Reverse polarity voltage
Supply voltage for short
circuit protection
P_4.1.3
See Chapter 6
and Figure 53
Supply voltage for Load dump VS(LD)
protection
–
–
41
V
3)
RI = 2 Ω
P_4.1.12
RL = 4 Ω
Short Circuit Capability
nRSC1
–
–
100
4)
k
cycles tON = 300ms
P_4.1.4
VIN
-0.3
–
–
6
7
V
P_4.1.13
IIN
VDEN
-2
–
2
mA
–
P_4.1.14
-0.3
–
–
6
7
V
–
t < 2 min
P_4.1.15
IDEN
VDSEL
-2
–
2
mA
–
P_4.1.16
-0.3
–
–
6
7
V
–
P_4.1.17
IDSEL
-2
–
2
mA
–
P_4.1.18
VIS
IIS
-0.3
–
VS
V
–
P_4.1.19
-25
–
50
mA
–
P_4.1.20
Load current
| IL |
–
–
IL(LIM)
A
–
P_4.1.21
Power dissipation (DC)
PTOT
–
–
2.1
W
TA = 85 °C
TJ < 150 °C
P_4.1.22
Permanent short circuit
IN pin toggles
Input Pins
Voltage at INPUT pins
Current through INPUT pins
Voltage at DEN pin
Current through DEN pin
Voltage at DSEL pin
Current through DSEL pin
–
t < 2 min
t < 2 min
Sense Pin
Voltage at IS pin
Current through IS pin
Power Stage
Data Sheet
PROFET™+ 12V
9
Rev. 2.1, 2011-09-01
BTS5030-2EKA
General Product Characteristics
Table 2
Absolute Maximum Ratings (cont’d)1)
TJ = -40°C to +150°C; (unless otherwise specified)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
Maximum energy dissipation EAS
Single pulse (one channel)
–
–
50
mJ
IL(0) = 6 A
TJ(0) = 150 °C
VS = 13.5 V
P_4.1.23
VDS
–
–
41
V
–
P_4.1.26
I GND
-10
-150
–
10
20
mA
–
P_4.1.27
TJ
TSTG
-40
–
150
°C
–
P_4.1.28
-55
–
150
°C
–
P_4.1.30
VESD
VESD
-2
–
2
kV
5)
HBM
P_4.1.31
-4
–
4
kV
5)
HBM
P_4.1.32
VESD
VESD
-500
–
500
V
6)
CDM
P_4.1.33
V
6)
CDM
P_4.1.34
Voltage at power transistor
Currents
Current through ground pin
t < 2 min
Temperatures
Junction temperature
Storage temperature
ESD Susceptibility
ESD susceptibility (all pins)
ESD susceptibility OUT Pin
vs. GND and VS connected
ESD susceptibility
ESD susceptibility pin
(corner pins)
-750
–
750
1)
2)
3)
4)
Not subject to production test. Specified by design.
Hardware set-up in accordance to AEC Q100-012 and AEC Q101-006.
VS(LD) is setup without the DUT connected to the generator per ISO 7637-1.
EOL tests according to AECQ100-012. Threshold limit for short circuit failures: 100 ppm. Please refer to the legal disclaimer
for short-circuit capability on Page 54 of this document.
5) ESD susceptibility HBM according to EIA/JESD 22-A 114B.
6) “CDM” EIA/JESD22-C101 or ESDA STM5.3.1
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Data Sheet
PROFET™+ 12V
10
Rev. 2.1, 2011-09-01
BTS5030-2EKA
General Product Characteristics
4.2
Functional Range
Table 3
Functional Range TJ = -40°C to +150°C; (unless otherwise specified)
Parameter
Symbol
Nominal operating voltage
VNOM
VS(OP)
Extended operating voltage
Values
Min.
Typ.
Max.
8
13.5
18
5
–
28
Unit
Note /
Test Condition
Number
V
–
P_4.2.1
V
2)
VIN = 4.5 V
P_4.2.2
RL = 4 Ω
VDS < 0.5 V
See Figure 15
Minimum functional supply
voltage
VS(OP)_MIN
3.8
4.3
5
V
1)
VIN = 4.5 V
RL = 4 Ω
From IOUT = 0 A
P_4.2.3
to
VDS < 0.5 V;
See Figure 15
See Figure 29
Undervoltage shutdown
VS(UV)
3
3.5
4.1
V
1)
VIN = 4.5 V
P_4.2.4
VDEN = 0 V
RL = 4 Ω
From VDS < 1 V;
to IOUT = 0 A
See Figure 15
See Figure 30
Undervoltage shutdown
hysteresis
VS(UV)_HYS
–
850
–
mV
2)
Operating current
One channel active
IGND_1
–
3.5
6
mA
P_4.2.5
VIN = 5.5 V
VDEN = 5.5 V
Device in RDS(ON)
VS = 18 V
–
P_4.2.13
See Figure 31
Operating current
All channels active
IGND_2
–
5
8
mA
VIN = 5.5 V
P_4.2.6
VDEN = 5.5 V
Device in RDS(ON)
VS = 18 V
See Figure 32
Standby current for whole
device with load (ambiente)
IS(OFF)
–
0.1
0.5
μA
1)
VS = 18 V
VOUT = 0 V
VIN floating
VDEN floating
TJ ≤ 85 °C
P_4.2.7
See Figure 33
Data Sheet
PROFET™+ 12V
11
Rev. 2.1, 2011-09-01
BTS5030-2EKA
General Product Characteristics
Table 3
Functional Range (cont’d)TJ = -40°C to +150°C; (unless otherwise specified)
Parameter
Symbol
Maximum standby current for IS(OFF)_150
whole device with load
Values
Min.
Typ.
Max.
–
4
20
Unit
Note /
Test Condition
Number
μA
VS = 18 V
VOUT = 0 V
VIN floating
VDEN floating
TJ = 150 °C
P_4.2.10
See Figure 33
Standby current for whole
device with load, diagnostic
active
IS(OFF_DEN)
–
0.6
–
mA
2)
VS = 18 V
VOUT = 0 V
VIN floating
VDEN = 5.5 V
P_4.2.8
1) Test at TJ = -40°C only
2) Not subject to production test. Specified by design.
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Table 4
Thermal Resistance
Parameter
Symbol
RthJS
RthJA
Junction to soldering point
Junction to ambient
Both channels active
Values
Min.
Typ.
Max.
–
5
–
–
31
–
Unit
Note /
Test Condition
Number
K/W
1)
P_4.3.1
K/W
1) 2)
P_4.3.2
1) Not subject to production test. Specified by design.
2)Specified Rthja value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The
product (chip + package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70μm
Cu, 2 x 35 μm Cu). Where applicable, a thermal via array under the exposed pad contacts the first inner copper
layer. Please refer to Figure 4 and Figure 5.
4.3.1
PCB set up
70µm
1.5mm
35µm
0.3mm
Figure 4
PCB 2s2p.vsd
2s2p PCB Cross Section
Data Sheet
PROFET™+ 12V
12
Rev. 2.1, 2011-09-01
BTS5030-2EKA
General Product Characteristics
PCB bottom view
PCB top view
1
14
2
13
3
12
COOLING
TAB
4
11
VS
5
10
6
9
7
8
thermique SO14.vsd
Figure 5
PC Board Top and Bottom View for Thermal Simulation with 600 mm² Cooling Area
4.3.2
Thermal Impedance
100
Zth-JA [K/W]
10
1
2s2p
1s0p - 600 mm²
1s0p - 300 mm²
1s0p - footprint
0.1
0.0001
0.001
0.01
0.1
1
10
100
1000
time [sec]
Figure 6
Typical Thermal Impedance. PCB set up according Figure 5
Data Sheet
PROFET™+ 12V
13
Rev. 2.1, 2011-09-01
BTS5030-2EKA
General Product Characteristics
100
90
Rthj [K/W]
80
70
60
1s0p
50
40
30
0
footprint
Figure 7
100
200
300
400
500
600
700
Area [mm2]
Typical Thermal Resistance. PCB set up 1s0p
Data Sheet
PROFET™+ 12V
14
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Power Stage
5
Power Stage
The power stages are built using an N-channel vertical power MOSFET (DMOS) with charge pump.
5.1
Output ON-state Resistance
The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature TJ. Figure 8
shows the dependencies in terms of temperature and supply voltage for the typical ON-state resistance. The
behavior in reverse polarity is described in Chapter 6.4.
100
55
90
80
70
RDS(ON)(mΩ )
RDS(ON)(mΩ )
45
35
60
50
40
30
25
20
10
15
0
-40
Figure 8
-10
20
50
80
Junction Temperature (Tj)
110
140
0
3
6
9
12
15
18
Supply Voltage VS (V) Rdson_30.vsd
Typical ON-state Resistance
A high signal at the input pin (see Chapter 8) causes the power DMOS to switch ON with a dedicated slope, which
is optimized in terms of EMC emission.
5.2
Turn ON/OFF Characteristics with Resistive Load
Figure 9 shows the typical timing when switching a resistive load.
IN
VIN_H
VIN_L
t
VOUT
dV/dt ON
dV/dt
t ON
90% VS
tOFF_DELAY
70% VS
30% VS
10% VS
OFF
tON_DELAY
tOFF
t
Switching times.vsd
Figure 9
Switching a Resistive Load Timing
Data Sheet
PROFET™+ 12V
15
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Power Stage
5.3
Inductive Load
5.3.1
Output Clamping
When switching OFF inductive loads with high side switches, the voltage VOUT drops below ground potential,
because the inductance intends to continue driving the current. To prevent the destruction of the device by
avalanche due to high voltages, there is a voltage clamp mechanism ZDS(AZ) implemented that limits negative
output voltage to a certain level (VS - VDS(AZ)). Please refer to Figure 10 and Figure 11 for details. Nevertheless,
the maximum allowed load inductance is limited.
VS
ZDS(AZ)
VDS
IN
LOGIC
IL
VBAT
GND
VIN
OUT
VOUT
L, RL
ZGND
Output clamp.svg
Figure 10
Output Clamp (OUT0 and OUT1)
IN
t
V OUT
VS
t
V S-VDS(AZ)
IL
t
Switching an inductance.vsd
Figure 11
Switching an Inductive Load Timing
Data Sheet
PROFET™+ 12V
16
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Power Stage
5.3.2
Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the BTS5030-2EKA. This energy can
be calculated with following equation:
V S – V DS ( AZ )
RL × IL ⎞
L
E = V DS ( AZ ) × ------ × -------------------------------× ln ⎛ 1 – -------------------------------+ IL
⎝
RL
RL
V S – V DS ( AZ )⎠
(1)
Following equation simplifies under the assumption of RL = 0 Ω.
VS
2
1
⎞
E = --- × L × I × ⎛⎝ 1 – -------------------------------2
V S – V DS ( AZ )⎠
(2)
The energy, which is converted into heat, is limited by the thermal design of the component. See Figure 12 for the
maximum allowed energy dissipation as a function of the load current.
E AS [mJ]
1000
100
10
0
2
4
6
I L [A]
Figure 12
Maximum Energy Dissipation Single Pulse, TJ(0) = 150 °C; VS = 13.5V
5.4
Inverse Current Capability
8
10
EAS30.vsd
In case of inverse current, meaning a voltage VINV at the OUTput higher than the supply voltage VS, a current IINV
will flow from output to VS pin via the body diode of the power transistor (please refer to Figure 13). The output
stage follows the state of the IN pin, except if the IN pin goes from OFF to ON during inverse. In that particular
case, the output stage is kept OFF until the inverse current disappears. Nevertheless, the current IINV should not
be higher than IL(INV). Otherwise, the second channel can be corrupted and erratic behavior can be observed. If
the affected channel is OFF, the diagnostic will detect an open load at OFF. If the affected channel is ON, the
diagnostic will detect open load at ON (the overtemperature signal is inhibited). At the appearance of VINV, a
parasitic diagnostic can be observed at the unaffected channel. After, the diagnosis is valid and reflects the output
state. At VINV vanishing, the diagnosis is valid and reflects the output state. During inverse current, no protection
function are available.
Data Sheet
PROFET™+ 12V
17
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Power Stage
VBAT
VS
Gate driver
Device
logic
VINV
IL(INV)
OL
comp.
INV
Comp.
OUT
GND
ZGND
inverse current.svg
Figure 13
Inverse Current Circuitry
Data Sheet
PROFET™+ 12V
18
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Power Stage
5.5
Electrical Characteristics Power Stage
Table 5
Electrical Characteristics: Power Stage
VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified).
Typical values are given at VS = 13.5 V, TJ = 25 °C
Parameter
ON-state resistance per
channel
Symbol
RDS(ON)_150
Values
Min.
Typ.
Max.
45
55
60
Unit
Note /
Test Condition
Number
mΩ
IL = IL4 = 7 A
VIN = 4.5 V
TJ = 150 °C
P_5.5.1
TJ = 25 °C
P_5.5.21
TA = 85 °C
P_5.5.2
See Figure 8
ON-state resistance per
channel
RDS(ON)_25
–
30
–
mΩ
1)
Nominal load current
One channel active
IL(NOM)1
–
6
–
A
1)
Nominal load current
All channel active
IL(NOM)2
–
4
–
A
Output voltage drop limitation VDS(NL)
at small load currents
–
10
25
mV
TJ < 150 °C
P_5.5.3
IL = IL0 = 50 mA
P_5.5.4
See Figure 34
Drain to source clamping
voltage
VDS(AZ) = [VS - VOUT]
VDS(AZ)
41
47
53
V
IDS = 20 mA
See Figure 11
See Figure 35
P_5.5.5
Output leakage current per
channel; TJ ≤ 85 °C
IL(OFF)
–
0.1
0.5
μA
2)
P_5.5.6
Output leakage current per
channel; TJ = 150 °C
IL(OFF)_150
–
2
10
μA
Inverse current capability
IL(INV)
dV/dtON
–
4
–
A
0.1
0.25
0.5
V/μs
Slew rate
70% to 30% VS
-dV/dtOFF
0.1
0.25
0.5
V/μs
Slew rate matching
dV/dtON - dV/dtOFF
ΔdV/dt
-0.15
0
0.15
V/μs
Turn-ON time to VOUT = 90% tON
30
100
230
μs
Turn-OFF time to VOUT = 10% tOFF
30
100
230
μs
P_5.5.15
-50
0
50
μs
P_5.5.16
Turn-ON time to VOUT = 10% tON_delay
10
35
100
μs
P_5.5.17
Turn-OFF time to VOUT = 90% tOFF_delay
10
35
100
μs
P_5.5.18
Slew rate
30% to 70% VS
VS
VIN floating
VOUT = 0 V
TJ ≤ 85 °C
VIN floating
VOUT = 0 V
TJ = 150 °C
1)
VS < VOUTx
RL = 4 Ω
VS = 13.5 V
See Figure 9
See Figure 36
See Figure 37
See Figure 38
See Figure 39
See Figure 40
P_5.5.8
P_5.5.9
P_5.5.11
P_5.5.12
P_5.5.13
P_5.5.14
VS
Turn-ON / OFF matching
tOFF - tON
ΔtSW
VS
VS
Data Sheet
PROFET™+ 12V
19
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Power Stage
Table 5
Electrical Characteristics: Power Stage (cont’d)
VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified).
Typical values are given at VS = 13.5 V, TJ = 25 °C
Parameter
Switch ON energy
Symbol
EON
Values
Min.
Typ.
Max.
–
1.2
–
Unit
Note /
Test Condition
Number
mJ
1)
P_5.5.19
RL = 4 Ω
VOUT = 90% VS
VS = 18 V
See Figure 41
Switch OFF energy
EOFF
–
1.1
–
mJ
1)
RL = 4 Ω
VOUT = 10% VS
VS = 18 V
P_5.5.20
See Figure 42
1) Not subject to production test, specified by design.
2) Test at TJ = -40°C only
Data Sheet
PROFET™+ 12V
20
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Protection Functions
6
Protection Functions
The device provides integrated protection functions. These functions are designed to prevent the destruction of
the IC from fault conditions described in the data sheet. Fault conditions are considered as “outside” normal
operating range. Protection functions are designed for neither continuous nor repetitive operation.
6.1
Loss of Ground Protection
In case of loss of the module ground and the load remains connected to ground, the device protects itself by
automatically turning OFF (when it was previously ON) or remains OFF, regardless of the voltage applied on IN
pins.
In case of loss of device ground, it’s recommended to use input resistors between the microcontroller and the
BTS5030-2EKA to ensure switching OFF of channels.
In case of loss of module or device ground, a current (IOUT(GND)) can flow out of the DMOS. Figure 14 sketches
the situation.
ZGND can be either resistor or diode.
VS
ZIS(AZ)
ZD(AZ)
IS
RSENSE
VBAT
ZDS(AZ)
DSEL
RDSEL
DEN
RDEN
INx
RIN
IOUT(GND)
LOGIC
OUTx
ZDESD
GND
RIS
ZGND
Loss of ground protection.svg
Figure 14
Loss of Ground Protection with External Components
6.2
Undervoltage Protection
Between VS(UV) and VS(OP), the undervoltage mechanism is triggered. VS(OP) represents the minimum voltage
where the switching ON and OFF can takes place. VS(UV) represents the minimum voltage the switch can hold ON.
If the supply voltage is below the undervoltage mechanism VS(UV), the device is OFF (turns OFF). As soon as the
supply voltage is above the undervoltage mechanism VS(OP), then the device can be switched ON. When the switch
is ON, protection functions are operational. Nevertheless, the diagnosis is not guaranteed until VS is in the VNOM
range. Figure 15 sketches the undervoltage mechanism.
Data Sheet
PROFET™+ 12V
21
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Protection Functions
VOUT
undervoltage behavior
.vsd
VS(UV)
Figure 15
Undervoltage Behavior
6.3
Overvoltage Protection
VS(OP)
VS
There is an integrated clamp mechanism for overvoltage protection (ZD(AZ)). To guarantee this mechanism
operates properly in the application, the current in the Zener diode has to be limited by a ground resistor. Figure 16
shows a typical application to withstand overvoltage issues. In case of supply voltage higher than VS(AZ), the power
transistor switches ON and the voltage across the logic section is clamped. As a result, the internal ground
potential rises to VS - VS(AZ). Due to the ESD Zener diodes, the potential at pin INx, DSEL and DEN rises almost
to that potential, depending on the impedance of the connected circuitry. In the case the device was ON, prior to
overvoltage, the BTS5030-2EKA remains ON. In the case the BTS5030-2EKA was OFF, prior to overvoltage, the
power transistor can be activated. In the case the supply voltage is in above VBAT(SC) and below VDS(AZ), the output
transistor is still operational and follows the input. If at least one channel is in the ON state, parameters are no
longer guaranteed and lifetime is reduced compared to the nominal supply voltage range. This especially impacts
the short circuit robustness, as well as the maximum energy EAS capability. ZGND as a resistor (150 Ω) will offer
superior results compared to a diode and resistor (1 kΩ).
ISOV
VS
ZIS(AZ)
IN1
ZD(AZ)
IS
RSENSE
VBAT
ZDS(AZ)
DSEL
RDSEL
DEN
RDEN
INx
RIN
LOGIC
IN0
OUTx
ZDESD
GND
RIS
ZGND
Overvoltage protection.svg
Figure 16
Overvoltage Protection with External Components
Data Sheet
PROFET™+ 12V
22
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Protection Functions
6.4
Reverse Polarity Protection
In case of reverse polarity, the intrinsic body diodes of the power DMOS causes power dissipation. The current in
this intrinsic body diode is limited by the load itself. Additionally, the current into the ground path and the logic pins
has to be limited to the maximum current described in Chapter 4.1 with an external resistor. Figure 17 shows a
typical application. RGND resistor is used to limit the current in the Zener protection of the device. Resistors RDSEL,
RDEN, and RIN are used to limit the current in the logic of the device and in the ESD protection stage. RSENSE is used
to limit the current in the sense transistor which behaves as a diode. The recommended value for RDEN = RDSEL =
RIN = RSENSE = 4.7 kΩ. ZGND can be either a 150 Ω resistor or Schottky diode with 1 kΩ resistor in parallel.
In case the overvoltage is not considered in the application, RGND can be replaced by a Schottky diode and 1kΩ
resistor in parallel. Optionally a capacitor in parallel is recommended for EMC reasons.
During reverse polarity, no protection functions are available.
Micro controller
protection diodes
ZIS(AZ)
VS
ZD(AZ)
IS
R SENSE
ZDS(AZ)
VDS(REV)
DSEL
RDSEL
DEN
RDEN
INx
RIN
LOGIC
-VS(REV)
IN0
OUTx
ZDESD
GND
RIS
ZGND
Reverse Polarity.vsd
Figure 17
Reverse Polarity Protection with External Components
6.5
Overload Protection
In case of overload, such as high inrush of cold lamp filament, or short circuit to ground, the BTS5030-2EKA offers
several protection mechanisms.
6.5.1
Current Limitation
At first step, the instantaneous power in the switch is maintained at a safe value by limiting the current to the
maximum current allowed in the switch IL(SC). During this time, the DMOS temperature is increasing, which affects
the current flowing in the DMOS. The current limitation value is VDS dependent. Figure 18 shows the behavior of
the current limitation as a function of the drain to source voltage.
Data Sheet
PROFET™+ 12V
23
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Protection Functions
50
IL5(SC)
45
40
Current Limit IL(SC) (A)
35
30
25
IL28(SC)
20
15
10
5
0
0
5
10
15
Drain source Voltage VDS (V)
Figure 18
Current Limitation (typical behavior)
6.5.2
Temperature Limitation in the Power DMOS
20
25
current limitation_30m.vsd
Each channel incorporates both an absolute (TJ(SC)) and a dynamic (TJ(SW)) temperature sensor. Activation of
either sensor will cause an overheated channel to switch OFF to prevent destruction. Any protective switch OFF
latches the output until the temperature has reached an acceptable value. Figure 19 gives a sketch of the
situation. The ΔTSTEP describes the device’s warming, due to the overcurrent in the channel.
A retry strategy is implemented such that when the DMOS temperature has cooled down enough, the switch is
switched ON again, if the IN pin signal is still high (restart behavior).
Data Sheet
PROFET™+ 12V
24
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Protection Functions
IN
t
IL
LOAD CURRENT LIMITATION PHASE
IL(x)SC
LOAD CURRENT BELOW
LIMITATION PHASE
IL(NOM)
t
TDMOS
ΔTJ(SW)
TJ(SC)
ΔTJ(SW)
ΔTJ(SW)
TA
tsIS(FAULT)
t
ΔTSTEP
IIS
tsIS(OT_blank)
IIS(FAULT)
IL( NOM) / kILIS
0A
V DEN
t
tsIS(OFF)
0V
t
Hard start.vsd
Figure 19
Overload Protection
Note: For better understanding, the time scale is not linear. The real timing of this drawing is application dependant
and cannot be described.
6.5.3
Short Circuit Appearance with Channel in Parallel
The two channels are not synchronized in the restart event. When the two channels are in temperature limitation,
the channel which has cooled down the fastest doesn’t wait for the second one to be cooled down as well to restart.
Thus, it is not recommended to use the device with channels in parallel.
Data Sheet
PROFET™+ 12V
25
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Protection Functions
6.6
Electrical Characteristics for the Protection Functions
Table 6
Electrical Characteristics: Protection
VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified).
Typical values are given at VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
–
0.1
–
mA
1) 2)
VS = 28 V
See Figure 14
P_6.6.1
200
650
700
mV
IL = - 4 A
TJ = 150 °C
P_6.6.2
Loss of Ground
Output leakage current while IOUT(GND)
GND disconnected
Reverse Polarity
Drain source diode voltage
during reverse polarity
VDS(REV)
See Figure 17
Overvoltage
Overvoltage protection
VS(AZ)
41
47
53
V
ISOV = 5 mA
P_6.6.3
See Figure 16
Overload Condition
Load current limitation
IL5(SC)
36
47
57
A
3)
VDS = 5 V
See Figure 18 and
Figure 43
P_6.6.4
Load current limitation
IL28(SC)
–
23
–
A
2)
VDS = 28 V
See Figure 18 and
Figure 44
P_6.6.7
Short circuit current during
over temperature toggling
IL(RMS)
–
5
–
A
2)
VIN = 4.5 V
RSHORT = 100 mΩ
LSHORT = 5 μH
P_6.6.12
Dynamic temperature
increase while switching
ΔTJ(SW)
–
80
–
K
4)
See Figure 19
P_6.6.8
Thermal shutdown
temperature
TJ(SC)
150
170 4)
200 4)
°C
5)
See Figure 19
P_6.6.10
20
–
K
5) 4)
Thermal shutdown hysteresis ΔTJ(SC)
–
1) All pins are disconnected except VS and OUT.
2)
3)
4)
5)
See Figure 19
P_6.6.11
Not Subject to production test, specified by design
Test at TJ = -40°C only
Functional test only
Test at TJ = +150°C only
Data Sheet
PROFET™+ 12V
26
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Diagnostic Functions
7
Diagnostic Functions
For diagnosis purpose, the BTS5030-2EKA provides a combination of digital and analog signals at pin IS. These
signals are called SENSE. In case the diagnostic is disabled via DEN, pin IS becomes high impedance. In case
DEN is activated, the SENSE of the channel X is enabled/disabled via associated pin DSEL. Table 7 gives the
truth table.
Table 7
Diagnostic Truth Table
DEN
DSEL
IS
0
don’t care
Z
1
0
Sense output 0 IIS(0)
1
1
Sense output 1 IIS(1)
7.1
IS Pin
The BTS5030-2EKA provides a SENSE current written IIS at pin IS. As long as no “hard” failure mode occurs (short
circuit to GND / current limitation / overtemperature / excessive dynamic temperature increase or open load at
OFF) a proportional signal to the load current (ratio kILIS = IL / IIS) is provided. The complete IS pin and diagnostic
mechanism is described on Figure 20. The accuracy of the SENSE depends on temperature and load current.
The IS pin multiplexes the current IIS(0) and IIS(1), via the pin DSEL. Thanks to this multiplexing, the matching
between kILISCHANNEL0 and kILISCHANNEL1 is optimized. Due to the ESD protection, in connection to VS, it is not
recommended to share the IS pin with other devices if these devices are using another battery feed. The
consequence is that the unsupplied device would be fed via the IS pin of the supplied device.
Vs
IIS1 =
IL1 / kILIS
IIS0 =
IL0 / kILIS
IIS(FAULT)
ZIS(AZ)
0
1
IS
FAULT
0
1
DEN
DSEL
Figure 20
Sense schematic.svg
Diagnostic Block Diagram
Data Sheet
PROFET™+ 12V
27
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Diagnostic Functions
7.2
SENSE Signal in Different Operating Modes
Table 8 gives a quick reference for the state of the IS pin during device operation.
Table 8
Sense Signal, Function of Operation Mode
Operation Mode
Input level Channel X
DEN1)
Normal operation
OFF
H
Output Level Diagnostic Output
Z
Z
Short circuit to GND
~ GND
Z
Overtemperature
Z
Z
Short circuit to VS
IIS(FAULT)
Current limitation
VS
< VOL(OFF)
> VOL(OFF)2)
~ VINV
~ VS
< VS
Short circuit to GND
~ GND
Overtemperature TJ(SW)
event
Z
IIS(FAULT)
IIS(FAULT)
IIS = IL / kILIS
IIS(FAULT)
IIS(FAULT)
IIS(FAULT)
Short circuit to VS
VS
~ VS3)
~ VINV
~ VS5)
IIS < IL / kILIS
IIS < IIS(OL)
IIS < IIS(OL)4)
IIS(OL) < IIS < IL(nom) / kILIS
Don’t care
Z
Open Load
Inverse current
Normal operation
ON
Open Load
Inverse current
Underload
Don’t care
1)
2)
3)
4)
5)
Don’t care
L
Z
The table doesn’t indicate but it is assumed that the appropriate channel is selected via the DSEL pin.
With additional pull-up resistor.
The output current has to be smaller than IL(OL).
After maximum tINV.
The output current has to be higher than IL(OL).
Data Sheet
PROFET™+ 12V
28
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Diagnostic Functions
7.3
SENSE Signal in the Nominal Current Range
Figure 21 and Figure 22 show the current sense as a function of the load current in the power DMOS. Usually, a
pull-down resistor RIS is connected to the IS pin. This resistor has to be higher than 560 Ω to limit the power losses
in the sense circuitry. A typical value is 1.2 kΩ. The blue curve represents the ideal SENSE, assuming an ideal
kILIS factor value. The red curves show the accuracy the device provides across full temperature range, at a
defined current.
6.0
5.0
IIS =
kilis4
IL
KILIS ideal
I I S [m A]
4.0
K ilis3
3.0
K ilis2
2.0
Kilis1
1.0
0.0
0
1
2
3
4
5
6
I L [A]
7
8
9
10
kilis BTS5030
Figure 21
Current Sense for Nominal Load
7.3.1
SENSE Signal Variation as a Function of Temperature and Load Current
In some applications a better accuracy is required around half the nominal current IL(NOM). To achieve this accuracy
requirement, a calibration on the application is possible. To avoid multiple calibration points at different load and
temperature conditions, the BTS5030-2EKA allows limited derating of the kILIS value, at nominal load current (IL3;
TJ = +25 °C). This derating is described by the parameter ΔkILIS. Figure 22 shows the behavior of the SENSE
current, assuming one calibration point at nominal load at +25 °C.
The blue line indicates the ideal kILIS ratio.
The green lines indicate the derating on the parameter across temperature and voltage, assuming one calibration
point at nominal temperature and nominal battery voltage.
The red lines indicate the kILIS accuracy without calibration.
Data Sheet
PROFET™+ 12V
29
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Diagnostic Functions
4000
3500
k ILIS
3000
2500
Calibration Point
2000
1500
1000
0
1
2
3
4
5
I L [A]
6
7
8
9
10
BTS5030
Figure 22
Improved SENSE Accuracy with One Calibration Point
7.3.2
SENSE Signal Timing
Figure 23 shows the timing during settling and disabling of the SENSE.
VINx
t
IL
t ONx
t OFFx
t ONx
90% of
IL static
t
VDEN
IIS
tsIS(LC)
t sIS(ON)
t sIS(OFF)
90% of
IIS static
t
tsIS(chC)
t sIS(ON_DEN)
t
VDSEL
t
VINy
t
I Ly
t ONy
t
current sense settling disabling time.vsd
Figure 23
SENSE Settling / Disabling Timing
Data Sheet
PROFET™+ 12V
30
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Diagnostic Functions
7.3.3
SENSE Signal in Open Load
7.3.3.1
Open Load in ON Diagnostic
If the channel is ON, a leakage current can still flow through an open load, for example due to humidity. The
parameter IL(OL) gives the threshold of recognition for this leakage current. If the current IL flowing out the power
DMOS is below this value, the device recognizes a failure, if the DEN (and DSEL) is selected. In that case, the
SENSE current is below IIS(OL). Otherwise, the minimum SENSE current is given above parameter IIS(OL).
Figure 24 shows the SENSE current behavior in this area. The red curve shows a typical product curve. The blue
curve shows the ideal kILIS ratio.
I IS
IIS(OL)
IL
IL(OL)
Sense for OL .vsd
Figure 24
Current Sense Ratio for Low Currents
7.3.3.2
Open Load in OFF Diagnostic
For open load diagnosis in OFF-state, an external output pull-up resistor (ROL) is recommended. For the
calculation of pull-up resistor value, the leakage currents and the open load threshold voltage VOL(OFF) have to be
taken into account. Figure 25 gives a sketch of the situation. Ileakage defines the leakage current in the complete
system, including IL(OFF) (see Chapter 5.5) and external leakages, e.g, due to humidity, corrosion, etc.... in the
application.
To reduce the stand-by current of the system, an open load resistor switch SOL is recommended. If the channel x
is OFF, the output is no longer pulled down by the load and VOUT voltage rises to nearly VS. This is recognized by
the device as an open load. The voltage threshold is given by VOL(OFF). In that case, the SENSE signal is switched
to the IIS(FAULT).
An additional RPD resistor can be used to pull VOUT to 0V. Otherwise, the OUT pin is floating. This resistor can be
used as well for short circuit to battery detection, see Chapter 7.3.4.
Data Sheet
PROFET™+ 12V
31
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Diagnostic Functions
Vbat
SOL
VS
IIS(FAULT)
ROL
OL
comp.
OUT
IS
ILOFF
Ileakage
GND
RIS
ZGND
VOL(OFF)
RPD
Rleakage
Open Load in OFF.svg
Figure 25
Open Load Detection in OFF Electrical Equivalent Circuit
7.3.3.3
Open Load Diagnostic Timing
Figure 26 shows the timing during either Open Load in ON or OFF condition when the DEN pin is HIGH. Please
note that a delay tsIS(FAULT_OL_OFF) has to be respected after the falling edge of the input, when applying an open
load in OFF diagnosis request, otherwise the diagnosis can be wrong.
Load is present
Open load
VIN
VOUT
t
VS-VOL(OFF)
RDS(ON) x IL
shutdown with load
t
IOUT
IIS
tsIS(FAULT_OL_OFF)
t
tsIS(LC)
90% of IIIS(FAULT) static
Error Settling Disabling Time.vsd
Figure 26
t
SENSE Signal in Open Load Timing
Data Sheet
PROFET™+ 12V
32
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Diagnostic Functions
7.3.4
SENSE Signal with OUT in Short Circuit to VS
In case of a short circuit between the OUTput-pin and the VS pin, all or portion (depending on the short circuit
impedance) of the load current will flow through the short circuit. As a result, a lower current compared to the
normal operation will flow through the DMOS of the BTS5030-2EKA, which can be recognized at the SENSE
signal. The open load at OFF detection circuitry can also be used to distinguish a short circuit to VS. In that case,
an external resistor to ground RSC_VS is required. Figure 27 gives a sketch of the situation.
Vbat
VS
IIS(FAULT)
VBAT
OL
comp.
IS
OUT
VOL(OFF)
GND
RIS
ZGND
RSC_VS
Short circuit to Vs.svg
Figure 27
Short Circuit to Battery Detection in OFF Electrical Equivalent Circuit
7.3.5
SENSE Signal in Case of Overload
An overload condition is defined by a current flowing out of the DMOS reaching the current limitation and / or the
absolute dynamic temperature swing TJ(SW) is reached, and / or the junction temperature reaches the thermal
shutdown temperature TJ(SC). Please refer to Chapter 6.5 for details.
In that case, the SENSE signal given is by IIS(FAULT) when the diagnostic is selected.
The device has a thermal restart behavior, such that when the overtemperature or the exceed dynamic
temperature condition has disappeared, the DMOS is reactivated if the IN is still at logical level one. If the DEN
pin is activated, and DSEL pin is selected to the correct channel, SENSE is not toggling with the restart mechanism
and remains to IIS(FAULT).
7.3.6
SENSE Signal in Case of Inverse Current
In the case of inverse current, the sense signal of the affected channel will indicate open load in OFF statement
state and indicate open load in ON state. The unaffected channel indicates normal behavior as long as the IINV
current is not exceeding the maximum value specified in Chapter 5.4.
Data Sheet
PROFET™+ 12V
33
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Diagnostic Functions
7.4
Electrical Characteristics Diagnostic Function
Table 9
Electrical Characteristics: Diagnostics
VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified).
Typical values are given at VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note /
Test Condition
–
6
V
Number
Load Condition Threshold for Diagnostic
Open load detection
threshold in OFF state
VS - VOL(OFF) 4
1)
VIN = 0 V
VDEN = 4.5 V
P_7.5.1
See Figure 26
Open load detection
threshold in ON state
IL(OL)
5
–
30
mA
VIN = VDEN = 4.5 V
IIS(OL) = 5.6 μA
P_7.5.2
See Figure 24
See Figure 46
Sense Pin
IS pin leakage current when
sense is disabled
IIS_(DIS)
–
Sense signal saturation
voltage
VS - VIS
0
–
1
–
3
μA
V
(RANGE)
1)
VIN = 4.5 V
P_7.5.4
VDEN = 0 V
IL = IL4 = 7 A
3)
VIN = 0 V
VOUT = VS > 10 V
VDEN = 4.5 V
IIS = 6 mA
P_7.5.6
See Figure 47
Sense signal maximum
current in fault condition
IIS(FAULT)
6
15
35
mA
VIS = VIN = VDSEL = 0 V P_7.5.7
VOUT = VS > 10 V
VDEN = 4.5 V
See Figure 20
See Figure 48
Sense pin maximum voltage
VIS(AZ)
41
47
53
V
IIS = 5 mA
P_7.5.3
See Figure 20
Current Sense Ratio Signal in the Nominal Area, Stable Load Current Condition
kILIS0
-50
2450
+50
%
Current sense ratio
IL1 = 0.5 A
kILIS1
-20
2250
+20
%
Current sense ratio
kILIS2
-8
2185
+8
%
P_7.5.10
kILIS3
-6.5
2185
+6.5
%
P_7.5.11
Current sense ratio
kILIS4
IL4 = 7 A
kILIS derating with current and ΔkILIS
-5.5
2185
+5.5
%
P_7.5.12
-5
0
+5
%
Current sense ratio
IL0 = 50 mA
IL2 = 2 A
Current sense ratio
IL3 = 4 A
temperature
VIN = 4.5 V
VDEN = 4.5 V
P_7.5.8
See Figure 21
P_7.5.9
TJ = -40 °C; 150 °C
3)
kILIS3 versus kILIS2
See Figure 22
P_7.5.17
Diagnostic Timing in Normal Condition
Data Sheet
PROFET™+ 12V
34
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Diagnostic Functions
Table 9
Electrical Characteristics: Diagnostics (cont’d)
VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified).
Typical values are given at VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Current sense settling time to tsIS(ON)
kILIS function stable after
positive input slope on both
INput and DEN
Current sense settling time
with load current stable and
transition of the DEN
tsIS(ON_DEN)
Values
Min.
Typ.
Max.
Unit Note /
Test Condition
0
–
250
μs
3)
VDEN = VIN = 0 to
4.5 V
VS = 13.5 V
RIS = 1.2 kΩ
CSENSE < 100 pF
IL = IL3 = 4 A
See Figure 23
P_7.5.18
0
–
20
μs
1)
P_7.5.19
VIN = 4.5 V
VDEN = 0 to 4.5 V
RIS = 1.2 kΩ
CSENSE < 100 pF
IL = IL3 = 4 A
Number
See Figure 23
Current sense settling time to tsIS(LC)
IIS stable after positive input
slope on current load
0
–
20
μs
1)
P_7.5.20
VIN = 4.5 V
VDEN = 4.5 V
RIS = 1.2 kΩ
CSENSE < 100 pF
IL = IL2 = 2 A to IL = IL3
=4A
See Figure 23
Diagnostic Timing in Open Load Condition
Current sense settling time to tsIS(FAULT_OL_ 0
IIS stable for open load
OFF)
detection in OFF state
–
150
μs
1)
VIN = 0V
VDEN = 0 to 4.5 V
RIS = 1.2 kΩ
CSENSE < 100 pF
VOUT = VS = 13.5 V
P_7.5.22
See Figure 26
Diagnostic Timing in Overload Condition
Current sense settling time to tsIS(FAULT)
IIS stable for overload
detection
Current sense over
temperature blanking time
tsIS(OT_blank)
0
–
250
μs
1) 2)
VIN = VDEN = 0 to
4.5 V
RIS = 1.2 kΩ
CSENSE < 100 pF
VDS = 5 V
See Figure 19
P_7.5.24
–
350
–
μs
3)
P_7.5.32
VIN = VDEN = 4.5 V
RIS = 1.2 kΩ
CSENSE < 100 pF
VDS = 5 V to 0 V
See Figure 19
Data Sheet
PROFET™+ 12V
35
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Diagnostic Functions
Table 9
Electrical Characteristics: Diagnostics (cont’d)
VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified).
Typical values are given at VS = 13.5 V, TJ = 25 °C
Parameter
Diagnostic disable time
DEN transition to
IIS < 50% IL /kILIS
Symbol
tsIS(OFF)
Values
Min.
Typ.
Max.
Unit Note /
Test Condition
0
–
30
μs
1)
VIN = 4.5 V
VDEN = 4.5 V to 0 V
RIS = 1.2 kΩ
CSENSE < 100 pF
IL = IL3 = 4 A
Number
P_7.5.25
See Figure 23
Current sense settling time
from one channel to another
tsIS(ChC)
0
–
20
μs
VIN0 = VIN1 = 4.5 V
VDEN = 4.5 V
VDSEL = 0 to 4.5 V
RIS = 1.2 kΩ
CSENSE < 100 pF
IL(OUT0) = IL3 = 4 A
IL(OUT1) = IL2 = 2 A
P_7.5.26
See Figure 23
1) DSEL pin select channel 0 only.
2) Test at TJ = -40°C only
3) Not subject to production test, specified by design
Data Sheet
PROFET™+ 12V
36
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Input Pins
8
Input Pins
8.1
Input Circuitry
The input circuitry is compatible with 3.3 and 5 V microcontrollers. The concept of the input pin is to react to voltage
thresholds. An implemented Schmidt trigger avoids any undefined state if the voltage on the input pin is slowly
increasing or decreasing. The output is either OFF or ON but cannot be in a linear or undefined state. The input
circuitry is compatible with PWM applications. Figure 28 shows the electrical equivalent input circuitry. In case the
pin is not needed, it must be left opened, or must be connected to device ground (and not module ground) via a
4.7kΩ input resistor.
IN
GND
Figure 28
Input Pin Circuitry
8.2
DEN / DSEL Pin
Input circuitry.vsd
The DEN / DSEL pins enable and disable the diagnostic functionality of the device. The pins have the same
structure as the Input pins, please refer to Figure 28.
8.3
Input Pin Voltage
The IN, DSEL and DEN use a comparator with hysteresis. The switching ON / OFF takes place in a defined region,
set by the thresholds VIN(L) Max. and VIN(H) Min. The exact value where the ON and OFF take place are unknown
and depends on the process, as well as the temperature. To avoid cross talk and parasitic turn ON and OFF, a
hysteresis is implemented. This ensures a certain immunity to noise.
Data Sheet
PROFET™+ 12V
37
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Input Pins
8.4
Electrical Characteristics
Table 10
Electrical Characteristics: Input Pins
VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified).
Typical values are given at VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Min.
Typ.
Unit
Max.
Note /
Test Condition
Number
INput Pins Characteristics
Low level input voltage range VIN(L)
-0.3
–
0.8
V
See Figure 49
P_8.4.1
High level input voltage range VIN(H)
2
–
6
V
See Figure 50
P_8.4.2
P_8.4.3
Input voltage hysteresis
Low level input current
High level input current
VIN(HYS)
IIN(L)
IIN(H)
–
250
–
mV
1)
1
10
25
μA
2
10
25
μA
VIN = 0.8 V
VIN = 5.5 V
See Figure 51
P_8.4.4
P_8.4.5
See Figure 52
DEN Pin
Low level input voltage range VDEN(L)
-0.3
–
0.8
V
–
P_8.4.6
High level input voltage range VDEN(H)
2
–
6
V
–
P_8.4.7
P_8.4.8
–
250
–
mV
1)
1
10
25
μA
P_8.4.9
2
10
25
μA
VDEN = 0.8 V
VDEN = 5.5 V
Low level input voltage range VDSEL(L)
-0.3
–
0.8
V
–
P_8.4.11
High level input voltage range VDSEL(H)
2
–
6
V
–
P_8.4.12
P_8.4.13
P_8.4.14
Input voltage hysteresis
Low level input current
High level input current
VDEN(HYS)
IDEN(L)
IDEN(H)
P_8.4.10
DSEL Pin
Input voltage hysteresis
Low level input current
High level input current
VDSEL(HYS)
IDSEL(L)
IDSEL(H)
–
250
–
mV
1)
1
10
25
μA
2
10
25
μA
VDSEL = 0.8 V
VDSEL = 5.5 V
P_8.4.15
1) Not subject to production test, specified by design
Data Sheet
PROFET™+ 12V
38
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Characterization Results
9
Characterization Results
The characterization have been performed on 3 lots, with 3 devices each. Characterization have been performed
at 8 V, 13.5 V and 18 V, from -40°C to 160°C. When no dependency to voltage is seen, only one curve (13,5V) is
sketched.
9.1
General Product Characteristics
9.1.1
Minimum Functional Supply Voltage
P_4.2.3
VS(OP)_MIN (V)
5
4,6
4,2
3,8
-40
0
40
80
Junction Temp (°C)
120
160
minimum functional supply.vsd
Figure 29
Minimum Functional Supply Voltage VS(OP)_MIN = f(TJ)
9.1.2
Undervoltage Shutdown
P_4.2.4
4
VS(UV) (V)
3,75
3,5
3,25
3
-40
0
40
80
120
160
Junction Temp (°C)
Undervoltage_shutdown.vsd
Figure 30
Undervoltage Threshold VS(UV) = f(TJ)
Data Sheet
PROFET™+ 12V
39
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Characterization Results
9.1.3
Current Consumption One Channel active
P_4.2.5
6
I_GND1 @ 8V
I_GND1 @ 13.5V
I_GND1 (mA)
I_GND1 @ 18V
3
0
-40
0
40
80
120
160
Junction Temp (°C)
Current consumption one channel active.vsd
Figure 31
Current Consumption for Whole Device with Load. One Channel Active IGND_1 = f(TJ;VS)
9.1.4
Current Consumption Two Channels active
P_4.2.6
9
I_GND2 @ 8V
I_GND2 @ 13.5V
I_GND2 (mA)
I_GND2 @ 18V
6
3
0
-40
0
40
80
120
160
Junction Temp (°C)
Current consumption two channel active.vsd
Figure 32
Current Consumption for Whole Device with Load. Two Channels Active IGND_2 = f(TJ;VS)
9.1.5
Standby Current for Whole Device with Load
P_4.2.7, P_4.2.10
Figure 33
Standby Current for Whole Device with Load. IS(OFF) = f(TJ;VS)
Data Sheet
PROFET™+ 12V
40
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Characterization Results
9.2
Power Stage
9.2.1
Output Voltage Drop Limitation at Low Load Current
P_5.5.4
VDS(NL) (mV)
13
11
9
7
-40
0
40
80
120
160
Junction Temp (°C)
Output Voltage drop limitation at low load current.vsd
Figure 34
Output Voltage Drop Limitation at Low Load Current VDS(NL) = f(TJ;VS) ; IL = IL(0) = 50mA
9.2.2
Drain to Source Clamp Voltage
P_5.5.5
VDS(AZ) (V)
52
48
44
40
-40
0
40
80
120
160
Junction Temp (°C)
Drain to source clamp voltage.vsd
Figure 35
Drain to Source Clamp Voltage VDS(AZ) = f(TJ)
Data Sheet
PROFET™+ 12V
41
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Characterization Results
9.2.3
Slew Rate at Turn ON
P_5.5.11
0,5
dV/dt_ON @ 8V
dV/dt_ON @ 13.5V
dV/dt_ON (V/µs)
dV/dt_ON @ 18V
0,3
0,1
-40
0
40
80
120
160
Junction Temp (°C)
dV_dt_ON.vsd
Figure 36
Slew Rate at Turn ON dV/dtON = f(TJ;VS), RL = 4 Ω
9.2.4
Slew Rate at Turn OFF
P_5.5.12
0,5
dV/dt_OFF @ 8V
dV/dt_OFF @ 13.5V
dV/dt_OFF (V/µs)
dV/dt_OFF @ 18V
0,3
0,1
-40
0
40
80
120
160
Junction Temp (°C)
dV_dt_OFF.vsd
Figure 37
Slew Rate at Turn OFF - dV/dtOFF = f(TJ;VS), RL = 4 Ω
9.2.5
Turn ON
P_5.5.14
230
tON 90%@18V
tON 90%@13,5V
t_ON 90% (µs)
tON 90%@8V
130
30
-40
0
40
80
Junction Temp (°C)
Figure 38
120
160
tON_90.vsd
Turn ON tON = f(TJ;VS), RL = 4 Ω
Data Sheet
PROFET™+ 12V
42
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Characterization Results
9.2.6
Turn OFF
P_5.5.11
230
tOFF 10%@18V
tOFF 10%@13,5V
t_OFF 10% (µs)
tOFF 10%@8V
130
30
-40
0
40
80
Junction Temp (°C)
Figure 39
Turn OFF tOFF = f(TJ;VS), RL = 4 Ω
9.2.7
Turn ON / OFF matching
120
160
tOFF_90.vsd
P_5.5.16
50
delta_t_SW @ 8V
delta_t_SW @ 13.5V
delta_t_SW @ 18V
delta t SW (µs)
25
0
-25
-50
-40
0
40
80
120
160
Junction Temp (°C)
delta_t_SW_OFF_ON.vsd
Figure 40
Turn ON / OFF matching ΔtSW = f(TJ;VS), RL = 4 Ω
Data Sheet
PROFET™+ 12V
43
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Characterization Results
9.2.8
Switch ON Energy
P_5.5.19
175 0
S w itc h O N energy @ 18V
S w itc h O N energy @ 13,5V
150 0
S w itc h O N energy @ 8V
E_ON (µJ)
125 0
100 0
75 0
50 0
25 0
0
-40
0
40
80
12 0
1 60
Ju n c tio n T em p (°C )
Figure 41
Switch ON Energy EON = f(TJ;VS), RL = 4 Ω
9.2.9
Switch OFF Energy
P_5.5.20
1 750
S w itc h O N energy @ 18V
S w itc h O N energy @ 13,5V
1 500
S w itc h O N energy @ 8V
E_ON (µJ)
1 250
1 000
750
500
250
0
-40
0
40
80
120
16 0
J un ctio n T em p (°C )
Figure 42
Switch OFF Energy EOFF = f(TJ;VS), RL = 4 Ω
Data Sheet
PROFET™+ 12V
44
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Characterization Results
9.3
Protection Functions
9.3.1
Overload Condition in the Low Voltage Area
P_6.6.4
Figure 43
Overload Condition in the Low Voltage Area IL5(SC) = f(TJ;VS)
9.3.2
Overload Condition in the High Voltage Area
P_6.6.7
Figure 44
Overload Condition in the High Voltage Area IL28(SC) = f(TJ;VS)
Data Sheet
PROFET™+ 12V
45
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Characterization Results
9.4
Diagnostic Mechanism
9.4.1
Current Sense at no Load
2,5
I_IS @ IL = 0mA (µA)
2
1,5
1
0,5
0
-40
0
40
80
Junction Temp (°C)
120
160
Current_sense_0mA.vsd
Figure 45
Current Sense at no Load IL(OL) = f(TJ;VS), IL = 0
9.4.2
Open Load Detection Threshold in ON State
P_7.5.2
Figure 46
Open Load Detection ON State Threshold IL(OL) = f(TJ;VS)
Data Sheet
PROFET™+ 12V
46
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Characterization Results
9.4.3
Sense Signal Maximum Voltage
P_7.5.3
3
VIS _R ANGE @ 8V
VIS _R ANGE @ 13.5V
2
V
S
- V
IS _RANGE
(V)
VIS _R ANGE @ 18V
1
-40
0
40
80
120
160
Junction T em p (°C)
Figure 47
Sense Signal Maximum Voltage VS - VIS(RANGE) =f(TJ;VS)
9.4.4
Sense Signal maximum Current
P_7.5.7
IIS_FAULT @ 8V
IIS_FAULT @ 13.5V
IIS_FAULT (mA)
36
IIS_FAULT @ 18V
26
16
6
-40
0
40
80
120
160
Junction Temp (°C)
IIS_FAULT.vsd
Figure 48
Sense Signal Maximum Current in Fault Condition IIS(FAULT) = f(TJ;VS)
Data Sheet
PROFET™+ 12V
47
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Characterization Results
9.5
Input Pins
9.5.1
Input Voltage Threshold ON to OFF
P_8.4.1
2
I_IN(L) @ 8V
I_IN(L) @ 13.5V
I_IN(L) @ 18V
V_INH(L) (V)
1,5
1
0,5
0
-40
0
40
80
120
160
Junction Temp (°C)
Input_pin_low_voltage.vsd
Figure 49
Input Voltage Threshold VIN(L) = f(TJ;VS)
9.5.2
Input Voltage Threshold OFF to ON
P_8.4.2
2
V_INH(H) (V)
1,5
1
0,5
0
-40
0
40
80
120
160
Junction Temp (°C)
Input_pin_high_voltage.vsd
Figure 50
Input Voltage Threshold VIN(H) = f(TJ;VS)
Data Sheet
PROFET™+ 12V
48
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Characterization Results
9.5.3
Input Voltage Hysteresis
P_8.4.3
400
V_IN(HYS) @ 8V
V_IN(HYS) 13.5V
V_IN(HYS) @ 18V
V_IN(HYS) (mV)
300
200
100
0
-40
0
40
80
120
160
Junction Temp (°C)
Input_pin_voltage_hysteresis.vsd
Figure 51
Input Voltage Hysteresis VIN(HYS) = f(TJ;VS)
9.5.4
Input Current High Level
P_8.4.5
25
I_INH(H) (µA)
20
15
10
5
0
-40
0
40
80
Junction Temp (°C)
Figure 52
120
160
Input_pin_high_current.vsd
Input Current High Level IIN(H) = f(TJ;VS)
Data Sheet
PROFET™+ 12V
49
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Application Information
10
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
VBAT
R/L cable
T1
Z2
CVS
VDD
ROL
Vs
Vdd
OUT
RIN
IN0
OUT
RIN
IN1
R/L cable
OUT0
COUT0
RPD
OUT
RDEN
DEN
OUT
RDSEL
DSEL
Micro controller
R/L cable
OUT1
RA/D
A/D
IS
RSENSE
GND
CSENSE
Z1
RIS
D
RGND
COUT1
RPD
Vss
Application example.svg
Figure 53
Application Diagram with BTS5030-2EKA
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
Table 11
Bill of Material
Reference
Value
Purpose
RIN
4.7 kΩ
Protection of the micro controller during overvoltage, reverse polarity
Guarantee BTS5030-2EKA channels OFF during loss of ground
RDEN
4.7 kΩ
Protection of the micro controller during overvoltage, reverse polarity
Guarantee BTS5030-2EKA channels OFF during loss of ground
RPD
47 kΩ
Polarization of the output
Improve BTS5030-2EKA immunity to electromagnetic noise
RDSEL
4.7 kΩ
Protection of the micro controller during overvoltage, reverse polarity
Guarantee BTS5030-2EKA channels OFF during loss of ground
RIS
1.2 kΩ
Sense resistor
Data Sheet
PROFET™+ 12V
50
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Application Information
Table 11
Bill of Material (cont’d)
Reference
Value
Purpose
RSENSE
4.7 kΩ
Overvoltage, reverse polarity, loss of ground. Value to be tuned with micro
controller specification.
ROL
1.5 kΩ
Ensure polarization of the BTS5030-2EKA output during open load in OFF
diagnostic
RA/D
4.7 kΩ
Protection of the micro controller during overvoltage, reverse polarity
D
BAS21
Protection of the BTS5030-2EKA during reverse polarity
RGND
Z1
Z2
1 kΩ
To keep the device GND at a stable potential during clamping
7 V Zener diode Protection of the micro controller during overvoltage
36 V Zener
diode
Protection of the device during overvoltage
T1
CSENSE
CVS
COUT0
COUT1
BC 807
Switch the battery voltage for open load in OFF diagnostic
100 pF
Sense signal filtering
100 nF
Filtering of the voltage spikes on the battery line
4.7 nF
Protection of the BTS5030-2EKA during ESD and BCI
4.7 nF
Protection of the BTS5030-2EKA during ESD and BCI
10.1
Further Application Information
•
•
•
Please contact us to get the pin FMEA
Existing App. Notes
For further information you may visit http://www.infineon.com/profet
Data Sheet
PROFET™+ 12V
51
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Package Outlines
11
Package Outlines
0.35 x 45˚
0.41±0.09
0˚...8˚
C
2)
0.2
M
0.19 +0.06
0.1 C D 2x
8˚ MAX.
0.08 C
Seating Plane
C A-B D 14x
0˚...8˚
0.64 ±0.25
6 ±0.2
D
0.2
8˚ MAX.
1.27
1.7 MAX.
0.2 -0.1
8˚ MAX.
Stand Off
(1.47)
0.1+0
-0.1
3.9 ±0.11)
M
D
Bottom View
14
8
1
1
7
14
7
8
2.65 ±0.1
6.4 ±0.1
A
B
8.65 ±0.1
Index Marking
0.1 C A-B 2x
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.13 max.
3) JEDEC reference MS-012 variation BB
Figure 54
GPS01207
PG-DSO-14-40 EP (Plastic Dual Small Outline Package) (RoHS-Compliant)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Data Sheet
PROFET™+ 12V
52
Rev. 2.1, 2011-09-01
BTS5030-2EKA
Revision History
12
Revision History
Version
Date
Parameter
2.0
2010-05-31
Creation of the Data Sheet
2.1
2011-09-01
Updated kilis specification and Figure 22 accordingly
change from 2150 +/- 34% to 2250 +/- 20%,
change from 2150 +/-13% to 2185 +/-8%,
change from 2150 +/-9% to 2185 +/-6.5%,
change from 2150 +/-8% to 2185 +/-5.5%
change from 8% to 5%
P_7.5.9
P_7.5.10
P_7.5.11
P_7.5.12
P_7.5.17
Changes
Updated characterisation results; Graphs in chapter 9.3.
switched the 18V and 8V graph in “Figure 33) Standby Current for Whole
Device with Load. IS(OFF) = f(TJ;VS)”
P_4.1.4
Data Sheet
PROFET™+ 12V
adapted the footnote; updated the Legal Disclaimer
53
Rev. 2.1, 2011-09-01
Edition 2011-09-01
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Legal Disclaimer for short-circuit capability
Infineon disclaims any warranties and liabilities, whether expressed nor implied, for any short-circuit failures below
the threshold limit.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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