BTS5090-1EJA

PR OFET™ + 12V BT S5090- 1E J A Smart High-Side Power Switch Single Channel, 90mΩ Data Sheet Rev. 2.2, 2013-09-06 Automotive Power BTS5090-1EJA Table of Contents Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 3.1 3.2 3.3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage and Current Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 4.2 4.3 4.3.1 4.3.2 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PCB set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 5.1 5.2 5.3 5.3.1 5.3.2 5.4 5.5 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output ON-state Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn ON/OFF Characteristics with Resistive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Load Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inverse Current Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 16 16 17 17 19 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.5.2 6.6 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Ground Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Limitation in the Power DMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics for the Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 22 23 23 23 24 26 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.3.1 7.3.3.2 7.3.3.3 7.3.4 7.3.5 7.3.6 7.4 Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal in Different Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal in the Nominal Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal Variation as a Function of Temperature and Load Current . . . . . . . . . . . . . . . . . . . SENSE Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal in Open Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load in ON Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load in OFF Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load Diagnostic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal with OUT in Short Circuit to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal in Case of Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal in Case of Inverse Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Diagnostic Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 28 29 29 30 31 31 31 32 33 33 33 34 8 8.1 8.2 Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DEN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Data Sheet PROFET™+ 12V 2 7 7 7 8 Rev. 2.2, 2013-09-06 BTS5090-1EJA Table of Contents 8.3 8.4 Input Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 9.3 9.3.1 9.3.2 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.5 9.5.1 9.5.2 9.5.3 9.5.4 Characterization Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum Functional Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Consumption Channel active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby Current for Whole Device with Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Drop Limitation at Low Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Drain to Source Clamp Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slew Rate at Turn ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slew Rate at Turn OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn ON / OFF matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch ON Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch OFF Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overload Condition in the Low Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overload Condition in the High Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Sense at no Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load Detection Threshold in ON State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Signal Maximum Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Signal maximum Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage Threshold ON to OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage Threshold OFF to ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Current High Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10.1 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Data Sheet PROFET™+ 12V 3 38 38 38 38 39 39 39 39 40 41 41 41 42 42 43 43 44 44 44 45 45 45 46 46 47 47 47 48 48 Rev. 2.2, 2013-09-06 Smart High-Side Power Switch 1 BTS5090-1EJA Overview Application • • • Suitable for resistive, inductive and capacitive loads Replaces electromechanical relays, fuses and discrete circuits Most suitable for loads with high inrush current, such as lamps Basic Features • • • • • • • • • One channel device Very low stand-by current 3.3 V and 5 V compatible logic inputs Electrostatic discharge protection (ESD) Optimized electromagnetic compatibility Logic ground independent from load ground Very low power DMOS leakage current in OFF state Green product (RoHS compliant) AEC qualified PG-DSO-8-43 EP Description The BTS5090-1EJA is a 90 mΩ single channel Smart High-Side Power Switch, embedded in a PG-DSO-8-43 EP, Exposed Pad package, providing protective functions and diagnosis. The power transistor is built by an N-channel vertical power MOSFET with charge pump. The device is integrated in Smart6 technology. It is specially designed to drive lamps up to 1 * P21W, as well as LEDs in the harsh automotive environment. Table 1 Product Summary Parameter Symbol Value Operating voltage range VS(OP) VS(LD) RDS(ON) IL(NOM) kILIS IL5(SC) IS(OFF) 5 V ... 28 V Maximum supply voltage Maximum ON state resistance at TJ = 150 °C Nominal load current Typical current sense ratio Minimum current limitation Maximum standby current with load at TJ = 25 C 41 V 180 mΩ 3A 1500 20 A 500 nA Type Package Marking BTS5090-1EJA PG-DSO-8-43 EP 5090-EJA Data Sheet PROFET™+ 12V 4 Rev. 2.2, 2013-09-06 BTS5090-1EJA Overview Diagnostic Functions • • • • • • Proportional load current sense Open load in ON and OFF Short circuit to battery and ground Overtemperature Stable diagnostic signal during short circuit Enhanced kILIS dependency with temperature and load current Protection Functions • • • • • • • Stable behavior during undervoltage Reverse polarity protection with external components Secure load turn-off during logic ground disconnect with external components Overtemperature protection with restart Overvoltage protection with external components Voltage dependent current limitation Enhanced short circuit operation Data Sheet PROFET™+ 12V 5 Rev. 2.2, 2013-09-06 BTS5090-1EJA Block Diagram 2 Block Diagram VS voltage sensor internal power supply over temperature driver logic IN ESD protection DEN gate control & charge pump T clamp for inductive load over current switch limit load current sense and open load detection OUT IS forward voltage drop detection GND Figure 1 Block diagram.emf Block Diagram for the BTS5090-1EJA Data Sheet PROFET™+ 12V 6 Rev. 2.2, 2013-09-06 BTS5090-1EJA Pin Configuration 3 Pin Configuration 3.1 Pin Assignment GND 1 8 OUT IN 2 7 OUT DEN 3 6 OUT IS 4 5 NC Pinout Single .vsd Figure 2 Pin Configuration 3.2 Pin Definitions and Functions Pin Symbol Function 1 GND GrouND; Ground connection 2 IN INput channel; Input signal for channel activation 3 DEN Diagnostic ENable; Digital signal to enable/disable the diagnosis of the device 4 IS Sense; Sense current of the selected channel 5 NC Not Connected; No internal connection to the chip 6, 7, 8 OUT OUTput; Protected high side power output channel1) Cooling Tab VS Voltage Supply; Battery voltage 1) All output pins must be connected together on the PCB. All pins of the output are internally connected together. PCB traces have to be designed to withstand the maximum current which can flow. Data Sheet PROFET™+ 12V 7 Rev. 2.2, 2013-09-06 BTS5090-1EJA Pin Configuration 3.3 Voltage and Current Definition Figure 3 shows all terms used in this data sheet, with associated convention for positive values. IS VS VS IIN IN VIN VDS IDEN IOUT DEN OUT VDEN IIS IS VOUT GND VIS IGND voltage and current convention single.vsd Figure 3 Voltage and Current Definition Data Sheet PROFET™+ 12V 8 Rev. 2.2, 2013-09-06 BTS5090-1EJA General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Table 2 Absolute Maximum Ratings 1) TJ = -40°C to +150°C; (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. VS -VS(REV) -0.3 – 28 V – P_4.1.1 0 – 16 V P_4.1.2 VBAT(SC) 0 – 24 V t < 2 min TA = 25 °C RL ≥ 6 Ω RGND = 150 Ω 2) RECU = 20 mΩ RCable= 16 mΩ/m LCable= 1 μH/m, l = 0 or 5 m Supply Voltages Supply voltage Reverse polarity voltage Supply voltage for short circuit protection P_4.1.3 See Chapter 6 and Figure 52 Supply voltage for Load dump VS(LD) protection – – 41 V 3) RI = 2 Ω P_4.1.12 RL = 6 Ω Short Circuit Capability Permanent short circuit IN pin toggles nRSC1 – – 100 2) k cycles tON = 300ms P_4.1.4 VIN -0.3 – – 6 7 V P_4.1.13 Input Pins Voltage at INPUT pin – t < 2 min IIN VDEN -2 – 2 mA – P_4.1.14 Voltage at DEN pin -0.3 – – 6 7 V – t < 2 min P_4.1.15 Current through DEN pin IDEN -2 – 2 mA – P_4.1.16 VIS IIS -0.3 – VS V – P_4.1.19 -25 – 50 mA – P_4.1.20 Load current | IL | – – IL(LIM) A – P_4.1.21 Power dissipation (DC) PTOT – – 1.5 W P_4.1.22 Maximum energy dissipation EAS Single pulse – – 50 mJ TA = 85 °C TJ < 150 °C IL(0) = 3 A TJ(0) = 150 °C VS = 13.5 V P_4.1.23 VDS – – 41 V – P_4.1.26 Current through INPUT pin Sense Pin Voltage at IS pin Current through IS pin Power Stage Voltage at power transistor Data Sheet PROFET™+ 12V 9 Rev. 2.2, 2013-09-06 BTS5090-1EJA General Product Characteristics Table 2 Absolute Maximum Ratings (cont’d)1) TJ = -40°C to +150°C; (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number – P_4.1.27 Min. Typ. Max. -10 -150 – 10 20 mA TJ TSTG -40 – 150 °C – P_4.1.28 -55 – 150 °C – P_4.1.30 VESD VESD -2 – 2 kV 4) HBM P_4.1.31 -4 – 4 kV 4) HBM P_4.1.32 VESD VESD -500 – 500 V 5) CDM P_4.1.33 V 5) CDM P_4.1.34 Currents Current through ground pin I GND t < 2 min Temperatures Junction temperature Storage temperature ESD Susceptibility ESD susceptibility (all pins) ESD susceptibility OUT Pin vs. GND and VS connected ESD susceptibility ESD susceptibility pin (corner pins) -750 – 750 1) Not subject to production test. Specified by design. 2) EOL tests according to AECQ100-012. Threshold limit for short circuit failures: 100 ppm. Please refer to the legal disclaimer for short-circuit capability on page 53 of this document. 3) VS(LD) is setup without the DUT connected to the generator per ISO 7637-1. 4) ESD susceptibility HBM according to EIA/JESD 22-A 114B. 5) “CDM” EIA/JESD22-C101 or ESDA STM5.3.1 Notes 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet PROFET™+ 12V 10 Rev. 2.2, 2013-09-06 BTS5090-1EJA General Product Characteristics 4.2 Functional Range Table 3 Functional Range TJ = -40°C to +150°C; (unless otherwise specified) Parameter Symbol Nominal operating voltage VNOM VS(OP) Extended operating voltage Values Min. Typ. Max. 8 13.5 18 5 – 28 Unit Note / Test Condition Number V – P_4.2.1 V 2) VIN = 4.5 V P_4.2.2 RL = 6 Ω VDS < 0.5 V See Figure 15 Minimum functional supply voltage VS(OP)_MIN 3.8 4.3 5 V 1) VIN = 4.5 V RL = 6 Ω From IOUT = 0 A P_4.2.3 to VDS < 0.5 V; See Figure 15 Undervoltage shutdown VS(UV) 3 3.5 4.1 V 1) VIN = 4.5 V VDEN = 0 V RL = 6 Ω From VDS < 1 V; to IOUT = 0 A P_4.2.4 See Figure 15 See Figure 30 Undervoltage shutdown hysteresis VS(UV)_HYS – 850 – mV 2) Operating current channel active IGND_1 – 3.5 6 mA P_4.2.5 VIN = 5.5 V VDEN = 5.5 V Device in RDS(ON) VS = 18 V Standby current for whole device with load (ambiente) IS(OFF) – 0.1 0.5 μA – P_4.2.13 See Figure 31 1) VS = 18 V P_4.2.7 VOUT = 0 V VIN floating VDEN floating TJ ≤ 85 °C See Figure 32 Maximum standby current for IS(OFF)_150 whole device with load – 3 20 μA VS = 18 V VOUT = 0 V VIN floating VDEN floating TJ = 150 °C P_4.2.10 See Figure 32 Standby current for whole device with load, diagnostic active IS(OFF_DEN) – 0.6 – mA 2) VS = 18 V VOUT = 0 V VIN floating VDEN = 5.5 V P_4.2.8 1) Test at TJ = -40°C only Data Sheet PROFET™+ 12V 11 Rev. 2.2, 2013-09-06 BTS5090-1EJA General Product Characteristics 2) Not subject to production test. Specified by design. Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 Thermal Resistance Table 4 Thermal Resistance Parameter Symbol RthJS RthJA Junction to soldering point Junction to ambient Values Min. Typ. Max. – 5 – – 42 – Unit Note / Test Condition Number K/W 1) P_4.3.1 K/W 1) 2) P_4.3.2 1) Not subject to production test. Specified by design. 2)Specified Rthja value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip + package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70μm Cu, 2 x 35 μm Cu). Where applicable, a thermal via array under the exposed pad contacts the first inner copper layer. Please refer to Figure 4 and Figure 5. 4.3.1 PCB set up 70µm 1.5mm 35µm P CB 2 s2 p. e mf 0.3mm Figure 4 2s2p PCB Cross Section Data Sheet PROFET™+ 12V 12 Rev. 2.2, 2013-09-06 BTS5090-1EJA General Product Characteristics PCB bottom view PCB top view 1 2 3 8 7 COOLING TAB VS 6 4 5 thermique So8.vsd Figure 5 PC Board Top and Bottom View for Thermal Simulation with 600 mm² Cooling Area 4.3.2 Thermal Impedance Figure 6 Typical Thermal Impedance. PCB set up according Figure 5 Data Sheet PROFET™+ 12V 13 Rev. 2.2, 2013-09-06 BTS5090-1EJA General Product Characteristics 100 90 Rthja [K/W] 80 70 60 1s0p 50 40 30 0 footprint Figure 7 100 200 300 400 500 600 700 Area [mm2] Typical Thermal Resistance. PCB set up 1s0p Data Sheet PROFET™+ 12V 14 Rev. 2.2, 2013-09-06 BTS5090-1EJA Power Stage 5 Power Stage The power stage is built using an N-channel vertical power MOSFET (DMOS) with charge pump. 5.1 Output ON-state Resistance The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature TJ. Figure 8 shows the dependencies in terms of temperature and supply voltage for the typical ON-state resistance. The behavior in reverse polarity is described in Chapter 6.4. 200 160 150 140 150 120 RDS(ON)(mΩ) RDS(ON)(mΩ) 130 110 100 90 80 100 50 70 60 50 0 -40 -10 20 50 80 Junction Temperature (Tj) 110 0 140 3 6 9 12 Supply Voltage VS (V) 15 18 Rdson_90.vsd Figure 8 Typical ON-state Resistance A high signal at the input pin (see Chapter 8) causes the power DMOS to switch ON with a dedicated slope, which is optimized in terms of EMC emission. 5.2 Turn ON/OFF Characteristics with Resistive Load Figure 9 shows the typical timing when switching a resistive load. IN VIN_H VIN_L t VOUT dV/dt ON dV/dt 90% VS tOFF_DELAY 70% VS 30% VS OFF t ON tON_DELAY tOFF 10% VS t Switching times.vsd Figure 9 Switching a Resistive Load Timing Data Sheet PROFET™+ 12V 15 Rev. 2.2, 2013-09-06 BTS5090-1EJA Power Stage 5.3 Inductive Load 5.3.1 Output Clamping When switching OFF inductive loads with high side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device by avalanche due to high voltages, there is a voltage clamp mechanism ZDS(AZ) implemented that limits negative output voltage to a certain level (VS - VDS(AZ)). Please refer to Figure 10 and Figure 11 for details. Nevertheless, the maximum allowed load inductance is limited. VS ZDS(AZ) VDS IN LOGIC IL VBAT GND VIN OUT VOUT L, RL ZGND Output clamp.svg Figure 10 Output Clamp IN t V OUT VS t V S-VDS(AZ) IL t Switching an inductance.vsd Figure 11 Switching an Inductive Load Timing Data Sheet PROFET™+ 12V 16 Rev. 2.2, 2013-09-06 BTS5090-1EJA Power Stage 5.3.2 Maximum Load Inductance During demagnetization of inductive loads, energy has to be dissipated in the BTS5090-1EJA. This energy can be calculated with following equation: V S – V DS ( AZ ) RL × IL ⎞ L E = V DS ( AZ ) × ------ × -------------------------------× ln ⎛ 1 – -------------------------------+ IL ⎝ RL RL V S – V DS ( AZ )⎠ (1) Following equation simplifies under the assumption of RL = 0 Ω. VS 2 1 ⎞ E = --- × L × I × ⎛⎝ 1 – -------------------------------2 V S – V DS ( AZ )⎠ (2) The energy, which is converted into heat, is limited by the thermal design of the component. See Figure 12 for the maximum allowed energy dissipation as a function of the load current. EAS [mJ] 1000 100 10 0 1 2 3 IL [A] 4 Figure 12 Maximum Energy Dissipation Single Pulse, TJ_START = 150 °C; VS = 13.5V 5.4 Inverse Current Capability 5 6 EAS90 In case of inverse current, meaning a voltage VINV at the OUTput higher than the supply voltage VS, a current IINV will flow from output to VS pin via the body diode of the power transistor (please refer to Figure 13). The output stage follows the state of the IN pin, except if the IN pin goes from OFF to ON during inverse. In that particular case, the output stage is kept OFF until the inverse current disappears. If the channel is OFF, the diagnostic will detect an open load at OFF. If the channel is ON, the diagnostic will detect open load at ON (the overtemperature signal is inhibited). At the appearance of VINV, a parasitic diagnostic can be observed. After, the diagnosis is valid and reflects the output state. At VINV vanishing, the diagnosis is valid and reflects the output state. During inverse current, no protection functions are available. Data Sheet PROFET™+ 12V 17 Rev. 2.2, 2013-09-06 BTS5090-1EJA Power Stage VBAT VS Gate driver Device logic VINV IL(INV) OL comp. INV Comp. OUT GND ZGND inverse current.svg Figure 13 Inverse Current Circuitry Data Sheet PROFET™+ 12V 18 Rev. 2.2, 2013-09-06 BTS5090-1EJA Power Stage 5.5 Electrical Characteristics Power Stage Table 5 Electrical Characteristics: Power Stage VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter ON-state resistance per channel Symbol RDS(ON)_150 Values Min. Typ. Max. 67 170 180 Unit Note / Test Condition Number mΩ IL = IL4 = 4 A VIN = 4.5 V TJ = 150 °C P_5.5.1 TJ = 25 °C P_5.5.21 TA= 85 °C P_5.5.2 See Figure 8 ON-state resistance per channel RDS(ON)_25 – 90 – mΩ 1) Nominal load current IL(NOM) – 3 – A 1) Output voltage drop limitation VDS(NL) at small load currents – 10 25 mV TJ < 150 °C IL = IL0 = 50 mA P_5.5.4 See Figure 33 Drain to source clamping voltage VDS(AZ) = [VS - VOUT] VDS(AZ) 41 47 53 V IDS = 20 mA See Figure 11 See Figure 34 P_5.5.5 Output leakage currentTJ ≤ 85 °C IL(OFF) – 0.1 0.5 μA 2) P_5.5.6 Output leakage currentTJ = 150 °C IL(OFF)_150 – 1.5 10 μA Inverse current capability IL(INV) dV/dtON – 2.5 – A 0.1 0.25 0.5 V/μs Slew rate 70% to 30% VS -dV/dtOFF 0.1 0.25 0.5 V/μs Slew rate matching dV/dtON - dV/dtOFF ΔdV/dt -0.15 0 0.15 V/μs 30 100 230 μs 30 100 230 μs P_5.5.15 -50 0 50 μs P_5.5.16 10 35 100 μs P_5.5.17 10 35 100 μs P_5.5.18 Slew rate 30% to 70% VS Turn-ON time to VOUT = 90% tON VS Turn-OFF time to VOUT = 10% tOFF VIN floating VOUT = 0 V TJ ≤ 85 °C VIN floating VOUT = 0 V TJ = 150 °C 1) VS < VOUT RL = 6 Ω VS = 13.5 V See Figure 9 See Figure 35 See Figure 36 See Figure 37 See Figure 38 See Figure 39 P_5.5.8 P_5.5.9 P_5.5.11 P_5.5.12 P_5.5.13 P_5.5.14 VS Turn-ON / OFF matching tOFF - tON ΔtSW Turn-ON time to VOUT = 10% tON_delay VS Turn-OFF time to VOUT = 90% tOFF_delay VS Data Sheet PROFET™+ 12V 19 Rev. 2.2, 2013-09-06 BTS5090-1EJA Power Stage Table 5 Electrical Characteristics: Power Stage (cont’d) VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Switch ON energy Symbol EON Values Min. Typ. Max. – 0.8 – Unit Note / Test Condition Number mJ 1) RL = 6 Ω VOUT = 90% VS VS = 18 V P_5.5.19 See Figure 40 Switch OFF energy EOFF – 0.7 – mJ RL = 6 Ω VOUT = 10% VS VS = 18 V 1) P_5.5.20 See Figure 41 1) Not subject to production test, specified by design. 2) Test at TJ = -40°C only Data Sheet PROFET™+ 12V 20 Rev. 2.2, 2013-09-06 BTS5090-1EJA Protection Functions 6 Protection Functions The device provides integrated protection functions. These functions are designed to prevent the destruction of the IC from fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are designed for neither continuous nor repetitive operation. 6.1 Loss of Ground Protection In case of loss of the module ground and the load remains connected to ground, the device protects itself by automatically turning OFF (when it was previously ON) or remains OFF, regardless of the voltage applied on IN pin. In case of loss of device ground, it’s recommended to use input resistors between the microcontroller and the BTS5090-1EJA to ensure switching OFF of channel. In case of loss of module or device ground, a current (IOUT(GND)) can flow out of the DMOS. Figure 14 sketches the situation. ZGND can be either resistor or diode. VS ZIS(AZ) ZD(AZ) IS RSENSE VBAT ZDS(AZ) DEN RDEN IN RIN IOUT(GND) LOGIC OUT ZDESD GND RIS ZGND Loss of ground protection single.svg Figure 14 Loss of Ground Protection with External Components 6.2 Undervoltage Protection Between VS(UV) and VS(OP), the undervoltage mechanism is triggered. VS(OP) represents the minimum voltage where the switching ON and OFF can takes place. VS(UV) represents the minimum voltage the switch can hold ON. If the supply voltage is below the undervoltage mechanism VS(UV), the device is OFF (turns OFF). As soon as the supply voltage is above the undervoltage mechanism VS(OP), then the device can be switched ON. When the switch is ON, protection functions are operational. Nevertheless, the diagnosis is not guaranteed until VS is in the VNOM range. Figure 15 sketches the undervoltage mechanism. Data Sheet PROFET™+ 12V 21 Rev. 2.2, 2013-09-06 BTS5090-1EJA Protection Functions VOUT undervoltage behavior .vsd VS(UV) Figure 15 Undervoltage Behavior 6.3 Overvoltage Protection VS(OP) VS There is an integrated clamp mechanism for overvoltage protection (ZD(AZ)). To guarantee this mechanism operates properly in the application, the current in the Zener diode has to be limited by a ground resistor. Figure 16 shows a typical application to withstand overvoltage issues. In case of supply voltage higher than VS(AZ), the power transistor switches ON and the voltage across the logic section is clamped. As a result, the internal ground potential rises to VS - VS(AZ). Due to the ESD Zener diodes, the potential at pin IN and DEN rises almost to that potential, depending on the impedance of the connected circuitry. In the case the device was ON, prior to overvoltage, the BTS5090-1EJA remains ON. In the case the BTS5090-1EJA was OFF, prior to overvoltage, the power transistor can be activated. In the case the supply voltage is in above VBAT(SC) and below VDS(AZ), the output transistor is still operational and follows the input. If the channel is in the ON state, parameters are no longer guaranteed and lifetime is reduced compared to the nominal supply voltage range. This especially impacts the short circuit robustness, as well as the maximum energy EAS capability. ZGND as a resistor (150 Ω) will offer superior results compared to a diode and resistor (1 kΩ). ISOV ZIS(AZ) VS IN1 ZD(AZ) IS RSENSE VBAT ZDS(AZ) DEN RDEN IN RIN LOGIC IN0 OUT ZDESD GND RIS ZGND Figure 16 Overvoltage Protection with External Components Data Sheet PROFET™+ 12V 22 Rev. 2.2, 2013-09-06 BTS5090-1EJA Protection Functions 6.4 Reverse Polarity Protection In case of reverse polarity, the intrinsic body diodes of the power DMOS causes power dissipation. The current in this intrinsic body diode is limited by the load itself. Additionally, the current into the ground path and the logic pins has to be limited to the maximum current described in Chapter 4.1 with an external resistor. Figure 17 shows a typical application. RGND resistor is used to limit the current in the Zener protection of the device. Resistors RDEN and RIN are used to limit the current in the logic of the device and in the ESD protection stage. RSENSE is used to limit the current in the sense transistor which behaves as a diode. The recommended value for RDEN = RIN = RSENSE = 4.7 kΩ. ZGND can be either a 150 Ω resistor or Schottky diode with 1 kΩ resistor in parallel. In case the overvoltage is not considered in the application, RGND can be replaced by a Schottky diode and 1kΩ resistor in parallel. Optionally a capacitor in parallel is recommended for EMC reasons. During reverse polarity, no protection functions are available. ZIS(AZ) Micro controller protection diodes VS ZD(AZ) IS RSENSE ZDS(AZ) VDS(REV) DEN RDEN IN RIN LOGIC -VS(REV) IN0 OUT ZDESD GND ZGND RIS Reverse Polarity single.svg Figure 17 Reverse Polarity Protection with External Components 6.5 Overload Protection In case of overload, such as high inrush of cold lamp filament, or short circuit to ground, the BTS5090-1EJA offers several protection mechanisms. 6.5.1 Current Limitation At first step, the instantaneous power in the switch is maintained at a safe value by limiting the current to the maximum current allowed in the switch IL(SC). During this time, the DMOS temperature is increasing, which affects the current flowing in the DMOS. The current limitation value is VDS dependent. Figure 18 shows the behavior of the current limitation as a function of the drain to source voltage. Data Sheet PROFET™+ 12V 23 Rev. 2.2, 2013-09-06 BTS5090-1EJA Protection Functions Figure 18 Current Limitation (typical behavior) 6.5.2 Temperature Limitation in the Power DMOS The channel incorporates both an absolute (TJ(SC)) and a dynamic (TJ(SW)) temperature sensor. Activation of either sensor will cause an overheated channel to switch OFF to prevent destruction. Any protective switch OFF latches the output until the temperature has reached an acceptable value. Figure 19 gives a sketch of the situation. The ΔTSTEP describes the device’s warming, due to the overcurrent in the channel. A retry strategy is implemented such that when the DMOS temperature has cooled down enough, the switch is switched ON again, if the IN pin signal is still high (restart behavior). Data Sheet PROFET™+ 12V 24 Rev. 2.2, 2013-09-06 BTS5090-1EJA Protection Functions IN t IL LOAD CURRENT LIMITATION PHASE IL(x)SC LOAD CURRENT BELOW LIMITATION PHASE IL(NOM) t TDMOS ΔTJ(SW) TJ(SC) ΔTJ(SW) ΔTJ(SW) TA tsIS(FAULT) t ΔTSTEP IIS tsIS(OT_blank) IIS(FAULT) IL( NOM) / kILIS 0A V DEN t tsIS(OFF) 0V t Hard start.vsd Figure 19 Overload Protection Note: For better understanding, the time scale is not linear. The real timing of this drawing is application dependant and cannot be described. Data Sheet PROFET™+ 12V 25 Rev. 2.2, 2013-09-06 BTS5090-1EJA Protection Functions 6.6 Electrical Characteristics for the Protection Functions Table 6 Electrical Characteristics: Protection VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. – 0.1 – mA 1) 2) VS = 28 V See Figure 14 P_6.6.1 200 650 700 mV IL = - 2 A TJ = 150 °C P_6.6.2 Loss of Ground Output leakage current while IOUT(GND) GND disconnected Reverse Polarity Drain source diode voltage during reverse polarity VDS(REV) See Figure 17 Overvoltage Overvoltage protection VS(AZ) 41 47 53 V ISOV = 5 mA P_6.6.3 See Figure 16 Overload Condition Load current limitation IL5(SC) 20 30 40 A 3) VDS = 5 V See Figure 18 and Figure 42 P_6.6.4 Load current limitation IL28(SC) – 15 – A 2) VDS = 28 V See Figure 18 and Figure 43 P_6.6.7 Short circuit current during over temperature toggling IL(RMS) – 3 – A 2) VIN = 4.5 V RSHORT = 100 mΩ LSHORT = 5 μH P_6.6.12 Dynamic temperature increase while switching ΔTJ(SW) – 80 – K 4) See Figure 19 P_6.6.8 Thermal shutdown temperature TJ(SC) 150 170 4) 200 4) °C 5) See Figure 19 P_6.6.10 20 – K 5) 4) Thermal shutdown hysteresis ΔTJ(SC) – 1) All pins are disconnected except VS and OUT. 2) 3) 4) 5) See Figure 19 P_6.6.11 Not Subject to production test, specified by design Test at TJ = -40°C only Functional test only Test at TJ = +150°C only Data Sheet PROFET™+ 12V 26 Rev. 2.2, 2013-09-06 BTS5090-1EJA Diagnostic Functions 7 Diagnostic Functions For diagnosis purpose, the BTS5090-1EJA provides a combination of digital and analog signals at pin IS. These signals are called SENSE. In case the diagnostic is disabled via DEN, pin IS becomes high impedance. In case DEN is activated, the SENSE of the channel is enabled. 7.1 IS Pin The BTS5090-1EJA provides a SENSE current written IIS at pin IS. As long as no “hard” failure mode occurs (short circuit to GND / current limitation / overtemperature / excessive dynamic temperature increase or open load at OFF) a proportional signal to the load current (ratio kILIS = IL / IIS) is provided. The complete IS pin and diagnostic mechanism is described on Figure 20. The accuracy of the SENSE depends on temperature and load current. Vs FAULT IIS(FAULT) IIS = IL / kILIS ZIS(AZ) 1 1 IS 0 0 DEN Sense schematic single.svg Figure 20 Diagnostic Block Diagram Data Sheet PROFET™+ 12V 27 Rev. 2.2, 2013-09-06 BTS5090-1EJA Diagnostic Functions 7.2 SENSE Signal in Different Operating Modes Table 7 gives a quick reference for the state of the IS pin during device operation. Table 7 Sense Signal, Function of Operation Mode Operation Mode Input level Channel X DEN Normal operation OFF H Output Level Diagnostic Output Z Z Short circuit to GND ~ GND Z Overtemperature Z Z Short circuit to VS IIS(FAULT) Current limitation VS < VOL(OFF) > VOL(OFF)1) ~ VINV ~ VS < VS Short circuit to GND ~ GND Overtemperature TJ(SW) event Z IIS(FAULT) IIS(FAULT) IIS = IL / kILIS IIS(FAULT) IIS(FAULT) IIS(FAULT) Short circuit to VS VS ~ VS2) ~ VINV ~ VS4) IIS < IL / kILIS IIS < IIS(OL) IIS < IIS(OL)3) IIS(OL) < IIS < IL(nom) / kILIS Don’t care Z Open Load Inverse current Normal operation ON Open Load Inverse current Underload Don’t care 1) 2) 3) 4) Don’t care L Z Stable with additional pull-up resistor. The output current has to be smaller than IL(OL). After maximum tINV. The output current has to be higher than IL(OL). Data Sheet PROFET™+ 12V 28 Rev. 2.2, 2013-09-06 BTS5090-1EJA Diagnostic Functions 7.3 SENSE Signal in the Nominal Current Range Figure 21 and Figure 22 show the current sense as a function of the load current in the power DMOS. Usually, a pull-down resistor RIS is connected to the IS pin. This resistor has to be higher than 560 Ω to limit the power losses in the sense circuitry. A typical value is 1.2 kΩ. The blue curve represents the ideal SENSE, assuming an ideal kILIS factor value. The red curves show the accuracy the device provides across full temperature range, at a defined current. 4 3.5 3 IIS [mA] 2.5 2 1.5 1 0.5 min/max Sense Current typical Sense Current 0 0 0.5 1 1.5 2 2.5 IL [A] 3 3.5 4 4.5 5 BTS5090-1EJA Figure 21 Current Sense for Nominal Load 7.3.1 SENSE Signal Variation as a Function of Temperature and Load Current In some applications a better accuracy is required around half the nominal current IL(NOM). To achieve this accuracy requirement, a calibration on the application is possible. To avoid multiple calibration points at different load and temperature conditions, the BTS5090-1EJA allows limited derating of the kILIS value, at a given point (IL3; TJ = +25 °C). This derating is described by the parameter ΔkILIS. Figure 22 shows the behavior of the SENSE current, assuming one calibration point at nominal load at +25 °C. The blue line indicates the ideal kILIS ratio. The green lines indicate the derating on the parameter across temperature and voltage, assuming one calibration point at nominal temperature and nominal battery voltage. The red lines indicate the kILIS accuracy without calibration. Data Sheet PROFET™+ 12V 29 Rev. 2.2, 2013-09-06 BTS5090-1EJA Diagnostic Functions 2600 calibrated kILIS 2400 min/max k ILIS typical kILIS 2200 2000 kILIS 1800 1600 1400 1200 1000 800 0 0.5 1 1.5 2 2.5 IL [A] 3 3.5 4 4.5 5 BTS5090-1EJA Figure 22 Improved Current SENSE Accuracy with One Calibration Point at 1A 7.3.2 SENSE Signal Timing Figure 23 shows the timing during settling and disabling of the SENSE. VIN t IL t ON 90% of I L static t V DEN t IIS TsIS(ON) TsIS(LC) tsIS(OFF) 90% of I IS static TsIS(ON) current sense settling disabling time single.vsd Figure 23 t SENSE Settling / Disabling Timing Data Sheet PROFET™+ 12V 30 Rev. 2.2, 2013-09-06 BTS5090-1EJA Diagnostic Functions 7.3.3 SENSE Signal in Open Load 7.3.3.1 Open Load in ON Diagnostic If the channel is ON, a leakage current can still flow through an open load, for example due to humidity. The parameter IL(OL) gives the threshold of recognition for this leakage current. If the current IL flowing out the power DMOS is below this value, the device recognizes a failure, if the DEN is selected. In that case, the SENSE current is below IIS(OL). Otherwise, the minimum SENSE current is given above parameter IIS(OL). Figure 24 shows the SENSE current behavior in this area. The red curve shows a typical product curve. The blue curve shows the ideal kILIS ratio. I IS IIS(OL) IL IL(OL) Sense for OL .vsd Figure 24 Current Sense Ratio for Low Currents 7.3.3.2 Open Load in OFF Diagnostic For open load diagnosis in OFF-state, an external output pull-up resistor (ROL) is recommended. For the calculation of pull-up resistor value, the leakage currents and the open load threshold voltage VOL(OFF) have to be taken into account. Figure 25 gives a sketch of the situation. Ileakage defines the leakage current in the complete system, including IL(OFF) (see Chapter 5.5) and external leakages, e.g, due to humidity, corrosion, etc.... in the application. To reduce the stand-by current of the system, an open load resistor switch SOL is recommended. If the channel is OFF, the output is no longer pulled down by the load and VOUT voltage rises to nearly VS. This is recognized by the device as an open load. The voltage threshold is given by VOL(OFF). In that case, the SENSE signal is switched to the IIS(FAULT). An additional RPD resistor can be used to pull VOUT to 0V. Otherwise, the OUT pin is floating. This resistor can be used as well for short circuit to battery detection, see Chapter 7.3.4. Data Sheet PROFET™+ 12V 31 Rev. 2.2, 2013-09-06 BTS5090-1EJA Diagnostic Functions Vbat SOL VS IIS(FAULT) ROL OL comp. OUT IS ILOFF Ileakage GND RIS ZGND RPD VOL(OFF) Rleakage Open Load in OFF.svg Figure 25 Open Load Detection in OFF Electrical Equivalent Circuit 7.3.3.3 Open Load Diagnostic Timing Figure 26 shows the timing during either Open load in ON or OFF condition. Please note that a delay tsIS(OT_BLANK) has to be respected between the falling edge of the input and rising edge of the DEN, when applying an open load in OFF diagnosis request, otherwise the voltage VOUT cannot be guaranteed and the diagnosis can be wrong. Load is present Open load VIN t VOUT V S-VOL(OFF) RDSON x IL shutdown with load t IOUT VDEN tsIS(OT_BLANK) t IIS tsIS(FAULT_OL_OFF) tsIS(LC) 90% of IIIS(FAULT) static t Error Settling Disabling Time.vsd Figure 26 SENSE Signal in Open Load Timing Data Sheet PROFET™+ 12V 32 Rev. 2.2, 2013-09-06 BTS5090-1EJA Diagnostic Functions 7.3.4 SENSE Signal with OUT in Short Circuit to VS In case of a short circuit between the OUTput-pin and the VS pin, all or portion (depending on the short circuit impedance) of the load current will flow through the short circuit. As a result, a lower current compared to the normal operation will flow through the DMOS of the BTS5090-1EJA, which can be recognized at the SENSE signal. The open load at OFF detection circuitry can also be used to distinguish a short circuit to VS. In that case, an external resistor to ground RSC_VS is required. Figure 27 gives a sketch of the situation. Vbat VS IIS(FAULT) VBAT OL comp. IS OUT VOL(OFF) GND RIS ZGND RSC_VS Short circuit to Vs.svg Figure 27 Short Circuit to Battery Detection in OFF Electrical Equivalent Circuit 7.3.5 SENSE Signal in Case of Overload An overload condition is defined by a current flowing out of the DMOS reaching the current limitation and / or the absolute dynamic temperature swing TJ(SW) is reached, and / or the junction temperature reaches the thermal shutdown temperature TJ(SC). Please refer to Chapter 6.5 for details. In that case, the SENSE signal given is by IIS(FAULT) when the diagnostic is selected. The device has a thermal restart behavior, such that when the overtemperature or the exceed dynamic temperature condition has disappeared, the DMOS is reactivated if the IN is still at logical level one. If the DEN pin is activated, the IS pin is not toggling with the restart mechanism and remains to IIS(FAULT). 7.3.6 SENSE Signal in Case of Inverse Current In the case of inverse current, the channel will indicate open load in OFF state and indicate open load in ON state. Data Sheet PROFET™+ 12V 33 Rev. 2.2, 2013-09-06 BTS5090-1EJA Diagnostic Functions 7.4 Electrical Characteristics Diagnostic Function Table 8 Electrical Characteristics: Diagnostics VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Load Condition Threshold for Diagnostic Open load detection threshold in OFF state VS - VOL(OFF) 4 – 6 V Open load detection threshold in ON state IL(OL) – 30 mA 5 VIN = 0 V VDEN = 4.5 V VIN = VDEN = 4.5 V IIS(OL) = 8 μA P_7.5.1 P_7.5.2 See Figure 24 See Figure 45 Sense Pin IS pin leakage current when sense is disabled IIS_(DIS) – – 1 μA Sense signal saturation voltage VS - VIS 0 – 3 V Sense signal maximum current in fault condition IIS(FAULT) 6 15 35 mA (RANGE) VIN = 4.5 V VDEN = 0 V IL = IL4 = 4 A VIN = 0 V VOUT = VS > 10 V VDEN = 4.5 V IIS = 6 mA P_7.5.4 P_7.5.6 See Figure 46 VIS = VIN = VDSEL = 0 V P_7.5.7 VOUT = VS > 10 V VDEN = 4.5 V See Figure 20 See Figure 47 Sense pin maximum voltage VIS(AZ) 41 47 53 V IIS = 5 mA P_7.5.3 See Figure 20 Current Sense Ratio Signal in the Nominal Area, Stable Load Current Condition Current sense ratio IL0 = 50 mA kILIS0 -50% 1650 +50% VIN = 4.5 V VDEN = 4.5 V P_7.5.8 Current sense ratio IL1 = 0.5 A kILIS1 -16% 1460 +16% See Figure 21 P_7.5.9 Current sense ratio kILIS2 -10% 1460 +10% P_7.5.10 kILIS3 -7% 1460 +7% P_7.5.11 -6.5% 1460 +6.5% P_7.5.12 -5 0 +5 TJ = -40 °C; 150 °C IL2 = 1 A Current sense ratio IL3 = 2 A Current sense ratio kILIS4 IL4 = 4 A kILIS derating with current and ΔkILIS temperature % 1) kILIS3 versus kILIS2 See Figure 22 P_7.5.17 Diagnostic Timing in Normal Condition Data Sheet PROFET™+ 12V 34 Rev. 2.2, 2013-09-06 BTS5090-1EJA Diagnostic Functions Table 8 Electrical Characteristics: Diagnostics (cont’d) VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Current sense settling time to tsIS(ON) kILIS function stable after positive input slope on both INput and DEN Values Min. Typ. Max. Unit Note / Test Condition 0 – 250 μs Number 1) VDEN=VIN= 0 to 4.5 V P_7.5.18 VS = 13.5 V RIS = 1.2 kΩ CSENSE < 100 pF IL = IL3 = 2 A See Figure 23 Current sense settling time with load current stable and transition of the DEN tsIS(ON_DEN) 0 – 20 μs 0 – 20 μs VIN = 4.5 V VDEN = 0 to 4.5 V RIS = 1.2 kΩ CSENSE < 100 pF IL = IL3 = 2 A P_7.5.19 See Figure 23 Current sense settling time to tsIS(LC) IIS stable after positive input slope on current load VIN = 4.5 V VDEN = 4.5 V RIS = 1.2 kΩ CSENSE < 100 pF IL = 1 A to IL = 2 A P_7.5.20 See Figure 23 Diagnostic Timing in Open Load Condition Current sense settling time to tsIS(FAULT_OL_ 0 IIS stable for open load OFF) detection in OFF state – 150 μs VIN = 0V VDEN = 0 to 4.5 V RIS = 1.2 kΩ CSENSE < 100 pF VOUT = VS = 13.5 V P_7.5.22 See Figure 26 Diagnostic Timing in Overload Condition Current sense settling time to tsIS(FAULT) IIS stable for overload detection 0 – 250 μs VIN = VDEN = 0 to 4.5 V P_7.5.24 RIS = 1.2 kΩ CSENSE < 100 pF VDS = 5 V See Figure 19 Current sense over temperature blanking time tsIS(OT_blank) – 350 – μs 1) VIN = VDEN = 4.5 V P_7.5.32 RIS = 1.2 kΩ CSENSE < 100 pF VDS = 5 V to 0 V See Figure 19 Diagnostic disable time DEN transition to IIS < 50% IL /kILIS tsIS(OFF) 0 – 30 μs VIN = 4.5 V VDEN = 4.5 V to 0 V RIS = 1.2 kΩ CSENSE < 100 pF IL = IL3 = 2 A P_7.5.25 See Figure 23 1) Not subject to production test, specified by design Data Sheet PROFET™+ 12V 35 Rev. 2.2, 2013-09-06 BTS5090-1EJA Input Pins 8 Input Pins 8.1 Input Circuitry The input circuitry is compatible with 3.3 and 5 V microcontrollers. The concept of the input pin is to react to voltage thresholds. An implemented Schmidt trigger avoids any undefined state if the voltage on the input pin is slowly increasing or decreasing. The output is either OFF or ON but cannot be in a linear or undefined state. The input circuitry is compatible with PWM applications. Figure 28 shows the electrical equivalent input circuitry. In case the pin is not needed, it must be left opened, or must be connected to device ground (and not module ground) via an input resistor. IN GND Figure 28 Input Pin Circuitry 8.2 DEN Pin Input circuitry.vsd The DEN pin enables and disables the diagnostic functionality of the device. The pin has the same structure as the INput pin, please refer to Figure 28. 8.3 Input Pin Voltage The IN and DEN use a comparator with hysteresis. The switching ON / OFF takes place in a defined region, set by the thresholds VIN(L) Max. and VIN(H) Min. The exact value where the ON and OFF take place are unknown and depends on the process, as well as the temperature. To avoid cross talk and parasitic turn ON and OFF, a hysteresis is implemented. This ensures a certain immunity to noise. Data Sheet PROFET™+ 12V 36 Rev. 2.2, 2013-09-06 BTS5090-1EJA Input Pins 8.4 Electrical Characteristics Table 9 Electrical Characteristics: Input Pins VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Min. Typ. Unit Max. Note / Test Condition Number INput Pins Characteristics Low level input voltage range VIN(L) -0.3 – 0.8 V See Figure 48 P_8.4.1 High level input voltage range VIN(H) 2 – 6 V See Figure 49 P_8.4.2 P_8.4.3 Input voltage hysteresis Low level input current High level input current VIN(HYS) IIN(L) IIN(H) – 250 – mV 1) 1 10 25 μA 2 10 25 μA VIN = 0.8 V VIN = 5.5 V See Figure 50 P_8.4.4 P_8.4.5 See Figure 51 DEN Pin Low level input voltage range VDEN(L) -0.3 – 0.8 V – P_8.4.6 High level input voltage range VDEN(H) 2 – 6 V – P_8.4.7 P_8.4.8 P_8.4.9 Input voltage hysteresis Low level input current High level input current VDEN(HYS) IDEN(L) IDEN(H) – 250 – mV 1) 1 10 25 μA 2 10 25 μA VDEN = 0.8 V VDEN = 5.5 V P_8.4.10 1) Not subject to production test, specified by design Data Sheet PROFET™+ 12V 37 Rev. 2.2, 2013-09-06 BTS5090-1EJA Characterization Results 9 Characterization Results The characterization have been performed on 3 lots, with 3 devices each. Characterization have been performed at 8 V, 13.5 V and 18 V over temperature range. When no dependency to voltage is seen, only one curve (13,5V) is sketched. 9.1 General Product Characteristics 9.1.1 Minimum Functional Supply Voltage P_4.2.3 VS(OP)_MIN (V) 5 4,6 4,2 3,8 -40 0 40 80 Junction Temp (°C) 120 160 minimum functional supply.vsd Figure 29 Minimum Functional Supply Voltage VS(OP)_MIN = f(TJ) 9.1.2 Undervoltage Shutdown P_4.2.4 4 VS(UV) (V) 3,75 3,5 3,25 3 -40 0 40 80 120 160 Junction Temp (°C) Undervoltage_shutdown.vsd Figure 30 Undervoltage Threshold VS(UV) =f(TJ) Data Sheet PROFET™+ 12V 38 Rev. 2.2, 2013-09-06 BTS5090-1EJA Characterization Results 9.1.3 Current Consumption Channel active P_4.2.5 6 I_GND1 @ 8V I_GND1 @ 13.5V I_GND1 (mA) I_GND1 @ 18V 3 0 -40 0 40 80 120 160 Junction Temp (°C) Current consumption one channel active.vsd Figure 31 Current Consumption for Whole Device with Load, Channel Active IGND_1 = f(TJ;VS) 9.1.4 Standby Current for Whole Device with Load P_4.2.7, P_4.2.10 6.00 IS(OFF) @ 18V IS(OFF) @ 13.5V IS(OFF) (µA) IS(OFF) @ 8V 3.00 0.00 -40 0 40 80 120 160 Junction Te m p (°C) Figure 32 Standby Current for Whole Device with Load. IS(OFF) = f(TJ;VS) 9.2 Power Stage 9.2.1 Output Voltage Drop Limitation at Low Load Current P_5.5.4 Data Sheet PROFET™+ 12V 39 Rev. 2.2, 2013-09-06 BTS5090-1EJA Characterization Results 13 VDS(NL) (mV) 11 9 7 -40 0 40 80 120 160 Junction Temp (°C) Output Voltage drop limitation at low load current.vsd Figure 33 Output Voltage Drop Limitation at Low Load Current VDS(NL) = f(TJ;VS) 9.2.2 Drain to Source Clamp Voltage P_5.5.5 VDS(AZ) (V) 52 48 44 40 -40 0 40 80 120 160 Junction Temp (°C) Drain to source clamp voltage.vsd Figure 34 Drain to Source Clamp Voltage VDS(AZ) = f(TJ) Data Sheet PROFET™+ 12V 40 Rev. 2.2, 2013-09-06 BTS5090-1EJA Characterization Results 9.2.3 Slew Rate at Turn ON P_5.5.11 0,5 dV/dt_ON @ 8V dV/dt_ON @ 13.5V dV/dt_ON (V/µs) dV/dt_ON @ 18V 0,3 0,1 -40 0 40 80 120 160 Junction Temp (°C) dV_dt_ON.vsd Figure 35 Slew Rate at Turn ON dV/dtON = f(TJ;VS), RL = 6 Ω 9.2.4 Slew Rate at Turn OFF P_5.5.12 0,5 dV/dt_OFF @ 8V dV/dt_OFF @ 13.5V dV/dt_OFF (V/µs) dV/dt_OFF @ 18V 0,3 0,1 -40 0 40 80 120 160 Junction Temp (°C) dV_dt_OFF.vsd Figure 36 Slew Rate at Turn OFF - dV/dtOFF = f(TJ;VS), RL = 6 Ω 9.2.5 Turn ON P_5.5.14 230 tON 90%@18V tON 90%@13,5V t_ON 90% (µs) tON 90%@8V 130 30 -40 0 40 80 Junction Temp (°C) Figure 37 120 160 tON_90.vsd Turn ON tON = f(TJ;VS), RL = 6 Ω Data Sheet PROFET™+ 12V 41 Rev. 2.2, 2013-09-06 BTS5090-1EJA Characterization Results 9.2.6 Turn OFF P_5.5.11 230 tOFF 10%@18V tOFF 10%@13,5V t_OFF 10% (µs) tOFF 10%@8V 130 30 -40 0 40 80 Junction Temp (°C) Figure 38 Turn OFF tOFF = f(TJ;VS), RL = 6 Ω 9.2.7 Turn ON / OFF matching 120 160 tOFF_90.vsd P_5.5.16 50 delta_t_SW @ 8V delta_t_SW @ 13.5V delta_t_SW @ 18V delta t SW (µs) 25 0 -25 -50 -40 0 40 80 120 160 Junction Temp (°C) delta_t_SW_OFF_ON.vsd Figure 39 Turn ON / OFF matching ΔtSW = f(TJ;VS), RL = 6 Ω Data Sheet PROFET™+ 12V 42 Rev. 2.2, 2013-09-06 BTS5090-1EJA Characterization Results 9.2.8 Switch ON Energy P_5.5.19 1000 S w itc h O N energy @ 18V S w itc h O N energy @ 13,5V S w itc h O N energy @ 8V E_ON (µJ) 750 500 250 0 -40 0 40 80 120 160 J u n c tio n T em p (°C ) Figure 40 Switch ON Energy EON = f(TJ;VS), RL = 6 Ω 9.2.9 Switch OFF Energy P_5.5.20 1000 S w itc h O N energy @ 18V S w itc h O N energy @ 13,5V S w itc h O N energy @ 8V E_ON (µJ) 750 500 250 0 -4 0 0 40 80 120 160 J u n c tio n T e m p (°C ) Figure 41 Switch OFF Energy EOFF = f(TJ;VS), RL = 6 Ω Data Sheet PROFET™+ 12V 43 Rev. 2.2, 2013-09-06 BTS5090-1EJA Characterization Results 9.3 Protection Functions 9.3.1 Overload Condition in the Low Voltage Area P_6.6.4 Figure 42 Overload Condition in the Low Voltage Area IL5(SC) = f(TJ;VS) 9.3.2 Overload Condition in the High Voltage Area P_6.6.7 Figure 43 Overload Condition in the High Voltage Area IL28(SC) = f(TJ;VS) Data Sheet PROFET™+ 12V 44 Rev. 2.2, 2013-09-06 BTS5090-1EJA Characterization Results 9.4 Diagnostic Mechanism 9.4.1 Current Sense at no Load 2,5 I_IS @ IL = 0mA (µA) 2 1,5 1 0,5 0 -40 0 40 80 Junction Temp (°C) 120 160 Current_sense_0mA.vsd Figure 44 Current Sense at no Load IIS = f(TJ;VS), IL = 0 9.4.2 Open Load Detection Threshold in ON State P_7.5.2 Figure 45 Open Load Detection ON State Treshold IL(OL) = f(TJ;VS) Data Sheet PROFET™+ 12V 45 Rev. 2.2, 2013-09-06 BTS5090-1EJA Characterization Results 9.4.3 Sense Signal Maximum Voltage P_7.5.3 3 VIS _R ANGE @ 8V VIS _R ANGE @ 13.5V 2 V S - V IS _RANGE (V) VIS _R ANGE @ 18V 1 -40 0 40 80 120 160 Junction T em p (°C) Figure 46 Sense Signal Maximum Voltage VS - VIS(RANGE) = f(TJ;VS) 9.4.4 Sense Signal maximum Current P_7.5.7 IIS_FAULT @ 8V IIS_FAULT @ 13.5V IIS_FAULT (mA) 36 IIS_FAULT @ 18V 26 16 6 -40 0 40 80 120 160 Junction Temp (°C) IIS_FAULT.vsd Figure 47 Sense Signal Maximum Current in Fault Condition IIS(FAULT) = f(TJ;VS) Data Sheet PROFET™+ 12V 46 Rev. 2.2, 2013-09-06 BTS5090-1EJA Characterization Results 9.5 Input Pins 9.5.1 Input Voltage Threshold ON to OFF P_8.4.1 2 I_IN(L) @ 8V I_IN(L) @ 13.5V I_IN(L) @ 18V V_INH(L) (V) 1,5 1 0,5 0 -40 0 40 80 120 160 Junction Temp (°C) Input_pin_low_voltage.vsd Figure 48 Input Voltage Threshold VIN(L) = f(TJ;VS) 9.5.2 Input Voltage Threshold OFF to ON P_8.4.2 2 V_INH(H) (V) 1,5 1 0,5 0 -40 0 40 80 120 160 Junction Temp (°C) Input_pin_high_voltage.vsd Figure 49 Input Voltage Threshold VIN(H) = f(TJ;VS) Data Sheet PROFET™+ 12V 47 Rev. 2.2, 2013-09-06 BTS5090-1EJA Characterization Results 9.5.3 Input Voltage Hysteresis P_8.4.3 400 V_IN(HYS) @ 8V V_IN(HYS) 13.5V V_IN(HYS) @ 18V V_IN(HYS) (mV) 300 200 100 0 -40 0 40 80 120 160 Junction Temp (°C) Input_pin_voltage_hysteresis.vsd Figure 50 Input Voltage Hysteresis VIN(HYS) = f(TJ;VS) 9.5.4 Input Current High Level P_8.4.5 25 I_INH(H) (µA) 20 15 10 5 0 -40 0 40 80 Junction Temp (°C) Figure 51 120 160 Input_pin_high_current.vsd Input Current High Level IIN(H) = f(TJ;VS) Data Sheet PROFET™+ 12V 48 Rev. 2.2, 2013-09-06 BTS5090-1EJA Application Information 10 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. VBAT R/L cable T1 Z2 VDD CVS ROL Vs Vdd OUT IN0 RIN R/L cable OUT0 COUT0 RPD OUT DEN RDEN Micro controller RA/D A/D IS RSENSE GND CSENSE Z1 D RIS RGND Vss Figure 52 Application Diagram with BTS5090-1EJA Note: This is a very simplified example of an application circuit. The function must be verified in the real application. Table 10 Bill of Material Reference Value Purpose RIN 4.7 kΩ Protection of the micro controller during overvoltage, reverse polarity Guarantee BTS5090-1EJA channel OFF during loss of ground RDEN 4.7 kΩ Protection of the micro controller during overvoltage, reverse polarity Guarantee BTS5090-1EJA channel OFF during loss of ground RPD 47 kΩ Polarization of the output Improve BTS5090-1EJA immunity to electromagnetic noise RIS RSENSE 1.2 kΩ Sense resistor 4.7 kΩ Overvoltage, reverse polarity, loss of ground. Value to be tuned with micro controller specification. ROL 1.5 kΩ Ensure polarization of the BTS5090-1EJA output during open load in OFF diagnostic RA/D 4.7 kΩ Protection of the micro controller during overvoltage, reverse polarity Data Sheet PROFET™+ 12V 49 Rev. 2.2, 2013-09-06 BTS5090-1EJA Application Information Table 10 Bill of Material (cont’d) Reference Value Purpose D BAS21 Protection of the BTS5090-1EJA during reverse polarity RGND Z1 Z2 1 kΩ To keep the device GND at a stable potential during clamping 7 V Zener diode Protection of the micro controller during overvoltage 36 V Zener diode Protection of the device during overvoltage T1 CSENSE CVS COUT0 BC 807 Switch the battery voltage for open load in OFF diagnostic 100 pF Sense signal filtering 100 nF Filtering of the voltage spikes on the battery line 4.7 nF Protection of the BTS5090-1EJA during ESD and BCI 10.1 Further Application Information • • • Please contact us to get the pin FMEA Existing App. Notes For further information you may visit http://www.infineon.com/profet Data Sheet PROFET™+ 12V 50 Rev. 2.2, 2013-09-06 BTS5090-1EJA Package Outlines 11 Package Outlines 0.35 x 45˚ 1.27 0.41±0.09 2) 0.2 M 0.19 +0.06 0.08 C Seating Plane C A-B D 8x 0.64 ±0.25 D 0.2 6 ±0.2 8˚ MAX. C 0.1 C D 2x 1.7 MAX. Stand Off (1.45) 0.1+0 -0.1 3.9 ±0.11) M D 8x Bottom View 8 1 5 1 4 8 4 5 2.65 ±0.2 3 ±0.2 A B 4.9 ±0.11) 0.1 C A-B 2x Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width 3) JEDEC reference MS-012 variation BA Figure 53 PG-DSO-8-27-PO V01 PG-DSO-8-43 EP (Plastic Dual Small Outline Package) (RoHS-Compliant) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Data Sheet PROFET™+ 12V 51 Rev. 2.2, 2013-09-06 BTS5090-1EJA Revision History 12 Revision History Version Date Parameter 2.0 2010-05-31 Creation of the Data Sheet 2.1 2011-06-20 Updated Figure 6) Typical Thermal Impedance Updated Figure 12) Maximum Energy Dissipation Single Pulse Changed the Maximum Energy Dissipation Single Pulse adapted the footnote; updated the Legal Disclaimer added the parameter IL(INV) Updated characterisation results; Graphs in chapter 9.3 P_4.1.23 P_4.1.4 P_5.5.9 2.2 2013-09-06 P_7.5.9 P_7.5.10 P_7.5.11 P_7.5.12 P_7.5.17 Data Sheet PROFET™+ 12V Changes changed kilis specification parameters and figures 21/22 accordingly changed from 34% to 16%, typical value changed from 1500 to 1460 changed from 13% to 10%, typical value changed from 1500 to 1460 changed from 9% to 7%, typical value changed from 1500 to 1460 changed from 8% to 6.5%, typical value changed from 1500 to 1460 changed from 8% to 5% Updated Fig 4) PCB 2s2p Cross Section device marking corrected to 5090-EJA 52 Rev. 2.2, 2013-09-06 Edition 2013-09-06 Published by Infineon Technologies AG 81726 Munich, Germany © 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Legal Disclaimer for short-circuit capability Infineon disclaims any warranties and liabilities, whether expressed nor implied, for any short-circuit failures below the threshold limit. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.