BTS52001EJAXUMA1

PR OFET™ + 12V BT S5200- 1E J A Smart High-Side Power Switch Single Channel, 200mΩ Data Sheet PROFET™+ 12V Rev. 1.0, 2015-11-09 Automotive Power BTS5200-1EJA Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 3.1 3.2 3.3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage and Current Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 4.2 4.3 4.3.1 4.3.2 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PCB set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 5.1 5.2 5.3 5.3.1 5.3.2 5.4 5.5 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output ON-state Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn ON/OFF Characteristics with Resistive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Load Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inverse Current Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 16 16 16 17 19 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.5.2 6.6 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Ground Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Limitation in the Power DMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics for the Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 22 23 23 23 23 25 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.3.1 7.3.3.2 7.3.3.3 7.3.4 7.3.5 7.3.6 7.4 Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal in Different Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal in the Nominal Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal Variation as a Function of Temperature and Load Current . . . . . . . . . . . . . . . . . . . . . SENSE Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal in Open Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load in ON Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load in OFF Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load Diagnostic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal in Short Circuit to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal in Case of Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SENSE Signal in Case of Inverse Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Diagnostic Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 27 27 28 29 30 30 30 31 31 32 32 33 Data Sheet PROFET™+ 12V 2 7 7 7 8 Rev. 1.0 2015-11-09 BTS5200-1EJA 8 8.1 8.2 8.3 8.4 Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 36 36 37 9 9.1 9.2 9.3 9.4 9.5 Characterization Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 38 39 41 42 43 10 10.1 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Data Sheet PROFET™+ 12V 3 Rev. 1.0 2015-11-09 BTS5200-1EJA 1 Overview Application • Suitable for resistive, inductive and capacitive loads • Replaces electromechanical relays, fuses and discrete circuits • Most suitable for loads with high inrush current, such as lamps Basic Features PG-DSO-8-43 EP • Single channel device • Very low stand-by current • 3.3 V and 5 V compatible logic inputs • Electrostatic discharge protection (ESD) • Optimized electromagnetic compatibility • Logic ground independent from load ground • Very low power DMOS leakage current in OFF state • Green product (RoHS compliant) • AEC qualified Description The BTS5200-1EJA is a 200 mΩ single channel Smart High-Side Power Switch, embedded in a PG-DSO-8-43 EP, Exposed Pad package, providing protective functions and diagnosis. The power transistor is built by an N-channel vertical power MOSFET with charge pump. The device is integrated in Smart6 technology. It is specially designed to drive lamps up to 1x R10W 12V, as well as LEDs in the harsh automotive environment. Table 1 Product Summary Parameter Symbol Value Operating voltage range VS(OP) 5 V ... 28 V Maximum supply voltage VS(LD) 41 V Maximum ON state resistance at TJ = 150 °C RDS(ON) 400 mΩ Nominal load current IL(NOM) 1.5 A Typical current sense ratio kILIS 300 Minimum current limitation IL5(SC) 9A Maximum standby current with load at TJ = 25 °C IS(OFF) 500 nA Type Package Marking BTS5200-1EJA PG-DSO-8-43 EP 5200-EJA Data Sheet 4 Rev. 1.0, 2015-11-09 BTS5200-1EJA Overview Diagnostic Functions • Proportional load current sense • Open load detection in ON and OFF • Short circuit to battery and ground indication • Overtemperature switch off detection • Stable diagnostic signal during short circuit • Enhanced kILIS dependency with temperature and load current Protection Functions • Stable behavior during undervoltage • Reverse polarity protection with external components • Secure load turn-off during logic ground disconnection with external components • Overtemperature protection with restart • Overvoltage protection with external components • Enhanced short circuit operation Data Sheet 5 Rev. 1.0 2015-11-09 BTS5200-1EJA Block Diagram 2 Block Diagram VS voltage sensor internal power supply over temperature driver logic IN ESD protection DEN gate control & charge pump T clamp for inductive load over current switch limit load current sense and open load detection OUT IS forward voltage drop detection GND Figure 1 Block diagram.emf Block Diagram for the BTS5200-1EJA Data Sheet PROFET™+ 12V 6 Rev. 1.0 2015-11-09 BTS5200-1EJA Pin Configuration 3 Pin Configuration 3.1 Pin Assignment GND 1 8 OUT IN 2 7 OUT DEN 3 6 OUT IS 4 5 NC Pinout Single.vsd Figure 1 Pin Configuration 3.2 Pin Definitions and Functions Pin Symbol Function 1 GND GrouND; Ground connection 2 IN INput channel; Input signal for channel activation 3 DEN Diagnostic ENable; Digital signal to enable/disable the diagnosis of the device 4 IS Sense; Sense current of the selected channel 5 NC Not Connected; No internal connection to the chip 6, 7, 8 OUT OUTput; Protected high side power output channel1) Cooling Tab VS Voltage Supply; Battery voltage 1) All output pins must be connected together on the PCB. All pins of the output are internally connected together. PCB traces have to be designed to withstand the maximum current which can flow. Data Sheet PROFET™+ 12V 7 Rev. 1.0 2015-11-09 BTS5200-1EJA Pin Configuration 3.3 Voltage and Current Definition Figure 2 shows all terms used in this data sheet, with associated convention for positive values. IS VS VS IIN IN VIN VDS IDEN IOUT DEN OUT VDEN IIS VOUT IS GND VIS IGND voltage and current convention .vsd Figure 2 Voltage and Current Definition Data Sheet PROFET™+ 12V 8 Rev. 1.0 2015-11-09 BTS5200-1EJA General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Table 2 Absolute Maximum Ratings1) TJ = -40°C to 150°C; (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Supply Voltages Supply voltage VS -0.3 – 28 V – P_4.1.1 Reverse polarity voltage -VS(REV) 0 – 16 V t < 2 min TA = 25 °C RL ≥ 25 Ω ZGND= Diode // 1k Ω P_4.1.2 Supply voltage for short circuit protection VBAT(SC) 0 – 24 V P_4.1.3 RSupply = 10 mΩ LSupply = 5 µH RECU= 20 mΩ RCable= 16 mΩ/m LCable= 1 µH/m, l = 0 or 5 m See Chapter 6 and Figure 26 Supply voltage for Load dump protection VS(LD) – – 41 V 2) nRSC1 – – 100 3) k cycles tON = 300ms P_4.1.4 Voltage at INPUT pin VIN -0.3 – – 6 7 V – t < 2 min P_4.1.13 Current through INPUT pin IIN -2 – 2 mA – P_4.1.14 Voltage at DEN pin VDEN -0.3 – – 6 7 V – t < 2 min P_4.1.15 Current through DEN pin IDEN -2 – 2 mA – P_4.1.16 Voltage at IS pin VIS -0.3 – VS V – P_4.1.19 Current through IS pin IIS -25 – 50 mA – P_4.1.20 | IL | – – IL5(SC) A – P_4.1.21 RI = 2 Ω RL = 25 Ω P_4.1.12 Short Circuit Capability Permanent short circuit IN pin toggles Input Pins Sense Pin Power Stage Load current Data Sheet PROFET™+ 12V 9 Rev. 1.0 2015-11-09 BTS5200-1EJA General Product Characteristics Table 2 Absolute Maximum Ratings1) (cont’d) TJ = -40°C to 150°C; (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Power dissipation (DC) PTOT – – 1.8 W TA = 85 °C TJ < 150 °C P_4.1.22 Maximum energy dissipation Single pulse EAS – – 40 mJ IL(0) = 1 A TJ(0) = 150 °C VS = 13.5 V P_4.1.23 Maximum Energy dissipation repetitive pulse EAR – – 50 mJ 1Mio cycles TA < 105 °C VS = 13.5 V IL(0) = 350 mA P_4.1.25 Voltage at power transistor VDS – – 41 V – P_4.1.26 -20 -150 – 20 20 mA – t < 2 min P_4.1.27 Currents Current through ground pin I GND Temperatures Junction temperature TJ -40 – 150 °C – P_4.1.28 Storage temperature TSTG -55 – 150 °C – P_4.1.30 VESD -2 – 2 kV 4) HBM P_4.1.31 HBM P_4.1.32 ESD Susceptibility ESD susceptibility (all pins) ESD susceptibility OUT Pin vs. GND and VS connected VESD -4 – 4 kV 4) ESD susceptibility VESD -500 – 500 V 5) CDM P_4.1.33 ESD susceptibility pin (corner pins) VESD -750 – 750 V 5) CDM P_4.1.34 1) Not subject to production test. Specified by design. 2) VS(LD) is setup without the DUT connected to the generator per ISO 7637-1. 3) EOL tests according to AECQ100-012. Threshold limit for short circuit failures: 100 ppm. Please refer to the legal disclaimer for short-circuit capability on the last page of this document. 4) ESD susceptibility HBM according to ANSI/ESDA/JEDEC JS-001. 5) “CDM” ESDA STM5.3.1 or ANSI/ESD 5.5.3.1 Notes 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet PROFET™+ 12V 10 Rev. 1.0 2015-11-09 BTS5200-1EJA General Product Characteristics 4.2 Functional Range Table 3 Functional RangeTJ = -40°C to 150°C; (unless otherwise specified) Parameter Nominal operating voltage Symbol VNOM Values Unit Min. Typ. Max. 8 13.5 18 Note or Test Condition Number V – P_4.2.1 2) Extended operating voltage VS(OP) 5 – 28 V VIN = 4.5 V RL = 25 Ω VDS < 0.5 V P_4.2.2 Minimum functional supply VS(OP)_MIN voltage 3.8 4.3 5 V 1) VIN = 4.5 V RL = 25 Ω From IOUT = 0 A to VDS < 0.5 V; see Figure 13 P_4.2.3 Undervoltage shutdown VS(UV) 3 3.5 4.1 V 1) P_4.2.4 VIN = 4.5 V VDEN = 0 V RL = 25 Ω From VDS < 1 V; to IOUT = 0 A See Chapter 9.1 and Figure 13 Undervoltage shutdown hysteresis VS(UV)_HYS – 850 – mV 2) Operating current channel active IGND_1 – 6 9 mA P_4.2.5 VIN = 5.5 V VDEN = 5.5 V Device in RDS(ON) VS = 18 V See Chapter 9.1 Standby current for whole device with load IS(OFF) – 0.1 0.5 µA 1) VS = 18 V VOUT = 0 V VIN floating VDEN floating TJ ≤ 85 °C P_4.2.7 Maximum standby current for whole device with load IS(OFF)_150 – – 5 µA VS = 18 V VOUT = 0 V VIN floating VDEN floating TJ = 150 °C P_4.2.10 Standby current for whole IS(OFF_DEN) device with load, diagnostic active – 0.6 – mA 2) P_4.2.8 Data Sheet PROFET™+ 12V 11 – VS = 18 V VOUT = 0 V VIN floating VDEN = 5.5 V P_4.2.13 Rev. 1.0 2015-11-09 BTS5200-1EJA General Product Characteristics 1)Test at TJ = -40°C only 2) Not subject to production test. Specified by design. Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 Thermal Resistance Table 4 Thermal Resistance Parameter Junction to soldering point Junction to ambient All channels active Symbol RthJS RthJA Values Min. Typ. Max. – 5 – – 38 – Unit Note or Test Condition Number K/W 1) P_4.3.1 K/W 1)2) P_4.3.2 1) Not subject to production test. Specified by design. 2) Specified Rthja value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip + package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35 µm Cu). Where applicable, a thermal via array under the exposed pad contacts the first inner copper layer. Please refer to Figure 2. Data Sheet PROFET™+ 12V 12 Rev. 1.0 2015-11-09 BTS5200-1EJA General Product Characteristics 4.3.1 PCB set up 70µm 1.5mm 35µm 0.3mm Figure 2 PCB 2s2p.vsd 2s2p PCB Cross Section 1 2 3 8 7 COOLING TAB VS 6 4 5 thermique So8.vsd Figure 3 PC Board Top and Bottom View for Thermal Simulation with 600 mm2 Cooling Area Data Sheet PROFET™+ 12V 13 Rev. 1.0 2015-11-09 BTS5200-1EJA General Product Characteristics 4.3.2 Thermal Impedance Zth-ja [K/W] 100 10 1s0p-footprint 1s0p-300mm² 1s0p-600mm² 2s2p 1 0.0001 Figure 4 0.001 0.01 0.1 1 Time [s] 10 100 1000 Typical Thermal Impedance. 2s2p PCB set up according Figure 2 90 85 80 Rthja [K/W] 75 70 65 60 55 1s0p 50 45 40 0 footprint Figure 5 100 200 300 400 500 600 700 Area [mm2] Typical Thermal Impedance. 2s2p PCB set up according Figure 2 Data Sheet PROFET™+ 12V 14 Rev. 1.0 2015-11-09 BTS5200-1EJA Power Stage 5 Power Stage The power stage is built using an N-channel vertical power MOSFET (DMOS) with charge pump. 5.1 Output ON-state Resistance The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature TJ. Figure 6 shows the dependencies in terms of temperature and supply voltage for the typical ON-state resistance. The behavior in reverse polarity is described in Chapter 6.4. 400 500 450 350 400 RDS(ON) [mΩ ] RDS(ON) [mΩ ] 300 250 350 300 200 250 150 100 -40 Figure 6 200 -20 0 20 40 60 80 100 Junction Temperature TJ [°C] 120 140 150 160 0 5 10 15 Supply Voltage VS [V] 20 25 30 Typical ON-state Resistance A high signal at the input pin (see Chapter 8) causes the power DMOS to switch ON with a dedicated slope, which is optimized in terms of EMC emission. 5.2 Turn ON/OFF Characteristics with Resistive Load Figure 7 shows the typical timing when switching a resistive load. IN VIN_H VIN_L t VOUT dV/dt ON dV/dt 90% VS tOFF_delay 70% VS 30% VS OFF t ON tON_delay tOFF 10% VS t Switching times.vsd Figure 7 Switching a Resistive Load Timing Data Sheet PROFET™+ 12V 15 Rev. 1.0 2015-11-09 BTS5200-1EJA Power Stage 5.3 Inductive Load 5.3.1 Output Clamping When switching OFF inductive loads with high side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device by avalanche due to high voltages, there is a voltage clamp mechanism ZDS(AZ) implemented that limits negative output voltage to a certain level (VS - VDS(AZ)). Please refer to Figure 8 and Figure 9 for details. Nevertheless, the maximum allowed load inductance is limited. VS ZDS(AZ) VDS INx LOGIC IL VBAT GND VIN OUTx L, RL VOUT ZGND Output clamp.vsd Figure 8 Output Clamp IN t V OUT VS t V S-VDS(AZ) IL t Switching an inductance.vsd Figure 9 Switching an Inductive Load Timing 5.3.2 Maximum Load Inductance During demagnetization of inductive loads, energy has to be dissipated in the BTS5200-1EJA. This energy can be calculated with following equation: V S – V DS ( AZ ) RL × IL ⎞ L E = V DS ( AZ ) × ------ × -------------------------------× ln ⎛ 1 – -------------------------------+ IL ⎝ RL RL V S – V DS ( AZ )⎠ Data Sheet PROFET™+ 12V 16 (5.1) Rev. 1.0 2015-11-09 BTS5200-1EJA Power Stage Following equation simplifies under the assumption of RL = 0 Ω. VS 2 1 ⎞ E = --- × L × I × ⎛⎝ 1 – -------------------------------2 V S – V DS ( AZ )⎠ (5.2) The energy, which is converted into heat, is limited by the thermal design of the component. See Figure 10 for the maximum allowed energy dissipation as a function of the load current. EAS [mJ] 100 10 1 0 0,5 1 1,5 2 2,5 3 IL [A] Figure 10 Maximum Energy Dissipation Single Pulse, TJ_START = 150 °C; VS = 13.5V 5.4 Inverse Current Capability In case of inverse current, meaning a voltage VINV at the OUTput higher than the supply voltage VS, a current IINV will flow from output to VS pin via the body diode of the power transistor (please refer to Figure 11). The output stage follows the state of the IN pin, except if the IN pin goes from OFF to ON during inverse. In that particular case, the output stage is kept OFF until the inverse current disappears. Nevertheless, the current IINV should not be higher than IL(INV). If the channel is OFF, the diagnostic will detect an open load at OFF. If the channel is ON, the diagnostic will detect open load at ON (the overtemperature signal is inhibited). At the appearance of VINV, a parasitic diagnostic can be observed. After, the diagnosis is valid and reflects the output state. At VINV vanishing, the diagnosis is valid and reflects the output state. During inverse current, no protection functions are available. Data Sheet PROFET™+ 12V 17 Rev. 1.0 2015-11-09 BTS5200-1EJA Power Stage VBAT VS Gate driver IL(INV) OL comp. Device logic INV Comp. VINV OUT GND IS ZGND inverse current.vsd Figure 11 Inverse Current Circuitry Data Sheet PROFET™+ 12V 18 Rev. 1.0 2015-11-09 BTS5200-1EJA Power Stage 5.5 Electrical Characteristics Power Stage Table 5 Electrical Characteristics: Power Stage VS = 8 V to 18 V, TJ = -40°C to 150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number ON-state resistance RDS(ON)_150 300 360 400 mΩ IL = IL4 = 1 A VIN = 4.5 V TJ = 150 °C See Figure 6 P_5.5.1 ON-state resistance RDS(ON)_25 – 200 – mΩ 1) P_5.5.21 1) TJ = 25 °C Nominal load current IL(NOM)1 – 1.5 – A TA= 85 °C TJ < 150 °C Output voltage drop limitation at small load currents VDS(NL) – 10 22 mV IL = IL0 = 25 mA P_5.5.4 See Chapter 9.3 Drain to source clamping voltage VDS(AZ) = [VS - VOUT] VDS(AZ) 41 47 53 V IDS = 20 mA P_5.5.5 See Figure 9 See Chapter 9.1 Output leakage current TJ ≤ 85 °C IL(OFF) – 0.1 0.5 µA 2) VIN floating VOUT = 0 V TJ ≤ 85 °C P_5.5.6 Output leakage current TJ = 150 °C IL(OFF)_150 – 1 5 µA VIN floating VOUT = 0 V TJ = 150 °C P_5.5.8 Inverse current capability IL(INV) – 1 – A 1) P_5.5.9 Data Sheet PROFET™+ 12V 19 P_5.5.2 VS< VOUTX See Figure 11 Rev. 1.0 2015-11-09 BTS5200-1EJA Power Stage Table 5 Electrical Characteristics: Power Stage (cont’d) VS = 8 V to 18 V, TJ = -40°C to 150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number RL = 25 Ω P_5.5.11 VS = 13.5 V See Figure 7 P_5.5.12 See Chapter 9.1 Slew rate 30% to 70% VS dV / dtON 0.20 0.47 1.0 V/µs Slew rate 70% to 30% VS -dV / dtOFF 0.20 0.47 1.0 V/µs Slew rate matching dV/dtON - dV/dtOFF ΔdV/ dt -0.15 0 0.15 V/µs P_5.5.13 Turn-ON time to VOUT = 90% VS tON 20 70 120 µs P_5.5.14 Turn-OFF time to VOUT = 10% tOFF VS 20 70 120 µs P_5.5.15 Turn-ON / OFF matching tOFF - tON ΔtSW -50 0 50 µs P_5.5.16 Turn-ON time to VOUT = 10% VS tON_delay 10 40 70 µs P_5.5.17 Turn-OFF time to VOUT = 90% tOFF_delay VS 10 40 70 µs P_5.5.18 Switch ON energy EON – 70 – µJ RL = 25 Ω P_5.5.19 VOUT = 90% VS VS = 18 V See Chapter 9.1 Switch OFF energy EOFF – 80 – µJ 1) 1) RL = 25 Ω P_5.5.20 VOUT = 10% VS VS = 18 V See Chapter 9.1 1) Not subject to production test, specified by design. 2) Test at TJ = -40°C only Data Sheet PROFET™+ 12V 20 Rev. 1.0 2015-11-09 BTS5200-1EJA Protection Functions 6 Protection Functions The device provides integrated protection functions. These functions are designed to prevent the destruction of the IC from fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are designed for neither continuous nor repetitive operation. 6.1 Loss of Ground Protection In case of loss of the module ground and the load remains connected to ground, the device protects itself by automatically turning OFF (when it was previously ON) or remains OFF, regardless of the voltage applied on IN pins. In case of loss of device ground, it’s recommended to use input resistors between the microcontroller and the BTS5200-1EJA to ensure switching OFF the channel. In case of loss of module or device ground, a current (IOUT(GND)) can flow out of the DMOS. Figure 12 sketches the situation. ZGND is recommended to be a resistor in parallel to a diode . ZIS(AZ) VS ZD(AZ) IS RSENSE VBAT ZDS(AZ) DEN R DEN LOGIC IN R IN IOUT(GND) OUT ZDESD GND RIS IS ZGND Loss of ground protection .vsd Figure 12 Loss of Ground Protection with External Components 6.2 Undervoltage Protection Between VS(UV) and VS(OP), the undervoltage mechanism is triggered. VS(OP) represents the minimum voltage where the switching ON and OFF can takes place. VS(UV) represents the minimum voltage the switch can hold ON. If the supply voltage is below the undervoltage mechanism VS(UV), the device is OFF (turns OFF). As soon as the supply voltage is above the undervoltage mechanism VS(OP), then the device can be switched ON. When the switch is ON, protection functions are operational. Nevertheless, the diagnosis is not guaranteed until VS is in the VNOM range. Figure 13 sketches the undervoltage mechanism. Data Sheet PROFET™+ 12V 21 Rev. 1.0 2015-11-09 BTS5200-1EJA Protection Functions VOUT undervoltage behavior .vsd VS(UV) Figure 13 Undervoltage Behavior 6.3 Overvoltage Protection VS(OP) VS There is an integrated clamp mechanism for overvoltage protection (ZD(AZ)). To guarantee this mechanism operates properly in the application, the current in the Zener diode has to be limited by a ground resistor. Figure 14 shows a typical application to withstand overvoltage issues. In case of supply voltage higher than VS(AZ), the power transistor switches ON and in addition the voltage across the logic section is clamped. As a result, the internal ground potential rises to VS - VS(AZ). Due to the ESD Zener diodes, the potential at pin IN and DEN rises almost to that potential, depending on the impedance of the connected circuitry. In the case the device was ON, prior to overvoltage, the BTS5200-1EJA remains ON. In the case the BTS5200-1EJA was OFF, prior to overvoltage, the power transistor can be activated. In the case the supply voltage is in above VBAT(SC) and below VDS(AZ), the output transistor is still operational and follows the input. If the channel is in the ON state, parameters are no longer guaranteed and lifetime is reduced compared to the nominal supply voltage range. This especially impacts the short circuit robustness, as well as the maximum energy EAS capability. ZGND is recommended to be a resistor in parallel to a diode. ISOV ZIS(AZ) VS ZD(AZ) IS RSENSE VBAT ZDS(AZ) DEN R DEN LOGIC IN R IN OUT ZDESD GND R IS ZGND Overvoltage protection.vsd Figure 14 Overvoltage Protection with External Components Data Sheet PROFET™+ 12V 22 Rev. 1.0 2015-11-09 BTS5200-1EJA Protection Functions 6.4 Reverse Polarity Protection In case of reverse polarity, the intrinsic body diode of the power DMOS causes power dissipation. The current in this intrinsic body diode is limited by the load itself. Additionally, the current into the ground path and the logic pins has to be limited to the maximum current described in Chapter 4.1 with an external resistor. Figure 15 shows a typical application. RGND resistor is used to limit the current in the Zener protection of the device. Resistors RDEN, and RIN are used to limit the current in the logic of the device and in the ESD protection stage. RSENSE is used to limit the current in the sense transistor which behaves as a diode. The recommended value for RDEN = RIN = RSENSE = 4.7 kΩ. It is recommended to use a resistor in parallel to a diode in the ground path. During reverse polarity, no protection functions are available. Micro controller protection diodes VS ZIS(AZ) ZD(AZ) IS RSENSE ZDS (AZ) VDS(REV) DEN RDEN LOGIC IN RIN -VS(REV) IN0 OUT ZD ESD GND IS RIS RGND D Reverse Polarity parallel .vsd Figure 15 Reverse Polarity Protection with External Components 6.5 Overload Protection In case of overload, such as high inrush of cold lamp filament, or short circuit to ground, the BTS5200-1EJA offers several protection mechanisms. 6.5.1 Current Limitation At first step, the instantaneous power in the switch is maintained at a safe value by limiting the current to the maximum current allowed in the switch IL(SC). During this time, the DMOS temperature is increasing, which affects the current flowing in the DMOS. 6.5.2 Temperature Limitation in the Power DMOS The channel incorporates both an absolute (TJ(SC)) and a dynamic (TJ(SW)) temperature sensor. Activation of either sensor will cause an overheated channel to switch OFF to prevent destruction. Any protective switch OFF latches the output until the temperature has reached an acceptable value. Figure 16 gives a sketch of the situation. Data Sheet PROFET™+ 12V 23 Rev. 1.0 2015-11-09 BTS5200-1EJA Protection Functions A retry strategy is implemented such that when the DMOS temperature has cooled down enough, the switch is switched ON again, if the IN pin is still high (restart behavior). IN t IL LOAD CURRENT LIMITATION PHASE IL(x)SC LOAD CURRENT BELOW LIMITATION PHASE IL(NOM) t TDMOS ΔT J(SW) TJ(SC) ΔTJ(SW) ΔTJ(SW) TA tsIS(FAULT) t ΔTSTEP IIS tsIS(OT_blank) IIS(FAULT) IL(NOM) / kILIS 0A VDEN t tsIS(OFF ) 0V t Hard start.vsd Figure 16 Overload Protection Note: For better understanding, the time scale is not linear. The real timing of this drawing is application dependant and cannot be described. Data Sheet PROFET™+ 12V 24 Rev. 1.0 2015-11-09 BTS5200-1EJA Protection Functions 6.6 Electrical Characteristics for the Protection Functions Table 6 Electrical Characteristics: Protection VS = 8 V to 18 V, TJ = -40°C to 150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. IOUT(GND) – 0.1 – mA 1)2) VS = 28 V See Figure 12 P_6.6.1 VDS(REV) 200 650 700 mV 3) IL = - 1 A See Figure 15 P_6.6.2 VS(AZ) 41 47 53 V ISOV = 5 mA See Figure 14 P_6.6.3 Load current limitation IL5(SC) 9 11 14 A 4) VDS = 5 V See Figure 16 and Chapter 9.3 P_6.6.4 Short circuit current during over temperature toggling IL(RMS) - 2 - A 2) VIN =4.5V RSHORT=100 mΩ LSHORT= 5 µH P_6.6.12 Dynamic temperature increase while switching ΔTJ(SW) – 80 – K 5) See Figure 16 P_6.6.8 Thermal shutdown temperature TJ(SC) 150 1705) 2005) °C 3) See Figure 16 P_6.6.10 Thermal shutdown hysteresis ΔTJ(SC) – 30 – K 3) 5) Loss of Ground Output leakage current while GND disconnected Reverse Polarity Drain source diode voltage during reverse polarity Overvoltage Overvoltage protection Overload Condition 1) 2) 3) 4) 5) See Figure 16 P_6.6.11 All pins are disconnected except VS and OUT. Not Subject to production test, specified by design Test at TJ = +150°C only Test at TJ = -40°C only Functional test only Data Sheet PROFET™+ 12V 25 Rev. 1.0 2015-11-09 BTS5200-1EJA Diagnostic Functions 7 Diagnostic Functions For diagnosis purpose, the BTS5200-1EJA provides a combination of digital and analog signals at pin IS. These signals are called SENSE. In case the diagnostic is disabled via DEN, pin IS becomes high impedance. In case DEN is activated, the sense current of the channel is enabled. 7.1 IS Pin The BTS5200-1EJA provides a sense signal called IIS at pin IS. As long as no “hard” failure mode occurs (short circuit to GND / current limitation / overtemperature / excessive dynamic temperature increase or open load at OFF) a proportional signal to the load current (ratio kILIS = IL / IIS) is provided. The complete IS pin and diagnostic mechanism is described on Figure 17. The accuracy of the sense current depends on temperature and load current. Due to the ESD protection, in connection to VS, it is not recommended to share the IS pin with other devices if these devices are using another battery feed. The consequence is that the unsupplied device would be fed via the IS pin of the supplied device. Vs FAULT IIS (FAULT) I IS = I L / k ILIS ZIS(AZ) 1 1 IS 0 0 DEN Sense schematic.vsd Figure 17 Diagnostic Block Diagram Data Sheet PROFET™+ 12V 26 Rev. 1.0 2015-11-09 BTS5200-1EJA Diagnostic Functions 7.2 SENSE Signal in Different Operating Modes Table 7 gives a quick reference for the state of the IS pin during device operation. Table 7 Sense Signal, Function of Operation Mode Operation Mode Input level Channel X DEN Output Level Diagnostic Output Normal operation OFF H Z Z Short circuit to GND ~ GND Z Overtemperature Z Z Short circuit to VS VS IIS(FAULT) Open Load < VOL(OFF) > VOL(OFF)1) Z IIS(FAULT) Inverse current ~ VINV IIS(FAULT) ~ VS IIS = IL/kILIS Current limitation < VS IIS(FAULT) Short circuit to GND ~ GND IIS(FAULT) Overtemperature TJ(SW) event Z IIS(FAULT) Short circuit to VS VS IIS< IL/ kILIS Open Load ~ VS2) IIS < IIS(OL) Inverse current ~ VINV IIS < IIS(OL)3) Underload ~ VS4) IIS (OL)< IIS < IL / kILIS Don’t care Z Normal operation Don’t care 1) 2) 3) 4) ON Don’t care L Stable with additional pull-up resistor. The output current has to be smaller than IL(OL). After maximum tINV. The output current has to be higher than IL(OL). 7.3 SENSE Signal in the Nominal Current Range Figure 18 shows the current sense as a function of the load current in the power DMOS. Usually, a pull-down resistor RIS is connected to the current sense IS pin. This resistor has to be higher than 560 Ω to limit the power losses in the sense circuitry. A typical value is 1.2 kΩ. The blue curve represents the ideal sense current, assuming an ideal kILIS factor value. The red curves shows the accuracy the device provides across full temperature range at a defined current. Data Sheet PROFET™+ 12V 27 Rev. 1.0 2015-11-09 BTS5200-1EJA Diagnostic Functions 6 5 IIS [mA] 4 3 2 1 min/max Sense Current typical Sense Current 0 0 0.2 0.4 0.6 0.8 IL [A] 1 1.2 1.4 1.6 BTS5200-1EJA Figure 18 Current Sense for Nominal Load 7.3.1 SENSE Signal Variation as a Function of Temperature and Load Current In some applications a better accuracy is required at smaller currents. To achieve this accuracy requirement, a calibration on the application is possible. To avoid multiple calibration points at different load and temperature conditions, the BTS5200-1EJA allows limited derating of the kILIS value, at a given point (IL3; TJ = +25 °C). This derating is described by the parameter ΔkILIS. Figure 19 shows the behavior of the sense current, assuming one calibration point at nominal load at +25 °C. The blue line indicates the ideal kILIS ratio. The red lines indicate the derating on the parameter across temperature and voltage, assuming one calibration point at nominal temperature and nominal battery voltage. The black lines indicate the kILIS accuracy without calibration. Data Sheet PROFET™+ 12V 28 Rev. 1.0 2015-11-09 BTS5200-1EJA Diagnostic Functions 500 calibrated k ILIS min/max k ILIS typical k ILIS 450 400 k ILIS 350 300 250 200 150 0 0.2 0.4 0.6 0.8 IL [A] 1 1.2 1.4 1.6 BTS5200-1EJA Figure 19 Improved Current Sense Accuracy with One Calibration Point 7.3.2 SENSE Signal Timing Figure 20 shows the timing during settling and disabling of the SENSE. V IN t IL tON tOFF tON 90% of IL static t VDEN IIS tsIS(ON) 90% of IIS static t tsIS(LC) tsIS(OFF) tsIS(ON_DEN) t current sense settling disabling time .vsd Figure 20 Current Sense Settling / Disabling Timing Data Sheet PROFET™+ 12V 29 Rev. 1.0 2015-11-09 BTS5200-1EJA Diagnostic Functions 7.3.3 SENSE Signal in Open Load 7.3.3.1 Open Load in ON Diagnostic If the channel is ON, a leakage current can still flow through an open load, for example due to humidity. The parameter IL(OL) gives the threshold of recognition for this leakage current. If the current IL flowing out the power DMOS is below this value, the device recognizes a failure, if the DEN is selected. In that case, the SENSE current is below IIS(OL). Otherwise, the minimum SENSE current is given above parameter IIS(OL). Figure 21 shows the SENSE current behavior in this area. The red curve shows a typical product curve. The blue curve shows the ideal current sense. I IS IIS(OL) IL IL(OL) Sense for OL .vsd Figure 21 Current Sense Ratio for Low Currents 7.3.3.2 Open Load in OFF Diagnostic For open load diagnosis in OFF-state, an external output pull-up resistor (ROL) is recommended. For the calculation of pull-up resistor value, the leakage currents and the open load threshold voltage VOL(OFF) have to be taken into account. Figure 22 gives a sketch of the situation. Ileakage defines the leakage current in the complete system, including IL(OFF) (see Chapter 5.5) and external leakages, e.g, due to humidity, corrosion, etc... in the application. To reduce the stand-by current of the system, an open load resistor switch SOL is recommended. If the channel is OFF, the output is no longer pulled down by the load and VOUT voltage rises to nearly VS. This is recognized by the device as an open load. The voltage threshold is given by VOL(OFF). In that case, the SENSE signal is switched to the IIS(FAULT). An additional RPD resistor can be used to pull VOUT to 0V. Otherwise, the OUT pin is floating. This resistor can be used as well for short circuit to battery detection, see Chapter 7.3.4. Data Sheet PROFET™+ 12V 30 Rev. 1.0 2015-11-09 BTS5200-1EJA Diagnostic Functions Vbat SOL VS R OL IIS(FAULT) OL comp. OUT IS ILOFF Ileakage GND Rleakage VOL(OFF) R PD RIS ZGND Open Load in OFF.vsd Figure 22 Open Load Detection in OFF Electrical Equivalent Circuit 7.3.3.3 Open Load Diagnostic Timing Figure 23 shows the timing during either Open Load in ON or OFF condition when the DEN pin is HIGH. Please note that a delay tsIS(FAULT_OL_ON_OFF) has to be respected after the falling edge of the input, when applying an open load in OFF diagnosis request, otherwise the diagnosis can be wrong. Load is present Open load VIN VOUT t VS-V OL(OFF) RDS(ON) x IL shutdown with load t IOUT IIS tsIS(FAULT_OL_ON_OFF) t tsIS(LC) Error Settling Disabling Time.vsd Figure 23 Sense Signal in Open Load Timing 7.3.4 SENSE Signal in Short Circuit to VS t In case of a short circuit between the OUTput-pin and the VS pin, all or portion (depending on the short circuit impedance) of the load current will flow through the short circuit. As a result, a lower current compared to the normal operation will flow through the DMOS of the BTS5200-1EJA, which can be recognized at the current sense signal. The open load at OFF detection circuitry can also be used to distinguish a short circuit to VS. In that case, an external resistor to ground RSC_VS is required. Figure 24 gives a sketch of the situation. Data Sheet PROFET™+ 12V 31 Rev. 1.0 2015-11-09 BTS5200-1EJA Diagnostic Functions Vbat VS IIS(FAULT) VBAT OL comp. IS OUT V OL(OFF) GND RIS IS ZGND RSC_VS Short circuit to Vs.vsd Figure 24 Short Circuit to Battery Detection in OFF Electrical Equivalent Circuit 7.3.5 SENSE Signal in Case of Overload An overload condition is defined by a current flowing out of the DMOS reaching the current limitation and / or the absolute dynamic temperature swing TJ(SW) is reached, and / or the junction temperature reaches the thermal shutdown temperature TJ(SC). Please refer to Chapter 6.5 for details. In that case, the SENSE signal given is by IIS(FAULT) when the diagnostic is selected. The device has a thermal restart behavior, such that when the overtemperature or the exceed dynamic temperature condition has disappeared, the DMOS is reactivated if the IN is still at logic level one. If the DEN pin is activated the SENSE is not toggling with the resstart mechanism and remains to IIS(FAULT). 7.3.6 SENSE Signal in Case of Inverse Current In the case of inverse current, the sense signal will indicate open load in OFF state and indicate open load in ON state. Data Sheet PROFET™+ 12V 32 Rev. 1.0 2015-11-09 BTS5200-1EJA Diagnostic Functions 7.4 Electrical Characteristics Diagnostic Function Table 8 Electrical Characteristics: Diagnostics VS = 8 V to 18 V, TJ = -40°C to 150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Load Condition Threshold for Diagnostic Open load detection threshold in OFF state VS- VOL(OFF) 4 – 6 V VIN = 0 V VDEN = 4.5 V See Figure 23 P_7.5.1 Open load detection threshold in ON state IL(OL) 5 – 15 mA VIN = VDEN = 4.5 V IIS(OL) = 33 μA See Figure 21 See Chapter 9.4 P_7.5.2 – 0.02 1 µA VIN = 4.5 V VDEN = 0 V IL = IL4 = 1 A P_7.5.4 – 3.5 V 2) VIN = 0 V VOUT = VS > 10 V VDEN = 4.5 V IIS = 6 mA See Chapter 9.4 P_7.5.6 6 15 35 mA VIS = VIN = VDSEL = 0 V VOUT = VS > 10 V VDEN = 4.5 V See Figure 17 See Chapter 9.4 P_7.5.7 41 47 53 V IIS = 5 mA See Figure 17 P_7.5.3 Sense Pin IS pin leakage current when IIS_(DIS) sense is disabled Sense signal saturation voltage VS- VIS (RANGE) 1 Sense signal maximum current in fault condition IIS(FAULT) Sense pin maximum voltage VIS(AZ) VS to IS Current Sense Ratio Signal in the Nominal Area, Stable Load Current Condition Current sense ratio IL0 = 10 mA kILIS0 -50% 330 +50% Current sense ratio IL1 = 0.05 A kILIS1 -40% 300 +40% Current sense ratio IL2 = 0.2 A kILIS2 -15% 300 +15% P_7.5.10 Current sense ratio IL3 = 0.5 A kILIS3 -11% 300 +11% P_7.5.11 Current sense ratio IL4 = 1 A kILIS4 -9% 300 +9% P_7.5.12 Data Sheet PROFET™+ 12V 33 VIN = 4.5 V VDEN = 4.5 V See Figure 18 TJ = -40 °C; 150 °C P_7.5.8 P_7.5.9 Rev. 1.0 2015-11-09 BTS5200-1EJA Diagnostic Functions Table 8 Electrical Characteristics: Diagnostics (cont’d) VS = 8 V to 18 V, TJ = -40°C to 150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Min. Typ. Max. Unit Note or Test Condition -5 0 +5 % 2) Current sense settling time tsIS(ON) to kILIS function stable after positive input slope on both INput and DEN – – 150 µs 2) VDEN = VIN = 0 to 4.5 V P_7.5.18 VS = 13.5 V RIS = 1.2 kΩ CSENSE < 100 pF IL = IL3 = 0.5 A See Figure 20 Current sense settling time tsIS(ON_DEN) with load current stable and transition of the DEN – – 10 µs VIN = 4.5 V VDEN = 0 to 4.5 V RIS = 1.2 kΩ CSENSE < 100 pF IL = IL3 =0.5 A See Figure 20 Current sense settling time to IIS stable after positive input slope on current load – – 15 µs P_7.5.20 VIN = 4.5 V VDEN = 4.5 V RIS = 1.2 kΩ CSENSE < 100 pF IL= IL2 = 0.2 A to IL = IL3= 0.5 A See Figure 20 – 50 µs VIN = 0V VDEN = 0 to 4.5 V RIS = 1.2 kΩ CSENSE < 100 pF VOUT = VS = 13.5 V See Figure 23 P_7.5.22 150 – µs 2) P_7.5.23 kILIS derating with current and temperature Symbol ΔkILIS Values kILIS3 versus kILIS2 See Figure 19 Number P_7.5.17 Diagnostic Timing in Normal Condition tsIS(LC) P_7.5.19 Diagnostic Timing in Open Load Condition Current sense settling time to IIS stable for open load detection in OFF state Current sense settling time to IIS stable for open load detection in ON-OFF transition Data Sheet PROFET™+ 12V tsIS(FAULT_OL_ – OFF) tsIS(FAULT_OL_ – ON_OFF) 34 VIN= 4.5 to 0V VDEN =4.5 V RIS = 1.2 kΩ CSENSE< 100 pF VOUT= VS = 13.5 V Rev. 1.0 2015-11-09 BTS5200-1EJA Diagnostic Functions Table 8 Electrical Characteristics: Diagnostics (cont’d) VS = 8 V to 18 V, TJ = -40°C to 150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Diagnostic Timing in Overload Condition 1) Current sense settling time to IIS stable for overload detection tsIS(FAULT) – – 150 µs VIN = VDEN = 0 to 4.5 V P_7.5.24 RIS = 1.2 kΩ CSENSE < 100 pF VDS = 5 V See Figure 16 Current sense over temperature blanking time tsIS(OC_blank) – 350 – µs 2) VIN = VDEN = 4.5 V RIS = 1.2 kΩ CSENSE < 100 pF VDS = 5 V to 0 V See Figure 16 P_7.5.32 Diagnostic disable time DEN transition to IIS < 50% IL /kILIS tsIS(OFF) – – 20 µs VIN = 4.5 V VDEN = 4.5 V to 0 V RIS = 1.2 kΩ CSENSE < 100 pF IL = IL3 =0.5 A See Figure 20 P_7.5.25 1)Test at TJ = -40°C only 2) Not subject to production test, specified by design Data Sheet PROFET™+ 12V 35 Rev. 1.0 2015-11-09 BTS5200-1EJA Input Pins 8 Input Pins 8.1 Input Circuitry The input circuitry is compatible with 3.3 and 5 V microcontrollers. The concept of the input pin is to react to voltage thresholds. An implemented Schmitt trigger avoids any undefined state if the voltage on the input pin is slowly increasing or decreasing. The output is either OFF or ON but cannot be in a linear or undefined state. The input circuitry is compatible with PWM applications. Figure 25 shows the electrical equivalent input circuitry. In case the pin is not needed, it must be left opened, or must be connected to device ground (and not module ground) via an 4.7 kΩ input resistor. IN GND Figure 25 Input Pin Circuitry 8.2 DEN Pin Input circuitry .vsd The DEN pins enable and disable the diagnostic functionality of the device. This pin has the same structure as the INput pin, please refer to Figure 25. 8.3 Input Pin Voltage The IN and DEN use a comparator with hysteresis. The switching ON / OFF takes place in a defined region, set by the thresholds VIN(L) Max. and VIN(H) Min. The exact value where the ON and OFF take place are unknown and depends on the process, as well as the temperature. To avoid cross talk and parasitic turn ON and OFF, a hysteresis is implemented. This ensures a certain immunity to noise. Data Sheet PROFET™+ 12V 36 Rev. 1.0 2015-11-09 BTS5200-1EJA Input Pins 8.4 Electrical Characteristics Table 9 Electrical Characteristics: Input Pins VS = 8 V to 18 V, TJ = -40°C to 150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number INput Pin Characteristics Low level input voltage range VIN(L) -0.3 – 0.8 V See Chapter 9.5 P_8.4.1 High level input voltage range VIN(H) 2 – 6 V See Chapter 9.5 P_8.4.2 Input voltage hysteresis VIN(HYS) – 250 – mV 1) Low level input current IIN(L) 1 10 25 µA VIN = 0.8 V High level input current IIN(H) 2 10 25 µA VIN= 5.5 V P_8.4.5 See Chapter 9.5 Low level input voltage range VDEN(L) -0.3 – 0.8 V – P_8.4.6 High level input voltage range VDEN(H) 2 – 6 V – P_8.4.7 Input voltage hysteresis VDEN(HYS) – 250 – mV 1) P_8.4.8 Low level input current IDEN(L) 1 10 25 µA VDEN= 0.8V P_8.4.9 High level input current IDEN(H) 2 10 25 µA VDEN = 5.5 V P_8.4.10 P_8.4.3 See Chapter 9.5 P_8.4.4 DEN Pin 1) Not subject to production test, specified by design Data Sheet PROFET™+ 12V 37 Rev. 1.0 2015-11-09 BTS5200-1EJA Characterization Results 9 Characterization Results The characterization have been performed on 3 lots, with 3 devices each. Characterization have been performed at 8 V, 13.5 V and 18 V over temperature range. When no dependency to voltage is seen, only one curve (13,5 V) is sketched. 9.1 General Product Characteristics P_4.2.4 6,00 6,00 5,50 5,50 5,00 5,00 4,50 4,50 [V] [V] P_4.2.3 4,00 4,00 3,50 3,50 3,00 3,00 2,50 2,50 2,00 2,00 ‐50 ‐25 0 25 50 75 100 125 150 ‐50 ‐25 0 25 Temperature [°C] 50 75 100 125 150 125 150 Temperature [°C] Undervoltage Threshold VS(UV) = f(TJ) Minimum Functional Supply Voltage VS(OP)_MIN = f(TJ) P_4.2.7, P_4.2.10 3,00 1,20 2,50 1,00 2,00 0,80 [µA] [mA] P_4.2.5 1,50 1,00 0,60 0,40 8V 0,50 0,20 13.5V 18V 0,00 0,00 ‐50 ‐25 0 25 50 75 100 125 150 ‐50 Temperature [°C] ‐25 0 25 50 75 100 Temperature [°C] Current Consumption for Whole Device with Load. Standby Current for Whole Device with Load. Channel Active IGND_1 = f(TJ;VS) IS(OFF) = f(TJ) Data Sheet PROFET™+ 12V 38 Rev. 1.0, 2015-11-09 BTS5200-1EJA Characterization Results 9.2 Power Stage P_5.5.4 P_5.5.5 50,00 18,00 49,00 16,00 48,00 14,00 47,00 12,00 [V] [mV] 46,00 10,00 45,00 8,00 44,00 6,00 43,00 4,00 42,00 2,00 41,00 0,00 40,00 ‐50 ‐25 0 25 50 75 100 125 150 ‐50 ‐25 0 25 Temperature [°C] 50 75 100 125 150 Temperature [°C] Output Voltage Drop Limitation at Low Load Current Drain to Source Clamp Voltage VDS(AZ) = f(TJ) VDS(NL) = f(TJ) P_5.5.12 1,00 1,00 0,90 0,90 0,80 0,80 0,70 0,70 0,60 0,60 [V\µs] [V\µs] P_5.5.11 0,50 0,50 0,40 0,40 0,30 0,30 0,20 8V 0,20 8V 13.5V 0,10 13.5V 0,10 18V 0,00 18V 0,00 ‐50 ‐25 0 25 50 75 100 125 150 ‐50 Temperature [°C] Slew Rate at Turn ON dV/dtON = f(TJ;VS), RL = 25 Ω Data Sheet PROFET™+ 12V ‐25 0 25 50 75 100 125 150 Temperature [°C] Slew Rate at Turn OFF - dV/dtOFF = f(TJ;VS), RL = 25 Ω 39 Rev. 1.0, 2015-11-09 BTS5200-1EJA Characterization Results P_5.5.14 P_5.5.15 90,00 80,00 80,00 70,00 70,00 60,00 60,00 50,00 50,00 [µs] [µs] 90,00 40,00 40,00 30,00 30,00 20,00 20,00 8V 13.5V 10,00 8V 13.5V 10,00 18V 18V 0,00 0,00 ‐50 ‐25 0 25 50 75 100 125 150 ‐50 ‐25 0 25 Temperature [°C] 50 75 100 150 Temperature [°C] Turn ON TON = f(TJ;VS), RL = 25 Ω Turn OFF TOFF = f(TJ;VS), RL = 25 Ω P_5.5.19 P_5.5.20 100,00 100,00 90,00 90,00 80,00 80,00 70,00 70,00 60,00 60,00 [µJ] [µJ] 125 50,00 40,00 50,00 40,00 30,00 8V 30,00 8V 13.5V 20,00 13.5V 20,00 18V 18V 10,00 10,00 0,00 0,00 ‐50 ‐25 0 25 50 75 100 125 150 ‐50 Temperature [°C] Switch ON Energy EON = f(TJ;VS), RL = 25 Ω Data Sheet PROFET™+ 12V ‐25 0 25 50 75 100 125 150 Temperature [°C] Switch OFF Energy EOFF = f(TJ;VS), RL = 25 Ω 40 Rev. 1.0, 2015-11-09 BTS5200-1EJA Characterization Results 9.3 Protection Functions P_6.6.4 16,00 14,00 12,00 [A] 10,00 8,00 6,00 4,00 2,00 0,00 ‐50 ‐25 0 25 50 75 100 125 150 Temperature [°C] Overload Condition in the Low Voltage Area IL5(SC) = f(TJ); Data Sheet PROFET™+ 12V 41 Rev. 1.0, 2015-11-09 BTS5200-1EJA Characterization Results 9.4 Diagnostic Mechanism P_7.5.2 1,60 14,00 1,40 12,00 1,20 10,00 1,00 [mA] [µA] 8,00 0,80 6,00 0,60 4,00 0,40 8V 2,00 13.5V 0,20 18V 0,00 0,00 ‐50 ‐25 0 25 50 75 100 125 150 ‐50 ‐25 0 25 Temperature [°C] 50 75 100 125 Current Sense at no Load Open Load Detection ON State Threshold IIS = f(TJ;VS), IL = 0 IL(OL) = f(TJ) P_7.5.3 P_7.5.7 50,00 30,00 49,00 28,00 48,00 26,00 47,00 24,00 46,00 22,00 [mA] [V] 150 Temperature [°C] 45,00 20,00 44,00 18,00 43,00 16,00 42,00 14,00 41,00 12,00 40,00 10,00 ‐50 ‐25 0 25 50 75 100 125 150 ‐50 ‐25 Temperature [°C] 0 25 50 75 100 125 150 Temperature [°C] Sense Signal Maximum Voltage Sense Signal Maximum Current in Fault Condition VIS(AZ) = f(TJ) IIS(FAULT) = f(TJ) Data Sheet PROFET™+ 12V 42 Rev. 1.0, 2015-11-09 BTS5200-1EJA Characterization Results 9.5 Input Pins P_8.4.1 P_8.4.2 1,80 1,50 1,40 1,70 1,30 1,60 1,20 1,50 [V] [V] 1,10 1,00 0,90 1,40 1,30 0,80 1,20 0,70 1,10 0,60 0,50 1,00 ‐50 ‐25 0 25 50 75 100 125 150 ‐50 ‐25 0 25 Temperature [°C] 50 75 100 125 150 75 100 125 150 Temperature [°C] Input Voltage Threshold Input Voltage Threshold VVIN(L)= f(TJ) VVIN(H)= f(TJ) P_8.4.3 P_8.4.5 20,00 600,00 18,00 500,00 16,00 14,00 400,00 [µA] [mV] 12,00 300,00 10,00 8,00 200,00 6,00 8V 100,00 4,00 13.5V 2,00 18V 0,00 0,00 ‐50 ‐25 0 25 50 75 100 125 150 ‐50 Temperature [°C] Input Voltage Hysteresis VIN(HYS) = f(TJ;VS) Data Sheet PROFET™+ 12V ‐25 0 25 50 Temperature [°C] Input Current High Level IIN(H) = f(TJ) 43 Rev. 1.0, 2015-11-09 BTS5200-1EJA Application Information 10 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. VBAT Voltage Regulator T1 OUT VS GND Z CVS ROL VS VDD I/O RDEN I/O RIN DEN Micro controller OUT IN OUT4 COUT RPD OUT3 IS RSENSE A/D GND CSENSE RIS GND RGND Figure 26 R5W D Application Diagram with BTS5200-1EJA Note: This is a very simplified example of an application circuit. The function must be verified in the real application. Table 10 Bill of Material Reference Value Purpose RIN 4.7 kΩ Protection of the microcontroller during overvoltage, reverse polarity Guarantee BTS5200-1EJA channel is OFF during loss of ground RDEN 4.7 kΩ Protection of the microcontroller during overvoltage, reverse polarity RPD 47 kΩ Polarization of the output for short circuit to VS detection Improve BTS5200-1EJA immunity to electomagnetic noise Data Sheet PROFET™+ 12V 44 Rev. 1.0 2015-11-09 BTS5200-1EJA Application Information Table 10 Bill of Material (cont’d) Reference Value Purpose ROL 1.5 kΩ Ensures polarization of the BTS5200-1EJA output during open load in OFF diagnostic RIS 1.2 kΩ Sense resistor RSENSE 4.7 kΩ Overvoltage, reverse polarity, loss of ground. Value to be tuned with micro controller specification. CSENSE 100 pF Sense signal filtering. COUT 10nF Protection of the device during ESD and BCI RGND 1 kΩ Protection of the BTS5200-1EJA during overvoltage D BAS21 Protection of the BTS5200-1EJA during reverse polarity Z 36V Zener diode Protection of the device during overvoltage CVS 100 nF Filtering of voltage spikes at the battery line T1 BC 807 Switch the battery voltage for open load in OFF diagnostic Data Sheet PROFET™+ 12V 45 Rev. 1.0 2015-11-09 BTS5200-1EJA Application Information 10.1 Further Application Information • Please contact us to get the pin FMEA • Existing App. Notes • For further information you may visit http://www.infineon.com/profet Data Sheet PROFET™+ 12V 46 Rev. 1.0 2015-11-09 BTS5200-1EJA Package Outlines 11 Package Outlines 0.35 x 45˚ 1.27 0.41±0.09 2) 0.2 M 0.19 +0.06 0.08 C Seating Plane C A-B D 8x 0.64 ±0.25 D 0.2 6 ±0.2 8˚ MAX. C 0.1 C D 2x 1.7 MAX. Stand Off (1.45) 0.1+0 -0.1 3.9 ±0.11) M D 8x Bottom View 8 1 5 1 4 8 4 5 2.65 ±0.2 3 ±0.2 A B 4.9 ±0.11) 0.1 C A-B 2x Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width 3) JEDEC reference MS-012 variation BA Figure 27 PG-DSO-8-27-PO V01 PG-DSO-8-43 EP (Plastic Dual Small Outline Package) (RoHS-Compliant) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Data Sheet PROFET™+ 12V 47 Rev. 1.0 2015-11-09 BTS5200-1EJA Revision History 12 Revision History Version Date Changes 1.0 2015-11-09 Creation of the document Data Sheet PROFET™+ 12V 48 Rev. 1.0 2015-11-09 Trademarks of Infineon Technologies AG AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I2RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, myd™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SPOC™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2011-11-11 www.infineon.com Edition 2015-11-09 Published by Infineon Technologies AG 81726 Munich, Germany © 2014 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Legal Disclaimer for short-circuit capability Infineon disclaims any warranties and liabilities, whether expressed nor implied, for any shortcircuit failures below the threshold limit. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. 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