BTS54040LBAXUMA1

SPOC™+ 12V BTS54040-LBA SPI Power Controller Data Sheet Rev. 2.2, 2016-10-10 Automotive BTS54040-LBA Revision History Page or Item Subjects (major changes since previous revision) Rev. 2.2, 2016-10-10 All Data Sheet Package name changed General: Typos corrected and wording improved Table 1: Channel description improved Table 4: Footnote added Table 5: Updated and Footnote added Chapter 5.1.3: Updated Chapter 5.1.6: Note added Chapter 5.2: Updated Chapter 6.3: Updated Chapter 7.2: Updated Figure 28 updated 2 Rev. 2.2, 2016-10-10 BTS54040-LBA Revision History Page or Item Subjects (major changes since previous revision) Rev. 2.0, 2014-05-26 All Data Sheet General: Numbering of Figures and Tables changed Table 1 updated Chapter 4.2.1 added Chapter 4.2.2 added Parameter P_4.1.4: number changed to P_4.1.5 and max. value improved Parameter P_4.1.11: Max. Value improved Parameter P_4.1.28: Max. Value improved Parameter P_4.1.31: Max. Value improved Parameter P_4.1.34: Max. Value improved Parameter P_4.1.37: Max. Value improved Parameter P_4.1.39: Min. Value improved Parameter P_4.1.42: Max. Value improved Chapter 5 rewritten (content improved) Parameter P_5.3.7: Max. Value improved Parameter P_5.3.8: Test Condition updated and Max. Value improved Parameter P_5.3.10: Max. Value improved Parameter P_5.3.13: Test Condition updated Parameter P_5.3.14: Max. Value improved Parameter P_5.3.16: Typ. and Max. value improved Parameter P_5.3.17: Typ. and Min. Value improved Parameter P_5.3.23: Max. Value improved Chapter 6.1: RDS(ON) graphs removed Chapter 6.1: RDS(ON) variation factor added Chapter 6.4: Description improved Figure 16: Content updated Chapter 6.4.4: Note added Chapter 7.1: Content improved Chapter 7.1: IL(LIM) graphs removed Chapter 7.1: IL(LIM) variation factor added Chapter 7.2: Content improved Figure 18: Content updated Figure 19: Content and Title updated Figure 20: added Undervoltage Behavior shifted from Chapter 7.4 to Chapter 5.2.1 Figure 21: Content updated Chapter 8.1: Content improved Figure 22: Content updated Figure 23: Content updated Chapter 8.2.3 added Chapter 8.4: Content improved Parameter P_8.5.118 added 3 Rev. 2.2, 2016-10-10 BTS54040-LBA Revision History Page or Item Subjects (major changes since previous revision) Parameter P_9.4.19: Test Condition updated Parameter P_9.4.20: Test Condition updated Parameter P_9.4.22: Max. Value improved Parameter P_9.4.24: Min. Value improved Parameter P_9.4.26: Min. Value improved Parameter P_9.4.28: Min. Value improved Parameter P_9.4.30: Min. Value improved Parameter P_9.4.32: Min. Value improved Parameter P_9.4.34: Test Condition updated and Max. Value improved Chapter 9.5: Content improved Figure 33: Content updated Figure 34: Content updated Chapter 9.6: Content improved Chapter 9.6.3 added Chapter 9.7: Content improved Chapter 9.7.8: Descriptions improved and Footnote added Chapter 9.8 removed. Redundant information Figure 35: Content updated Table 15 updated BTS54040-LBA Parameter P_5.3.26: Max. Value improved Parameter P_5.3.27: Max. Value improved Parameter P_6.6.26: Max. Value improved Table 10 split into different tables Table 10 to Table 11: Unit of kILIS updated Parameter P_8.5.95: Max. Value improved Parameter P_8.5.96: Max. Value improved Rev. 1.0, 2013-03-24 All Data Sheet released Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, SPOC™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, μVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Data Sheet 4 Rev. 2.2, 2016-10-10 BTS54040-LBA Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2014-03-27 Data Sheet 5 Rev. 2.2, 2016-10-10 BTS54040-LBA Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 3.1 3.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Assignment BTS54040-LBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 4.1 4.2 4.2.1 4.2.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 19 19 21 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.2 5.2.1 5.3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ready mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operative mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limp Home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 24 25 25 25 26 26 26 26 27 28 6 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Status Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bulb and LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Inductive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Channels in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 30 31 32 32 32 33 33 34 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 37 41 41 41 41 42 8 8.1 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Data Sheet 6 Rev. 2.2, 2016-10-10 BTS54040-LBA Table of Contents 8.2 8.2.1 8.2.2 8.2.3 8.3 8.4 8.5 Load Current Sense Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Sense Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Sense Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load at ON Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Bypass Monitor Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Back Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 45 45 46 46 47 48 9 9.1 9.2 9.3 9.4 9.5 9.6 9.6.1 9.6.2 9.6.3 9.7 9.7.1 9.7.2 9.7.3 9.7.4 9.7.5 9.7.6 9.7.7 9.7.8 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Diagnosis Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Errors Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Warnings Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Swap Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Mode Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Back Regulation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register Bit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 52 53 54 55 57 60 60 61 61 62 62 62 62 63 63 63 64 64 10 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11 Package Outlines BTS54040-LBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Data Sheet 7 Rev. 2.2, 2016-10-10 BTS54040-LBA List of Figures List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Data Sheet Block Diagram BTS54040-LBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage and Current Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration TSON-24-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2s2p PCB Cross Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Board for Thermal Simulation with 600 mm² Cooling Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Board for Thermal Simulation with 2s2p Cooling Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Solder Area / Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Thermal Impedance. PCB setup according Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Thermal Resistance. PCB setup 1s0p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Mode state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limp Home Activation as function of VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS undervoltage behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RDS(ON) variation factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Switch Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching a Load (resistive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Current Limitation variation according to VDS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Temperature Sensor Operations - Short Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic and Absolute Temperature Sensor Operations - Overload Condition . . . . . . . . . . . . . . . Different counter reset according to HWCR.RCR bit value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram: Diagnosis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Sense Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Sense Multiplexer Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Sense Ratio in Open Load at ON condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combinatorial Logic for TER Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer in Daisy Chain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagram SPI Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relationship between SI and SO during SPI communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register content sent back to µC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BTS54040-LBA response after an error in transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BTS54040-LBA response after coming out of Power-On reset at VDD . . . . . . . . . . . . . . . . . . . . . . BTS54040-LBA response in case of a negative battery voltage transient . . . . . . . . . . . . . . . . . . . Application Circuit Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSON-24-8 Package drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSON-24 Package pads and stencil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 13 14 19 20 20 21 21 22 24 26 27 30 31 32 32 37 39 40 41 43 45 46 46 52 52 53 54 54 57 57 57 58 58 66 68 69 Rev. 2.2, 2016-10-10 BTS54040-LBA List of Tables List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Data Sheet Product Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device capability as function of VS and VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device function in relation to operation modes, VS and VDD voltages . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Diagnosis kILIS 39 mΩ ch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suggested Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 16 19 23 25 28 34 42 44 48 49 55 59 62 67 Rev. 2.2, 2016-10-10 BTS54040-LBA 1 Overview Features • 8-bit serial peripheral interface (daisy chain capable SPI) for control and diagnosis • CMOS compatible parallel input pins for four channels • Selectable AND- / OR-combination for parallel inputs (PWM control) • Load type configuration via SPI (bulbs or LEDs) for optimized load control • Very low stand-by current • Device ground independent from load ground • Green Product (RoHS-Compliant) • AEC Qualified  TSON-24-8 Description The BTS54040-LBA is a four channel high-side smart power switch in TSON-24-8 package providing embedded protective functions. It is specially designed to control standard exterior lighting in automotive applications. In order to use the same hardware, the device can be configured to bulb or LED mode. As a result, both load types are optimized in terms of switching and diagnosis behavior. It is designed to drive exterior lamps up to 27 W or the equivalent LED light. Table 1 Product Summary Operating Voltage Power Switch VS 5.5 … 28 V Logic Supply Voltage VDD 3.8 … 5.5 V Over Voltage Protection VS(AZ,min) 42 V Maximum Stand-By Current at 25 °C IVS(STB) 1 µA Maximum ON State Resistance at Tj = 150 °C 39 mΩ channels (Channel 1, 2, 3, 4) RDS(ON,max) 78 mΩ SPI Access Frequency fSCLK(max) 3 MHz Configuration and status diagnosis are done via SPI. An 8-bit serial peripheral interface (SPI) is used. The SPI is daisy chain capable. Type Package Marking BTS54040-LBA TSON-24-8 BTS54040-LBA Data Sheet 10 Rev. 2.2, 2016-10-10 BTS54040-LBA Overview The device provides a current sense signal per channel that is multiplexed to the diagnosis pin IS. It can be enabled and disabled via SPI commands. An over temperature flag per output is provided in the SPI diagnosis word. A multiplexed switch bypass monitor provides short-circuit to VS diagnosis. 39 mΩ channels can be configured to bulb or LED mode for maximum flexibility. The BTS54040-LBA provides a fail-safe feature via a Limp Home Input (LHI) pin and direct Input pins. The power transistors are built by N-channel vertical power MOSFETs with charge pumps. The device is monolithically integrated in SMART technology. Applications • High-side power switch for 12 V in automotive or industrial applications such as lighting, heating, motor driving, energy and power distribution • Especially designed for standard exterior lighting like position light, tail light, brake light, parking light, license plate light, indicators and equivalent in the LED technology • Replaces electromechanical relays, fuses and discrete circuits Protective Functions • Reverse battery protection with external components • Short circuit to ground protection • Stable behavior at under voltage • Current limitation • Absolute and dynamic temperature sensor • Thermal shutdown with latch after a limited amount of retries • Overvoltage protection • Loss of ground protection • Electrostatic discharge protection (ESD) Diagnostic Functions • Multiplexed proportional load current sense signal (IS) • Enable function for current sense signal configurable via SPI • High accuracy of current sense signal at wide load current range • Current sense ratio (kILIS) configurable for LEDs or bulbs • Very fast diagnosis in LED mode • Feedback on over temperature via SPI • Short circuit to VS detection • Monitoring of Input pins status Application Specific Functions • Fail-safe activation via LHI pin and control via input pins • Enhanced electromagnetic compatibility (EMC) for bulbs as well as LEDs • LED mode selection available • SPI with daisy chain capability • Switch bypass monitoring for detecting short circuit to VS Data Sheet 11 Rev. 2.2, 2016-10-10 BTS54040-LBA Block Diagram 2 Block Diagram VS VDD power supply IN1 temperature sensor gate control & charge pump driver logic IN2 IN3 clamp for inductive load IN4 load current sense load current limitation channel 1 2 IS LHI CS ESD protection 34 OUT4 OUT3 OUT2 current sense multiplexer limp home control LED mode control OUT1 switch bypass monitor SCLK SPI SO SI GND BlockDiagram_4chnoED.emf Figure 1 Data Sheet Block Diagram BTS54040-LBA 12 Rev. 2.2, 2016-10-10 BTS54040-LBA Block Diagram 2.1 Terms Figure 2 shows all terms used in this data sheet, with associated convention for positive values. VS IS VS IDD ISO VDD VDD SO I SI VSO SI I CS V SI I L1 CS V DS1 OUT1 ISCLK VCS VOUT1 SCLK V SCLK I L2 VDS 2 OUT2 ILHI V OUT2 LHI V LHI I L3 VDS3 OUT3 VOUT3 IIN1 I L4 IN1 OUT4 IIN2 VIN 1 IIN3 VIN2 IIN4 V IN3 VIN4 I IS VDS 4 V OUT4 IN2 IN3 IN4 IS VIS GND IGND Terms_4chnoED.emf Figure 2 Voltage and Current Definition In all tables of electrical characteristics, symbols related to channels without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS1 … VDS4). All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.STB) with the exception of the bits in the Diagnosis frames which are marked only with PARAMETER (e.g. VSMON). Data Sheet 13 Rev. 2.2, 2016-10-10 BTS54040-LBA Pin Configuration 3 Pin Configuration 3.1 Pin Assignment BTS54040-LBA (top view ) GND VDD SO SI SCLK CS LHI IN1 IN2 IN3 IN4 IS 1 24 2 23 3 22 4 21 5 20 6 7 25 VS 8 9 10 19 18 17 exposed pad (bottom ) 16 15 11 14 12 13 n.c.* n.c.* OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 n.c.* n.c.* Pinout_040noED.emf Figure 3 Data Sheet Pin Configuration TSON-24-8 14 Rev. 2.2, 2016-10-10 BTS54040-LBA Pin Configuration 3.2 Pin Definitions and Functions Pin Symbol I/O Function 25 VS – Positive power supply for high-side power switch 1 GND – Ground connection 2 VDD – Logic supply (5 V) 3 SO O Serial output of SPI interface 4 SI I Serial input of SPI interface (“high” active) 5 SCLK I Serial clock of SPI interface (“high” active) 6 CS I Chip select of SPI interface (“low” active); Integrated pull up to VDD 12 IS O Current sense output signal Power Supply Pins SPI & Diagnosis Pins Limp Home Input Pin (integrated pull-down, leave unused Limp Home Input pin unconnected) 7 LHI I Limp home activation signal (“high” active) Parallel Input Pins (integrated pull-down, leave unused pins unconnected) 8 IN1 I Input signal of channel 1 (“high” active) 9 IN2 I Input signal of channel 2 (“high” active) 10 IN3 I Input signal of channel 3 (“high” active) 11 IN4 I Input signal of channel 4 (“high” active) 21, 22 1) OUT1 O Protected high-side power output of channel 1 1) OUT2 O Protected high-side power output of channel 2 17, 18 1) OUT3 O Protected high-side power output of channel 3 1) OUT4 O Protected high-side power output of channel 4 13, 14 n.c.* – Not connected, internally not bonded, shorted together 23, 24 n.c.* – Not connected, internally not bonded, shorted together Power Output Pins 19, 20 15, 16 Not connected Pins 1) All outputs pins of each channel must be connected together on the PCB. All pins of an output are internally connected together. PCB traces have to be designed to withstand the maximum current which can flow. Data Sheet 15 Rev. 2.2, 2016-10-10 BTS54040-LBA Electrical Characteristics 4 Electrical Characteristics 4.1 Absolute Maximum Ratings Tj = -40 to +150 °C; all voltages with respect to ground Typical resistive loads connected to the outputs (unless otherwise specified): 39 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”) Table 2 Absolute Maximum Ratings1) Parameter Symbol Values Min. Typ. Unit Note / Test Condition Number Max. Supply Voltage Power supply voltage VS -0.3 28 V – P_4.1.1 Logic supply voltage VDD -0.3 5.5 V – P_4.1.2 V 2) P_4.1.3 Reverse polarity voltage -VS(rev) – 16 TjStart = 25 °C t ≤ 2 min. See Chapter 10 for setup Supply voltage for short circuit protection (single pulse) VS(SC) 0 Permanent short circuit number channel activations All channels nRSC1 - Voltage at power transistor VDS – 28 V 3) P_4.1.5 RECU = 20 mΩ l = 0 or 5 m RCable = 16 mΩ/m LCable = 1 µH/m 100 k 3) P_4.1.6 VDD = 5 V tON = 300 ms 42 V – P_4.1.8 V 4) P_4.1.9 Supply voltage for load dump protection VS(LD) – Current through ground pin IGND -100 25 mA t ≤ 2 min. P_4.1.10 Current through VDD pin IDD -25 30 mA t ≤ 2 min. P_4.1.11 |IL| – IL(LIM) A 5) P_4.1.12 mJ 6) P_4.1.15 42 RI = 2 Ω t = 400 ms Power Stages Load current Maximum energy dissipation single pulse 39 mΩ ch. EAS – 45 Tj(0) = 150 °C IL(0) = IL(nom) = P_6.6.17 Diagnosis Pin Voltage at sense pin IS VIS -0.3 VS V – P_4.1.24 Current through sense pin IS IIS -10 40 mA t ≤ 2 min. P_4.1.25 Input Pins Data Sheet 16 Rev. 2.2, 2016-10-10 BTS54040-LBA Electrical Characteristics Table 2 Absolute Maximum Ratings1) (cont’d) Parameter Symbol Values Min. Typ. Unit Note / Test Condition Number Max. Voltage at input pins VIN -0.3 6.0 V – P_4.1.26 Current through input pins IIN -0.75 0.75 mA – P_4.1.27 Current through input pins IIN -2.0 10 mA t ≤ 2 min. P_4.1.28 Voltage at chip select pin VCS -0.3 6.0 V – P_4.1.29 Current through chip select pin ICS -0.75 0.75 mA – P_4.1.30 Current through chip select pin ICS -2.0 10 mA t ≤ 2 min. P_4.1.31 Voltage at serial input pin VSI -0.3 6.0 V – P_4.1.32 Current through serial input pin ISI -0.75 0.75 mA – P_4.1.33 Current through serial input pin ISI -2.0 10 mA t ≤ 2 min. P_4.1.34 Voltage at serial clock pin VSCLK -0.3 6.0 V – P_4.1.35 Current through serial clock pin ISCLK -0.75 0.75 mA – P_4.1.36 Current through serial clock pin ISCLK -2.0 10 mA t ≤ 2 min. P_4.1.37 Current through serial output pin SO ISO -0.75 0.75 mA – P_4.1.38 Current through serial output pin SO ISO -10 2.0 mA t ≤ 2 min. P_4.1.39 -0.3 6.0 V – P_4.1.40 Current through Limp Home Input pin ILHI -0.75 0.75 mA – P_4.1.41 Current through Limp Home Input pin ILHI -2.0 10 mA t ≤ 2 min. P_4.1.42 -40 150 °C – P_4.1.45 – 60 K – P_4.1.46 Tstg -55 150 °C – P_4.1.47 ESD susceptibility HBM OUT pins vs. VS VESD -4 4 kV 7) P_4.1.48 ESD susceptibility HBM all pins vs. VDD VESD SPI Pins Limp Home Input Pin Voltage at Limp Home Input pin VLHI Temperatures Junction temperature Tj Dynamic temperature increase while ∆Tj switching Storage temperature ESD Susceptibility HBM 1.5 -2 2 7) kV 7) P_4.1.54 VESD V 8) V 8) 500 VESD1, 12, 13, 24 P_4.1.49 HBM -500 ESD Resistivity Pin 1, 12, 13, 24 (corner pins) to GND kV HBM ESD susceptibility HBM VESD other pins vs. GND incl. OUT pins vs. GND ESD Resistivity to GND -1.5 -750 750 P_4.1.51 CDM P_4.1.52 CDM 1) Not subject to production test, specified by design. 2) Device is mounted on an FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product (chip and package) was simulated on a 76.4 * 114.3 * 1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. Data Sheet 17 Rev. 2.2, 2016-10-10 BTS54040-LBA Electrical Characteristics 3) EOL tests according to AECQ100-012. Threshold limit for short circuit failures: 100 ppm. Please refer to the legal disclaimer for short-circuit capability at the end of this document. 4) RI is the internal resistance of the load dump pulse generator. 5) Current limitation is a protection feature. Protection features are not designed for continuous repetitive operation. 6) Pulse shape represents inductive switch OFF: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse 7) ESD resistivity, HBM according to ANSI/ESDA/JEDEC JS-001-2010 8) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1 Notes 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 18 Rev. 2.2, 2016-10-10 BTS54040-LBA Electrical Characteristics 4.2 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 3 Thermal Resistance Parameter Symbol Junction to Soldering Point Junction to Ambient Values Min. Typ. Max. RthJSP – 2 – RthJA – Unit Note / Test Condition Number K/W 1) P_4.2.1 Tj(0) = 105 °C measured to pin 25 21 – K/W 1)2) P_4.2.2 Tj(0) = 105 °C 1) Not subject to production test, specified by design. 2) Specified RthJA values is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip and package) was simulated on a 76.4 * 114.3 * 1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. 4.2.1 PCB Setup 70µm 1.5mm 35µm 0.3mm Figure 4 Data Sheet Zth_PCB_2s2p.emf 2s2p PCB Cross Section 19 Rev. 2.2, 2016-10-10 BTS54040-LBA Electrical Characteristics Figure 5 PC Board for Thermal Simulation with 600 mm² Cooling Area Figure 6 PC Board for Thermal Simulation with 2s2p Cooling Area Data Sheet 20 Rev. 2.2, 2016-10-10 BTS54040-LBA Electrical Characteristics Figure 7 Solder Area / Vias 4.2.2 Thermal Impedance BTS54040LBx 100 ZthJA[K/W] 10 1 0,1 0,0001 2s2p 1s0p600mm² 1s0p300mm² 1s0pfootprint 0,001 0,01 0,1 1 10 100 1000 Time[s] Figure 8 Data Sheet Typical Thermal Impedance. PCB setup according Figure 6 21 Rev. 2.2, 2016-10-10 BTS54040-LBA Electrical Characteristics BTS54040LBx 60 55 RthJA[K/W] 50 1s0p 45 40 35 30 0 100 200 300 400 500 600 700 Area[mm²] Figure 9 Data Sheet Typical Thermal Resistance. PCB setup 1s0p 22 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Supply 5 Power Supply The BTS54040-LBA is supplied by two voltage sources: VS (analog supply voltage) • VDD (digital supply voltage) The VS supply line is connected to a battery feed and used for the driving circuitry of the power stages, while VDD • is used for the SPI logic and for driving SO pin. VS and VDD supply voltages have an undervoltage detection circuit, which prevents the activation of the associated function in case the measured voltage is below the undervoltage threshold. More in detail: • An undervoltage on VDD supply prevents SPI communication. SPI registers are reset to default values. The retry counters used to protect the channels are reset therefore the channels are in “unlimited restart” mode. • An undervoltage on VS supply switches OFF all channels, even in Limp Home mode. The channels are enabled again as soon as VS = VS(OP). The voltage at pin VS is also monitored. In case of a negative voltage transient resulting in VS < VSMON with DCR.MUX ≠ “111B”, any SPI command sent by the micro-controller is not accepted (see Chapter 9.5 for further details). An overview of channel behavior according to different VS and VDD supply voltages is shown in Table 4 (the table is valid after a successful supply voltage ramp-up). Table 4 Device capability as function of VS and VDD VS ≤ VSMON (VSMON = P_5.3.12) VSMON < VS ≤ VS(UV) (VS(UV) = P_5.3.2) VS > VS(UV)3) VDD ≤ VDD(PO) (VDD(PO) = P_5.3.17) VDD > VDD(PO) Channels are OFF Channels are OFF SPI registers reset SPI registers protected1) SPI communication not available (fSCLK = 0 MHz) SPI communication available2) (fSCLK = 3 MHz) Limp Home mode not available Limp Home mode not available Channels are OFF Channels are OFF SPI registers reset SPI registers available SPI communication not available (fSCLK = 0 MHz) SPI communication available (fSCLK = 3 MHz) Limp Home mode available (channels are OFF) Limp Home mode available (channels are OFF) Channels cannot be controlled by SPI Channels can be switched ON and OFF SPI registers reset SPI registers available SPI communication not available (fSCLK = 0 MHz) SPI communication available (fSCLK = 3 MHz) Limp Home mode available Limp Home mode available 1) If DCR.MUX ≠ 111B, othervise SPI registers are available. 2) SPI response depends on DCR.MUX value. See Chapter 9.5 for further details. 3) The undervoltage condition on VS supply must be considered. See Chapter 5.2.1 for further details. Data Sheet 23 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Supply 5.1 Operation modes BTS54040-LBA has the following operation modes: • Stand-by mode • Idle mode • Ready mode • Operative mode • Limp Home mode The transition between operation modes is determined according to these variables: • logic level at LHI pin • logic level at INn pins • DCR.MUX bits state • OUT.OUTn bits state The state diagram including the possible transitions is shown in Figure 10. The behavior of BTS54040-LBA as well as some parameters may change in dependence from the operation mode of the device. Furthermore, due to the undervoltage detection circuitry which monitors VS and VDD supply voltages, some changes within the same operation mode can be seen accordingly. Power -up LHI = "low" & INn = "low" DCR.MUX ≠ "111" Idle Stand-by DCR.MUX = "111" or VDD < VDD(PO) or HWCR.RST = "1" (V (H D D WC < R. VD RS D( P T O) = &I "1 N " n & = I N „l o n w = “) „l o or w “) OUT.OUTn = "1" or INn = "high" LHI = "high" OUT.OUTn = "0" or (V DD < V DD(PO) & INn = "low") or HWCR.RST = "1" OUT.OUTn = "0" & INn = "low" Limp Home OUT.OUTn = "1" or INn = "high" LHI = "low" & INn = "high" DCR.MUX ≠ "111" Operative Ready DCR.MUX = "111" or (VDD < VDD(PO ) & INn = "high") or (HWCR.RST = "1" & INn = "high") LHI = "high" LHI = "high" LHI = "high" Note: Registers which are not mentioned are considered to be in default state Figure 10 PowerSupply_OpModes.emf Operation Mode state diagram There are three parameters describing the behavior of BTS54040-LBA: • status of output channels • status of SPI registers • status of SPI communication It is necessary to set DCR.MUX to a value different from 111B to command a switch ON of one or more channels. In alternative it is necessary to set the LHI to “high” - in this case the logic state of the Input pins is reflected to the outputs (if there is no undervoltage condition on VS supply). Data Sheet 24 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Supply Table 5 shows the correlation between device operation modes, VS and VDD supply voltages, and the state of the most important functions (channel status, SPI communication and SPI registers). Table 5 Device function in relation to operation modes, VS and VDD voltages Operation Mode Function VS ≤ VSMON VSMON > VS ≤ VS(UV) VS > VS(UV) Stand-by Channels OFF OFF Idle Ready Operative Limp Home 1) OFF 1) available1) SPI comm. available SPI registers available1) available1) available1) Channels OFF OFF OFF available 1) available1) SPI comm. all commands rejected1) available SPI registers available1) available1) available1) Channels OFF OFF OFF 1) 1) available1) SPI comm. available SPI registers available1) available1) available1) Channels OFF OFF follow OUT.OUTn and/or Input pins SPI comm. all commands rejected1) available1) available1) SPI registers available1) available1) available1) Channels OFF OFF follow Input pins SPI comm. available (read-only)1)2) available (read-only)1)2) available (read-only)1)2) SPI registers reset reset reset available 1) If VDD > VDD(PO), otherwise not available or in reset. 2) HWCR.CTC and HWCR.RST commands are accepted. 5.1.1 Power-up The Power-up condition is entered when one of the supply voltages (VS or VDD) is applied to the device. Both supplies are rising until they are above the undervoltage thresholds VS(OP) and VDD(PO) therefore the internal poweron signals are set. 5.1.2 Stand-by mode When BTS54040-LBA is in Stand-by mode, all outputs are OFF. The SPI registers can be programmed if VDD > VDD(PO). The current consumption is minimum (see parameter IVS(STB)). The circuitry that monitors VS versus the threshold VSMON is disabled, allowing the programming of the registers. Even if one Input pin is set to “high” or if one OUT.OUTn bit is set to “1”, all outputs stay switched OFF. 5.1.3 Idle mode In Idle mode, the internal supply circuitry is working and the device current consumption is increased. All channels are OFF and a command to switch ON one or more outputs (either via SPI or via Input pins) is accepted and executed, bringing the device into Operative mode. Data Sheet 25 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Supply 5.1.4 Ready mode In Ready mode, one or more outputs received a command to switch ON (either via SPI or via Input pins). Nevertheless all outputs are OFF because of DCR.MUX bits still set to 111B. It is necessary to change the value of those bits to bring the device into Operative mode and switch ON the channels. 5.1.5 Operative mode Operative mode is the normal operation mode of BTS54040-LBA when no Limp Home condition is set and one or more outputs are switched ON. Device current consumption is specified by parameter IGND. An undervoltage condition on VDD supply voltage brings the device into Stand-by mode (if all Input pins are set to “low”) or into Ready mode (if at least one Input pin is set to “high”). 5.1.6 Limp Home mode BTS54040-LBA enters Limp Home mode when LHI pin is set to “high”. SPI registers are reset to the default values after tLHI(ac) from the rising edge at pin LHI (see Figure 11 for further details). SPI communication is possible but only in read-only mode (SPI registers can be read but cannot be written, meaning that current sensing is not available). When VS ≤ VSMON and DCR.MUX ≠ 111B the logic state detected at pin LHI is ignored and the device doesn’t enter Limp Home mode. Note: The only write commands excepted in Limp Home mode are HWCR.CTC and HWCR.RST to clear the protection latches. VS VSMON LHI pin t < tLHI(ac ), min t < tLHI(ac ), min LHI bit t LHI(ac ) SPI state Normal operation t LHI(ac ) Reset Normal operation PowerSupply_LimpHomeActive.emf Figure 11 Limp Home Activation as function of VS 5.2 Reset condition One of the following 3 conditions resets the SPI registers to their default values: • VDD is not present or below the undervoltage threshold VDD(PO) LHI pin is set to “high” and VS > VSMON • a reset command (HWCR.RST = 1B) is executed • In particular, all channels are switched OFF (if the device is not in Limp Home mode with one or more Input pins set to “high”). In case of lack of VDD supply the internal retry counters are disabled therefore all channels are in “unlimited restart” mode. Data Sheet 26 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Supply 5.2.1 Undervoltage on VS Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative and the supply voltage drops below the undervoltage threshold VS(UV), the logic switches OFF the channels. As soon as the supply voltage VS is above the minimum operative voltage threshold VS(OP), the channels having either the corresponding Input pin set to “high” or the OUT.OUTn bit set to “1” are switched ON again (as shown in Figure 12). VOUT t VS VS(OP ) VS (UV) VS(HYS ) t PowerSupply_UVRVS.emf Figure 12 Data Sheet VS undervoltage behavior 27 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Supply 5.3 Electrical Characteristics Unless otherwise specified: VS = 7 V to 18 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °C Typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C Typical resistive loads connected to the outputs (unless otherwise specified): 39 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”) Table 6 Electrical Characteristics Power Supply Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number VS pin Operating voltage power switch VS(OP) 5.5 – 281) V VDS < 0.5 V P_5.3.1 Undervoltage shutdown VS(UV) – – 4.5 V OUTn = ON From VDS < 1 V to ILn = 0 A (see Figure 12) P_5.3.2 Undervoltage shutdown Hysteresis VS(HYS) – 350 – mV 1) P_5.3.3 Stand-by current for whole device IVS(STB) with loads – 0.1 1 μA 1) P_5.3.7 Stand-by current for whole device IVS(STB) with loads – Stand-by current for whole device IVS(STB) with loads – 4 15 μA VDD = 0 V VLHI = 0 V Tj = 150 °C P_5.3.26 Idle current for whole device with IVS(idle) loads, all channels OFF – 2.25 5 mA VDD = 5 V P_5.3.10 VDD = 0 V VLHI = 0 V Tj = 25 °C 0.1 2.5 μA 1) P_5.3.8 VDD = 0 V VLHI = 0 V Tj = 85 °C DCR.MUX = 110B Operating current for whole device IGND – 7 14 mA fSCLK = 0 MHz P_5.3.27 VS threshold for Limp Home VSMON 0.6 1.2 1.8 V VSMON = 1 P_5.3.12 Logic supply voltage VDD 3.8 – 5.51) V fSCLK = 3 MHz P_5.3.13 Logic supply current Normal operation IDD – 125 220 μA fSCLK = 0 MHz VCS = VDD= 5 V P_5.3.14 validation VDD pin DCR.MUX ≠ 111B Logic Stand-by current IDD(STB) – 35 70 μA fSCLK = 0 MHz VCS = VDD= 5 V P_5.3.16 DCR.MUX = 111B Data Sheet 28 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Supply Table 6 Electrical Characteristics Power Supply (cont’d) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. VDD(PO) 2.3 2.75 3.8 V SI = 0 V SCLK = 0 V CS = 0 V SO from 0 to Z P_5.3.17 L-input level at pin LHI VLHI(L) -0.3 – 1.0 V LHI = 1 (see Chapter 9.6.1) P_5.3.18 H-input level at pin LHI VLHI(H) 2.6 – 6.0 V – P_5.3.19 L-input current through pin LHI ILHI(L) 3 27 75 μA VLHI = 1.0 V P_5.3.20 H-input current through pin LHI ILHI(H) 7 30 75 μA VLHI = 2.6 V P_5.3.21 Power-On wake up time tWU(PO) – 200 – μs 1) P_5.3.22 Limp Home acknowledgement time tLHI(ac) 5 – 30 μs P_5.3.23 VDD = 5 V polling of Standard Diagnosis (see Chapter 9.6.1) until LHI = STB = 1 Reset command delay time td(RST) – – 100 μs 1) Power-On reset threshold voltage LHI Input Characteristics Timings P_5.3.25 1) Not subject to production test, specified by design. Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Typical values show the typical parameters expected from manufacturing at VS = 13.5 V, VDD = 4.3 V and Tj = 25 °C Data Sheet 29 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Stages 6 Power Stages The high-side power stages are built by N-channel vertical power MOSFETs with charge pumps. There are four channels implemented in the device. Each channel can be switched on via SPI register OUT or via an input pin, when available. All channels provide a load type configuration for bulbs or LEDs in register LGCR (see Chapter 9.7.4). The load type configuration can be changed in ON- as well as in OFF-state. 6.1 Output ON-State Resistance The ON-state resistance RDS(ON) depends mainly on the junction temperature Tj. Figure 13 shows the variation of RDS(ON) across the whole temperature range. The value “1” corresponds to the typical RDS(ON) measured at TJ = 25°C. RDS(ON) variation factor ("1" = RDS(ON) typical @ 25°C) 2.00 1.80 1.60 RDS(ON) variation factor 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -40 -20 0 20 40 60 80 100 120 140 160 Junction Temperature (°C) Figure 13 RDS(ON) variation factor The behavior in reverse polarity mode is described in Chapter 7. 6.2 Input Circuit There are two ways of using the input pins in combination with the register OUT by programming bit HWCR.COL in register HWCR (see Chapter 9.7.6). • HWCR.COL = 0: A channel is switched ON either by the according OUT.OUTn bit or by the input pin. • HWCR.COL = 1: A channel is switched ON by the according OUT.OUTn bit only, when the input pin is “high”. In this configuration, a PWM signal can be applied to the input pin and the channel is activated by the SPI register OUT (see Chapter 9.7.1). The default state (HWCR.COL = 0) is the OR-combination of the input signal and the SPI-bit. In Limp Home Mode (LHI pin set to “high”) the combinatorial logic is switched to OR-mode to enable a channel activation via the input pins only. Figure 14 shows the complete input switch matrix. Data Sheet 30 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Stages The zener diode protects the input circuit against ESD pulses. The current sink to ground ensures that the input signal is low in case of an open input pin. 6.3 Input Status Monitor The level of the input stage can be monitored via the input status monitor. The input status is indicated in the OUT register for the available input pin. After setting the bit SWCR.SWR = 1B, the readout of OUT.INSTn shows the state of the input pins. OUT4 OUT3 OUT2 OUT1 OR IN1 I IN1 & OR IN2 I IN2 & OR IN3 I IN2 & OR IN4 I IN3 INST & Gate Driver 1 Gate Driver 2 Gate Driver 3 Gate Driver 4 COL INST4 INST3 INST2 INST1 PowerStage_InputMatrix_4chnoED.emf Figure 14 Data Sheet Input Switch Matrix 31 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Stages 6.4 Power Stage Output The power stages are built to be used in high side configuration (Figure 15). The power DMOS switches with a dedicated slope, which is optimized in terms of electromagnetic emission (EME). Defined slew rates allow lowest EME during PWM operation at low switching losses. VS VDS VS OUT GND VOUT PowerStage_Output.emf Figure 15 Power Stage Output 6.4.1 Bulb and LED Mode All four channels can be configured in bulb and LED mode via the SPI initialization registers LGCR when SWCR.SWR = 0. The default state is LGCR.LEDn = 0. During LED mode the following parameters are changed for an optimized functionality with LED loads: ON-state resistance RDS(ON), switching timings (tdelay(ON), tdelay(OFF), tON, tOFF), slew rates dV/dtON and dV/dtOFF, load current protections IL(LIM) and current sense ratio kILIS. 6.4.2 Switching Resistive Loads When switching resistive loads the following switching times and slew rates can be considered. IN / OUT.OUTn V OUT tON tOFF t delay(ON) tdelay (OFF ) t 90% of Vs 70% of Vs 70% of Vs dV / dtOFF dV / dtON 30% of Vs 30% of Vs 10% of Vs t PowerStage_SwitchON.emf Figure 16 Data Sheet Switching a Load (resistive) 32 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Stages 6.4.3 Switching Inductive Loads When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device due to overvoltage, there is a voltage clamp mechanism implemented which limits that negative output voltage to a certain level (VDS(CL) (Chapter 6.5)). See Figure 15 for details.Please refer also to Chapter 7.4. The maximum allowed load inductance is limited. 6.4.4 Switching Channels in Parallel In case of appearance of a short circuit with channels in parallel driving a single load, BTS54040-LBA output stages are not synchronized in the restart event. When all channels connected to the same load are in temperature limitation, the channel which has cooled down the fastest doesn't wait for the other ones to be cooled down as well to restart. Thus, it is not recommended to use the device with channels in parallel. Note: In case of parallel channel operation, short circuit robustness may be reduced and nRSC1 is not guaranteed any more. Data Sheet 33 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Stages 6.5 Electrical Characteristics Unless otherwise specified: VS = 7 V to 18 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °C Typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C Typical resistive loads connected to the outputs (unless otherwise specified): 39 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”) Table 7 Electrical Characteristics Power Stages Parameter Symbol Values Min. Typ. Max. – 39 – Unit Note / Test Condition Number mΩ 1) P_6.6.9 Output Characteristics On-State resistance 39 mΩ ch. RDS(ON) VS = 9 V to 18 V IL = 2.6 A Tj = 25 °C LGCR.LEDn = 0 On-State resistance 39 mΩ ch. RDS(ON) – – 78 mΩ VS = 9 V to 18 V IL = 2.6 A Tj = 150 °C P_6.6.10 LGCR.LEDn = 0 On-State resistance 39 mΩ ch. in LED mode RDS(ON) – 137 – mΩ 1) P_6.6.11 VS = 9 V to 18 V IL = 0.6 A Tj = 25 °C LGCR.LEDn = 1 On-State resistance 39 mΩ ch. in LED mode RDS(ON) – – 275 mΩ VS = 9 V to 18 V IL = 0.6 A Tj = 150 °C P_6.6.12 LGCR.LEDn = 1 Nominal load current 39 mΩ ch. (all channels active) IL(nom) – Output clamp VDS(CL) 42 Output leakage current per channel Tj ≤ 85°C 39 mΩ ch. IL(OFF) 2 – A 1) P_6.6.17 TA = 85 °C Tj < 150 °C – 47 0.02 54 0.5 V IL = 20 mA P_6.6.19 µA 2) P_6.6.22 VIN = 0 V or floating OUT.OUTn = 0 Tj ≤ 85°C Stand-by or Idle mode Output leakage current per channel Tj = 150°C 39 mΩ ch. IL(OFF) – 1.3 4.5 µA VIN = 0 V or floating P_6.6.26 OUT.OUTn = 0 Tj = 150°C Stand-by or Idle mode Input Characteristics L-input level VIN(L) -0.3 – 1.0 V – P_6.6.28 H-input level VIN(H) 2.6 – 6.0 V – P_6.6.29 L-input current IIN(L) 3 27 75 µA VIN = 1.0 V P_6.6.30 H-input current IIN(H) 7 30 75 µA VIN = 2.6 V P_6.6.31 Data Sheet 34 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Stages Table 7 Electrical Characteristics Power Stages (cont’d) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Turn-ON delay to tdelay(ON) 10% VS (Logical propagation delay from input INn to output OUTn) 39 mΩ ch. 10 30 70 µs VS = 13.5 V LGCR.LEDn = 0 P_6.6.36 Turn-ON delay to tdelay(ON) 10% VS (Logical propagation delay from input INn to output OUTn) 39 mΩ ch. in LED mode 3 10 25 µs VS = 13.5 V LGCR.LEDn = 1 P_6.6.37 tdelay(OFF) Turn-OFF delay to 90% VS (Logical propagation delay from input INn to output OUTn) 39 mΩ ch. 10 30 70 µs VS = 13.5 V LGCR.LEDn = 0 P_6.6.43 Turn-OFF delay to tdelay(OFF) 90% VS (Logical propagation delay from input INn to output OUTn) 39 mΩ ch. in LED mode 3 10 25 µs VS = 13.5 V LGCR.LEDn = 1 P_6.6.44 30 75 180 µs VS = 13.5 V P_6.6.50 Timings Turn-ON time to 90% VS 39 mΩ ch. tON Turn-ON time to 90% VS 39 mΩ ch. in LED mode tON 10 25 55 µs VS = 13.5 V LGCR.LEDn = 1 P_6.6.51 Turn-OFF time to 10% VS 39 mΩ ch. tOFF 30 75 180 µs VS = 13.5 V LGCR.LEDn = 0 P_6.6.57 Turn-OFF time to 10% VS 39 mΩ ch. in LED mode tOFF 10 25 55 µs VS = 13.5 V LGCR.LEDn = 1 P_6.6.58 Turn-ON/OFF matching 39 mΩ ch. tON - tOFF -30 0 50 µs VS = 13.5 V LGCR.LEDn = 0 P_6.6.68 Turn-ON/OFF matching 39 mΩ ch. in LED mode tON - tOFF -20 0 20 µs VS = 13.5 V LGCR.LEDn = 1 P_6.6.69 Turn-ON slew rate 30% to 70% VS 39 mΩ ch. dV/ dtON 0.1 0.25 0.5 V/µs VS = 13.5 V LGCR.LEDn = 0 P_6.6.75 Turn-ON slew rate 30% to 70% VS 39 mΩ ch. in LED mode dV/ dtON 0.35 0.88 1.75 V/µs VS = 13.5 V LGCR.LEDn = 1 P_6.6.76 Data Sheet LGCR.LEDn = 0 35 Rev. 2.2, 2016-10-10 BTS54040-LBA Power Stages Table 7 Electrical Characteristics Power Stages (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Turn-OFF slew rate 70% to 30% VS 39 mΩ ch. -dV/dtOFF 0.1 0.25 0.5 V/µs VS = 13.5 V LGCR.LEDn = 0 P_6.6.82 Turn-OFF slew rate 70% to 30% VS 39 mΩ ch. in LED mode -dV/dtOFF 0.35 0.88 1.75 V/µs VS = 13.5 V P_6.6.83 LGCR.LEDn = 1 Output Voltage Drop Output voltage drop limitation at small load currents 39 mΩ ch. in LED mode VDS(NL) - 10 25 mV IL = 50 mA LGCR.GBRn = 1 P_6.6.94 1) Not subject to production test, specified by design. 2) Tested at Tj = -40 °C Data Sheet 36 Rev. 2.2, 2016-10-10 BTS54040-LBA Protection Functions 7 Protection Functions The device provides embedded protective functions, which are designed to prevent IC destruction under fault conditions described in this data sheet. Fault conditions are considered as “outside” normal operating range. Protective functions are neither designed for continuous nor for repetitive operation. 7.1 Over Load Protection The load current IL is limited by the device itself in case of over load or short circuit to ground. All channels have 2 steps of current limitation which are selected automatically depending on the voltage VDS across the power DMOS as show in Figure 17. Please note that VOUT = VS - VDS. The current limitation threshold when VDS = 5 V is taken as reference. Current limitation to the value IL(LIM) is realized by increasing the resistance of the output channel, which leads to fast DMOS temperature rise. Current limitation variation ("1" = IL(LIM) @ VDS = 5 V) 1.1 1 0.9 Current limitation variation factor 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 4 8 12 16 20 24 28 Drain Source Voltage (V) Figure 17 Typical Current Limitation variation according to VDS voltage 7.2 Over Temperature Protection Each channel incorporates both an absolute (Tj(SC)) and a dynamic (∆Tj(SW)) temperature sensor. An increase of junction temperature Tj above one of the two thresholds (Tj(SC) or ΔTj(SW)) switches OFF an overheated channel to prevent destruction. Any protective switch OFF deactivates the output until the temperature has reached an acceptable value. Each protective switch OFF event increments the error counter by one. The number of automatic reactivations is limited by nretry. If this number of retries is reached the channel turns OFF and latches OFF. The error information related to the given channel is available on the Standard Diagnosis and Errors Diagnosis. Executing HWCR.CTC = 1B will clear all thermal counters and errors on all channels. If the channel is active (either OUT.OUTn = 1B or INn = “high” and DCR.MUX ≠ 111B) it is turned on immediately after the SPI command. In addition the execution of the reset command (HWCR.RST = 1B) will clear the thermal counters. Data Sheet 37 Rev. 2.2, 2016-10-10 BTS54040-LBA Protection Functions For the condition n < nretry the counter of automatic reactivations is reset by every channel activation if HWCR.RCR bit is set to 1. In Figure 20 the different behavior of retry counters according to HWCR.RCR bit value can be seen. In Limp Home Mode, the thermal counters of the protection functions are only operative if VDD is provided in the specified range. Otherwise the counters are not active and all channels are in „unlimited restart“ mode. In case of the short circuit to ground, current sense ratio (kILIS) is deactivated as soon as VDS > VDS(SB) (Switch bypass monitor threshold). Usually a short circuit to ground condition tends to set VDS = VS therefore in most of the cases no current sensing diagnostic is possible in short circuit. The error information related to the given channel are available also on Warnings Diagnosis (ERRn bits). Refer to Figure 18 and Figure 19 for details. Data Sheet 38 Rev. 2.2, 2016-10-10 BTS54040-LBA Protection Functions IN / OUT.OUTn t IL IL(LIM) t Tj ΔTjS W ΔTjSW ΔTj SW ΔTjSW Tj (SC) t I IS t Internal counter 0 1 2 nretry ... 0 1 t ERR 0 1 0 1 t ERR_COUNTER 0 1 * ERR reset by : HWCR.CTC = 1 Figure 18 Data Sheet 0 t Protection_DynT_SC.emf Dynamic Temperature Sensor Operations - Short Circuit 39 Rev. 2.2, 2016-10-10 BTS54040-LBA Protection Functions IN / OUT.OUTn t IL IL(LIM ) t Tj Tj(SC) ΔTjSW ΔTjSW ΔTjSW t IIS t Internal counter 0 1 2 ... n retry 0 t ERR 0 1 0 t ERR_COUNTER 0 1 0 t * ERR reset by: HWCR.CTC = 1 Protection_DynT_OverLoad.emf Figure 19 Data Sheet Dynamic and Absolute Temperature Sensor Operations - Overload Condition 40 Rev. 2.2, 2016-10-10 BTS54040-LBA Protection Functions IN / OUT.OUTn t IL I L(LIM ) t Internal counter 0 1 2 3 4 5 0 1 2 0 1 t ERR 0 1 0 1 0 1 t 0 (default ) HWCR.RCR 1 t Protection_RCR.emf Figure 20 Different counter reset according to HWCR.RCR bit value 7.3 Reverse Polarity Protection In reverse polarity condition, power dissipation is caused by the intrinsic body diode of each DMOS channel as well as each ESD diode of the logic pins. The reverse current through the channels has to be limited by the connected loads.The current through ground pin GND, sense pin IS, logic power supply pin VDD, SPI pins, input pins and Limp Home Input pin has to be limited as well (please refer to the maximum ratings listed on Chapter 4.1). Note: No protection mechanism like temperature protection or current limitation is active during reverse polarity. 7.4 Over Voltage Protection In the case of supply voltages between VS(SC)max and VS(AZ) the output transistors are still operational and follow the input or the OUT register. Parameters are not warranted and lifetime is reduced compared to nominal voltage supply. In addition to the output clamp for inductive loads as described in Chapter 6.4.3, there is a clamp mechanism available for over voltage protection for the logic and all channels. 7.5 Loss of Ground In case of complete loss of the device ground connection, but loads connected to ground, the BTS54040-LBA securely changes to or stays in OFF-state. Please refer to Chapter 10 where an application setup is described. 7.6 Loss of VS In case of loss of VS connection in ON-state, all inductances of the loads have to be demagnetized through the ground connection or through an additional path from VS to ground. For example, a suppressor diode is recommended between VS and GND. Data Sheet 41 Rev. 2.2, 2016-10-10 BTS54040-LBA Protection Functions 7.7 Electrical Characteristics Unless otherwise specified: VS = 7 V to 18 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C Typical resistive loads connected to the outputs (unless otherwise specified): 39 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”) Table 8 Electrical Characteristics Protection Functions Parameter Symbol Values Min. Typ. Max. 25 32 44 Unit Note / Test Condition Number A 1) P_7.7.9 Over Load Protection Load current limitation 39 mΩ ch. IL(LIM) VDS = 5 V LGCR.LEDn = 0 Load current limitation 39 mΩ ch. IL(LIM) – 16 – A 1) P_7.7.10 VDS = 26 V LGCR.LEDn = 0 Load current limitation 39 mΩ ch. in LED mode IL(LIM) 6.5 9 16 A VDS = 5 V Tj = -40 °C P_7.7.11 LGCR.LEDn = 1 Load current limitation 39 mΩ ch. in LED mode IL(LIM) – 4.5 – A 1) P_7.7.12 VDS = 26 V LGCR.LEDn = 1 Over Temperature Protection Thermal shut down temperature Tj(SC) 150 170 200 °C 1) P_7.7.14 Thermal hysteresis of thermal shutdown ∆Tj(SC) – 20 – K 1) P_7.7.15 Dynamic temperature increase limitation while switching ∆Tj(SW) – 80 – K 1) P_7.7.16 Number of automatic retries at dynamic temperature sensor or over temperature shut down nretry – 8 9 1) P_7.7.17 VDS(REV) 400 650 800 mV IL = IL(nom) = P_6.6.17 Tj = 150 °C P_7.7.20 VS(AZ) 42 47 54 V IS = 4 mA P_7.7.22 Reverse Polarity Drain source diode voltage during reverse polarity 39 mΩ ch. Over Voltage Overvoltage protection 1) Not subject to production test, specified by design. Data Sheet 42 Rev. 2.2, 2016-10-10 BTS54040-LBA Diagnosis 8 Diagnosis For diagnosis purpose, the BTS54040-LBA provides a current sense signal at pin IS and a diagnosis word via SPI. There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be disabled by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. Please refer to Figure 21 for details. VS IIS 0 latch temperature sensor T gate control OR load current limitation OUT4 OUT3 OUT2 latch load current sense ERR1 OUT1 channel 1 VS DCR.MUX V DS(SB ) DCR. SBM current sense multiplexer IS RIS Diagnosis_4ch.emf Figure 21 Block Diagram: Diagnosis For diagnosis feedback at different operation modes, please see Table 9. Data Sheet 43 Rev. 2.2, 2016-10-10 BTS54040-LBA Diagnosis Table 9 Operation Modes 1) Operation Mode Input Level Output Current OUT.OUTn Level Sense VOUT IIS Error Flag ERR_COUNTERn2) Warning DCR.SBM Flag bit ERRn3) Normal Operation (Channel OFF) L / 0 (OFF-state) Short Circuit to GND GND Z 0 0 1 GND Z 0 0 1 Thermal shut down Z Z 02) 02) X Short Circuit to VS VS Z 0 0 0 Open Load Z Z 0 0 X ~ VS IL / kILIS 0 0 0 < VS Z 0 0 X Dynamic or Absolute Thermal Limitation → Channel switched OFF Z Z 0 1 X Dynamic or Absolute Thermal Limitation nretry reached → Channel latched OFF Z Z 12) 1 X Short Circuit to GND ~GND Z 0 0 1 Short Circuit to VS VS < IL / kILIS 0 0 0 Open Load VS Z 0 0 Normal Operation (Channel ON) Current Limitation H/1 (ON-state) 0 1) L = “low” level, H = “high” level, Z = high impedance, potential depends on leakage currents and external circuit. X = undefined. 2) The over temperature flag is set latched and can be cleared by setting HWCR.CTC = 1B. 3) The warning flags are latched until they are reset (see HWCR.RCR description). 8.1 Diagnosis Word at SPI Diagnostic information about the status of each channel is provided through SPI. In the Standard Diagnosis the ERR_MUX bit reports if there is a channel which had already enough restarts to reach the maximum allowed number of retries nretry (P_7.7.17). If 2 or more channels are latched OFF due to that, ERR_MUX bits aren't enough to identify which channels are OFF. In such cases, it is possible to get an overview channel by channel using ERR_COUNTERn bits in Errors Diagnosis (see Chapter 9.6.2) It is possible to check if one or more channels had some retries during switching ON, although the limit of nretry was not reached. An overview channel by channel of thermal counter status is available using ERRn bits in Warnings Diagnosis (see Chapter 9.6.3). For both ERR_COUNTERn and ERRn the information on channel n is given at bit n-1 (e.g. bit 0 indicates status of channel 1). Data Sheet 44 Rev. 2.2, 2016-10-10 BTS54040-LBA Diagnosis 8.2 Load Current Sense Diagnosis There is a current sense signal available at pin IS which provides a current proportional to the load current of one selected channel. The selection is done by a multiplexer which is configured via SPI. 8.2.1 Current Sense Signal The current sense signal (ratio kILIS = IL / IS) is provided during ON-state as long as no failure mode occurs. For dedicated channels the ratio kILIS can be adjusted to the load type (LED or bulb) via SPI register LGCR. The accuracy of the ratio kILIS depends on the load current and temperature. Usually a resistor RIS is connected to the current sense pin. It is recommended to use resistors 1.5 kΩ < RIS < 5 kΩ. A typical value is 2.7 kΩ. The current sense signal of a channel is not active when the channel is OFF or when the protection functions (current limitation, over temperature or dynamic temperature sensors) are active. If the maximum number of automatic reactivations nretry is reached (n = nretry), the current sense signal of the affected channel is deactivated until the reset of the counters by setting HWCR.CTC bit to 1. Details about timings between the current sense signal IIS and the output voltage VOUT and the load current IL can be found in Figure 22. IN / OUT.OUTn OFF ON OFF tON tOFF t VOUT t IL ts IS (ON) ts IS (LC) tdIS (OFF) t IIS t Diagnosis_SenseTiming.emf Figure 22 Current Sense Signal Timings 8.2.2 Current Sense Multiplexer There is a current sense multiplexer implemented in the BTS54040-LBA that routes the sense current of the selected channel to the diagnosis pin IS. The channel is selected via SPI register DCR.MUX. The sense current can also be disabled by SPI register DCR.MUX. For details on timing of the current sense multiplexer, please refer to Figure 23. Data Sheet 45 Rev. 2.2, 2016-10-10 BTS54040-LBA Diagnosis CS DCR.MUX 110 001 000 110 ts IS (EN) t s IS(MUX) t tdIS (MUX ) IIS t Diagnosis_MuxTiming.emf Figure 23 Current Sense Multiplexer Timings 8.2.3 Open Load at ON Diagnosis If a channel is ON in Open Load condition, a small current can still flow, for example because of humidity. The parameter IL(OL) gives the threshold of recognition for such leakage current. If the voltage measured at the sense resistor RSENSE corresponds to a current IIS(OL) (4 µA), then the current flowing at the output in ON state is within the limits given by IL(OL). Figure 24 shows the sense current behavior once a channel in Open Load at ON condition is selected with the sense current multiplexer. The red curve show a typical product curve. The blue line shows the ideal kILIS ratio. IIS IIS(OL ) IIS(en) IL(OL ) Figure 24 Current Sense Ratio in Open Load at ON condition 8.3 Switch Bypass Monitor Diagnosis IL To detect short circuit to VS, there is a switch bypass monitor implemented. In case of short circuit between the output pin OUT and VS in ON-state, the current flows through the power transistor as well as through the short circuit (bypass) with undefined share between the two. As a result, the current sense signal shows lower values than expected by the load current. In OFF-state, the output voltage remains close to VS potential which leads to a small VDS. The switch bypass monitor compares the threshold VDS(SB) with the voltage VDS across the power transistor of that channel which is selected by the current sense multiplexer (DCR.MUX). The result of the comparison can be read in SPI register DCR.SBM. Data Sheet 46 Rev. 2.2, 2016-10-10 BTS54040-LBA Diagnosis 8.4 Gate Back Regulation To increase the current sense accuracy, the Gate Back Regulation (GBR) function is implemented. This function monitors the VDS voltage at the output and if the value is equal to or lower than VDS(NL) the output DMOS gate is partially discharged. This increases output DMOS resistance so that VDS = VDS(NL) even for very small output currents. The VDS increase allows the current sensing circuitry to work with better accuracy, providing tighter kILIS values for output currents in the low range. This function is active by default (LGCR.GBRn bits set to “1” after a reset). According to output current, GBR function can be left active or disabled. Even if left active, Gate Back Regulation circuitry may not be working because the measured VDS is bigger than VDS(NL) (depending on output current, junction temperature, output DMOS resistance). Due to production and temperature variations, GBR circuitry can affect kILIS performance in negative way for some output current values. For this reason, Table 10 indicates for which output currents it is necessary to deactivate GBR (setting the corresponding LGCR.GBRn bit to “0”) to reach the desired current accuracy. If no indication is given, then the GBR function is assumed to be enabled (LGCR.GBRn bit set to “1”). It is recommended to keep GBR circuitry enabled for Open Load at ON diagnosis. The circuitry that controls GBR function can be deactivated with the following SPI command sequence: • SWCR.SWR = 1 (SPI command: 11001100B) • LGCR.GBRn = 0 (SPI command: 1101aaaaB where “aaaa”B is the new value for LGCR.GBRn bits) • (optional but recommended: SWCR.SWR = 0 (SPI command: 11000100B) Refer to Chapter 9.7 for more details. Data Sheet 47 Rev. 2.2, 2016-10-10 BTS54040-LBA Diagnosis 8.5 Electrical Characteristics Unless otherwise specified: VS = 7 V to 18 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °C Typical values: VS = 13.5 V, VDD= 4.3 V, Tj = 25 °C Typical resistive loads connected to the outputs (unless otherwise specified): 39 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”) Measurement setup used for kILIS (unless otherwise specified): When IL ≤ 1.3 A all channels are ON at the same time with equal IL When IL ≥ 2.0 A only the measured channel is ON, all other channels have IL = 0 Table 10 Electrical Characteristics Diagnosis kILIS 39 mΩ ch. Parameter Symbol Values Min. Typ. Unit Max. Note / Test Condition Number Current Sense Ratio Signal in the Nominal Area, Stable Load Current Condition 39 mΩ ch. kILIS03 -36 % 2000 +36 % – P_8.5.49 Current sense ratio IL05 = 600 mA kILIS05 -29 % 2000 +29 % – P_8.5.51 Current sense ratio IL07 = 1.3 A kILIS07 -15 % 2000 +15 % – P_8.5.53 Current sense ratio IL09 = 2.6 A kILIS09 -12 % 2000 +12 % – P_8.5.55 Current sense ratio IL10 = 4 A kILIS10 -11 % 2000 +11 % – P_8.5.56 Current sense ratio IL03 = 300 mA Current Sense Ratio Signal in the Nominal Area, Stable Load Current Condition 39 mΩ ch. in LED mode kILIS00 -52 % 620 +52 % – P_8.5.57 Current sense ratio IL02 = 150 mA kILIS02 -30 % 570 +30 % – P_8.5.59 Current sense ratio IL03 = 300 mA kILIS03 -15 % 570 +15 % – P_8.5.60 Current sense ratio IL05 = 600 mA kILIS05 -11 % 570 +11 % – P_8.5.62 Current sense ratio IL06 = 1 A kILIS06 -10 % 570 +10 % – P_8.5.63 Current sense ratio IL00 = 20 mA Data Sheet 48 Rev. 2.2, 2016-10-10 BTS54040-LBA Diagnosis Table 11 Electrical Characteristics Diagnosis Parameter Sense pin maximum voltage Symbol VIS(AZ) Values Min. Typ. Max. 42 47 54 Unit Note / Test Condition Number V IIS = 5 mA P_8.5.75 % 1) P_8.5.80 Current Sense Drift Over Current and Temperature per Device Current sense drift over current and temperature per device 39 mΩ ch. ΔkILIS(T) Current sense drift over current and temperature per device 39 mΩ ch. in LED mode ΔkILIS(T) Data Sheet -8 – 8 kILIS09 versus kILIS07 LGCR.LEDn = 0 -9.5 – 9.5 % 1) P_8.5.81 kILIS05 versus kILIS03 LGCR.LEDn = 1 49 Rev. 2.2, 2016-10-10 BTS54040-LBA Diagnosis Table 11 Electrical Characteristics Diagnosis (cont’d) Parameter Symbol Values Min. Typ. Unit Max. Note / Test Condition Number Current Sense Drift of Unaffected Channel during Inverse Current of other Channels One channel with IL(IC) = - ILn, all other channels with ILn DCR.MUX ≠ and set to sense any of the channels not in Inverse current condition Current sense drift of ΔkILIS(IC) unaffected channels during inverse current of one channel -20 – 20 % 1) P_8.5.84 IL1 = 2.6 A IL2 = 2.6 A IL3 = 2.6 A IL4 = 2.6 A Sense Pin - Currents Maximum steady state current sense output current 39 mΩ ch. IIS(MAX) 3.8 – 15 mA VIS = 0 V VS ≥ 8 V P_8.5.88 Current sense leakage / offset current IIS(en) – – 1 μA 1) P_8.5.118 Tj ≤ 85 °C IL = 0 mA DCR.MUX ≠ B Current sense leakage / offset current IIS(en) – – 3.2 μA Tj = 150 °C IL = 0 mA P_8.5.90 DCR.MUX ≠ B Open load detection threshold in ON state 39 mΩ ch. IL(OL) Open load detection threshold in ON state 39 mΩ ch. in LED mode IL(OL) – – 7.5 mA IIS(OL) = 4 μA LGCR.LEDn = 1 P_8.5.96 Current sense leakage, while diagnosis disabled IIS(dis) – 0.01 1 μA IL2 = 2.6 A P_8.5.98 – – 21.5 mA IIS(OL) = 4 μA P_8.5.95 LGCR.LEDn = 0 DCR.MUX = 110B Sense Pin - Timings Current sense settling time tsIS(ON) after channel activation 39 mΩ ch. – Current sense settling time tsIS(ON) after channel activation 39 mΩ ch. in LED mode – Current sense desettling time after channel deactivation Data Sheet tdIS(OFF) – 250 μs VS = 13.5 V RIS = 2.7 kΩ P_8.5.103 LGCR.LEDn = 0 – 100 μs VS = 13.5 V RIS = 2.7 kΩ P_8.5.104 LGCR.LEDn = 1 – – 25 μs P_8.5.106 VS = 13.5 V RIS = 2.7 kΩ 50 Rev. 2.2, 2016-10-10 BTS54040-LBA Diagnosis Table 11 Electrical Characteristics Diagnosis (cont’d) Parameter Symbol Current sense settling time tsIS(LC) after change of load current 39 mΩ ch. Values Min. Typ. Max. – – 25 Unit Note / Test Condition Number μs 1) P_8.5.111 IL = 2.6 A to 1.3 A VS = 13.5 V RIS = 2.7 kΩ LGCR.LEDn = 0 Current sense settling time tsIS(LC) after change of load current 39 mΩ ch. in LED mode – – 25 μs 1) P_8.5.112 IL = 1.0 A to 0.6 A VS = 13.5 V RIS = 2.7 kΩ LGCR.LEDn = 1 Current sense settling time tsIS(EN) after current sense activation – – 25 μs P_8.5.114 RIS = 2.7 kΩ IL2 = 2.6 A DCR.MUX: 110B → 001B Current sense settling time tsIS(MUX) after multiplexer channel change – – 25 μs P_8.5.115 RIS = 2.7 kΩ IL2 = 2.6 A IL3 = 4 A DCR.MUX: 001B → 010B Current sense deactivation tdIS(MUX) time – – 25 μs 1) P_8.5.116 RIS = 2.7 kΩ DCR.MUX: 010B → 110B Switch Bypass Monitor Switch bypass monitor threshold VDS(SB) 1.5 3.3 4.5 V OFF state P_8.5.117 1) Not subject to production test, specified by design. Data Sheet 51 Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) 9 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is taken only when a multiple of 8 bit has been transferred. The interface provides daisy chain capability with 8-bit SPI devices. SO SI CS MSB MSB 6 5 4 3 2 1 6 5 4 3 2 1 LSB LSB CS SCLK time SPI _8bit.emf Figure 25 Serial Peripheral Interface 9.1 SPI Signal Description CS - Chip Select The system micro controller selects the BTS54040-LBA by means of the CS pin. Whenever the pin is in “low” state, data transfer can take place. When CS is in “high” state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS “high” to “low” Transition • The requested information is transferred into the shift register. • SO changes from high impedance state to “high” or “low” state depending on the signal level at pin SI. TER SI OR 1 SO 0 SI SO S SPI CS SCLK S SPI _TER.emf Figure 26 Data Sheet Combinatorial Logic for TER Flag 52 Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) CS “low” to “high” Transition • Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the command is ignored. • Data from shift register is transferred into the addressed register. SCLK - Serial Clock This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in “low” state whenever chip select CS makes any transition, otherwise the command may be not accepted. SI - Serial Input Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Chapter 9.5 for further information. SO Serial Output Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to “low” state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Chapter 9.5 for further information. 9.2 Daisy Chain Capability The SPI of BTS54040-LBA provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 27), in order to build a chain. The end of the chain is connected to the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line of each device in the chain. Figure 27 SO SPI SI SO SPI SCLK SI device 3 CS SCLK MI MCS MCLK SO SPI CS SI CS MO device 2 SCLK device 1 SPI_DaisyChain.emf Daisy Chain Configuration In the SPI block of each device, there is one shift register where each bit from SI line is shifted in each SCLK. The bit shifted out occurs at the SO pin. After eight SCLK cycles, the data transfer for one device is finished. In single chip configuration, the CS line must turn “high” to make the device acknowledge the transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in daisy chain, three times 8 bits have to be shifted through the devices. After that, the MCS line must turn “high” (see Figure 28). Data Sheet 53 Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) MI MO SO device 3 SO device 2 SO device 1 SI device 3 SI device 2 SI device 1 MCS MCLK time SPI_DaisyChain_2.emf Figure 28 Data Transfer in Daisy Chain Configuration 9.3 Timing Diagrams t CS(lead) tCS (lag) tCS(td) tSCLK(P ) CS tSCLK (H) V CS(H) V CS(L) tSCLK (L) V SCLK(H) V SCLK(L) SCLK tSI (s u) t SI (h) V SI(H) V SI(L) SI t SO(en) tSO(v ) tSO (dis ) V SO(H) V SO(L) SO SPI _Timings.emf Figure 29 Data Sheet Timing Diagram SPI Access 54 Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) 9.4 Electrical Characteristics Unless otherwise specified: VS = 7 V to 18 V, Tj = -40 °C to +150 °C, VDD = 3.8 V to 5.5 V Typical values: VS = 13.5 V, Tj = 25 °C, VDD = 4.3 V Table 12 Electrical Characteristics Serial Peripheral Interface (SPI) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Input Characteristics (CS, SCLK, SI) - L Level of pin CS VCS(L) -0.3 – 1.0 V VDD = 4.3 V P_9.4.1 SCLK VSCLK(L) -0.3 – 1.0 V VDD = 4.3 V P_9.4.2 SI VSI(L) -0.3 – 1.0 V VDD = 4.3 V P_9.4.3 Input Characteristics (CS, SCLK, SI) - H Level of pin CS VCS(H) 2.6 – VDD V VDD = 4.3 V P_9.4.4 SCLK VSCLK(H) 2.6 – VDD V VDD = 4.3 V P_9.4.5 SI VSI(H) 2.6 – VDD V VDD = 4.3 V P_9.4.6 L-input pull-up current at CS pin -ICS(L) 7 30 75 μA VDD = 4.3 V VCS = 1.0 V P_9.4.7 H-input pull-up current at CS pin -ICS(H) 3 27 75 μA VDD = 4.3 V VCS = 2.6 V P_9.4.8 SCLK ISCLK(L) 3 27 75 μA VSCLK = 1.0 V VDD = 4.3 V P_9.4.9 SI ISI(L) 3 27 75 μA VSI = 1.0 V VDD = 4.3 V P_9.4.10 SCLK ISCLK(H) 7 30 75 μA VSCLK = 2.6 V VDD = 4.3 V P_9.4.11 SI ISI(H) 7 30 75 μA VSI = 2.6 V VDD = 4.3 V P_9.4.12 L level output voltage VSO(L) 0 – 0.5 V ISO = -0.5 mA P_9.4.13 H level output voltage VSO(H) VDD - – VDD V ISO = 0.5 mA VDD = 4.3 V P_9.4.14 L-Input Pull-Down Current at Pin H-Input Pull-Down Current at Pin Output Characteristics (SO) 0.5 V ISO(OFF) -1 – 1 μA VCS =VDD VSO = 0 V VSO = VDD P_9.4.15 Enable lead time (falling CS to rising SCLK) tCS(lead) 200 – – ns –1) P_9.4.16 Enable lag time (falling SCLK to rising CS) tCS(lag) 200 – – ns –1) P_9.4.17 Transfer delay time (rising CS to falling CS) tCS(td) 1 – – μs –1) P_9.4.18 Output tristate leakage current Timings Data Sheet 55 Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) Table 12 Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition – 1 μs 1) Number Output enable time (falling CS to SO valid) tSO(en) – Output disable time (rising CS to SO tristate) tSO(dis) – Serial clock frequency fSCLK 0 – 3 MHz –1) P_9.4.22 Serial clock period tSCLK(P) 333 – – ns –1) P_9.4.24 ns – 1) P_9.4.26 – 1) P_9.4.28 1) P_9.4.30 Serial clock “high” time Serial clock “low” time tSCLK(H) tSCLK(L) P_9.4.19 CL = 50 pF – 1 μs 1) P_9.4.20 CL = 50 pF 150 150 – – – – ns Data setup time (required time SI to tSI(su) falling SCLK) 65 – – ns – Data hold time (falling SCLK to SI) tSI(h) 65 – – ns –1) P_9.4.32 ns 1) P_9.4.34 Output data valid time with capacitive load tSO(v) – – 166 CL = 50 pF 1) Not subject to production test, specified by design Data Sheet 56 Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) 9.5 SPI Protocol The relationship between SI and SO content during SPI communication is shown in Figure 30. SI line represents the frame sent from the µC and SO line is the answer provided by BTS54040-LBA. The “(previous response)” means that the frame sent back depends on the command frame sent from the µC before. SI frame A frame B frame C SO (previous response ) response to frame A response to frame B SPI_SI2SO.emf Figure 30 Relationship between SI and SO during SPI communication The SPI protocol provides the answer to a command frame only with the next transmission triggered by the µC. Although the biggest majority of commands and frames implemented in BTS54040-LBA can be decoded without the knowledge of what happened before, it is advisable to consider what the µC sent in the previous transmission to decode BTS54040-LBA response frame completely. More in detail, the sequence of commands to “read” and “write” the content of a register will look as follows: SI write register A read register A (new command ) SO (previous response ) Standard diagnostic register A content SPI_RWseq.emf Figure 31 Register content sent back to µC There are 3 special situations where the frame sent back to the µC doesn't depend on the previous received frame: • in case an error in transmission happened during the previous frame (for instance, the clock pulses were not multiple of 8), shown in Figure 32 • when BTS54040-LBA logic supply comes out of Power-On reset condition, as shown in Figure 33 • when VS < VSMON and DCR.MUX ≠ 111B, as shown in Figure 34 SI frame A (error in transmission ) SO (previous response ) (new command) Standard diagnostic + TER SPI_SO_TER.emf Figure 32 Data Sheet BTS54040-LBA response after an error in transmission 57 Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) VDD VDD(PO) SI frame A SO frame B frame C Standard Diagnosis + TER (SO = „Z“) response to frame B SPI _SO_POR.emf Figure 33 BTS54040-LBA response after coming out of Power-On reset at VDD VS VSMON,max V SMON,min t VSMON 0 x 1 x 0 t SI frame A frame B frame C frame D SO (response ) Std. Diag. + TER + VSMON Std. Diag. + TER + VSMON (response to frame C) SPI_SO_VSMON.emf Figure 34 BTS54040-LBA response in case of a negative battery voltage transient A summary of all possible SPI commands is presented in Table 13, including the answer that BTS54040-LBA will send back at the next transmission. Data Sheet 58 Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) Table 13 SPI Command Summary Requested Operation Frame sent to SPOC+ (SI pin) Frame received from SPOC+ (SO pin) with the next command Write OUT register 100xaaaaB where: “xaaaaB” = new OUT register content (“xxB” = don't care) 0aaaaaaaB (Standard Diagnosis) Read OUT register 00xx0000B (“xxB” = don't care) 10aaaaaaB (“aaaaaaB” = OUT register content) Write Configuration register 11aabbbbB where: “aaB” = register address “bbbbB” = new register content 0aaaaaaaB (Standard Diagnosis) Read Configuration register 01aa0000B where: “aaB” = register address 11aabbbbB where: “aaB” = register address “bbbbB” = register content Read Standard Diagnosis 0xxx0001B (“xxxB” = don't care) 0aaaaaaaB (Standard Diagnosis) Read Errors Diagnosis 0xxx0011B (“xxxB” = don't care) 00aaaaaaB (Error Diagnosis) Read Warnings Diagnosis 0xxx0101B (“xxxB” = don't care) 00aaaaaaB (Warning Diagnosis) Data Sheet 59 Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) 9.6 SPI Diagnosis Registers 9.6.1 Standard Diagnosis SO 7 0 6 TER 5 LHI 4 STB 3 VSMON 2 1 ERR_MUX 0 Default 50H Field Bits Type Description TER 6 r Transmission Error 0B Previous transmission was successful (modulo 8 clocks received) 1B (default) Previous transmission failed or first transmission after reset LHI 5 r Limp Home monitor 0B (default) Normal mode operation 1B Limp Home Mode STB 4 r Standby mode monitor 0B Normal mode operation 1B (default) Stand-by mode VSMON 3 r VS monitor 0B 1B ERR_MUX Data Sheet 2:0 r (default) VS always > VSMON since last Standard Diagnosis readout VS < VSMON at least once Diagnosis of Channel n in error 000B (default) No channel latched OFF 001B Channel one latched OFF 010B Channel two latched OFF 011B Channel three latched OFF 100B Channel four latched OFF 101B Not used 110B Not used 111B More than one channel latched OFF 60 Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) 9.6.2 Errors Diagnosis SO 7 0 6 0 5 0 4 1 3 2 1 Default 10H ERR_COUNTERn Field Bits Type Description ERR_COUNTERn n = 4 to 1 3:0 r Diagnosis of Channel n 0B (default) No failure 1B Over temperature counter reached to nretry 9.6.3 0 Warnings Diagnosis SO 7 0 6 0 5 1 4 0 3 2 ERRn Field Bits Type Description ERRn n = 4 to 1 3:0 r Warning Diagnosis of Channel n 0B (default) No failure 1B Over temperature counter > 0 Data Sheet 61 1 0 Default 20H Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) 9.7 SPI Configuration Registers The following table provides an overview on the registers available and the available addressing space. Table 14 Register Overview Register name Register Bank Address SWCR.SWR bit Content OUT 0 (na) 0 Output configuration OUT 0 (na) 1 Input status SWCR 1 00 (na) Swap configuration LGCR 1 01 0 LED mode configuration LGCR 1 01 1 Gate Back Regulation configuration HWCR 1 10 (na) Hardware configuration DCR 1 11 (na) Diagnostic configuration 9.7.1 Output Configuration Register SWCR.SWR = 0 Bit 7 6 5 4 3 2 1 0 Name W=1 R=0 RB 5 4 3 2 1 0 OUT W/R 9.7.2 0 0 x Default 80H OUT.OUTn Input Status Register SWCR.SWR = 1 Bit 7 6 5 4 3 2 1 0 Name W=1 R=0 RB 5 4 3 2 1 0 OUT R 9.7.3 0 1 LHI Default 90H OUT.INSTn Swap Configuration Register Bit 7 6 Name W=1 R=0 RB SWCR W/R Data Sheet 1 5 4 3 2 1 0 ADDR 3 2 1 0 00 SWCR.SWR 1 0 62 0 Default C4H Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) 9.7.4 LED Mode Configuration Register SWCR.SWR = 0 Name W=1 R=0 LGCR W/R 9.7.5 RB 1 ADDR 01 3 2 1 0 Default D0H LGCR.LEDn Gate Back Regulation Register SWCR.SWR = 1 Name W=1 R=0 LGCR W/R 9.7.6 RB 1 ADDR 01 3 2 1 0 Default DFH LGCR.GBRn Hardware Configuration Register Name W=1 R=0 HWCR R 1 10 HWCR.RCR HWCR.COL HWCR.STB 0 E2H W 1 10 HWCR.RCR HWCR.COL HWCR.RST HWCR.CTC - Data Sheet RB ADDR 3 2 63 1 0 Default Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) 9.7.7 Diagnosis Control Register Name W=1 R=0 DCR R 1 11 DCR.SBM DCR.MUX F7H W 1 11 0 DCR.MUX - 9.7.8 RB ADDR 3 2 1 0 Default Configuration Register Bit Overview Field Bits Type Description RB 6 rw Register Bank 0B (default) Read / write to OUT register 1B Read / write to other registers OUT.OUTn n = 4 to 1 3:0 rw Output Control Register of Channel n 0B (default) channel is OFF 1B Channel is ON OUT.INSTn n = 4 to 1 3:0 r Input Status Monitor Channel n 0B (default) Input signal is “low” 1B Input signal is “high” LGCR.LEDn n = 4 to 1 3:0 rw Set LED Mode for Channel n 0B (default) Channel n is in bulb mode 1B Channel n is in LED mode LGCR.GBRn n = 4 to 1 3:0 rw Gate Back Regulation for Channel n 0B Gate back regulation for Channel n is forced OFF (default) Gate back regulation for Channel n is active 1B HWCR.CTC 0 w Clear Thermal Counter 0B (default) Thermal latches are untouched 1B Command: Clear all thermal latches HWCR.RST 1 w Reset Command 0B (default) Normal operation 1B Execute reset command HWCR.STB 1 r Standby Mode 0B Device is awake 1B (default) Device is in Standby mode HWCR.COL 2 rw Input Combinatorial Logic Configuration 0B (default) Input signal OR-combined with according OUT register bit1) 1B Input signal AND-combined with according OUT register bit HWCR.RCR 3 rw Retry Counter Reset 0B (default) Retry Counter is reset only for HWCR.CTC=1 (and VDD reset) 1B Retry Counter is reset for every IN-pin or OUT.OUTn “high” to “low” transition for nretry < nretry,max and also for HWCR.CTC=1 (and VDD reset) Data Sheet 64 Rev. 2.2, 2016-10-10 BTS54040-LBA Serial Peripheral Interface (SPI) Field Bits Type Description SWCR.SWR 1 rw Switch Register 0B (default) OUT.OUTn and LGCR.LEDn can be written and read 1B OUT.INSTn can be read and LGCR.GBRn can be written and read DCR.SBM 3 r Switch Bypass Monitor2) 0B VDS < VDS(SB) 1B VDS > VDS(SB) DCR.MUX 2:0 rw Set Current Sense Multiplexer Configuration in OFF-state 000B IS pin is high impedance 001B IS pin is high impedance 010B IS pin is high impedance 011B IS pin is high impedance 100B IS pin is high impedance 101B IS pin is high impedance 110B IS pin is high impedance 111B Stand-by mode (IS pin is high impedance) Set Multiplexer Configuration in ON-state 000B Current sense of channel 1 is routed to IS pin 001B Current sense of channel 2 is routed to IS pin 010B Current sense of channel 3 is routed to IS pin 011B Current sense of channel 4 is routed to IS pin 100B IS pin is high impedance 101B IS pin is high impedance 110B IS pin is high impedance 111B Stand-by mode (IS pin is high impedance)) 1) In Limp Home Mode (LHI pin set to “high”) the combinatorial logic is switched to OR-mode. 2) The switch bypass monitor compares the threshold VDS(SB) with the voltage VDS across the power transistor of that channel which is selected by the current sense multiplexer (DCR.MUX). Data Sheet 65 Rev. 2.2, 2016-10-10 BTS54040-LBA Application Description 10 Application Description The following figure describes a typical operating circuit. It shall not be considered as a warranty of a certain functionality, condition or quality of the device. The Table 15 shows suggested component values and purposes. Vbat 5V RVDD CVS1 CVDD WD-OUT VDD VS VCC GPIO RIN IN1 RIN IN2 RIN IN3 RIN IN4 Z2 AD SPI 27 W OUT4 27 W GND COUT CADC VDD µC e.g. XC2267 27 W OUT3 RSENSE RADC CVS2 27 W OUT2 IS R1 Z1 OUT1 RCS RSCLK CS SPI SCLK RSO SO RSI SI LHI RLHI WD-OUT GND VSS RGN D RREC CGND DGND Application _040noED.emf Figure 35 Data Sheet Application Circuit Example 66 Rev. 2.2, 2016-10-10 BTS54040-LBA Application Description Table 15 Suggested Component Values Reference Value Purpose RVDD 500 Ω Device logic protection (Size 1206 recommended) RIN 8 kΩ Protection of the µC during overvoltage, reverse polarity and loss of ground R1 4.7 kΩ Protection resistor for overvoltage, reverse polarity and loss of ground. Value to be tuned with µC specification RIS 2.7 kΩ Sense resistor RADC 1 kΩ µC-ADC voltage spikes filtering RCS 3.9 kΩ Protection of the µC during overvoltage and reverse polarity RSCLK 3.9 kΩ Protection of the µC during overvoltage and reverse polarity RSO 3.9 kΩ Protection of the µC during overvoltage and reverse polarity RSI 3.9 kΩ Protection of the µC during overvoltage and reverse polarity RLHI 8 kΩ Protection of the µC during overvoltage and reverse polarity CADC 1 nF µC-ADC voltage spikes filtering CVDD 100 nF Logic supply voltage spikes filtering CVS1 68 nF Battery voltage spikes filtering CVS2 100 nF Battery voltage spikes filtering COUT 10 nF For improved electromagnetic compatibility (EMC) CGND 8.2 nF Ground voltage spikes filtering (optional for improved robustness against battery voltage transients) RGND 100 Ω Ground voltage spikes filtering (optional for improved robustness against battery voltage transients) RREC 1 kΩ Ground voltage recycling path (optional for providing a recycle path in case of loss of Battery) Z1 7V Protection of µC during overvoltage. Zener diode Z2 P6SMB30 Protection of device during overvoltage. Zener diode DGND BAS70 Protection of device during reverse polarity. Schottky diode Data Sheet 67 Rev. 2.2, 2016-10-10 BTS54040-LBA Package Outlines BTS54040-LBA 11 Package Outlines BTS54040-LBA Figure 36 TSON-24-8 Package drawing Data Sheet 68 Rev. 2.2, 2016-10-10 BTS54040-LBA Package Outlines BTS54040-LBA Figure 37 TSON-24 Package pads and stencil Green Product (RoHS Compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Note: You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 69 Rev. 2.2, 2016-10-10 Edition 2016-10-10 Published by Infineon Technologies AG 81726 Munich, Germany © 2016 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Legal Disclaimer for short-circuit capability Infineon disclaims any warranties and liabilities, whether expressed nor implied, for any short-circuit failures below the threshold limit. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.