PROFET® BTS 640 S2
Smart Sense High-Side Power Switch
Features
• Short circuit protection
• Current limitation
• Proportional load current sense
• CMOS compatible input
• Open drain diagnostic output
• Fast demagnetization of inductive loads
• Undervoltage and overvoltage shutdown with
auto-restart and hysteresis
• Overload protection
• Thermal shutdown
• Overvoltage protection including load dump (with
external GND-resistor)
• Reverse battery protection (with external GNDresistor)
• Loss of ground and loss of Vbb protection
• Electrostatic discharge (ESD) protection
Product Summary
Operating voltage
On-state resistance
Load current (ISO)
Current limitation
Vbb(on)
RON
IL(ISO)
IL(SCr)
5.0 ... 34
V
30 mΩ
12.6
A
24
A
Package
TO220-7-11
1
Standard (staggered)
TO263-7-2
TO220-7-12
1
SMD
1
Straight
Application
• µC compatible power switch with diagnostic feedback for 12 V and 24 V DC grounded loads
• All types of resistive, inductive and capacitve loads
• Replaces electromechanical relays, fuses and discrete circuits
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, proportional sense of load current, monolithically integrated in Smart SIPMOS technology. Fully
protected by embedded protection functions.
Block Diagram
4
+ V bb
Voltage
Overvoltage
Current
Gate
source
protection
limit
protection
V Logic
3
1
OUT
Voltage
Charge pump
sensor
Level shifter
Rectifier
IN
ST
Limit for
unclamped
ind. loads
ESD
Output
Voltage
detection
Logic
IL
Current
Sense
Load
R
Temperature
sensor
5
O
GND
IS
I IS
R
6, 7
GND
IS
PROFET
Load GND
2
Signal GND
Semiconductor Group
Page 1 of 14
1999-Jul-20
BTS 640 S2
Pin
Symbol
1
ST
Function
Diagnostic feedback: open drain, invers to input level
2
GND
Logic ground
3
IN
Input, activates the power switch in case of logical high signal
4
Vbb
5
IS
Positive power supply voltage, the tab is shorted to this pin
Sense current output, proportional to the load current, zero in
the case of current limitation of load current
6&7
OUT
(Load, L)
Output, protected high-side power output to the load.
Both output pins have to be connected in parallel for operation
according this spec (e.g. kILIS).
Design the wiring for the max. short circuit current
Maximum Ratings at Tj = 25 °C unless otherwise specified
Parameter
Supply voltage (overvoltage protection see page 4)
Supply voltage for full short circuit protection
Symbol
Vbb
Vbb
Values
43
34
Unit
V
V
60
V
self-limited
-40 ...+150
-55 ...+150
85
A
°C
0,41
3,5
1.0
4.0
8.0
J
Tj Start=-40 ...+150°C
Load dump protection1) VLoadDump = VA + Vs, VA = 13.5V
VLoad dump3)
Load current (Short circuit current, see page 5)
Operating temperature range
Storage temperature range
Power dissipation (DC), TC ≤ 25 °C
Inductive load switch-off energy dissipation, single pulse
IL
Tj
Tstg
Ptot
RI2)= 2 Ω, RL= 1 Ω, td= 200 ms, IN= low or high
Vbb = 12V, Tj,start = 150°C, TC = 150°C const.
IL = 12.6 A, ZL = 4,2 mH, 0 Ω: EAS
IL = 4 A, ZL = 330 mH, 0 Ω: EAS
Electrostatic discharge capability (ESD)
IN: VESD
(Human Body Model)
ST, IS:
out to all other pins shorted:
W
kV
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
R=1.5kΩ; C=100pF
VIN
IIN
IST
IIS
Input voltage (DC)
Current through input pin (DC)
Current through status pin (DC)
Current through current sense pin (DC)
-10 ... +16
±2.0
±5.0
±14
V
mA
see internal circuit diagrams page 7
1)
2)
3)
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150 Ω
resistor in the GND connection is recommended).
RI = internal resistance of the load dump test pulse generator
VLoad dump is setup without the DUT connected to the generator according to ISO 7637-1 and DIN 40839
Semiconductor Group
Page 2
1999-Jul-20
BTS 640 S2
Thermal Characteristics
Parameter and Conditions
Thermal resistance
Symbol
chip - case: RthJC
junction - ambient (free air): RthJA
SMD version, device on PCB4):
min
----
Values
typ
max
-- 1.47
-75
33
--
Unit
K/W
Electrical Characteristics
Parameter and Conditions
Symbol
at Tj = 25 °C, Vbb = 12 V unless otherwise specified
Values
min
typ
max
Unit
Load Switching Capabilities and Characteristics
On-state resistance (pin 4 to 6&7)
Tj=25 °C: RON
Tj=150 °C:
--
27
54
30
60
mΩ
--
50
--
mV
11.4
12.6
--
A
IL(NOM)
IL(GNDhigh)
4.0
--
4.5
--
-8
A
mA
ton
toff
25
25
70
80
150
200
µs
Slew rate on
dV /dton
0.1
--
1
V/µs
Slew rate off
-dV/dtoff
0.1
--
1
V/µs
IL = 5 A
Output voltage drop limitation at small load
currents (pin 4 to 6&7), see page 13
IL = 0.5 A
VON(NL)
Tj =-40...+150°C:
Nominal load current, ISO Norm (pin 4 to 6&7)
IL(ISO)
VON = 0.5 V, TC = 85 °C
Nominal load current, device on PCB4)
TA = 85 °C, Tj ≤ 150 °C VON ≤ 0.5 V,
Output current (pin 6&7) while GND disconnected
or GND pulled up, Vbb=30 V, VIN= 0, see diagram page
9; not tested, specified by design
Turn-on time
Turn-off time
RL = 12 Ω, Tj =-40...+150°C
IN
IN
to 90% VOUT:
to 10% VOUT:
10 to 30% VOUT, RL = 12 Ω, Tj =-40...+150°C
70 to 40% VOUT, RL = 12 Ω, Tj =-40...+150°C
4)
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air.
Semiconductor Group
Page 3
1999-Jul-20
BTS 640 S2
Parameter and Conditions
at Tj = 25 °C, Vbb = 12 V unless otherwise specified
Symbol
Values
min
typ
max
Operating Parameters
Operating voltage 5)
Undervoltage shutdown
Undervoltage restart
5.0
3.2
--
--4.5
34
5.0
5.5
6.0
V
V
V
----
4.7
-0.5
6.5
7.0
--
V
34
33
-41
43
--1
-47
43
---52
V
V
V
V
----
4
12
--
15
25
10
µA
--
1.2
3
mA
Vbb(on)
Tj =-40...+150°C: Vbb(under)
Tj =-40...+25°C: Vbb(u rst)
Tj =+150°C:
Undervoltage restart of charge pump
see diagram page 12
Tj =-40...+25°C: Vbb(ucp)
Tj =25...150°C:
Undervoltage hysteresis
∆Vbb(under)
Tj =-40...+150°C:
∆Vbb(under) = Vbb(u rst) - Vbb(under)
Overvoltage shutdown
Overvoltage restart
Overvoltage hysteresis
Overvoltage protection6)
Ibb=40 mA
Vbb(over)
Tj =-40...+150°C: Vbb(o rst)
Tj =-40...+150°C: ∆Vbb(over)
Tj =-40°C: Vbb(AZ)
Tj =+25...+150°C
Tj =-40...+150°C:
Standby current (pin 4)
Tj=-40...+25°C: Ibb(off)
Tj= 150°C:
IL(off)
Off state output current (included in Ibb(off))
VIN=0
VIN=0,
6)
7)
V
µA
Tj =-40...+150°C:
Operating current (Pin 2)7), VIN=5 V
5)
Unit
IGND
At supply voltage increase up to Vbb= 4.7 V typ without charge pump, VOUT ≈Vbb - 2 V
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150 Ω
resistor in the GND connection is recommended). See also VON(CL) in table of protection functions and
circuit diagram page 8.
Add IST, if IST > 0, add IIN, if VIN>5.5 V
Semiconductor Group
Page 4
1999-Jul-20
BTS 640 S2
Parameter and Conditions
Symbol
at Tj = 25 °C, Vbb = 12 V unless otherwise specified
Protection Functions
Initial peak short circuit current limit (pin 4 to 6&7)
IL(SCp)
Tj =-40°C:
Tj =25°C:
Tj =+150°C:
Repetitive short circuit shutdown current limit
IL(SCr)
Tj = Tjt (see timing diagrams, page 11)
Output clamp (inductive load switch off)
at VOUT = Vbb - VON(CL); IL= 40 mA,
Tj =-40°C:
Tj =+25..+150°C:
Thermal overload trip temperature
Thermal hysteresis
Reverse battery (pin 4 to 2) 8)
Reverse battery voltage drop (Vout > Vbb)
IL = -5 A
Tj=150 °C:
VON(CL)
Tjt
∆Tjt
-Vbb
-VON(rev)
Values
min
typ
max
Unit
48
40
31
56
50
37
65
58
45
A
--
24
--
A
41
43
150
---
-47
-10
--
-52
--32
V
°C
K
V
--
600
--
mV
4550
3300
5000
5000
6000
8000
4550
4000
5000
5000
5550
6500
5.4
6.1
6.9
V
0
0
0
----
1
15
10
µA
--
--
300
µs
Diagnostic Characteristics
Current sense ratio9), static on-condition,
VIS = 0...5 V, Vbb(on) = 6.510)...27V,
kILIS = IL / IIS
Tj = -40°C, IL = 5 A:
kILIS
Tj= -40°C, IL= 0.5 A:
Tj= 25...+150°C, IL= 5 A:
,
Tj= 25...+150°C, IL = 0.5 A:
Current sense output voltage limitation
Tj = -40 ...+150°C
IIS = 0, IL = 5 A:
VIS(lim)
Current sense leakage/offset current
Tj = -40 ...+150°C
VIN=0, VIS = 0, IL = 0: IIS(LL)
VIN=5 V, VIS = 0, IL = 0: IIS(LH)
VIN=5 V, VIS = 0, VOUT = 0 (short circuit) IIS(SH)
:
(IIS(SH) not tested, specified by design)
Current sense settling time to IIS static±10% after
positive input slope, IL = 0
5 A,
tson(IS)
Tj= -40...+150°C (not tested, specified by design)
8)
Requires 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal
operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature
protection is not active during reverse current operation! Input and Status currents have to be limited (see
max. ratings page 2 and circuit page 8).
9) This range for the current sense ratio refers to all devices. The accuracy of the k can be raised at least by
ILIS
a factor of two by matching the value of kILIS for every single device.
In the case of current limitation the sense current IIS is zero and the diagnostic feedback potential VST is
High. See figure 2b, page 10.
10) Valid if V
bb(u rst) was exceeded before.
Semiconductor Group
Page 5
1999-Jul-20
BTS 640 S2
Parameter and Conditions
Symbol
at Tj = 25 °C, Vbb = 12 V unless otherwise specified
Current sense settling time to 10% of IIS static after
negative input slope, IL = 5
0A,
tsoff(IS)
Values
min
typ
max
Unit
--
30
100
µs
--
10
--
µs
VOUT(OL)
2
3
4
V
RO
5
15
40
kΩ
3,0
4,5
7,0
kΩ
-1.5
--
--0.5
3.5
---
V
V
V
1
--
50
µA
20
50
90
µA
td(ST OL3)
--
400
--
µs
tdon(ST)
--
13
--
µs
tdoff(ST)
--
1
--
µs
5.4
----
6.1
----
6.9
0.4
0.7
2
V
Tj= -40...+150°C (not tested, specified by design)
Current sense rise time (60% to 90%) after change
of load current IL = 2.5
5 A (not tested, specified tslc(IS)
by design)
Open load detection voltage11) (off-condition)
Tj=-40..150°C:
Internal output pull down
(pin 6 to 2), VOUT=5 V, Tj=-40..150°C
Input and Status Feedback12)
Input resistance
RI
see circuit page 7
Input turn-on threshold voltage
Tj =-40..+150°C: VIN(T+)
Input turn-off threshold voltage
Tj =-40..+150°C: VIN(T-)
Input threshold hysteresis
∆ VIN(T)
Off state input current (pin 3), VIN = 0.4 V
Tj =-40..+150°C IIN(off)
On state input current (pin 3), VIN = 5 V
Tj =-40..+150°C
IIN(on)
Delay time for status with open load
after Input neg. slope (see diagram page 12)
Status delay after positive input slope (not tested,
specified by design)
Tj=-40 ... +150°C:
Status delay after negative input slope (not tested,
specified by design)
Tj=-40 ... +150°C:
Status output (open drain)
Zener limit voltage Tj =-40...+150°C, IST = +1.6 mA: VST(high)
ST low voltage
Tj =-40...+25°C, IST = +1.6 mA: VST(low)
Tj = +150°C, IST = +1.6 mA:
Status leakage current, VST = 5 V,
Tj=25 ... +150°C: IST(high)
11)
12)
µA
External pull up resistor required for open load detection in off state.
If a ground resistor RGND is used, add the voltage drop across this resistor.
Semiconductor Group
Page 6
1999-Jul-20
BTS 640 S2
Truth Table
Input
Output
Status
Current
Sense
level
level
level
IIS
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
L
H
L
L13)
L
L
H
H
H
L
H
H
H
H
H
H
L14)
L
H (L17))
L
H
L
H
L
H
0
nominal
0
0
0
0
0
0
0
typ.3V. Under this condition the sense current IIS is
zero
An external short of output to Vbb, in the off state, causes an internal current from output to ground. If RGND
is used, an offset voltage at the GND and ST pins will occur and the VST low signal may be errorious.
Low ohmic short to Vbb may reduce the output current IL and therefore also the sense current IIS.
Power Transistor off, high impedance
with external resistor between pin 4 and pin 6&7
Semiconductor Group
Page 7
1999-Jul-20
BTS 640 S2
Status output
Overvoltage protection of logic part
+5V
+ 5V
+ V bb
R ST(ON)
R ST
ST
V
RI
IN
Z2
ST
ESDZD
GND
Logic
IS
RV
ESD-Zener diode: 6.1 V typ., max 5 mA;
RST(ON) < 440 Ω at 1.6 mA, The use of ESD zener
V
R IS
Z1
GND
diodes as voltage clamp at DC conditions is not
recommended.
R GND
Signal GND
VZ1 = 6.1 V typ., VZ2 = 47 V typ., RI= 4 kΩ typ,
RGND= 150 Ω, RST= 15 kΩ, RIS= 1 kΩ, RV= 15 kΩ,
Current sense output
V
IS
IS
Reverse battery protection
+ 5V
I
IS
- Vbb
R
ESD-ZD
R ST
IS
GND
RI
IN
Logic
ST
VZ1
IS
ESD-Zener diode: 6.1 V typ., max 14 mA;
RIS = 1 kΩ nominal
OUT
Power
Inverse
Diode
RV
R IS
Inductive and overvoltage output clamp
GND
+ V bb
V
Z
OUT
GND
Power GND
Signal GND
VON
RL
RGND
The load RL is inverse on, temperature protection is not
active
RGND= 150 Ω, RI= 4 kΩ typ, RST≥ 500 Ω, RIS≥ 200 Ω,
RV≥ 500 Ω,
PROFET
Open-load detection
VON clamped to 47 V typ.
OFF-state diagnostic condition: VOUT > 3 V typ.; IN low
V
R
bb
EXT
OFF
Out
ST
V
OUT
Logic
R
O
Signal GND
Semiconductor Group
Page 8
1999-Jul-20
BTS 640 S2
GND disconnect
V
bb
Vbb disconnect with charged external
inductive load
4
3
Ibb
4
Vbb
IN
6
OUT
1
5
ST
3
Vbb
IN
OUT
PROFET
1
7
OUT
IS
high
5
GND
ST
D
7
GND
2
V V V
IN ST IS
PROFET
OUT
IS
6
2
V
GND
R
L
Any kind of load. In case of Input=high is VOUT ≈ VIN - VIN(T+) .
Due to VGND >0, no VST = low signal available.
If other external inductive loads L are connected to the PROFET,
additional elements like D are necessary.
GND disconnect with GND pull up
Inductive Load switch-off energy
dissipation
4
3
E bb
IN
Vbb
ST
PROFET
OUT
1
5
OUT
IS
6
E AS
4
7
3
GND
V
bb
IN
ELoad
Vbb
OUT
2
V V V
IN ST IS
L
V
bb
1
=
V
GND
5
ST
PROFET
OUT
6
7
EL
IS
GND
Vbb
2
Any kind of load. If VGND > VIN - VIN(T+) device stays off
Due to VGND >0, no VST = low signal available.
ER
Vbb disconnect with energized inductive
load
Energy stored in load inductance:
2
EL = 1/2·L·I L
4
high
3
IN
Vbb
OUT
1
5
ST
PROFET
OUT
IS
While demagnetizing load inductance, the energy
dissipated in PROFET is
6
EAS= Ebb + EL - ER= ∫ VON(CL)·iL(t) dt,
7
with an approximate solution for RL > 0 Ω:
GND
2
EAS=
IL· L
IL·RL
·(V + |VOUT(CL)|)· ln (1+
)
|VOUT(CL)|
2·RL bb
V
bb
Normal load current can be handled by the PROFET
itself.
Semiconductor Group
Page 9
1999-Jul-20
BTS 640 S2
Timing diagrams
Figure 2a: Switching a lamp
Figure 1a: Switching a resistive load,
change of load current in on-condition:
IN
IN
ST
ST
t don(ST)
t doff(ST)
V
VOUT
t on
IL
OUT
t off
t slc(IS)
Load 1
IL
t slc(IS)
Load 2
I IS
IIS
t
tson(IS)
t
t soff(IS)
The sense signal is not valid during settling time after turn or
change of load current.
Figure 2b: Switching a lamp with current limit:
IN
Figure 1b: Vbb turn on:
IN
ST
Vbb
VOUT
I
IL
L
IIS
I IS
t
ST
t
proper turn on under all conditions
Semiconductor Group
Page 10
1999-Jul-20
BTS 640 S2
Figure 2c: Switching an inductive load:
Figure 4a: Overtemperature:
Reset if Tj
