BTS70012-1ESP
PROFET™ +2 12V
1x 1.4 mΩ
Smart High-Side Power Switch
1
Package
PG-TSDSO-24
Marking
BTS70012-1ESP
Overview
Potential Applications
•
Suitable for driving 31.3 A resistive, inductive and capacitive loads
•
Replaces electromechanical relays, fuses and discrete circuits
•
Suitable for driving glow plug, heating loads, DC motor and for power
distribution
VBAT
ZWIRE
Optional
Optional
CVS
Logic Supply
CVSGND
GPIO
RDEN
DEN
PROFET™ +2
12V
Microcontroller
ADC
OUT
RADC
RIS_PROT
RPD
RIN
COUT0
ZWIRE
CVS2
GPIO
ROL
GND VS
IN
VDD
DZ2
T1
RGND
IS
DZ1
ZLOAD*
CSENSE
RSENSE
VSS
Logic GND
Power GND
Optional
Chassis GND
*See Chapter 1 „Potential Applications“
App_1CH_INTD IO_CVG.emf
Figure 1
Data Sheet
BTS70012-1ESP Application Diagram. Further information in Chapter 10
www.infineon.com
1
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Overview
Basic Features
•
High-Side Switch with Diagnosis and Embedded Protection
•
Part of PROFET™ +2 12V Family
•
Capacitive Load Switching mode
•
ReverseON for low power dissipation in Reverse Polarity
•
Switch ON capability while Inverse Current condition (InverseON)
•
Green Product (RoHS compliant)
Protection Features
•
Absolute and dynamic temperature limitation with controlled reactivation
•
Overcurrent protection (tripping) with Intelligent Latch
•
Undervoltage shutdown
•
Overvoltage protection with external components (as shown in Figure 39)
Diagnostic Features
•
Proportional load current sense
•
Open Load in ON and OFF state
•
Short circuit to ground and battery
Product Validation
Qualified for automotive applications. Product validation according to AEC-Q100 Grade 1.
Description
The BTS70012-1ESP is a Smart High-Side Power Switch, providing protection functions and diagnosis.
Table 1
Product Summary
Parameter
Symbol
Values
Minimum Operating voltage
VS(OP)
4.1 V
Minimum Operating voltage (cranking)
VS(UV)
3.1 V
Maximum Operating voltage
VS
28 V
Minimum Overvoltage protection (TJ ≥ 25 °C)
VDS(CLAMP)_25
35 V
Maximum current in OFF mode (TJ ≤ 85 °C)
IVS(OFF)_85
2.2 µA
Maximum operative current
IGND(ON_D)
3.3 mA
Typical ON-state resistance (TJ = 25 °C)
RDS(ON)_25
1.4 mΩ
Maximum ON-state resistance (TJ = 150 °C)
RDS(ON)_150
2.47 mΩ
Nominal load current (TA = 85 °C)
IL(NOM)
31.3 A
Minimum overload detection current
IL(OVL0)_-40
187 A
Typical current sense ratio at IL = IL(NOM)
kILIS
34100
Data Sheet
2
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Block Diagram and Terms
2
Block Diagram and Terms
2.1
Block Diagram
VS
Supply Voltage
Monitoring
Overvoltage
Protection
Internal Power Supply
Channel
Voltage Sensor
Intelligent Restart
Control
IS
Overtemperature
SENSE Output
Driver
Logic
IN
DEN
Gate Control
+
Chargepump
Overvoltage
Clamping
T
Overcurrent
Protection
ReverseON
InverseON
ESD
Protection
+
Input Logic
OUT
Load Current Sense
Output Voltage Limitation
Internal Reverse
Polarity Protection
GND Circuitry
GND
Figure 2
Data Sheet
Block_HE AT1ch.emf
Block Diagram of BTS70012-1ESP
3
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BTS70012-1ESP
PROFET™ +2 12V
Block Diagram and Terms
2.2
Terms
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.
IVS
VSIS
IIN
VS
VDS
IN
IDEN
DEN
VS
OUT
VIN
VDEN
IIS
IS
IL
VOUT
GND
VIS
IGND
Terms_1CH.emf
Figure 3
Data Sheet
Voltage and Current Convention
4
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
n.c.
n.c.
n.c.
GND
IN
DEN
IS
n.c.
n.c.
n.c.
n.c.
n.c.
1
24
2
23
3
22
4
21
5
20
6
19
VS
7
18
8
17
9
16
10
15
11
14
12exposed pad (bottom)13
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Pinout_PROFET1ch_PDH_24.emf
Figure 4
Data Sheet
Pin Configuration
5
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Pin Configuration
3.2
Pin Definitions and Functions
Table 2
Pin Definition
Pin
Symbol
Function
EP
VS
(exposed pad)
Supply Voltage
Battery voltage
4
GND
Ground
Signal ground
5
IN
Input Channel
Digital signal to switch ON the channel (“high” active)
If not used: connect with a 10 kΩ resistor either to GND pin or to module
ground
6
DEN
Diagnostic Enable
Digital signal to enable device diagnosis (“high” active) and to clear the
protection latch of channel
If not used: connect with a 10 kΩ resistor either to GND pin or to module
ground
7
IS
SENSE current output
Analog/digital signal for diagnosis
If not used: left open
1-3, 8-12
n.c.
Not connected, internally not bonded
13-24
OUT
Output
Protected high-side power output channel1)
1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally connected
together. PCB traces have to be designed to withstand the maximum current which can flow.
Data Sheet
6
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings - General
Table 3
Absolute Maximum Ratings1)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Number
Test Condition
Supply pins
Power Supply Voltage
VS
-0.3
–
28
V
–
P_4.1.0.1
Load Dump Voltage
VBAT(LD)
–
–
35
V
suppressed
Load Dump
acc. to
ISO16750-2
(2010).
Ri = 2 Ω
P_4.1.0.3
Supply Voltage for Short Circuit VBAT(SC)
Protection
0
–
24
V
Setup acc. to
AEC-Q100-012
Rsupply = 10 mΩ
Lsupply = 5 µH
Rshort = 25 mΩ
Lshort = 5 µH
P_4.1.0.25
Reverse Polarity Voltage
-VBAT(REV)
–
–
16
V
t ≤ 2 min
TA = +25 °C
Setup as
described in
Chapter 10
P_4.1.0.5
Current through GND Pin
IGND
-50
–
50
mA
RGND according P_4.1.0.9
to Chapter 10
Logic & control pins (Digital Input = DI)
DI = IN, DEN
Current through DI Pin
IDI
-1
–
2
mA
2)
P_4.1.0.14
Current through DI Pin
Reverse Battery Condition
IDI(REV)
-1
–
10
mA
2)
P_4.1.0.36
Voltage at IS Pin
VIS
-1.5
–
VS
Current through IS Pin
IIS
-25
–
IIS(SAT),M mA
t ≤ 2 min
IS pin
V
IIS = 10 μA
P_4.1.0.16
–
P_4.1.0.18
AX
Data Sheet
7
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
General Product Characteristics
Table 3
Absolute Maximum Ratings1) (continued)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Number
Test Condition
Temperatures
Junction Temperature
TJ
-40
–
150
°C
–
P_4.1.0.19
Storage Temperature
TSTG
-55
–
150
°C
–
P_4.1.0.20
VESD(HBM)
-2
–
2
kV
HBM3)
P_4.1.0.21
ESD Susceptibility OUT vs GND VESD(HBM)_OU -4
and VS connected (HBM)
T
–
4
kV
HBM3)
P_4.1.0.22
ESD Susceptibility
ESD Susceptibility all Pins
(HBM)
ESD Susceptibility all Pins
(CDM)
VESD(CDM)
-500
–
500
V
CDM4)
P_4.1.0.23
ESD Susceptibility Corner Pins
(pins 1, 12, 13, 24)
VESD(CDM)_CR -750
–
750
V
CDM4)
P_4.1.0.24
1)
2)
3)
4)
N
Not subject to production test - specified by design.
Maximum VDI to be considered for Latch-Up tests: 5.5 V.
ESD susceptibility, Human Body Model “HBM”, according to AEC Q100-002.
ESD susceptibility, Charged Device Model “CDM”, according to AEC Q100-011.
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
8
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
General Product Characteristics
4.2
Absolute Maximum Ratings - Power Stages
4.2.1
Power Stages - 1.2 mΩ
Table 4
Absolute Maximum Ratings - 1.2 mΩ 1)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Maximum Energy Dissipation
Single Pulse
EAS
–
–
525
mJ
IL = 2*IL(NOM)
TJ(0) = 150 °C
VS = 28 V
P_4.2.21.1
Maximum Energy Dissipation
Repetitive Pulse
EAR
–
–
160
mJ
IL = IL(NOM)
TJ(0) = 85 °C
VS = 13.5 V
1M cycles
P_4.2.21.2
Load Current
|IL|
–
–
IL(OVL0), A
–
P_4.2.21.3
MAX
1) Not subject to production test - specified by design.
4.3
Functional Range
Table 5
Functional Range - Supply Voltage and Temperature1)
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
6
13.5
18
V
–
P_4.3.0.1
Lower Extended Supply
VS(EXT,LOW)
Voltage Range for Operation
3.1
–
6
V
2)3)
P_4.3.0.2
VS(EXT,CVG)
Supply Voltage Range
reached after Overload
Protection activation
leading to “Undervoltage on
VS” condition
–
Supply Voltage Range for
Normal Operation
Data Sheet
VS(NOR)
(parameter
deviations possible)
–
9
3.1
V
CVSGND is required
when the Overload
Protection is
triggered (see
Chapter 8.2) and
the observed
number of retries is
different from what
specified in
Chapter 8.3.1
P_4.3.0.7
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
General Product Characteristics
Table 5
Functional Range - Supply Voltage and Temperature1) (continued)
Parameter
Symbol
Values
Min.
Typ.
Max.
Upper Extended Supply
VS(EXT,UP)
Voltage Range for Operation
18
–
28
Junction Temperature
-40
Unit
Note or
Test Condition
Number
V
3)
P_4.3.0.3
(parameter
deviations possible)
TJ
–
150
°C
–
P_4.3.0.5
1) Not subject to production test - specified by design.
2) In case of VS voltage decreasing: VS(EXT,LOW),MIN = 3.1 V. In case of VS voltage increasing: VS(EXT,LOW),MIN = 4.1 V.
3) Protection functions still operative.
Note:
Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics
tables.
4.4
Thermal Resistance
Note:
This thermal data was generated in accordance with JEDEC JESD51 standards. For more
information, go to www.jedec.org.
Table 6
Thermal Resistance1)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Thermal Characterization
Parameter Junction-Top
ΨJTOP
–
0.7
1.3
K/W
2)
P_4.4.0.12
Thermal Resistance
Junction-to-Case
RthJC
–
0.4
0.7
K/W
2)
P_4.4.0.13
Thermal Resistance
Junction-to-Ambient
RthJA
–
simulated at
exposed pad
24.2
–
K/W
2)
P_4.4.0.14
1) Not subject to production test - specified by design.
2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package) was
simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable
a thermal via array under the exposed pad contacted the first inner copper layer. Simulation done at TA = 105°C,
PDISSIPATION = 1 W.
Data Sheet
10
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
General Product Characteristics
4.4.1
PCB Setup
1,5 mm
70 µm modeled (traces, cooling area)
70 µm, 5% metalization*
*: means percentual Cu metalization on each layer
PCB_Zth_1s0p.emf
Figure 5
1s0p PCB Cross Section
70 µm modeled (traces)
1,5 mm
35 µm, 90% metalization*
35 µm, 90% metalization*
70 µm, 5% metalization*
*: means percentual Cu metalization on each layer
PCB_Zth_2s2p.emf
Figure 6
2s2p PCB Cross Section
PCB 1s0p + 600 mm2 cooling
PCB 2s2p / 1s0p footprint
PCB_sim_setup_TSDSO24.emf
Figure 7
PCB setup for thermal simulations
PCB_2s2p_vias_TSDSO24.emf
Figure 8
Data Sheet
Thermal vias on PCB for 2s2p PCB setup
11
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
General Product Characteristics
4.4.2
Thermal Impedance
ZthJA - BTS70012-ESP
JEDEC 2s2p
100
JEDEC 1s0p - 600 mm²
JEDEC 1s0p - 300 mm²
JEDEC 1s0p - footprint
ZthJA [K/W]
TA = 105 °C
10
1
0.1
0.0001
0.001
Figure 9
0.01
0.1
Time [s]
1
10
100
1000
Typical Thermal Impedance. PCB setup according Chapter 4.4.1
RthJA - BTS70012-1ESP
80
JEDEC 1s0p
75
70
65
RthJA [K/W]
TA = 105 °C
60
55
50
45
40
35
30
0
Figure 10
Data Sheet
100
200
300
Cooling area [mm²]
400
500
600
Thermal Resistance on 1s0p PCB with various cooling surfaces
12
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BTS70012-1ESP
PROFET™ +2 12V
Logic Pins
5
Logic Pins
The device has 2 digital pins.
5.1
Input Pin (IN)
The input pin IN activates the output channel. The input circuitry is compatible with 3.3V and 5V
microcontroller (see Chapter 10 for the complete application setup overview). The electrical equivalent of the
input circuitry is shown in Figure 11. In case the pin is not used, it must be connected with a 10 kΩ resistor
either to GND pin or to module ground.
VS
IN
VS(CLAMP)
IDI
ESD
IDI
VDI(CLAMP)
VDI
GND
RGND
IGND
Input_IN_INTDIO.emf
Figure 11
Input circuitry
The logic thresholds for “low” and “high” states are defined by parameters VDI(TH) and VDI(HYS). The relationship
between these two values is shown in Figure 12. The voltage VIN needed to ensure a “high” state is always
higher than the voltage needed to ensure a “low” state.
V DI
V DI(TH ),M AX
V DI(TH)
V DI(HYS)
V DI(TH ),M IN
t
Internal channel
activation signal
0
x
1
x
0
t
Input_VDITH_2.emf
Figure 12
Data Sheet
Input Threshold voltages and hysteresis
13
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BTS70012-1ESP
PROFET™ +2 12V
Logic Pins
5.2
Diagnosis Pin
The Diagnosis Enable (DEN) pin controls the diagnosis circuitry and can be used to reset the latched protection
(Protection circuitry not disabled by DEN). When DEN pin is set to “high”, the diagnosis is enabled (see
Chapter 9.2 for more details). When it is set to “low”, the diagnosis is disabled (IS pin is set to high
impedance).
The transition from “high” to “low” of DEN pin clears the protection latch of the channel depending on the
logic state of IN pin and DEN pulse length (see Chapter 8.3 for more details). The internal structure of
diagnosis pins is the same as the one of input pins. See Figure 11 for more details.
5.3
Electrical Characteristics Logic Pins
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Digital Input (DI) pins = IN, DEN
Table 7
Electrical Characteristics: Logic Pins - General
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Digital Input Voltage
Threshold
VDI(TH)
0.8
1.3
2
V
See Figure 11 and P_5.4.0.1
Figure 12
Digital Input Clamping
Voltage
VDI(CLAMP1)
–
7
–
V
1)
Digital Input Clamping
Voltage
VDI(CLAMP2)
6.5
7.5
8.5
V
IDI = 2 mA
P_5.4.0.3
See Figure 11 and
Figure 12
Digital Input Hysteresis
VDI(HYS)
–
0.25
–
V
1)
IDI(H)
2
10
25
µA
VDI = 2 V
P_5.4.0.5
See Figure 11 and
Figure 12
Digital Input Current (“low”) IDI(L)
2
10
25
µA
VDI = 0.8 V
P_5.4.0.6
See Figure 11 and
Figure 12
Digital Input Current
(“high”)
P_5.4.0.2
IDI = 1 mA
See Figure 11 and
Figure 12
P_5.4.0.4
See Figure 11 and
Figure 12
1) Not subject to production test - specified by design.
Data Sheet
14
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Supply
6
Power Supply
The BTS70012-1ESP is supplied by VS, which is used for the internal logic as well as supply for the power output
stage. VS has an undervoltage detection circuit, which prevents the activation of the power output stage and
diagnosis in case the applied voltage is below the undervoltage threshold (VS < VS(OP)). During power up, the
internal power on signal is set when supply voltage (VS) exceeds the minimum operating voltage (VS > VS(OP)).
6.1
Operation Modes
BTS70012-1ESP has the following operation modes in case of VS > VS(OP):
•
OFF mode
•
ON mode
•
Diagnosis in ON mode
•
Diagnosis in OFF mode
•
Fault
•
CLS mode
The transition between operation modes is determined according to these variables:
•
Logic level at IN pin
•
PWM signal at IN pin
•
Logic level at DEN pin
•
Internal latch
•
VDS voltage level
The truth table in case of VS > VS(OP) is shown in Table 8. The behavior of BTS70012-1ESP as well as some
parameters may change in dependence on the operation mode of the device.
There are three parameters describing each operation mode of BTS70012-1ESP:
•
Status of the output channel
•
Status of the diagnosis
•
Current consumption at VS pin (measured by IVS in OFF mode, IGND in all other operative modes)
Table 8
Operation Mode truth table
IN
DEN
Internal IIS
latch
Operative Mode Comment
L
L
L
leakage
OFF
DMOS channel is OFF
L
L
H
leakage
OFF
DMOS channel is OFF
L
H
L
leakage
OFF_DIAG
Diagnostic in OFF-mode
open load
Diagnostic in OFF-mode
Diagnostic in OFF-mode
L
H
H
fault
H
L
L
leakage
ON
DMOS channel is ON, no diagnostic
H
L
H
leakage
fault
DMOS channel is switched OFF due to
failure
H
H
L
IIS
ON_DIAG
DMOS channel is ON and diagnostic
Data Sheet
15
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Supply
Table 8
Operation Mode truth table
IN
DEN
Internal IIS
latch
Operative Mode Comment
H
H
H
fault
fault
DMOS channel is switched OFF due to
failure
fIN(CLS)
X
L
leakage
CLS
DMOS channel is ON in Capacitive Load
Switching mode
6.1.1
OFF mode
When BTS70012-1ESP is in OFF mode, the output channel is OFF. The current consumption is minimum (see
parameter IVS(OFF)). No Overtemperature, Overload protection mechanism and no diagnosis function is active
when the device is in OFF mode.
6.1.2
ON mode
ON (IN = High; DEN = Low) mode is the normal operation mode of BTS70012-1ESP. Device current
consumption is specified with IGND(ON_D) + IIS(OFF) (measured at GND pin because the current at VS pin includes
the load current). Overcurrent and Overtemperature protections are active. No diagnosis function is active.
6.1.3
OFF_Diag mode
The device is in OFF_Diag mode as long as DEN pin is set to “high” and IN pin is set to “low”. The output
channel is OFF. Depending on the load condition, either a fault current IIS(FAULT) or an Open Load in OFF current
(IIS(OLOFF)) may be present at IS pin. In such situation, the current consumption of the device is increased.
6.1.4
ON_Diag mode
The device is in ON_Diag mode with current sense function enabled. IIS is present at IS pin. Device current
consumption is specified with IGND(ON_D). Depending on the load condition, either a fault current IIS(FAULT) or IIS
current may be present at IS pin.
6.1.5
Fault mode
The device is in Fault mode as soon as a protection event happens which affects that the device switches off
due to its protection function. In Fault mode, a IIS(FAULT) signal is presenting at IS pin during the DEN signal is
"high".
6.1.6
CLS mode
The device has a Capacitive Load Switching mode (CLS) implemented to charge capacitive loads. The CLS
mode is entered when an input frequency of fVIN(CLS) with the duty cycle of DCVIN(CLS) is applied at the input pin
(for more details see Chapter 7.2.3). The device current consumption in CLS is specified by the parameter
IGND(ON_D).
Data Sheet
16
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Supply
6.2
Undervoltage on VS
Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative (in ON mode) and
the supply voltage drops below the undervoltage threshold VS(UV), the internal logic switches OFF the output
channel.
As soon as the supply voltage VS is above the operative threshold VS(OP), the channel is switched ON again. The
restart is delayed with a time tDELAY(UV) which protects the device in case the undervoltage condition is caused
by a short circuit event (according to AEC-Q100-012), as shown in Figure 13.
If the device is in OFF mode and the input is set to “high”, the channel will be switched ON if VS > VS(OP) without
waiting for tDELAY(UV).
VS
VS(OP)
VS(UV)
VS(HYS)
t
Channel
activat ion signal
t
VOUT
tDELA Y(UV)
t
PowerSupply_UVRVS.emf
Figure 13
Data Sheet
VS undervoltage behavior
17
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Supply
6.3
Electrical Characteristics Power Supply
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω
Table 9
Electrical Characteristics: Power Supply - General
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
Power Supply Undervoltage VS(UV)
Shutdown
1.8
2.3
3.1
V
VS decreasing
IN = “high”
From VDS ≤ 0.5 V to
VDS = VS
See Figure 13
P_6.4.0.1
Power Supply Minimum
Operating Voltage
2.0
3.0
4.1
V
VS increasing
IN = “high”
From VDS = VS to
VDS ≤ 0.5 V
See Figure 13
P_6.4.0.3
Power Supply Undervoltage VS(HYS)
Shutdown Hysteresis
–
0.7
–
V
1)
P_6.4.0.6
Power Supply Undervoltage tDELAY(UV)
Recovery Time
2.5
5
7.5
ms
dVS/dt ≤ 0.5 V/µs
VS ≥ -1 V
See Figure 13
P_6.4.0.7
Breakdown Voltage
-VS(REV)
between GND and VS Pins in
Reverse Battery
16
–
30
V
1)
P_6.4.0.9
VS pin
VS(OP)
VS(OP) - VS(UV)
See Figure 13
IGND(REV) = 7 mA
TJ = 150 °C
1) Not subject to production test - specified by design.
Data Sheet
18
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Supply
6.4
Electrical Characteristics Power Supply - Product Specific
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω
6.4.1
BTS70012-1ESP
Table 10
Electrical Characteristics: Power Supply BTS70012-1ESP
Parameter
Symbol
Values
Min.
Typ.
Max.
0.2
2.2
Unit
Note or
Test Condition
Number
µA
1)
P_6.5.25.1
Supply Current
Consumption in OFF Mode
with Loads
IVS(OFF)_85
–
Supply Current
Consumption in OFF Mode
with Loads
IVS(OFF)_150
–
1
65
µA
VS = 18 V
VOUT = 0 V
IN = DEN = “low”
TJ = 150 °C
P_6.5.25.2
Operating Current in
ON_Diag Mode (Channel
ON)
IGND(ON_D)
–
2
3.3
mA
VS = 18 V
IN = DEN = “high”
P_6.5.25.3
Operating Current in
OFF_Diag Mode
IGND(OFF_D)
–
1.2
1.8
mA
VS = 18 V
IN = “low”;
DEN = “high”
P_6.5.25.5
VS = 18 V
VOUT = 0 V
IN = DEN = “low”
TJ ≤ 85 °C
1) Not subject to production test - specified by design.
Data Sheet
19
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Stages
7
Power Stages
The high-side power stage is built using a N-channel vertical Power MOSFET with charge pump.
7.1
Output ON-State Resistance
The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 14 shows the variation of
RDS(ON) across the whole TJ range. The value “2” on the y-axis corresponds to the maximum RDS(ON) measured
at TJ = 150 °C.
RDS(ON) variation over TJ
2.20
Reference value:
"2" = RDS(ON),MAX @ 150 °C
2.00
1.80
RDS(ON) variation factor
1.60
1.40
1.20
1.00
0.80
0.60
0.40
Typical
0.20
0.00
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
Junction Temperature (°C)
Figure 14
RDS(ON) variation factor
The behavior in Reverse Polarity is described in Chapter 8.4.1.
Data Sheet
20
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Stages
7.2
Switching loads
7.2.1
Switching Resistive Loads
When switching resistive loads, the switching times and slew rates shown in Figure 15 can be considered. The
switch energy values EON and EOFF are proportional to load resistance and times tON and tOFF.
IN
VIN(TH)
VIN(HYS)
t
VOUT
tON
90% of VS
tOFF(DELAY)
70% of VS
70% of VS
-(dV/dt)OFF
(dV/dt)ON
30% of VS
tON(DELAY)
10% of VS
30% of VS
tOFF
t
PDMOS
EON
EOFF
t
PowerStage_SwitchRes.emf
Figure 15
Data Sheet
Switching a Resistive Load
21
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Stages
7.2.2
Switching Inductive Loads
When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential,
because the inductance intends to continue driving the current. To prevent the destruction of the device due
to overvoltage, a voltage clamp mechanism is implemented. The clamping structure limits the negative
output voltage so that VDS = VDS(CLAMP). Figure 16 shows a concept drawing of the implementation. The
clamping structure is available in all operation modes listed in Chapter 6.1.
VS
High-side
Channel
VS
VSIS(CLAMP)
VDS
VDS(CLAMP)
IS
IL
RSEN SE
VS(CLAMP)
OUT
VOUT
GND
L,
RL
RGND
IL
PowerStage_Clamp_INTDIO_1CH.emf
Figure 16
Output Clamp concept
During demagnetization of inductive loads, energy has to be dissipated in BTS70012-1ESP. The energy can be
calculated with Equation (7.1):
RL ⋅ IL
V S – V DS ( CLAMP )
L
ö + I ⋅ -----E = V DS ( CLAMP ) ⋅ -------------------------------------------- ⋅ ln æ 1 – ------------------------------------------L
è
RL
RL
V S – V DS ( CLAMP )ø
(7.1)
The maximum energy, therefore the maximum inductance for a given current, is limited by the thermal design
of the component. Please refer to Chapter 4.2 for the maximum allowed values of EAS (single pulse energy)
and EAR (repetitive energy).
Data Sheet
22
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Stages
7.2.3
Switching Capacitive Loads
When switching a resistive load with the Capacitive Load Switching (CLS) mode the switching times as well as
the Switch-ON Slew Rate will change to tON_CLS, tON_CLS(DELAY), (dV/dt)ON_CLS as shown in Figure 17. The CLS mode
is entered by applying a PWM signal at the IN pin with a frequency of fVIN(CLS) and a duty cycle of DCVIN(CLS).
During this mode the thermal shut down temperature is reduced to TJ_CLS(DYN) and the device is set to autorestart.
IN
1
fVIN(CLS)
VIN(TH)
VIN(HYS)
VOUT
t
tON_CLS
90% of VS
70% of VS
(dV/dt)ON_CLS
30% of VS
tON_CLS(DELAY)
10% of VS
nACT
tCLS
t
nCLS_ACT = 1
t
Figure 17
Switching a Resistive Load with CLS mode
The CLS mode has to be left after a maximum time of tCLS by setting the input to "high" or "low" state. A
transition from the CLS mode to the ON mode will be automatically done when VDS < VDS(OLOFF).
Before changing from CLS mode to normal mode, it shall be ensured that there is no short circuit at the output.
To distinguish between short circuit and normal load, a current sense measurement shall be performed before
leaving CLS mode. If the current measurement delivers an expected value, the transition from CLS mode to
normal mode is possible. If the current measurement delivers an open load value (no output current), it has
to be assumed that there is either an open load or a short circuit at the output. Additionally, a short circuit
condition could be excluded by an external voltage measurement at the output.
Data Sheet
23
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Stages
tCLS
IN
t
VOUT
VDS(OLOFF)
t
IL
t
nACT
nCLS_ACT = 1
t
Operation
Mode
ON
CLS
t
Figure 18
Switching a Capacitive Load with CLS mode
7.2.4
Output Voltage Limitation
To increase the current sense accuracy, VDS voltage is monitored. When the output current IL decreases while
the channel is diagnosed (DEN pin set to “high” - see Figure 19) bringing VDS equal or lower than VDS(SLC), the
output DMOS gate is partially discharged. This increases the output resistance so that VDS = VDS(SLC) even for
very small output currents. The VDS increase allows the current sensing circuitry to work more efficiently,
providing better kILIS accuracy for output current in the low range.
IN
t
DEN
IL
t
VDS
t
VDS(SLC)
t
Figure 19
Data Sheet
Output Voltage Limitation activation during diagnosis
24
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Stages
7.3
Advanced Switching Characteristics
7.3.1
Inverse Current behavior
When VOUT > VS, a current IINV flows into the power output transistor (see Figure 20). This condition is known
as “Inverse Current”.
If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses
therefore an increase of overall device temperature. If the channel is in ON state, RDS(INV) can be expected and
power dissipation in the output stage is comparable to normal operation in RDS(ON).
During Inverse Current condition, the channel remains in ON or OFF state as long as |-IL| < |-IL(INV)|.
With InverseON, it is possible to switch ON the channel during Inverse Current condition as long as |-IL| < |-IL(INV)|
(see Figure 21).
VBAT
VS
Gate
Driver
Device
Logic
-IL
INV
Comp.
VOUT > VS
OUT
RGND
GND
PowerStage_Inverse_HEAT.emf
Figure 20
Data Sheet
Inverse Current Circuitry
25
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Stages
IN
IN
CASE 1 : Switch is ON
CASE 2 : Switch is OFF
OFF
ON
t
IL
NORMAL
t
IL
NORMAL
NORMAL
t
INVERSE
NORMAL
t
INVERSE
DMOS state
DMOS state
OFF
ON
t
t
CASE 3 : Switch ON into Inverse Current
CASE 4 : Switch OFF into Inverse Current
IN
IN
OFF
ON
IL
NORMAL
t
IL
NORMAL
NORMAL
t
INVERSE
OFF
ON
t
NORMAL
t
INVERSE
DMOS state
DMOS state
OFF
ON
ON
OFF
t
t
PowerStage_InvCurr_INVON.emf
Figure 21
InverseON - Channel behavior in case of applied Inverse Current
Note:
No protection mechanism like Overtemperature or Overload protection is active during applied
Inverse Currents.
Data Sheet
26
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Stages
7.3.2
Cross Current robustness with H-Bridge configuration
When BTS70012-1ESP is used as high-side switch e.g. in a bridge configuration (therefore paired with a lowside switch as shown in Figure 22), the maximum slew rate applied to the output by the low-side switch must
be lower than | dVOUT / dt |.
VBAT
R/L cable
HSS 1
VS
HSS 2
VS
T
T
ON (DC)
IN
IN
OUT
OFF
OUT
Current through Motor
| dVOUT / dt |
Cross
Current
M
ON ( PWM)
OFF
PowerStage
_ PassiveSlew
_ PROFET1Ch.emf
Figure 22
Data Sheet
High-Side switch used in Bridge configuration
27
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Stages
7.4
Electrical Characteristics Power Stages
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω
Table 11
Electrical Characteristics: Power Stages - General
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Voltages
Drain to Source Clamping
Voltage at TJ = -40 °C
VDS(CLAMP)_-40 33
36.5
42
V
IL = 20 mA
TJ = -40°C
DEN = “high”
See Figure 16
P_7.4.0.4
Drain to Source Clamping
Voltage at TJ ≥ 25 °C
VDS(CLAMP)_25 35
38
44
V
1)
P_7.4.0.5
IL = 20 mA
TJ ≥ 25°C
DEN = “high”
See Figure 16
1) Tested at TJ = 150°C.
7.4.1
Electrical Characteristics Power Stages
Table 12
Electrical Characteristics: Power Stages
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
10
70
140
μs
VS = 13.5 V
VOUT = 10% VS
See Figure 15
P_7.4.5.13
Switch-ON Delay Capacitive tON_CLS(DELAY)
Load Switching
20
460
900
μs
VS = 13.5 V
VOUT = 10% VS
See Figure 17
P_7.4.5.12
Switch-OFF Delay
tOFF(DELAY)
10
50
160
μs
VS = 13.5 V
VOUT = 90% VS
See Figure 15
P_7.4.5.2
Switch-ON Time
tON
50
130
210
μs
VS = 13.5 V
VOUT = 90% VS
See Figure 15
P_7.4.5.3
Switch-ON Time Capacitive
Load Switching
tON_CLS
350
1075
1800
μs
VS = 13.5 V
VOUT = 90% VS
See Figure 17
P_7.4.5.10
Timings
Switch-ON Delay
Data Sheet
tON(DELAY)
28
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Stages
Table 12
Electrical Characteristics: Power Stages (continued)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Switch-OFF Time
tOFF
30
100
220
μs
VS = 13.5 V
VOUT = 10% VS
See Figure 15
P_7.4.5.4
Switch-ON/OFF Matching
tON - tOFF
ΔtSW
-85
-10
65
μs
VS = 13.5 V
P_7.4.5.19
(dV/dt)ON
0.16
0.27
0.39
V/μs
VS = 13.5 V
P_7.4.5.6
VOUT = 30% to 70%
of VS
See Figure 15
0.021
0.034
V/μs
VS = 13.5 V
P_7.4.5.11
VOUT = 30% to 70%
of VS
See Figure 17
Voltage Slope
Switch-ON Slew Rate
Switch-ON Slew Rate in CLS (dV/dt)ON_CLS 0.008
Switch-OFF Slew Rate
-(dV/dt)OFF
0.16
0.27
0.39
V/μs
VS = 13.5 V
P_7.4.5.7
VOUT = 70% to 30%
of VS
See Figure 15
Slew Rate Matching
(dV/dt)ON - (dV/dt)OFF
Δ(dV/dt)SW
-0.15
0
+0.15
V/μs
VS = 13.5 V
P_7.4.5.8
VDS(SLC)
2
10
20
mV
1)
P_7.4.5.9
Input Frequency for CLS
Mode Activation
fVIN(CLS)
22
Duty Cycle for CLS Mode
Activation
DCVIN(CLS)
30%
Voltages
Output Voltage Drop
Limitation at Small Load
Currents
IOUT = IOUT(OL) = 20
mA
CLS Mode
30
38
kHz
2)
P_7.4.5.14
DCVIN(CLS) = 50%
See Figure 17
50%
1)
70%
P_7.4.5.15
fVIN(CLS) = 30 kHz
See Figure 17
Maximum Time in CLS Mode tCLS
–
Maximum Number of CLS
Mode Activations
nCLS(ACT)
–
Thermal Shutdown
Temperature in CLS Mode
(Dynamic)
TJ_CLS(DYN)
–
–
100
ms
1)
P_7.4.5.16
See Figure 18
–
1)
50k
P_7.4.5.17
See Figure 18
20
–
K
1)
P_7.4.5.18
1) Not subject to production test - specified by design
2) Functional test only
Data Sheet
29
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Stages
7.5
Electrical Characteristics - Power Output Stages
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω
7.5.1
Power Output Stage - 1.2 mΩ
Table 13
Electrical Characteristics: Power Stages - 1.2 mΩ
Parameter
Symbol
Values
Min.
Typ.
Max.
1.4
–
Unit
Note or
Test Condition
Number
mΩ
1)
P_7.5.23.1
Output characteristics
ON-State Resistance at
TJ = 25 °C
RDS(ON)_25
–
ON-State Resistance at
TJ = 150 °C
RDS(ON)_150
–
–
2.47
mΩ
TJ = 150 °C
P_7.5.23.2
ON-State Resistance in
Cranking
RDS(ON)_CRAN –
–
2.9
mΩ
TJ = 150 °C
VS = 3.1 V
P_7.5.23.3
1.5
–
mΩ
1)
P_7.5.23.4
TJ = 25 °C
K
RDS(INV)_25
ON-State Resistance in
Inverse Current at TJ = 25 °C
–
ON-State Resistance in
RDS(INV)_150
Inverse Current at TJ = 150 °C
–
–
2.9
mΩ
TJ = 150 °C
VS = 13.5 V
IL = -4 A
DEN = “low”
see Figure 20
P_7.5.23.5
RDS(REV)_25
ON-State Resistance in
Reverse Polarity at TJ = 25 °C
–
2.9
–
mΩ
1)
P_7.5.23.6
ON-State Resistance in
Reverse Polarity at
TJ = 150 °C
RDS(REV)_150
–
–
4.6
mΩ
TJ = 150 °C
VS = -13.5 V
IL = -4 A
P_7.5.23.7
Nominal Load Current
IL(NOM)
–
31.3
–
A
1)
P_7.5.23.8
Data Sheet
TJ = 25 °C
VS = 13.5 V
IL = -4 A
DEN = “low”
see Figure 20
TJ = 25 °C
VS = -13.5 V
IL = -4 A
see Figure 31
TA = 85 °C
TJ ≤ 150 °C
30
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Power Stages
Table 13
Electrical Characteristics: Power Stages - 1.2 mΩ (continued)
Parameter
Symbol
Values
Min.
Typ.
Max.
0.2
2.2
Unit
Note or
Test Condition
Number
μA
1)
P_7.5.23.9
Output Leakage Current at
TJ ≤ 85 °C
IL(OFF)_85
–
Output Leakage Current at
TJ = 150 °C
IL(OFF)_150
–
–
65
μA
VOUT = 0 V
VIN = “low”
TA = 150 °C
P_7.5.23.10
Inverse Current Capability
IL(INV)
–
-31.3
–
A
1)
P_7.5.23.11
VOUT = 0 V
VIN = “low”
TA ≤ 85 °C
VS < VOUT
IN = “high”
see Figure 20
Voltage Slope
Passive Slew Rate (e.g. for
Half Bridge Configuration)
| dVOUT / dt | –
–
10
V/μs
1)
P_7.5.23.12
VS = 13.5 V
see Figure 22
Voltages
Drain Source Diode Voltage | VDS(DIODE) |
–
550
700
mV
IL = -190 mA
TJ = 150 °C
P_7.5.23.13
EON
–
1.5
–
mJ
1)
P_7.5.23.14
EOFF
–
Switching Energy
Switch-ON Energy
Switch-OFF Energy
VS = 18 V
see Figure 15
1.65
–
mJ
1)
P_7.5.23.15
VS = 18 V
see Figure 15
1) Not subject to production test - specified by design.
Data Sheet
31
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Protection
8
Protection
The BTS70012-1ESP is protected against Overtemperature, Overload, Reverse Battery (with ReverseON) and
Overvoltage. Overtemperature and Overload protections are working when the device is in ON or ON_Diag
mode but not during InverseON and ReverseON function. Overvoltage protection works in all operation
modes. Reverse Battery protection works when the GND and VS pins are reverse supplied.
8.1
Overtemperature Protection
The device incorporates both an absolute (TJ(ABS)) and a dynamic (TJ(DYN)) temperature protection circuitry for
the channel. An increase of junction temperature TJ above either one of the two thresholds (TJ(ABS) or TJ(DYN))
switches OFF the overheated channel to prevent destruction. The channel remains switched OFF until
junction temperature has reached the “Reactivation” condition described in Table 14. The behavior is shown
in Figure 23 (absolute Overtemperature Protection) and Figure 24 (dynamic Overtemperature Protection).
TJ(REF) is the reference temperature used for dynamic temperature protection.
IN
t
DEN
t
IL
IL(OVL0 )
IL(NOM)
t
TJ
TJ( ABS)
t
IIS
IIS( FAULT)
IIS = IL kILIS
t
Internal
latch
1
0
t
Over_Temperature_Behavior.emf
Figure 23
Data Sheet
Overtemperature Protection (Absolute)
32
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Protection
IN
t
DEN
t
IL
IL( OVL)
t
TJ(DYN)
TJ
TJ( ABS)
TJ(REF)
IIS
t
IL / k ILIS
IIS( FAULT)
t
Internal
Latch
0
1
t
Figure 24
Overtemperature Protection (Dynamic)
When the Overtemperature protection circuitry allows the channel to be switched ON again, the Intelligent
Latch strategy described in Chapter 8.3 is followed.
Data Sheet
33
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Protection
8.2
Overload Protection
The BTS70012-1ESP is protected in case of Overload or short circuit to ground. Two Overload thresholds are
defined (see Figure 25) and selected automatically depending on the voltage VDS across the power DMOS:
•
IL(OVL0) when VDS < 13 V
•
IL(OVL1) when VDS > 22 V
Figure 25
Overload Current Thresholds
In order to allow a higher load inrush at low ambient temperature, Overload threshold is maximum at low
temperature and decreases when TJ increases (see Figure 26). IL(OVL0) typical value remains approximately
constant up to a junction temperature of +75 °C.
Data Sheet
34
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Protection
Figure 26
Overload Current Thresholds variation with TJ
Power supply voltage VS can increase above 18 V for short time, for instance in Load Dump or in Jump Start
condition. Whenever VS ≥ VS(JS), the overload detection current is set to IL(OVL_JS) as shown in Figure 27.
IL(OVL)
IL(OVL0)
IL(OVL_JS)
VS(JS),min
VS(JS),max
VS
Protection_JS.emf
Figure 27
Overload Detection Current variation with VS voltage
When IL ≥ IL(OVL) (either IL(OVL0), IL(OVL1) or IL(OVL_JS)) the channel is switched OFF. The channel is allowed to be
reactivated according to the intelligent latch strategy described in Chapter 8.3.
Data Sheet
35
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Protection
8.3
Protection and Diagnosis in case of Fault
Any event that triggers a protection mechanism (either Overtemperature or Overload) has 2 consequences:
•
The channel switches OFF and the internal latch is set to “1”
•
If the diagnosis is active for the channel, a current IIS(FAULT) is provided by IS pin (see Chapter 9.2.2 for
further details)
The channel can be switched ON again if all the protection mechanisms fulfill the ”reactivation” conditions
described in Table 14. Furthermore, the device has the intelligent latch to protect itself against unwanted
repetitive reactivation in fault condition.
Table 14
Protection “Reactivation” Condition
Fault condition
Switch OFF event
“Reactivation” condition
Overtemperature
TJ ≥ TJ(ABS) or (TJ - TJ(REF)) ≥ TJ(DYN)
TJ < TJ(ABS) and (TJ - TJ(REF)) < TJ(DYN)
(including hysteresis)
Overload
IL ≥ IL(OVL)
Device is OFF
8.3.1
Intelligent Latch Strategy
At normal condition, when IN is set to “high”, the channel is switched ON. In case of fault condition the output
stage latches OFF. There are two ways to de-latch the switch.
With IN pin:
It is necessary to set the input pin to “low” for a time longer than tDELAY(LR) (“latch reset delay” time) to de-latch
the channel. The channel can be allowed to restart only if the “latch” conditions for the protection
mechanisms are fulfilled (see Table 14 ).
During the “latch reset delay” time, if the input is set to “high” the channel remains switched OFF and the timer
tDELAY(LR) is reset. The timer tDELAY(LR) restarts as soon as the input pin is set to “low” again.
The intelligent latch strategy is shown in Figure 30 (flowchart) and Figure 28 (timing diagram).
With DEN pin:
It is possible to “force” a reset of the internal latch without waiting for tDELAY(LR) by applying a pulse (rising edge
followed by a falling edge) to the DEN pin while IN pin is “low”. The pulse applied to DEN pin must have a
duration longer than tDEN(LR) to ensure a reset of the internal latch.
The timing is shown in Figure 29.
Data Sheet
36
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Protection
tDELAY (LR)
IN
t
Short circuit
to ground
t
IL
t
Internal
latch
0
1
0
1
t
DEN
t
ts IS(DIAG )
tON
IIS (FAULT)
IIS (FAULT)
IIS
t
Protection_Latch_Timing.emf
Figure 28
Intelligent Latch Timing Diagram
IN
t
Short circuit
to ground
t
IL
t
Internal
latch
0
1
0
1
t
t > tDEN(LR)
t < t DEN(LR)
DEN
tsIS (DIAG)
IIS (FAULT)
ts IS(DIAG )
IIS (FAULT )
t s IS(DIAG)
IIS (FAULT)
t
IIS
t
Protection_Latch_DENforce.emf
Figure 29
Data Sheet
Intelligent Latch Timing Diagram with Forced Reset
37
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Protection
START
no
IN is "high"
yes
yes
Latch = 1
no
Reactivation
condition fulfilled
(TJ and / or ΔT / and / or
Overload)
no
yes
Latch = 0
Switch channel ON
Yes
no
Fault
(Overtemperature
or Overload)
DEN pulse > tDEN(LR)
no
yes
Switch channel OFF
Wait until
DEN pulse > tDEN(LR)
Latch = 1
Set DEN to „high“
Wait until IN is "low"
then start counting for
tDELAY(LR)
no
IN is "low"
yes
yes
De-latching with
DEN
no
Continue latching for
tDELAY(LR)
tDELAY(LR) elapsed
no
yes
Latch = 0
Protection_PROFET_Flow_PDH.emf
Figure 30
Data Sheet
Intelligent Latch Flowchart
38
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Protection
8.4
Additional protections
8.4.1
Reverse Polarity Protection
In Reverse Polarity condition (also known as Reverse Battery), the output stage is switched ON (see parameter
RDS(REV)) because of ReverseON feature which limits the power dissipation in the output stage. Each ESD diode
of the logic contributes to total power dissipation. The reverse current through the output stage must be
limited by the connected load. The current through Digital Input pins has to be limited as well by an external
resistor (please refer to the Absolute Maximum Ratings listed in Chapter 4.1 and to Application Information in
Chapter 10).
Figure 31 shows a typical application including a device with ReverseON. A current flowing into GND pin (-IGND)
during Reverse Polarity condition is necessary to activate ReverseON, therefore a resistive path between
module ground and device GND pin must be present.
-VBA T(REV)
High-side
Channel
Microcontroller
VS
IDI
DO
RDI
DI
ReverseON
OUT
-IL
IS
GND
RGND
-IIS
RSEN SE
GND
L, C, R
-IGND
Protection_RevBatt_HEAT.emf
Figure 31
Reverse Battery Protection (application example)
8.4.2
Overvoltage Protection
In the case of supply voltages between VS(EXT,UP) and VBAT(LD), the output transistor is still operational and
follows the input pin. In addition to the output clamp for inductive loads as described in Chapter 7.2.2, there
is a clamp mechanism available for Overvoltage protection for the logic circuit and the output channel,
monitoring the voltage between VS and GND pins (VS(CLAMP)).
Data Sheet
39
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Protection
8.5
Protection against loss of connection
8.5.1
Loss of Battery and Loss of Load
The loss of connection to battery or to the load has no influence on device robustness when load and wire
harness are purely resistive. In case of driving an inductive load, the energy stored in the inductance must be
handled. PROFET™ +2 12V devices can handle the inductivity of the wire harness up to 10 µH with IL(NOM). In
case of applications where currents and/or the aforementioned inductivity are exceeded, an external
suppressor diode (like diode DZ2 shown in Chapter 10) is recommended to handle the energy and to provide
a well-defined path to the load current.
8.5.2
Loss of Ground
In case of loss of device ground, it is recommended to have a resistor connected between any Digital Input pin
and the microcontroller to ensure a channel switch OFF (as described in Chapter 10).
Note:
Data Sheet
In case any Digital Input pin is pulled to ground (either by a resistor or active) a parasitic ground
path is available, which could keep the device operational during loss of device ground.
40
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Protection
8.6
Electrical Characteristics Protection
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω
Table 15
Electrical Characteristics: Protection - General
Parameter
Symbol
Values
Min.
Typ.
Max.
175
200
Thermal Shutdown
Temperature (Absolute)
TJ(ABS)
150
Thermal Shutdown
Hysteresis (Absolute)
THYS(ABS)
–
Thermal Shutdown
Temperature (Dynamic)
TJ(DYN)
–
Power Supply Clamping
Voltage at TJ = -40 °C
VS(CLAMP)_-40 33
Power Supply Clamping
Voltage at TJ ≥ 25 °C
VS(CLAMP)_25
Power Supply Voltage
VS(JS)
Threshold for Overcurrent
Threshold Reduction in case
of Short Circuit
Unit
Note or
Test Condition
Number
°C
1)2)
P_8.6.0.1
See Figure 23
30
–
K
3)
P_8.6.0.2
See Figure 23
80
–
K
3)
P_8.6.0.3
See Figure 24
35
36.5
42
V
IVS = 5 mA
TJ = -40 °C
See Figure 16
P_8.6.0.6
38
44
V
2)
P_8.6.0.7
IVS = 5 mA
TJ ≥ 25 °C
See Figure 16
20.5
22.5
24.5
V
3)
P_8.6.0.8
Setup acc. to AECQ100-012
Rsupply = 10 mΩ
Lsupply = 5 µH
Rshort = 25 mΩ
Lshort = 5 µH
1) Functional test only.
2) Tested at TJ = 150°C only.
3) Not subject to production test - specified by design.
8.6.1
Electrical Characteristics Protection
Table 16
Electrical Characteristics: Protection
Parameter
Symbol
Values
Min.
Typ.
Max.
Latch Reset Delay Time after tDELAY(LR)
Fault Condition
40
70
100
Minimum DEN Pulse
Duration for Latch Reset
50
tDEN(LR)
Unit
Note or
Test Condition
Number
ms
1)
P_8.6.4.1
See Figure 28
100
150
µs
2)
P_8.6.4.2
See Figure 29
1) Functional test only.
2) Not subject to production test - specified by design.
Data Sheet
41
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Protection
8.7
Electrical Characteristics Protection - Power Output Stages
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω
8.7.1
Protection Power Output Stage - 1.2 mΩ
Table 17
Electrical Characteristics: Protection - 1.2 mΩ
Parameter
Symbol
Values
Min.
Typ.
Max.
Overload Detection Current IL(OVL0)_-40
at TJ = -40 °C
187
217
248
Overload Detection Current IL(OVL0)_25
at TJ = 25 °C
180
Overload Detection Current IL(OVL0)_150
at TJ = 150 °C
146
Overload Detection Current IL(OVL1)
at High VDS
–
Overload Detection Current IL(OVL_JS)
Jump Start Condition
–
Unit
Note or
Test Condition
Number
A
1)
P_8.7.24.1
TJ = -40 °C
dI/dt = 0.4 A/µs
see Figure 25 and
Figure 26
209
238
A
2)
P_8.7.24.7
TJ = 25 °C
dI/dt = 0.4 A/µs
see Figure 25 and
Figure 26
170
193
A
2)
P_8.7.24.8
TJ = 150 °C
dI/dt = 0.4 A/µs
see Figure 25 and
Figure 26
130
–
A
2)
P_8.7.24.5
dI/dt = 0.4 A/µs
see Figure 25
130
–
A
2)
P_8.7.24.6
VS > VS(JS)
dI/dt = 0.4 A/µs
see Figure 27
1) Functional test only.
2) Not subject to production test - specified by design.
Data Sheet
42
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Diagnosis
9
Diagnosis
For diagnosis purpose, the BTS70012-1ESP provides a sense current signal (IIS) at pin IS. In case of disabled
diagnostic (DEN pin set to “low”), IS pin becomes high impedance.
A sense resistor RSENSE must be connected between IS pin and module ground if the current sense diagnosis is
used. RSENSE value has to be higher than 820 Ω (or 400 Ω when a central Reverse Battery protection is present
on the battery feed) to limit the power losses in the sense circuitry. A typical value is RSENSE = 1.2 kΩ.
Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS
pin to the sense current output of other devices, if they are supplied by a different battery feed.
See Figure 32 for details as an overview.
VS
Output
Channel
T
Overtemperature
Latch
IS Pin Control
Logic
OUT
IN
IL / kILIS
DEN
IIS(FAULT)
+
VDS(OLOFF)
IIS(OLOFF)
MUX
RSEN SE
IS
Diagnosis_HEAT_1CH.emf
Figure 32
Data Sheet
Diagnosis Block Diagram
43
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Diagnosis
9.1
Overview
Table 18 gives a quick reference to the state of the IS pin during BTS70012-1ESP operation.
Table 18
SENSE Signal, Function of Application Condition
Application Condition
Input level DEN level VOUT
Diagnostic Output
Normal operation
“low”
~ GND
Z
IIS(FAULT) if latch ≠ 0
Short circuit to GND
~ GND
Z
IIS(FAULT) if latch ≠ 0
Overtemperature
Z
IIS(FAULT)
Short circuit to VS
VS
IIS(OLOFF)
(IIS(FAULT) if latch ≠ 0)
Open Load
< VS - VDS(OLOFF)
> VS - VDS(OLOFF)1)
Z
IIS(OLOFF)
(in both cases IIS(FAULT) if
latch ≠ 0)
Inverse current
VOUT > VS
IIS(OLOFF)
(IIS(FAULT) if latch ≠ 0)
~ VS
IIS = IL / kILIS
Overload
< VS
IIS(FAULT)
Short circuit to GND
~ GND
IIS(FAULT)
Overtemperature
Z
IIS(FAULT)
Short circuit to VS
VS
Normal operation
“high”
“high”
IIS < IL / kILIS
~ VS
2)
IIS = IIS(EN)
Under load (e.g. Output Voltage
Limitation condition)
~ VS
3)
IIS(EN) < IIS < IL(NOM) / kILIS
Inverse current
VOUT > VS
IIS = IIS(EN)
Open Load
CLS mode
“pwm”
“high”
< VS - VDS(OLOFF)
Z
All conditions
n.a.
“low”
n.a.
Z
1) With additional pull-up resistor.
2) The output current has to be smaller than IL(OL).
3) The output current has to be higher than IL(OL).
9.2
Diagnosis in ON state
A current proportional to the load current (ratio kILIS = IL / IIS) is provided at pin IS when the following conditions
are fulfilled:
•
The power output stage is switched ON with VDS < VDS(OLOFF)
•
The diagnosis is enabled
•
No fault (as described in Chapter 8.3) is present or was present and not cleared yet (see Chapter 9.2.2 for
further details)
If a “hard” failure mode is present or was present and not cleared yet a current IIS(FAULT) is provided at IS pin.
Data Sheet
44
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Diagnosis
9.2.1
Current Sense (kILIS)
The accuracy of the sense current depends on temperature and load current. IIS increases linearly with IL
output current until it reaches the saturation current IIS(SAT). In case of Open Load at the output stage (IL close
to 0 A), the maximum sense current IIS(EN) (no load, diagnosis enabled) is specified. This condition is shown in
Figure 34. The blue line represents the ideal kILIS line, while the red lines show the behavior of a typical
product.
An external RC filter between IS pin and microcontroller ADC input pin is recommended to reduce signal ripple
and oscillations (a minimum time constant of 1 µs for the RC filter is recommended).
The kILIS factor is specified with limits that take into account effects due to temperature, supply voltage and
manufacturing process. Tighter limits are possible (within a defined current window) with calibration:
•
A well-defined and precise current (IL(CAL)) is applied at the output during End of Line test at customer side
•
The corresponding current at IS pin is measured and the kILIS is calculated (kILIS @ IL(CAL))
•
Within the current range going from IL(CAL)_L to IL(CAL)_H the kILIS is equal to kILIS @ IL(CAL) with limits defined by
ΔkILIS
The derating of kILIS after calibration is calculated using the formulas in Figure 33 and it is specified by ΔkILIS
Diagnosis_dKILIS.emf
Figure 33
ΔkILIS calculation formulas
The calibration is intended to be performed at TA(CAL) = 25°C. The parameter ΔkILIS includes the drift
overtemperature as well as the drift over the current range from IL(CAL)_L to IL(CAL)_H.
IIS
I IS(OL)
IIS(EN)
I L(OL)
IL
Diagnosis_OLON_adv .emf
Figure 34
Current Sense Ratio in Open Load at ON condition
9.2.2
Fault Current (IIS(FAULT))
As soon as a protection event occurs, the value of the internal latch (see Chapter 8.3 for more details) is
changed from 0 to 1, a current IIS(FAULT) is provided by pin IS when DEN is set to “high”.
If internal latch is 1, and it is not reset, the current IIS(FAULT) is provided each time the device diagnosis is
activated by DEN=High.
Data Sheet
45
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Diagnosis
Figure 35 shows the relation between IIS = IL / kILIS, IIS(SAT) and IIS(FAULT).
IIS
IIS (SA T).max
IIS (SA T)
IIS (FA ULT).max
IIS (FA ULT)
IIS (SA T).min
IIS (FA ULT).min
IL / kILI S
IL(OV L).min
IL(OV L).max
IL
Diagnosis_HEAT_IISFAULT_IISSAT.emf
Figure 35
SENSE behavior - overview
9.3
Diagnosis in OFF state
When a power output stage is in OFF state, the BTS70012-1ESP can measure the drain-source voltage and
compare it with a threshold voltage. In this way, using some additional external components (a pull-down
resistor and a switchable pull-up current source), it is possible to detect if the load is missing or if there is a
short circuit to battery. If a Fault condition was detected by the device (if internal latch is 1, fault current is
provided by IS pin independent of drain-source or output voltage, as long as DEN=High) a current IIS(FAULT) is
provided by IS pin each time the channel diagnosis is checked also in OFF state. See Chapter 9.2.2 for further
details.
9.3.1
Open Load current (IIS(OLOFF))
In OFF state, when DEN pin is set to “high”, the VDS voltage is compared with a threshold voltage VDS(OLOFF). If
the load is properly connected and there is no short circuit to battery, VDS ~ VS therefore VDS > VDS(OLOFF). When
the diagnosis is active and VDS ≤ VDS(OLOFF), a current IIS(OLOFF) is provided by IS pin. Figure 36 shows the
relationship between IIS(OLOFF) and IIS(FAULT) as functions of VDS. The two currents do not overlap making it always
possible to differentiate between Open Load in OFF and Fault condition.
Data Sheet
46
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Diagnosis
IIS
IIS(FAULT)
IIS(OLOFF)
VDS(OLOFF)
Figure 36
VDS
IIS in OFF State
It is necessary to wait a time tIS(OLOFF)_D between the falling edge of the input pin and the sensing at pin IS for
Open Load in OFF diagnosis to allow the internal comparator to settle. In Figure 37 the timings for an Open
Load detection are shown - the load is always disconnected.
IN
t
DEN
VOUT
tIS(OLOFF)_D
t
~ VS
VDS(OLOFF)
Load
conn ect ed
t
IIS
IIS(OLOFF)
IIS(OL)
t
Diagnosis_PROFET_OLOFF_time.emf
Figure 37
Data Sheet
Open Load in OFF Timings - load disconnected
47
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Diagnosis
9.4
SENSE Timings
Figure 38 shows the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including the case of load
change). As a proper signal cannot be established before the load current is stable (therefore before tON),
tsIS(DIAG) ≤ 3 × ( tON_max + tsIS(ON)_max ).
IN
OFF
OFF
ON
t
DEN
t
IL
tsIS (L C)
IIS
tsIS (O FF)
tsIS (ON)
tsIS (O FF)
Diagnose_PROFET_SENSE_timings_Heat.emf
Figure 38
Data Sheet
t
tsIS (DI AG)
t
SENSE Settling / Disabling Timing
48
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Diagnosis
9.5
Electrical Characteristics Diagnosis
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω
Table 19
Electrical Characteristics: Diagnosis - General
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
mA
1)
P_9.6.0.1
Min.
Typ.
Max.
IIS(SAT)
4.4
–
15
SENSE Leakage Current
when Disabled
IIS(OFF)
–
0.01
0.5
µA
DEN = “low”
VIS = 0 V
P_9.6.0.2
SENSE Leakage Current
when Enabled at TJ ≤ 85 °C
IIS(EN)_85
–
0.2
1
µA
1)
P_9.6.0.3
SENSE Saturation Current
SENSE Leakage Current
IIS(EN)_150
when Enabled at TJ = 150 °C
VSIS = VS - VIS ≥ 2 V
See Figure 35
TJ ≤ 85 °C
DEN = “high”
IL = 0 A
See Figure 34
–
0.2
1
µA
TJ = 150 °C
DEN = “high”
IL = 0 A
See Figure 34
P_9.6.0.4
0.5
1
V
1)
P_9.6.0.6
Saturation Voltage in kILIS
Operation
(VS - VIS)
VSIS_k
–
Saturation Voltage in Open
Load at OFF Diagnosis
(VS - VIS)
VSIS_OL
–
Saturation Voltage in Fault
Diagnosis
(VS - VIS)
VSIS_F
–
Power Supply to IS Pin
Clamping Voltage at
TJ = -40 °C
VSIS(CLAMP)_-
33
Power Supply to IS Pin
Clamping Voltage at
TJ ≥ 25 °C
VSIS(CLAMP)_25 35
VS = 6 V
IN = DEN = “high”
IL ≤ 2 * IL(NOM)
0.5
1
V
1)
P_9.6.0.7
VS = 6 V
IN = “low”
DEN = “high”
0.5
1
V
1)
P_9.6.0.8
VS = 6 V
IN = “low”
DEN = “high”
latch ≠ 0
36.5
42
V
IIS = 1 mA
TJ = -40 °C
See Figure 16
P_9.6.0.9
38
44
V
2)
P_9.6.0.10
40
IIS = 1 mA
TJ ≥ 25 °C
See Figure 16
1) Not subject to production test - specified by design.
2) Tested at TJ = 150°C.
Data Sheet
49
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Diagnosis
9.5.1
Electrical Characteristics Diagnosis
Table 20
Electrical Characteristics: Diagnosis
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
SENSE Fault Current
IIS(FAULT)
4.4
5.5
10
mA
–
P_9.6.4.1
SENSE Open Load in OFF
Current
IIS(OLOFF)
1.8
2.5
3.5
mA
–
P_9.6.4.2
SENSE Open Load in OFF
Delay Time
tIS(OLOFF)_D
70
185
300
µs
VDS < VOL(OFF)
P_9.6.4.4
from IN falling
edge to VIS = RSENSE
* 0.9 * IIS(OLOFF),MIN
DEN = “high”
Open Load VDS Detection
Threshold in OFF State
VDS(OLOFF)
1.3
1.8
2.3
V
–
SENSE Settling Time with
Nominal Load Current
Stable
tsIS(ON)
–
5
40
µs
P_9.6.4.6
IL = IL(NOM)
DEN from “low” to
“high”
SENSE Disable Time
tsIS(OFF)
–
5
20
µs
1)
SENSE Settling Time after
Load Change
tsIS(LC)
–
SENSE Settling Time after
Load Change with Small
Load Current
tsIS(LC)_SLC
–
P_9.6.4.5
P_9.6.4.8
From DEN falling
edge to IIS = IIS(OFF)
See Figure 38
5
20
µs
1)
P_9.6.4.9
from IL = IL22 to
IL = IL23
See Figure 38
500
800
µs
1)
P_9.6.4.15
DEN = “high”
Load Change from
IL22 to IL10
1) Not subject to production test - specified by design.
Data Sheet
50
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Diagnosis
9.6
Electrical Characteristics Diagnosis - Power Output Stages
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω
9.6.1
Diagnosis Power Output Stage - 1.2 mΩ
Table 21
Electrical Characteristics: Diagnosis - 1.2 mΩ
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
mA
IIS = IIS(OL) = 8 µA
see Figure 34
P_9.7.26.3
Open Load Output Current
at IIS = 8 µA
IL(OL)_8u
82
–
464
Current Sense Ratio at
IL = IL07
kILIS07
-65%
34100
+65%
IL07 = 200 mA
P_9.7.26.11
Current Sense Ratio at
IL = IL10
kILIS10
-65%
34100
+65%
IL10 = 700 mA
P_9.7.26.14
Current Sense Ratio at
IL = IL13
kILIS13
-55%
34100
+55%
IL13 = 2 A
P_9.7.26.17
Current Sense Ratio at
IL = IL17
kILIS17
-40%
34100
+40%
IL17 = 7 A
P_9.7.26.21
Current Sense Ratio at
IL = IL20
kILIS20
-24%
34100
+24%
IL20 = 20 A
P_9.7.26.24
Current Sense Ratio at
IL = IL22
kILIS22
-8%
34100
+8%
IL22 = 30 A
P_9.7.26.26
Current Sense Ratio at
IL = IL23
kILIS23
-8%
34100
+8%
1)
P_9.7.26.31
SENSE Current Derating
with Low Current
Calibration
ΔkILIS(OL)
-30
SENSE Current Derating
with Nominal Current
Calibration
ΔkILIS(NOM)
-5
IL23 = 35 A
0
+30
%
1)
P_9.7.26.27
IL(CAL) = IL10
IL(CAL)_H = IL13
IL(CAL)_L = IL07
TA(CAL) = 25 °C
0
+5
%
1)
P_9.7.26.29
IL(CAL) = IL22
IL(CAL)_H = IL23
IL(CAL)_L = IL20
TA(CAL) = 25 °C
1) Not subject to production test - specified by design.
Data Sheet
51
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Application Information
10
Application Information
Note:
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
10.1
Application setup
VBAT
ZWIRE
Optional
Optional
CVS
Logic Supply
CVSGND
GND VS
IN
GPIO
RDEN
DEN
CVS2
PROFET™ +2
12V
Microcontroller
ADC
OUT
RADC
RIS_PROT
COUT0
ZWIRE
RIN
RPD
GPIO
ROL
RGND
VDD
DZ2
T1
IS
DZ1
Logic GND
Power GND
ZLOAD*
CSENSE
RSENSE
VSS
Optional
Chassis GND
*See Chapter 1 „Potential Applications“
App_1CH_INTDIO_CVG.emf
Figure 39
BTS70012-1ESP Application Diagram
Note:
This is a very simplified example of an application circuit. The function must be verified in the real
application.
Data Sheet
52
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Application Information
10.2
External Components
Table 22
Suggested Component values
Reference
Value
Purpose
RIN
4.7 kΩ
Protection of the microcontroller during Overvoltage and Reverse Polarity
Necessary to switch OFF BTS70012-1ESP output during Loss of Ground
RDEN
4.7 kΩ
Protection of the microcontroller during Overvoltage and Reverse Polarity
Necessary to switch OFF BTS70012-1ESP output during Loss of Ground
RPD
47 kΩ
Output polarization (pull-down)
Ensures polarization of BTS70012-1ESP outputs to distinguish between
Open Load and Short to VS in OFF Diagnosis
ROL
1.5 kΩ
Output polarization (pull-up)
Ensures polarization of BTS70012-1ESP output during Open Load in OFF
diagnosis
COUT
10 nF
Protection of BTS70012-1ESP output during ESD events and BCI
T1
BC 807
Switch the battery voltage for Open Load in OFF diagnosis
CVS
100 nF
Filtering of voltage spikes on the battery line
CVSGND
47 nF
Buffer capacitor for fast transient
See Table 5 (P_4.3.0.7) for the boundary conditions
A placeholder on PCB layout is recommended
DZ2
33 V TVS Diode Transient Voltage Suppressor diode
Protection during Overvoltage and in case of Loss of Battery while driving
an inductive load
CVS2
–
Filtering / buffer capacitor located at VBAT connector
RSENSE
1.2 kΩ
SENSE resistor
RIS_PROT
4.7 kΩ
Protection during Overvoltage, Reverse Polarity, Loss of Ground
Value to be tuned according to microcontroller specifications
DZ1
7 V Z-Diode
Protection of microcontroller during Overvoltage
RADC
4.7 kΩ
Protection of microcontroller ADC input during Overvoltage, Reverse
Polarity, Loss of Ground
Value to be tuned according to microcontroller specifications
CSENSE
220 pF
Sense signal filtering
A time constant (RADC + RIS_PROT) * CSENSE longer than 1 µs is recommended
RGND
47 Ω
Protection in case of Overvoltage and Loss of Battery while driving
inductive loads
10.3
Further Application Information
•
Please contact us for information regarding the Pin FMEA
•
For further information you may contact http://www.infineon.com/
Data Sheet
53
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Package Outlines
11
Package Outlines
Figure 40
PG-TSDSO-24 (Thin (Slim) Dual Small Outline 24 pins) Package drawing
Data Sheet
54
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Package Outlines
Figure 41
PG-TSDSO-24 (Thin (Slim) Dual Small Outline 24 pins) Package pads and stencil
Green product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Further information on packages
https://www.infineon.com/packages
Data Sheet
55
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Revision History
12
Revision History
Table 23
BTS70012-1ESP - List of changes
Revision
Changes
1.10, 2020-12-14 Typo fixed (PROFET™+2 → PROFET™ +2)
P_4.2.21.1 updated (Typ.: 525 → –; Max.: – → 525)
P_4.2.21.2 updated (Typ.: 160 → –; Max.: – → 160)
1.00, 2020-10-16 Data Sheet available
Data Sheet
56
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Table of Contents
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
2.1
2.2
Block Diagram and Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
4.1
4.2
4.2.1
4.3
4.4
4.4.1
4.4.2
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings - General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings - Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Stages - 1.2 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PCB Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
5.1
5.2
5.3
Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Pin (IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
14
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.2
6.3
6.4
6.4.1
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFF_Diag mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON_Diag mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLS mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Supply - Product Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BTS70012-1ESP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
16
16
16
16
16
16
17
18
19
19
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.3.1
7.3.2
7.4
7.4.1
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Inductive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inverse Current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cross Current robustness with H-Bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
21
21
22
23
24
25
25
27
28
28
Data Sheet
57
Rev. 1.10
2020-12-14
BTS70012-1ESP
PROFET™ +2 12V
Table of Contents
7.5
7.5.1
Electrical Characteristics - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Power Output Stage - 1.2 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8
8.1
8.2
8.3
8.3.1
8.4
8.4.1
8.4.2
8.5
8.5.1
8.5.2
8.6
8.6.1
8.7
8.7.1
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection and Diagnosis in case of Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intelligent Latch Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection against loss of connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss of Battery and Loss of Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Protection - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Power Output Stage - 1.2 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
32
34
36
36
39
39
39
40
40
40
41
41
42
42
9
9.1
9.2
9.2.1
9.2.2
9.3
9.3.1
9.4
9.5
9.5.1
9.6
9.6.1
Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis in ON state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense (kILIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Current (IIS(FAULT)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis in OFF state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Load current (IIS(OLOFF)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SENSE Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Diagnosis - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis Power Output Stage - 1.2 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
44
44
45
45
46
46
48
49
50
51
51
10
10.1
10.2
10.3
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
52
53
53
11
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data Sheet
58
Rev. 1.10
2020-12-14
Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2020-12-14
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2020 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
Z8F65710207
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics ("Beschaffenheitsgarantie").
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer's compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer's products and any use of the product of
Infineon Technologies in customer's applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer's technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to
such application.
For further information on technology, delivery terms
and conditions and prices, please contact the nearest
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Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
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authorized representatives of Infineon Technologies,
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any applications where a failure of the product or any
consequences of the use thereof can reasonably be
expected to result in personal injury.
