CHL8103-13CRT

Digital Multi-Phase Buck Controller DESCRIPTION  Pb-Free, RoHS, QFN packages APPLICATIONS  Intel® VR12 & AMD® SVI based systems  High Performance Desktops CPU VRs  Value Servers CPU & DDR Memory VRs 40 39 38 37 36 ISEN_L2  3.3V +10%/-15% supply voltage; 0ºC to 85ºC operation IRTN_L2 PIN DIAGRAM 35 34 33 32 31 RCSP 1 30 RCSP_L2 RCSM 2 29 RCSM_L2 VPGM2 3 28 VCC VSEN 4 27 VSEN_L2 VRTN 5 26 VRTN_L2 RRES 6 TSEN1 7 V18A 8 VR_READY1/ PWRGD2 9 VR_READY_L21/ PWROK2 CHL8103/4 40 Pin 6x6 QFN Top View 1 2 Intel Mode AMD Mode 25 PWM_L2 24 PWM4 (CHL8104)/ NC (CHL8103) 23 PWM3 22 PWM2 21 PWM1 41 GND 10 11 12 13 14 15 16 17 18 19 20 TSEN2  Compatible with IR ATL and 3.3V tri-state Drivers ISEN4 (CHL8104)/ NC (CHL8103)  Multiple time programmable (MTP) memory for custom configuration SMB_CLK  Thermal Protection (OTP) and VRHOT# flag (CHL8103/04/13) The CHL8102/03/04/13 includes numerous features like register diagnostics for fast design cycles and platform differentiation, truly simplifying VRD design and enabling fastest time-to-market (TTM) with “set-and-forget” methodology. SMB_DAT  Per-Loop Fault Protection: OVP, UVP, OCP ISEN 3  IR Adaptive Transient Algorithm (ATA) on both loops minimizes output bulk capacitors and system cost The CHL8102/03/04/13 provides extensive OVP, UVP, OCP and OTP fault protection and the CHL8103/04/13 includes thermistor based temperature sensing with VRHOT signal. IRTN4 (CHL8104)/ NC (CHL8103)  1-phase & Active Diode Emulation modes for light load efficiency ADDR/PROT/EN_L2  IR Efficiency Shaping with Dynamic Phase Control (DPC) IRTN 3  Independent loop switching frequencies from 200kHz to 1.2MHz per phase ENABLE  I2C security enable pin (CHL8103/04/13) IR’s unique Adaptive Transient Algorithm (ATA), based on proprietary non-linear digital PWM algorithms, minimizes output bulk capacitors and Multiple Time Programmable (MTP) storage saves pins and enables a small package size. Device configuration and fault parameters are easily defined using the IR Digital Power Design Center (DPDC) GUI and stored in on-chip MTP. ISEN 2  Flexible I2C bus security features VR_HOT#  Overclocking support with I2C voltage override and Vmax setting IRTN 2  Pin programmable I2C address (CHL8103/04/13) SV_DAT1/SVD2  I2C interface for configuration & telemetry The CHL8102/03/04/13 includes IR Efficiency Shaping Technology to deliver exceptional efficiency at minimum cost across the entire load range. IR Dynamic Phase Control adds/drops active phases based upon load current and can be configured to enter 1-phase operation and diode emulation mode automatically or by command. ISEN 1  Fully supports Intel® VR12 (CHL8103/04/13) and AMD® SVI with dual OCP & programmable addressing (CHL8103/04) SV_CLK1/SVC2  Footprint compatible with CHL8325A/B (CHL8103/4) IRTN 1  Easiest layout and fewest pins in the industry The CHL8102/03/04 are dual-loop, digital multi-phase buck controllers designed for CPU voltage regulation. The CHL8113 is a single-loop, digital multiphase buck controller ideal for Server DDR memory voltage regulation. They are fully compliant with the Intel® VR12 and AMD® SVI (CHL8103/04) specifications. VINSEN  Dual output 2/3/4+1-phase PWM Controller (CHL8102/03/04) and single output 3-phase PWM Controller (CHL8113) SV_ALERT1/NC2 FEATURES CHL8102/03/04/13 Figure 1: CHL8103/04 Package Top View 1 August 28, 2013 | FINAL | V1.09 Digital Multi-Phase Buck Controller CHL8102/03/04/13 IRTN 1 ISEN 1 IRTN 2 ISEN 2 IRTN 3 ISEN 3 IRTN4 (CHL8104)/ NC (CHL8103) ISEN4 (CHL8104)/ NC (CHL8103) IRTN_L2 ISEN_L2 PIN DIAGRAM ENLARGED 40 39 38 37 36 35 34 33 32 31 RCSP 1 30 RCSP_L2 RCSM 2 29 RCSM_L2 VPGM2 3 28 VCC VSEN 4 27 VSEN_L2 26 VRTN_L2 25 PWM_L2 CHL8103/4 40 Pin 6x6 QFN Top View VRTN 5 RRES 6 TSEN1 7 24 PWM4 (CHL8104)/ NC (CHL8103) V18A 8 23 PWM3 22 PWM2 21 PWM1 1 VR_READY / PWRGD2 1 9 2 1 2 41 GND 11 12 13 14 15 16 17 18 19 20 SV_ALERT1/NC2 SV_CLK1/SVC2 SV_DAT1/SVD2 VR_HOT# ENABLE ADDR/PROT/EN_L2 SMB_DAT SMB_CLK TSEN2 10 VINSEN VR_READY_L2 / PWROK2 Intel Mode AMD Mode August 28, 2013 | FINAL | V1.09