CHL8318CRT

CHL8318 DIGITAL MULTI-PHASE BUCK CONTROLLER PRODUCT BRIEF FEATURES DESCRIPTION  Intel VR11.x compliant Digital PWM Controller  Programmable 1-phase to 8-phase operation  Configurable switching frequency from 200 kHz to 1MHz per phase with accuracy better than 2%  Customized Digital Over-Clocking Features o Easy-to-use SMBus Gamer command o Gamer VID control up to 2.3V, Gamer Vmax, VID Override or Track, Digital Load-Line Adjust, Gamer OC/OVP, Gamer OFF pin, Gamer OTP The CHL8318 is a 8-phase digital synchronous buck ® controller for core regulation of high-performance INTEL VR11.1 and VR11.0 platforms. The CHL8318 is fully compliant with VR11.1 including Power Status Indicator (PSI) and for improved light load efficiency and accurate current output (IMON). SMBus interface for configuring and monitoring; SMBus commands include monitoring input current and power  Compatible with CHiL ATL Drivers and tri-state Drivers  Nine bytes of NVM storage available for customer use  +3.3V supply voltage; 0ºC to 85ºC Ambient operation  RoHS Compliant, MSL level 1 package The CHL8318 deploys a number of efficiency shaping features. The CHL8318 can be configured to optimize MOSFET gate drive versus load current, PSI can be programmed to be up to four phases for optimum light-load efficiency, and the controller can autonomously add/drop phases in low-current and mid-current regions to deliver 90+% efficiency across the entire load range. CHiL’s unique Adaptive Transient Algorithm, based on nonlinear digital PWM algorithms, minimizes output bulk capacitors. Coupled inductor mode of operation allows two phase PSI and add/drop of phases which are 180°out of phase for further improvement in transient response and form factor. CHL8318 supports three NTC temperature sensors to report temperature and trigger VR HOT and OTP faults. Digital thermal balancing allows proportional current imbalance between phases. ISEN7 IRTN7  ISEN6 SMBus Fault Indicators: OVP, UVP, OCP, OTP IRTN6 Enables Thermal Phase Balancing  ISEN5  ISEN4 Designed for use with coupled inductors IRTN5  ISEN3 Adaptive Transient Algorithm minimizes output bulk capacitors IRTN4 1-phase to 4-phase PSI for Light Loads  IRTN3  IRTN2 ISEN2 CHiL Efficiency Shaping Features o Variable Gate Drive o Dynamic Phase Control IRTN1 ISEN1  The CHiL CHL8318 includes a customized set of digital over-clocking features which require no external components. Gaming applications can use the SMBus interface to place the VRD into “Gamer Mode”. Gamer Mode features include Extended Gamer VID up to 2.3V with 6.25 mV resolution, Gamer Vmax, CPU VID Override or Track, Digital Load-Line adjust, Gamer OC/OVP and Gamer OFF pin. 56 55 54 53 52 51 50 49 48 47 46 45 44 43 RCSP 1 42 IRTN8 RCSM 2 41 ISEN8 VCC 3 40 VCPU 4 39 VCC PWM8 38 PWM7 37 PWM6 36 PWM5 35 PWM4 34 CHiL CHL8318 56 Pin 8mmx8mm QFN TOP VIEW VRTN 5 SADDR/ GAMER_OFF 6 IMON RRES 7 VINSEN 9 TSEN1 10 TSEN2 11 32 PWM3 PWM2 PWM1 TSEN3 12 31 NC EN 13 VCC V18A 14 30 29 8 33 GND VR_HOT VR_READY VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 SCL PSI# SDA SALERT# 15 16 17 18 19 20 21 22 23 24 25 26 27 28 The CHL8318 provides extensive OVP, UVP, OCP and OTP fault protection. Device and fault configuration parameters are easily defined using the CHiL Intuitive Power Designer (IPD) GUI and stored in on-chip non-volatile memory (NVM). The 3-pin SMBus interface can be used to monitor a variety of operating parameters on up to seven CHL8318 based VRs. The controller includes a unique sensorless and lossless input current monitoring capability. The CHL8318 truly simplifies VRD design and enables fastest time-to-market with its “set-and-forget” methodology. VAR_GATE APPLICATIONS  Intel® VR11.x CPU VRD and VRM; DDR Memory  High Performance Desktops and Servers  Over-clocking and High-Efficiency Applications Figure 1. CHL8318 56 Pin QFN Package Trademarks and registered trademarks are the property of the respective owners. PB0006 Rev. 1.00, October 26, 2009 Page 1 of 4 One Highwood Drive, Tewksbury, MA 01876 Tel: +1(978)-640-0011 www.chilsemi.com © 2009 CHiL Semiconductor Corp. All rights reserved CHL8318 PRODUCT BRIEF DIGITAL MULTI-PHASE BUCK CONTROLLER FUNCTIONAL BLOCK DIAGRAM RRES V18A 3.3V VID0 1.8V VID1 VID3 VID4 LDO Reference VID2 VID decode and DAC Digital Processor VID5 Vref VID6 VID7 PID + Controller OVP VCPU VRTN ISEN1 IRTN1 ISEN2 IRTN2 ISEN3 IRTN3 ISEN4 IRTN4 ISEN5 IRTN5 ISEN6 IRTN6 ISEN7 IRTN7 ISEN8 IRTN8 PWM1 Voltage Error ADC Σ PWM2 PWM3 Transient Controller PWM Generator PWM4 PWM5 PWM6 PWM7 PWM8 Channel Current Sense Current Balance RCSP RCSM Monitor ADC TSEN1 TSEN2 TSEN3 VINSEN EN SADDR/ VAR_GATE OVP Oscillator, NVM State Control, and Monitoring Current Monitor IMON GAMER_OFF PSI SDA SCL SMBus Interface SALERT VRHOT VR_Ready GND Figure 2. Functional Block Diagram Page 2 of 4 PB0006 Rev. 1.00, October 26, 2009 CHL8318 PRODUCT BRIEF DIGITAL MULTI-PHASE BUCK CONTROLLER 12V V TYPICAL APPLICATIONS RCSP CCS 2 +3.3V 3 30 40 32 55 ISEN1 56 IRTN1 PWM1 RCSM VCC V_VGD VCPU 5 VRTN 6 SADDR/ GAMER_OFF PWM 2 33 53 ISEN2 54 IRTN2 7 IMON V_VGD CHL8318 ISEN3 8 RRES +12V IRTN3 34 51 CHL8510 52 12V RVIN_1 9 VINSEN 10 TSEN1 RVIN_2 V_VGD RTh PWM4 TSEN2 ISEN4 RTh IRTN4 12 35 CHL8510 49 50 12V TSEN3 14 V18A IRTN5 36 CHL8510 47 48 12V V_VGD 37 PWM6 45 ISEN6 46 IRTN6 V 21 V 22 23 V V 26 27 To CPU 28 V 12V PSI# VID7 V_VGD VID6 38 PWM7 43 ISEN7 44 IRTN7 VID5 VID4 BOOT HI_GATE Vcc HVCC SWITCH LVCC PWM LO_GATE MODE GND CHL8510 12V VID3 24 VID2 25 CHL8510 V V 20 V V V 19 V From CPU 18 BOOT HI_GATE Vcc HVCC SWITCH LVCC PWM LO_GATE MODE GND V V V 15 SALERT# 16 SDA 17 SCL V SMBus +3.3V V ISEN5 V PWM5 EN V_VGD VID1 V 13 BOOT HI_GATE Vcc HVCC SWITCH LVCC PWM LO_GATE MODE GND 39 PWM8 41 ISEN8 42 IRTN8 VID0 VR_READY CHL8510 12V VR_HOT BOOT HI_GATE Vcc HVCC SWITCH LVCC PWM LO_GATE MODE GND NC 31 VAR_GATE 29 GND V V V_VGD V RTh From System BOOT HI_GATE Vcc HVCC SWITCH LVCC LO_GATE PWM MODE GND V 11 BOOT HI_GATE Vcc HVCC SWITCH LVCC PWM LO_GATE MODE GND V PWM3 V VRTN V C_IMON R_IMON BOOT HI_GATE Vcc HVCC SWITCH LVCC PWM LO_GATE MODE GND CHL8510 12V To CPU L O A D CHL8510 12V 4 V_CPU V Rseries V RCS BOOT HI_GATE Vcc HVCC SWITCH LVCC PWM LO_GATE MODE GND V RTh V_VGD V 1 Rseries BOOT HI_GATE Vcc HVCC SWITCH LVCC LO_GATE PWM MODE GND CHL8510 V_VGD Optional Variable Gate Drive Circuit Figure 3. 8-phase VRD using CHL8318 Controller and CHL8510 MOSFET drivers Page 3 of 4 PB0006 Rev. 1.00, October 26, 2009 CHL8318 PRODUCT BRIEF DIGITAL MULTI-PHASE BUCK CONTROLLER ORDERING INFORMATION CHL8318    Package QFN Tape & Reel Qty 3000 Part Number CHL8318CRT T: Tape & Reel Package type R : QFN Operating Temperature Range C: Commercial Standard PACKAGE INFORMATION Page 4 of 4 PB0006 Rev. 1.00, October 26, 2009