CHL8326-00CRT

CHL8326/8 DIGITAL MULTI-PHASE GPU BUCK CONTROLLER PRODUCT BRIEF PRELIMINARY 46 45 44 43 42 41 40 39 38 37 36 RCSP_L2 RCSM 2 35 RCSM_L2 VCC 3 34 VCC CFP1 / VFIXEN_PSI2 4 33 VSEN_L2 CHiL Adaptive Transient Algorithm (ATA) on both loops minimizes output bulk capacitors and system cost VSEN 5 VRTN 6 Designed for use with coupled inductors RRES 7 TSEN 8 29 PWM4 V18A 9 28 PWM3 VR_READY1 / PWRGD2 10 27 PWM2 VR_READY_L212 / PWROK 11 VINSEN 12 Programmable 1-phase or 2-phase for Light Loads and Active Diode Emulation for Very Light Loads The CHL8326/8 are dual-loop digital multi-phase buck controllers. The CHL8326 drives up to 6 phases and the CHL8328 drives up to 8 phases. The CHL8326/8 is fully Intel® VR12 and AMD® SVI/PVI compliant on both loops and provides a Vtt tracking function for DDR memory. The I2C/PMBus interface can communicate with up to 16 CHL8326/8 based VR loops. Device configuration and fault parameters are easily defined using the CHiL Intuitive Power Designer (IPD) GUI and stored in on-chip NVM. The CHL8326/8 provides extensive OVP, UVP, OCP and OTP fault protection and includes thermistor based Trademarks and registered trademarks are the property of the respective owners. PB0011 Rev. 0.05, June 10, 2010 IRTN7 PM_ADDR_GPO_C1 / PM_ADDRVID[0]2 ISEN6 SV_ADDR_GPO_D1 / VID[1]2 IRTN6 SMB_CLK ISEN5 SMB_DIO 24 IRTN5 SMB_ALERT# 23 ISEN4 ENABLE VR_HOT#1 / VRHOT_ICRIT#2 22 IRTN4 SV_DIO1 / SVDVID[2]2 21 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 42 ISEN7 RCSP 2 41 RCSP_L2 RCSM 3 40 RCSM_L2 VCC 4 39 VCC CFP1 / VFIXEN_PSI2 5 38 VSEN_L2 VSEN 6 37 VRTN_L2 VRTN 7 36 PWM8 RRES 8 35 PWM7 TSEN 9 34 PWM6 V18A 10 33 PWM5 VR_READY1 / PWRGD2 11 32 PWM4 VR_READY_L212 / PWROK 12 31 PWM3 GPO_B 13 30 PWM2 VINSEN 14 29 PWM1 CHL8328 56 Pin 8x8 QFN Top View 19 20 21 22 23 24 25 26 27 28 PM_ADDR_GPO_C1 / PM_ADDR_VID[0]2 TSEN2 VAR_GATE 18 SV_ADDR_GPO_D1 / VID[1]2 17 SMB_CLK Intel/MPoL mode AMD mode 2 16 SMB_DIO 1 15 SMB_ALERT# 57 GND ENABLE CHiL’s unique Adaptive Transient Algorithm (ATA), based on proprietary non-linear digital PWM algorithms, minimizes output bulk capacitors. In addition, a coupled inductor mode, with phases added/dropped in pairs, enables further improvement in transient response and form factor. 20 ISEN8 NVM storage saves pins and enables a small package size. The CHL8326/8 includes the CHiL Efficiency Shaping Technology to deliver exceptional efficiency at minimum cost across the entire load range. CHiL Variable Gate Drive optimizes the MOSFET gate drive voltage based on realtime load current. CHiL Dynamic Phase Control adds/drops phases based upon load current. The CHL8326/8 can be configured to enter 1-phase operation and active diode emulation mode automatically or by command. 19 ISEN3 DESCRIPTION 18 IRTN3 Pb-Free, RoHS, 7x7 48 pin & 8x8 56 pin QFN packages 17 VR_HOT#1 / VRHOT_ICRIT#2  16 SV_CLK1 / SVC_VID[3]2 +3.3V supply voltage; 0ºC to 85ºC ambient operation 15 ISEN2 Compatible with CHiL ATL and 3.3V tri-state Drivers  14 SV_DIO1 / SVDVID[2]2  13 SV_ALERT1 / VID[4]2 Non-Volatile Memory (NVM) for custom configuration 25 VAR_GATE IRTN2  26 PWM1 49 GND SV_CLK1 / SVC_VID[3]2 I2C/SMBus/PMBus system interface for telemetry of Temperature, Voltage, Current & Power for both loops GPO_B_PSI1 / VID[5]2  GPO_A1 / CBOUT2 Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP 30 PWM5 ISEN1  31 PWM6 IRTN1 Auto-Phase Detection with auto-compensation SV_ALERT1 / VID[4]2  32 VRTN_L2 CHL8326 48 Pin 7x7 QFN Top View IRTN8  47 1 PSI(MPoL)1 / VID[5]2  48 RCSP GPO_A1 / CBOUT2  ISEN6 CHiL Efficiency Shaping Features including Variable Gate Drive, Dynamic Phase Control IRTN6  ISEN5 Switching frequency from 200kHz to 1.2MHz per phase IRTN5 Overclocking & Gaming Mode with Vmax setting  ISEN4  IRTN4 Intel® VR12, AMD® SVI/PVI/G34 & Memory modes ISEN3 Phases are flexibly assigned between Loops 1 & 2  IRTN3  The CHL8326/8 also includes numerous features like register diagnostics for fast design cycles and platform differentiation, truly simplifying VRD design and enabling fastest time-to-market with its “set-and-forget” methodology. ISEN2 6-phase & 8-phase dual output PWM Controller IRTN2  ISEN1 temperature sensing with VRHOT signal. IRTN1 FEATURES Figure 1: CHL8326 & CHL8328 Packages APPLICATIONS  Intel® VR12 & AMD® SVI & PVI based systems  DDR Memory with Vtt tracking  Overclocked & Gaming platforms Page 1 of 2 One Highwood Drive, Tewksbury, MA 01876 Tel: +1(978)-640-0011 www.chilsemi.com © 2010 CHiL Semiconductor Corp. All rights reserved CHL8326/8 PRODUCT BRIEF DIGITAL MULTI-PHASE BUCK CONTROLLER RCSP Rseries RCS V_VGD CCS PWM1 Rseries RCSM Boot CHL8510 HiGate Vcc HVCC Switch LVCC PWM LoGate GND Mode V_CPU_L1 L O A D ISEN1 VCC VSEN VRTN RRES V_VGD V 12V V IRTN1 +3.3V 12V V RTh V 12V V TYPICAL APPLICATIONS BLOCK DIAGRAM PWM 2 Boot CHL8510 HiGate Vcc HVCC Switch LVCC PWM LoGate GND Mode ISEN2 IRTN2 TSEN RTh2 V_VGD V V18A 12V V CHL8326/8 PWM3 Boot CHL8510 HiGate Vcc HVCC Switch LVCC PWM LoGate GND Mode ISEN3 VR_RDY_L1 VR_RDY_L2 +12V Main IRTN3 RVIN_1 V_VGD RVIN_2 V VINSEN PWM4 TSEN21 Boot CHL8510 HiGate Vcc HVCC Switch LVCC PWM LoGate GND Mode ISEN4 IRTN4 RTh2 PWM5 ISEN5 V SV_ALERT# IRTN5 V SV_CLK SV_DIO V To/From CPU PWM6 Unused Phases ISEN6 VR_HOT# 3.3V IRTN6 PWM71 CFP GPO_A GPO_B1 PSI2 V V 12V SV_ADDR V_VGD V IRTN71 SMB_DIO SMB_CLK SMB_ALERT V I2C or SMBus ISEN71 V To/From System PM_ADDR PWM8 RCSP_L2 RCS V_CPU_L2 L O A D ISEN81 IRTN81 Rseries RTh 1 Boot CHL8510 HiGate Vcc HVCC Switch LVCC PWM LoGate GND Mode CCS Rseries 12V Notes 1 2 CHL8328 only MPoL mode only V RCSM_L2 Boot CHL8510 HiGate Vcc HVCC Switch LVCC PWM LoGate GND Mode VSEN_L2 VAR_GATE VRTN_L2 GND Only Intel/MPoL Mode pin names shown V_VGD Optional Variable Gate Drive Circuit ORDERING INFORMATION CHL832  -      T: Tape & Reel Package type R : QFN Operating Temperature C: Commercial Standard Range xx: Configuration file R : QFN Part 6: CHL8326 8: CHL8328 Package QFN QFN QFN QFN Tape & Reel Qty 3000 3000 3000 3000 Part Number 1 CHL8326-00CRT 2 CHL8326-xxCRT 1 CHL8328-00CRT 2 CHL8328-xxCRT Notes 1 For unprogrammed/default parts, use configuration file 00. Unprogrammed parts will not start up until programmed in order to insure a safe power up. 2 -xx indicates a customer specific configuration file. Page 2 of 2 PB0011 Rev. 0.05, June 10, 2010