CHL8328-01CRT

IR3536/38 CHL8326/28 Digital Multi-Phase Buck Controller FEATURES DESCRIPTION  6-phase & 8-phase dual output PWM Controller  Phases are flexibly assigned between Loops 1 & 2  Intel® VR12, AMD® 3.4MHz SVI/PVI & Memory modes  Overclocking & Gaming Mode with Vmax setting  Switching frequency from 200kHz to 1.2MHz per phase  IR Efficiency Shaping Features including Variable Gate Drive and Dynamic Phase Control  Programmable 1-phase or 2-phase for Light Loads and Active Diode Emulation for Very Light Loads  IR Adaptive Transient Algorithm (ATA) on both loops minimizes output bulk capacitors and system cost  Auto-Phase Detection with auto-compensation  Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP  I2C/SMBus/PMBus system interface for telemetry of Temperature, Voltage, Current & Power for both loops  Non-Volatile Memory (NVM) for custom configuration  Compatible with IR ATL and 3.3V Tri-state Drivers  +3.3V supply voltage; -20ºC to 85ºC ambient operation  Pb-Free, RoHS, 7x7 48-pin & 8x8 56-pin QFN, MSL2 package APPLICATIONS  Intel ® VR12 & AMD® SVI & PVI based systems  DDR Memory with Vtt tracking  Overclocked & Gaming platforms The IR3536/CHL8326 and IR3538/CHL8328 are dual-loop digital multi-phase buck controllers. The IR3536/CHL8326 drive up to 6 phases and the IR3538/CHL8328 drives up to 8 phases. The IR3536/CHL8326 and IR3538/CHL8328 are fully Intel® VR12 and AMD® SVI/PVI compliant on both loops and provide a Vtt tracking function for DDR memory. The IR3536/CHL8326 and IR3538/CHL8328 include the IR Efficiency Shaping Technology to deliver exceptional efficiency at minimum cost across the entire load range. IR Variable Gate Drive optimizes the MOSFET gate drive voltage based on real-time load current. IR Dynamic Phase Control adds/drops phases based upon load current. The IR3536/CHL8326 and IR3538/CHL8328 can be configured to enter 1-phase operation and active diode emulation mode automatically or by command. IR’s unique Adaptive Transient Algorithm (ATA), based on proprietary non-linear digital PWM algorithms, minimizes output bulk capacitors. The I2C/PMBus interface can communicate with up to 16 IR3536/CHL8326 and IR3538/CHL8328 based VR loops. Device configuration and fault parameters are easily defined using the IR Intuitive Power Designer (DPDC) GUI and stored in on-chip NVM. The IR3536/CHL8326 and IR3538/CHL8328 provides extensive OVP, UVP, OCP and OTP fault protection and includes thermistor based temperature sensing with VR_HOT signal. NVM storage saves pins and enables a small package size. The IR3536/CHL8326 and IR3538/CHL8328 also include numerous features like register diagnostics for fast design cycles and platform differentiation, truly simplifying VRD design and enabling fastest time-to-market with its “set-and-forget” methodology. ISEN6 51 50 49 48 47 46 45 44 43 42 ISEN7 41 RCSP_L2 40 RCSM_L2 VCC 4 39 VCC 33 VSEN_L2 CFP1 / VFIXEN_PSI2 5 38 VSEN_L2 32 VRTN_L2 VSEN 6 37 VRTN_L2 31 PWM6 VRTN 7 36 PWM8 RRES 8 35 PWM7 TSEN 9 34 PWM6 35 RCSM_L2 VCC 3 34 VCC CFP1 / VFIXEN_PSI2 4 VSEN 5 VRTN 6 RRES 7 TSEN 8 29 PWM4 V18A 9 28 PWM3 VR_READY1 / PWRGD2 10 27 PWM2 30 PWM5 CHL8328 56 Pin 8x8 QFN Top View V18A 10 33 PWM5 VR_READY1 / PWRGD2 11 32 PWM4 VR_READY_L212 12 31 PWM3 GPO_B 13 30 PWM2 29 PWM1 / PWROK 26 PWM1 49 GND 57 GND SV_CLK1 / SVC_VID[3]2 SV_DIO1 / SVD_VID[2]2 VR_HOT#1 / VRHOT_ICRIT#2 ENABLE SMB_ALERT# SMB_DIO SMB_CLK SV_ADDR_GPO_D1 / VID[1]2 PM_ADDR_GPO_C1 / PM_ADDR_VID[0]2 17 18 19 20 21 22 23 24 25 26 27 28 VAR_GATE PSI1 / VID[5]2 Intel/MPoL mode AMD mode 2 16 TSEN2 GPO_A1 / CBOUT2 June 21, 2013 | FINAL | V1.09 1 15 PM_ADDR_GPO_C1 / PM_ADDR_VID[0]2 24 SMB_CLK 23 SV_ADDR_GPO_D1 / VID[1]2 22 SMB_DIO 21 SMB_ALERT# 20 ENABLE 19 VR_HOT# / VRHOT_ICRIT#2 18 1 17 SV_DIO1 / SVD_VID[2]2 16 SV_CLK1 / SVC_VID[3]2 15 GPO_A1 / CBOUT2 14 14 PSI(MPoL)1 / VID[5]2 13 SV_ALERT1 / VID[4]2 VINSEN SV_ALERT1 / VID[4]2 25 VAR_GATE Figure 1: IR3536/CHL8326 Package Top View 1 52 3 2 12 53 RCSM RCSM 11 54 2 36 RCSP_L2 VINSEN 55 1 RCSP 1 VR_READY_L212 / PWROK 56 ISEN8 RCSP CHL8326 48 Pin 7x7 QFN Top View IRTN6 37 IRTN7 ISEN6 38 ISEN5 IRTN6 39 IRTN5 ISEN5 40 ISEN4 IRTN5 41 IRTN4 ISEN4 42 ISEN3 IRTN4 43 IRTN3 ISEN3 44 ISEN2 IRTN3 45 IRTN2 ISEN2 46 ISEN1 IRTN2 47 IRTN1 ISEN1 48 IRTN8 IRTN1 PIN DIAGRAM Figure 2: IR3538/CHL8328 Package Top View IR3536/38 CHL8326/28 Digital Multi-Phase Buck Controller ORDERING INFORMATION IR353M          Package Packing Qty Part Number QFN TR=3000 TY=2600 IR3536MTRPBF IR3536MTYPBF Default QFN TR=3000 TY=2600 IR3538MTRPBF IR3538MTYPBF Default QFN TR=3000 IR3536MxxyyTRP Customer Configuration QFN TR=3000 IR3538MxxyyTRP1 Customer Configuration P/PBF – Lead Free TR – Tape & Reel / TY - Tray yy – Configuration File ID xx – Customer ID Programming 1 Notes: Package Type (QFN) Part – 6: IR3536 8: IR3538 1. Customer Specific Configuration File, where xx = Customer ID and yy = Configuration File (Codes assigned by IR Marketing). Package Packing Qty QFN T=3000 TY=2600 Part Number CHL8326-00CRT CHL8326-00CRTY QFN T=3000 CHL8326-xxCRT1 QFN T=3000 TY=2600 CHL8328-00CRT CHL8328-00CRTY QFN T=3000 CHL8328-xxCRT1 CHL832 ―      T – Tape & Reel / TY - Tray R – Package Type (QFN) C – Operating Temperature, Commercial xx – Configuration File Notes: 1. “xx” indicates a customer specific configuration file. 48 RCSP 47 46 45 44 43 42 41 40 39 38 37 IRTN8 IRTN1 ISEN1 IRTN2 ISEN2 IRTN3 ISEN3 IRTN4 ISEN4 IRTN5 ISEN5 IRTN6 ISEN6 IRTN7 ISEN6 IRTN6 ISEN5 IRTN5 ISEN4 IRTN4 ISEN3 IRTN3 ISEN2 IRTN2 ISEN1 IRTN1 Part – 6: CHL8326 8: CHL8328 56 55 54 53 52 51 50 49 48 47 46 45 44 43 ISEN8 1 42 ISEN7 RCSP 2 41 RCSP_L2 RCSM 3 40 RCSM_L2 VCC 4 39 VCC CFP1 / VFIXEN_PSI2 5 38 VSEN_L2 37 VRTN_L2 36 PWM8 35 PWM7 36 RCSP_L2 1 35 RCSM_L2 RCSM 2 VCC 3 34 VCC CFP1 / VFIXEN_PSI2 4 33 VSEN_L2 VSEN 6 VSEN 5 32 VRTN_L2 VRTN 7 VRTN 6 31 PWM6 RRES 8 RRES 7 30 PWM5 TSEN 9 34 PWM6 TSEN 8 V18A 10 33 PWM5 VR_READY1 / PWRGD2 11 32 PWM4 VR_READY_L221 / PWROK 12 31 PWM3 GPO_B 13 30 PWM2 VINSEN 14 29 PWM1 29 PWM4 28 PWM3 9 57 GND 26 PWM1 49 GND 21 22 23 24 PSI1 / VID[5]2 SV_ALERT1 / VID[4]2 SV_CLK1 / SVC_VID[3]2 SV_DIO1 / SVD_VID[2]2 VR_HOT#1 / VRHOT_ICRIT#2 ENABLE SMB_ALERT# SMB_DIO SMB_CLK SV_ADDR_GPO_D1 / VID[1]2 PM_ADDR_GPO_C1 / PM_ADDR_VID[0]2 Figure 3: IR3536/CHL8326 Package Top View, Enlarged 2 June 21, 2013 | FINAL | V1.09 1 Intel/MPoL mode AMD mode 2 23 24 25 26 27 28 VAR_GATE 20 22 TSEN2 19 21 PM_ADDR_GPO_C1 / PM_ADDR_VID[0]2 18 20 SV_ADDR_GPO_D1 / VID[1]2 17 19 SMB_CLK 16 18 SMB_DIO 15 17 SMB_ALERT# 14 16 ENABLE 13 15 VR_HOT#1 / VRHOT_ICRIT#2 25 VAR_GATE 12 GPO_A1 / CBOUT2 VINSEN SV_DIO1 / SVD_VID[2]2 11 SV_CLK1 / SVC_VID[3]2 VR_READY_L221 / PWROK 27 PWM2 SV_ALERT1 / VID[4]2 10 GPO_A1 / CBOUT2 VR_READY1 / PWRGD2 PSI(MPoL)1 / VID[5]2 V18A CHL8326 48 Pin 7x7 QFN Top View CHL8328 56 Pin 8x8 QFN Top View Figure 4: IR3538/CHL8328 Package Top View, Enlarged Digital Multi-Phase Buck Controller IR3536/38 CHL8326/28 FUNCTIONAL BLOCK DIAGRAM V18A RCSP_L2 VCC VID_2 RSCM_L2 1.8V AFE_2 LDO VSEN_L2 VRTN_L2 ITOT_2 RCSP Vout1_Error Voltage ADC PWM1 RSCM Vout2_Error AFE_1 PWM2 VSEN VID_1 VRTN PWM3 PWM4 ISEN1 Mode Control IRTN1 . . . ISENx . . . IP1 . . . PWM Generator PWM5 Control and Monitoring IPx IRTNx IR3536/ IR3538/ CHL8326 CHL8326 CHL8328 3 4 4 5 6 8 Σ Phase_ Period_1 Phase_ Period_2 ITOT_1 PWM7 x y z PWM8 Iout ISENy IRTNy . . . ISENz . . . IRTNz Vin IPy . . . IPz PWM6 ITOT_2 Only for CHL8328 IR3538/CHL8328 VAR_GATE Vout Temp Σ Current ADC Fault Bus System Clock IP1 . . . IP6 Only for IR3538/ CHL8328 System Clock IP7 . . . IP8 ADC Clocks MUX Clocks 1 Intel/MPoL mode AMD mode 2 Phase_Period_1 TSEN2 Phase_Period_2 VID_1 TSEN VID_2 VINSEN Monitor ADC V3_3 EN SV_CLK1/SVC_VID[3]2 SV_DIO1/SVD_VID[2]2 SV_ALERT#1/VID[4]2 Reference, Oscillator, State Control, Interfaces, Registers and NVM Iout Vin Temp Fault Bus VR_HOT#1/ VRHOT_ICRIT#2 SMB_DIO SMB_CLK SMB_ALERT VR_READY1/PWRGD2 VR_READY_L21/ PWROK2 GPO_A Only for GPO_B CHL8328 IR3538/CHL8328 PSI1/VID[5]2 SV_ADDR1/VID[1]2 PM_ADDR1/ PM_ADDR_VID[0]2 CFP1/VFIXEN_PSI2 RRES Figure 5: IR3536/CHL8326 and CHL8328 Functional Block Diagram 3 June 21, 2013 | FINAL | V1.09