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CY15B108QN-20LPXC

CY15B108QN-20LPXC

  • 厂商:

    EUPEC(英飞凌)

  • 封装:

    UQFN8

  • 描述:

    CY15B108QN-20LPXC

  • 数据手册
  • 价格&库存
CY15B108QN-20LPXC 数据手册
CY15B108QN, CY15V108QN 8Mb EXCELO N™ LP Fe rroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Features • 8-Mbit ferroelectric random access memory (F-RAM) logically organized as 1024K × 8 - Virtually unlimited endurance 1000 trillion (1015) read/writes - 151-year data retention (see “Data retention and endurance” on page 23) - Infineon instant non-volatile write technology - Advanced high-reliability ferroelectric process • Fast SPI (FSPI) - Up to 50 MHz frequency - Supports SPI mode 0 (0, 0) and mode 3 (1, 1) • Sophisticated write protection scheme - Hardware protection using the Write Protect (WP) pin - Software protection using Write Disable (WRDI) instruction - Software block protection for 1/4, 1/2, or entire array • Device ID and serial number - Manufacturer ID and Product ID - Unique Device ID - Serial Number • Dedicated 256-byte special sector F-RAM - Dedicated special sector write and read - Stored content can survive up to three standard reflow soldering cycles • Low-power consumption - 2.8 mA (typ) active current at 50 MHz - 7.5 µA (typ) standby current - 0.9 µA (typ) Deep Power Down mode current - 0.1 µA (typ) Hibernate mode current • Low-voltage operation - CY15V108QN: VDD = 1.71 V to 1.89 V - CY15B108QN: VDD = 1.8 V to 3.6 V • Operating temperature - Industrial temperature (I): -40°C to +85°C • Package - 24-ball fine pitch ball grid array (24-ball FBGA) • Restriction of hazardous substances (RoHS) compliant Datasheet www.infineon.com Please read the Important Notice and Warnings at the end of this document page 1 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional description Functio nal de sc ript ion The EXCELON™ LP CY15X108QN is a low power, 8-Mbit non-volatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is non-volatile and performs reads and writes similar to a RAM. It provides reliable data retention for 151 years while eliminating the complexities, overhead, and system-level reliability problems caused by serial flash, EEPROM, and other non-volatile memories. Unlike serial flash and EEPROM, the CY15X108QN performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte is successfully transferred to the device. The next bus cycle can commence without the need for data polling. In addition, the product offers substantial write endurance compared to other non-volatile memories. The CY15X108QN is capable of supporting 1015 read/write cycles, or 1000 million times more write cycles than EEPROM. These capabilities make the CY15X108QN ideal for non-volatile memory applications, requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of serial flash or EEPROM can cause data loss. The CY15X108QN provides substantial benefits to users of serial EEPROM or flash as a hardware drop-in replacement. The CY15X108QN uses the high-speed SPI bus, which enhances the high-speed write capability of F-RAM technology. The device incorporates a read-only Device ID and Unique ID features, which allow the host to determine the manufacturer, product density, product revision, and unique ID for each part. The device also provides a writable, 8-byte serial number registers, which can be used to identify a specific board or a system. For a complete list of related resources, click here. Logi c blo ck diagram WP 256-Byte Special Sector F-RAM CS SCK SI Instruction Decoder Control Logic Write Protect F-RAM Control Data I/O Register 1024K x 8 F-RAM Array SO Non-volatile Status Register Device ID and Serial Number Registers Datasheet 2 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Table of contents Table of contents Features ...........................................................................................................................................1 Functional description .......................................................................................................................2 Logic block diagram ..........................................................................................................................2 Table of contents ...............................................................................................................................3 1 Pinout............................................................................................................................................4 2 Pin definition..................................................................................................................................5 3 Functional overview .......................................................................................................................6 3.1 Memory architecture ..............................................................................................................................................6 3.2 SPI bus .....................................................................................................................................................................6 3.3 SPI overview............................................................................................................................................................6 3.4 Terms used in SPI protocol ....................................................................................................................................7 3.4.1 SPI master ............................................................................................................................................................7 3.4.2 SPI slave ...............................................................................................................................................................7 3.4.3 Chip Select (CS)....................................................................................................................................................7 3.4.4 Serial Clock (SCK).................................................................................................................................................7 3.4.5 Data transmission (SI/SO) ...................................................................................................................................7 3.4.6 Most significant bit (MSb) ....................................................................................................................................8 3.4.7 Serial opcode .......................................................................................................................................................8 3.4.8 Invalid opcode......................................................................................................................................................8 3.4.9 Status Register .....................................................................................................................................................8 3.5 SPI modes................................................................................................................................................................9 3.6 Power-up to first access .........................................................................................................................................9 4 Functional description ..................................................................................................................10 4.1 Command structure..............................................................................................................................................10 4.1.1 Write Enable Control commands ......................................................................................................................11 4.1.2 Register Access commands ...............................................................................................................................12 4.1.3 Memory operation .............................................................................................................................................14 4.1.4 Memory Write Operation commands................................................................................................................14 4.1.5 Memory Read commands..................................................................................................................................15 4.1.6 Special Sector Memory Access commands ......................................................................................................16 4.1.7 Identification and Serial Number commands ..................................................................................................17 4.1.8 Low Power Mode commands ............................................................................................................................19 5 Maximum ratings ..........................................................................................................................21 6 Operating range ...........................................................................................................................21 7 DC electrical characteristics...........................................................................................................22 8 Data retention and endurance .......................................................................................................23 9 Capacitance .................................................................................................................................23 10 Thermal resistance......................................................................................................................23 11 AC test conditions .......................................................................................................................24 12 AC switching characteristics ........................................................................................................24 13 Power cycle timing......................................................................................................................26 14 Ordering information ..................................................................................................................27 14.1 Ordering code definitions...................................................................................................................................27 15 Package diagram ........................................................................................................................28 16 Acronyms ...................................................................................................................................29 17 Document conventions................................................................................................................30 17.1 Units of measure .................................................................................................................................................30 Revision history ..............................................................................................................................31 Datasheet 3 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Pinout 1 Pinout 1 A Figure 1 4 5 2 3 NC NC NC NC B NC SCK VSS VDD NC C NC CS NC WP NC D NC SO SI DNU NC E NC NC NC NC NC 24-ball FBGA pinout Note 1. SI may be connected to SO for a single pin data interface. Datasheet 4 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Pin definition 2 Pin definition Pin name I/O type Description Input Chip Select. This active LOW input activates the device. When HIGH, the device enters low-power standby mode, ignores other inputs, and the output is tristated. When LOW, the device internally activates the SCK signal. A falling edge on CS must occur before every opcode. SCK Input Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge of the serial clock. The clock frequency may be any value between 0 and 50 MHz and may be interrupted at any time due to its synchronous behavior. SI[1] Input Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a valid logic level to meet the power (IDD) specifications. SO[1] Output Serial Output. This is the data output pin. It is driven during a read and remains tristated at all other times. Data transitions are driven on the falling edge of the serial clock SCK. WP Input Write Protect. This Active LOW pin prevents write operation to the Status Register when WPEN bit in the Status Register is set to ‘1’. This is critical because other write protection features are controlled through the Status Register. A complete explanation of write protection is provided in “Status Register” on page 8 and “Write protection” on page 13. This pin must be tied to VDD if not used. DNU Do Not Use Do Not Use. Either leave this pin floating (not connected on the board) or tie to VDD. CS VSS Power Supply Ground for the device. Must be connected to the ground of the system. VDD Power Supply Power supply input to the device. NC Datasheet NC No Connect. Die pads are not connected to the package pin. 5 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional overview 3 Functional overview The CY15X108QN is a serial F-RAM memory. The memory array is logically organized as 1,048,576 × 8 bits and is accessed using an industry-standard serial peripheral interface (SPI) bus. The functional operation of the F-RAM is similar to serial flash and serial EEPROMs. The major difference between the CY15X108QN and a serial flash or EEPROM with the same pinout is the F-RAM’s superior write performance, high endurance, and low power consumption. 3.1 Memory architecture When accessing CY15X108QN, the user addresses 1,024K locations of eight data bits each. These eight data bits are shifted in or out serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an opcode, and a three-byte address. The upper four bits of the address range are ‘don’t care’ values. The complete address of 20 bits specifies each byte address uniquely. Most functions of the CY15X108QN are either controlled by the SPI interface or handled by on-board circuitry. The access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike a serial flash or EEPROM, it is not necessary to poll the device for a ready condition because writes occur at bus speed. By the time a new bus transaction can be shifted into the device, a write operation is complete. This is explained in more detail in the interface section. 3.2 SPI bus The CY15X108QN is an SPI slave device and operates at speeds of up to 50 MHz. This high-speed serial bus provides high-performance serial communication to an SPI master. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is simple to emulate the port using ordinary port pins for microcontrollers that do not have this feature. The CY15X108QN operates in SPI Modes 0 and 3. 3.3 SPI overview The SPI is a four-pin interface with Chip Select (CS), Serial Input (SI), Serial Output (SO), and Serial Clock (SCK) pins. The SPI is a synchronous serial interface, which uses clock and data pins for memory access and supports multiple devices on the data bus. A device on the SPI bus is activated using the CS pin. The relationship between chip select, clock, and data is dictated by the SPI mode. This device supports SPI modes 0 and 3. In both of these modes, data is clocked into the F-RAM on the rising edge of SCK starting from the first rising edge after CS goes active. The SPI protocol is controlled by opcodes. These opcodes specify the commands from the bus master to the slave device. After CS is activated, the first byte transferred from the bus master is the opcode. Following the opcode, any addresses and data are then transferred. The CS must go inactive after an operation is complete and before a new opcode can be issued. Datasheet 6 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional overview 3.4 Terms used in SPI protocol The commonly used terms in the SPI protocol are as follows. 3.4.1 SPI master The SPI master device controls the operations on the SPI bus. An SPI bus may have only one master with one or more slave devices. All the slaves share the same SPI bus lines and the master may select any of the slave devices using the CS pin. All of the operations must be initiated by the master activating a slave device by pulling the CS pin of the slave LOW. The master also generates the SCK and all the data transmission on SI and SO lines are synchronized with this clock. 3.4.2 SPI slave The SPI slave device is activated by the master through the Chip Select line. A slave device gets the SCK as an input from the SPI master and all the communication is synchronized with this clock. An SPI slave never initiates a communication on the SPI bus and acts only on the instruction from the master. The CY15X108QN operates as an SPI slave and may share the SPI bus with other SPI slave devices. 3.4.3 Chip Select (CS) To select any slave device, the master needs to pull down the corresponding CS pin. Any instruction can be issued to a slave device only while the CS pin is LOW. When the device is not selected, data through the SI pin is ignored and the serial output pin (SO) remains in a high-impedance state. Note A new instruction must begin with the falling edge of CS. Therefore, only one opcode can be issued for each active Chip Select cycle. 3.4.4 Serial Clock (SCK) The serial clock is generated by the SPI master and the communication is synchronized with this clock after CS goes LOW. The CY15X108QN supports SPI modes 0 and 3 for data communication. In both of these modes, the inputs are latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the first rising edge of SCK signifies the arrival of the first Most Significant Bit (MSb) of an SPI instruction on the SI pin. Further, all data inputs and outputs are synchronized with SCK. 3.4.5 Data transmission (SI/SO) The SPI data bus consists of two lines, SI and SO, for serial data communication. SI is also referred to as Master Out Slave In (MOSI) and SO is referred to as Master In Slave Out (MISO). The master issues instructions to the slave through the SI pin, while the slave responds through the SO pin. Multiple slave devices may share the SI and SO lines as described earlier. The CY15X108QN has two separate pins for SI and SO, which can be connected with the master as shown in Figure 2. For a microcontroller that has no dedicated SPI bus, a general-purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off (HIGH) the WP pin. Figure 3 shows such a configuration, which uses only three pins. Datasheet 7 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional overview SCK MOSI MISO SCK SPI Hostcontroller or SPI Master SI SO SCK CY15x108QN CS SI SO CY15x108QN WP CS WP CS1 WP1 CS2 WP2 Figure 2 System configuration with SPI port P1.0 P1.1 SCK SPI Hostcontroller or SPI Master SI SO CY15x108QN CS WP P1.2 Figure 3 System configuration without SPI port 3.4.6 Most significant bit (MSb) The SPI protocol requires that the first bit to be transmitted is the MSb. This is valid for both address and data transmission. The 8-Mbit serial F-RAM requires a 3-byte address for any read or write operation. Because the address is only 20 bits, the first four bits, which are fed in are ignored by the device. Although these four bits are ‘don’t care’, Infineon recommends that these bits be set to 0s to enable seamless transition to higher memory densities. 3.4.7 Serial opcode After the slave device is selected with CS going LOW, the first byte received is treated as the opcode for the intended operation. CY15X108QN uses the standard opcodes for memory accesses. 3.4.8 Invalid opcode If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the SI pin until the next falling edge of CS, and the SO pin remains tristated. 3.4.9 Status Register CY15X108QN has an 8-bit Status Register. The bits in the Status Register are used to configure the device. These bits are described in Table 3. Datasheet 8 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional overview 3.5 SPI modes CY15X108QN may be driven by a microcontroller with its SPI peripheral running in either of the following two modes: • SPI Mode 0 (CPOL = 0, CPHA = 0) • SPI Mode 3 (CPOL = 1, CPHA = 1) For both these modes, the input data is latched in on the rising edge of SCK starting from the first rising edge after CS goes active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles is considered. The output data is available on the falling edge of SCK. The two SPI modes are shown in Figure 4 and Figure 5. The status of the clock when the bus master is not transferring data is: • SCK remains at 0 for Mode 0 • SCK remains at 1 for Mode 3 The device detects the SPI mode from the status of the SCK pin when the device is selected by bringing the CS pin LOW. If the SCK pin is LOW when the device is selected, SPI Mode 0 is assumed and if the SCK pin is HIGH, it works in SPI Mode 3. CS 0 1 2 3 4 5 6 7 SCK SI Figure 4 7 6 5 4 3 2 1 0 SPI Mode 0 CS 0 1 2 3 4 5 6 7 SCK SI 7 6 Figure 5 SPI Mode 3 3.6 Power-up to first access 5 4 3 2 1 0 The CY15X108QN is not accessible for a tPU time after power-up. Users must comply with the timing parameter, tPU, which is the minimum time from VDD (min) to the first CS LOW. Refer to “Power cycle timing” on page 26 for details. Datasheet 9 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional description 4 Functional description 4.1 Command structure There are 15 commands, called opcodes, that can be issued by the bus master to the CY15X108QN (see Table 1). These opcodes control the functions performed by the memory. Table 1 Opcode commands Name Opcode Description Hex Binary Max. frequency (MHz) Write enable control WREN Set write enable latch 06h 0000 0110b 50 WRDI Reset write enable latch 04h 0000 0100b 50 RDSR Read Status Register 05h 0000 0101b 50 WRSR Write Status Register 01h 0000 0001b 50 Write memory data 02h 0000 0010b 50 READ Read memory data 03h 0000 0011b 35 FAST_READ Fast read memory data 0Bh 0000 1011b 50 Register access Memory write WRITE Memory read Special sector memory access SSWR Special Sector Write 42h 0100 0010b 50 SSRD Special Sector Read 4Bh 0100 1011b 35 Identification and serial number RDID Read device ID 9Fh 1001 1111b 50 RUID Read Unique ID 4Ch 0100 1100b 50 WRSN Write Serial Number C2h 1100 0010b 50 RDSN Read Serial Number C3h 11000 011b 50 DPD Enter Deep Power-Down BAh 1011 1010b 50 HBN Enter Hibernate mode B9h 1011 1001b 50 Reserved Reserved Low power modes Datasheet Unused opcodes are reserved for future use. 10 of 32 – 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional description 4.1.1 Write Enable Control commands 4.1.1.1 Set Write Enable Latch (WREN, 06h) The CY15X108QN will power up with writes disabled. The WREN command must be issued before any write operation. Sending the WREN opcode allows the user to issue subsequent opcodes for write operations. These include writing to the Status Register (WRSR), the memory (WRITE), Special Sector (SSWR), and Write Serial Number (WRSN). Sending the WREN opcode causes the internal Write Enable Latch to be set. A flag bit in the Status Register, called WEL, indicates the state of the latch. WEL = ‘1’ indicates that writes are permitted. Attempting to write the WEL bit in the Status Register has no effect on the state of this bit - only the WREN opcode can set this bit. The WEL bit will be automatically cleared on the rising edge of CS following a WRDI, a WRSR, a WRITE, a SSWR, or a WRSN operation. This prevents further writes to the Status Register or the F-RAM array without another WREN command. Figure 6 illustrates the WREN command bus configuration. CS 0 Mode 3 1 2 3 4 5 6 7 SCK Mode 0 SI 0 0 0 0 0 1 1 0 Hi-Z SI Opcode (06h) Figure 6 WREN bus configuration 4.1.1.2 Reset Write Enable Latch (WRDI, 04h) The WRDI command disables all write activity by clearing the Write Enable Latch. Verify that the writes are disabled by reading the WEL bit in the Status Register and verify that WEL is equal to ‘0’. Figure 7 illustrates the WRDI command bus configuration. CS 0 1 2 3 4 5 6 7 SCK SI 0 SI 0 0 0 0 1 0 0 Hi-Z Opcode (04h) Figure 7 Datasheet WRDI bus configuration 11 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional description 4.1.2 Register Access commands 4.1.2.1 Status Register and Write Protection The write protection features of the CY15X108QN are multi-tiered and are enabled through the Status Register. The Status Register is organized as follows (The default value shipped from the factory for WEL, BP0, BP1, bits 4–5, and WPEN is ‘0’, and for bit 6 is ‘1’). Table 2 Bit 7 WPEN (0) Table 3 Bit Bit 0 Status Register Bit 6 X (1) Bit 5 X (0) Bit 4 X (0) Bit 3 BP1 (0) Bit 2 BP0 (0) Bit 1 WEL (0) Bit 0 X (0) Status Register bit definition Definition Description Don’t care This bit is non-writable and always returns ‘0’ upon read. Bit 1 (WEL) Write enable WEL indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up. WEL = ‘1’ --> Write enabled WEL = ‘0’ --> Write disabled Bit 2 (BP0) Block protect bit ‘0’ Used for block protection. For details, see Table 4. Bit 3 (BP1) Block protect bit ‘1’ Used for block protection. For details, see Table 4. Bit 4–5 Don’t care These bits are non-writable and always return ‘0’ upon read. Bit 6 Don’t care This bit is non-writable and always returns ‘1’ upon read. Bit 7 (WPEN) Write protect enable bit Used to enable the function of Write Protect Pin (WP) (see Table 5). Bits 0 and 4–5 are fixed at ‘0’ and bit 6 is fixed at ‘1’; none of these bits can be modified. Note that bit 0 (“Ready or Write in progress” bit in serial flash and EEPROM) is unnecessary, as the F-RAM writes in real-time and is never busy, so it reads out as a '0'. An exception to this is when the device is waking up either from “Deep Power-down Mode (DPD, BAh)” on page 19 or “Hibernate Mode (HBN, B9h)” on page 19. The BP1 and BP0 control the software write-protection features and are non-volatile bits. The WEL flag indicates the state of the Write Enable Latch. Attempting to directly write the WEL bit in the Status Register has no effect on its state. This bit is internally set and cleared via the WREN and WRDI commands, respectively. BP1 and BP0 are memory block write protection bits. They specify portions of memory that are write-protected as shown in Table 4. Table 4 BP1 0 0 1 1 Block memory write protection BP0 0 1 0 1 Protected address range None 0x0C0000h to 0x0FFFFF (upper 1/4) 0x080000h to 0x0FFFFF (upper 1/2) 0x000000h to 0x0FFFFFh (all) The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. The remaining write protection features protect inadvertent changes to the block protect bits. The write protect enable bit (WPEN) in the Status Register controls the effect of the hardware write protect (WP) pin. Refer to Figure 23 for the WP pin timing diagram. When the WPEN bit is set to ‘0’, the status of the WP pin is ignored. When the WPEN bit is set to ‘1’, a LOW on the WP pin inhibits a write to the Status Register. Thus the Status Register is write-protected only when WPEN = ‘1’ and WP = ‘0’. Table 5 summarizes the write protection conditions. Datasheet 12 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional description Table 5 Write protection WEL WPEN WP Protected blocks Unprotected blocks Status Register 0 X X Protected Protected Protected 1 0 X Protected Unprotected Unprotected 1 1 0 Protected Unprotected Protected 1 1 1 Protected Unprotected Unprotected 4.1.2.2 Read Status Register (RDSR, 05h) The RDSR command allows the bus master to verify the contents of the Status Register. Reading the Status Register provides information about the current state of the write-protection features. Following the RDSR opcode, the CY15X108QN will return one byte with the contents of the Status Register. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 D3 D2 D1 7 SCK 0 SI 0 0 0 0 1 0 Hi-Z 1 Hi-Z SO D7 D6 D5 D4 D0 MSb LSb Opcode (05h) Read Data Figure 8 RDSR bus configuration 4.1.2.3 Write Status Register (WRSR, 01h) The WRSR command allows the SPI bus master to write into the Status Register and change the write protect configuration by setting the WPEN, BP0, and BP1 bits as required. Before issuing a WRSR command, the WP pin must be HIGH or inactive. Note that on the CY15X108QN, WP only prevents writing to the Status Register, not the memory array. Before sending the WRSR command, the user must send a WREN command to enable writes. Executing a WRSR command is a write operation and therefore, clears the Write Enable Latch. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 D7 D6 D5 D4 D3 D2 D1 D0 SCK SI 0 0 0 0 0 0 0 1 MSb SO Hi-Z Opcode (01h) Figure 9 Datasheet LSb Write Data WRSR bus configuration (WREN not shown) 13 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional description 4.1.3 Memory operation The SPI interface, which is capable of a high clock frequency, highlights the fast write capability of the F-RAM technology. Unlike serial flash and EEPROMs, the CY15X108QN can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. 4.1.4 Memory Write Operation commands 4.1.4.1 Write operation (WRITE, 02h) All writes to the memory begin with a WREN opcode with CS being asserted and deasserted. The next opcode is WRITE. The WRITE opcode is followed by a three-byte address containing the 20-bit address (A19–A0) of the first data byte to be written into the memory. The upper four bits of the three-byte address are ignored. Subsequent bytes are data bytes, which are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks and keeps CS LOW. If the last address of FFFFFh is reached, the internal address counter will roll over to 00000h. Every data byte to be written is transmitted on SI in 8-clock cycles with MSb first and the LSb last. The rising edge of CS terminates a write operation. The CY15X108QN write operation is shown in Figure 10. Notes • When a burst write reaches a protected block address, the automatic address increment stops and all the subsequent data bytes received for write will be ignored by the device. EEPROMs use page buffers to increase their write throughput. This compensates for the technology’s inherently slow write operations. F-RAM memories do not have page buffers because each byte is written to the F-RAM array immediately after it is clocked in (after the eighth clock). This allows any number of bytes to be written without page buffer delays. • If power is lost in the middle of the write operation, only the last completed byte will be written. CS 0 1 2 3 4 5 6 7 0 1 2 3 A22 A21 A20 4 20 21 22 23 0 1 2 3 4 5 6 D7 D6 MSb D5 D4 D3 D2 D1 7 SCK SI SO 0 0 0 0 0 0 Opcode (02h) Figure 10 Datasheet 1 0 A23 A3 Hi-Z A2 A1 A0 D0 LSb Hi-Z Address Write Data Memory write (WREN not shown) operation 14 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional description 4.1.5 Memory Read commands 4.1.5.1 Read Operation (READ, 03h) After the falling edge of CS, the bus master can issue a READ opcode. Following the READ command is a three-byte address containing the 20-bit address (A19–A0) of the first byte of the read operation. The upper four bits of the address are ignored. After the opcode and address are issued, the device drives out the read data on the next eight clocks. The SI input is ignored during read data bytes. Subsequent bytes are data bytes, which are read out sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks and CS is LOW. If the last address of FFFFFh is reached, the internal address counter will roll over to 00000h. Every read data byte on SO is driven in 8-clock cycles with MSb first and the LSb last. The rising edge of CS terminates a read operation and tristates the SO pin. The CY15X108QN read operation is shown in Figure 11. CS 0 1 2 3 4 5 6 7 0 1 2 3 A22 A21 A20 4 20 21 22 23 0 1 2 3 4 5 6 D3 D2 D1 7 SCK 0 SI 0 0 0 0 0 1 1 A23 A3 A2 A1 Hi-Z A0 Hi-Z SO D7 D6 D5 D4 MSb Opcode (03h) D0 LSb Address Read Data Figure 11 Memory read operation 4.1.5.2 Fast Read Operation (FAST_READ, 0Bh) The CY15X108QN supports a FAST_READ opcode (0Bh) that is provided for opcode compatibility with serial flash devices. The FAST_READ opcode is followed by a three-byte address containing the 20-bit address (A19–A0) of the first byte of the read operation and then a dummy byte. The dummy byte inserts a read latency of 8-clock cycle. The fast read operation is otherwise the same as an ordinary read operation except that it requires an additional dummy byte. After receiving the opcode, address, and a dummy byte, the CY15X108QN starts driving its SO line with data bytes, with MSb first, and continues transmitting as long as the device is selected and the clock is available. In case of bulk read, the internal address counter is incremented automatically, and after the last address FFFFFh is reached, the internal address counter rolls over to 00000h. When the device is driving data on its SO line, any transition on its SI line is ignored. The rising edge of CS terminates a fast read operation and tristates the SO pin. The CY15X108QN Fast Read operation is shown in Figure 12. Note The dummy byte can be any 8-bit value but Axh (8’b1010xxxx). The lower 4 bits of Axh are don’t care bits. Hence, Axh essentially represents 16 different 8-bit values which shouldn’t be transmitted as the dummy byte. 00h is typically used as the dummy byte in most use cases. CS 0 1 2 3 4 5 6 7 0 1 2 3 A22 A21 A20 4 20 21 22 23 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 D3 D2 D1 7 SCK SI SO 0 0 0 0 1 0 Hi-Z 1 1 A23 A3 A2 A1 MSb A0 x x x x x x x Hi-Z x LSb D7 D6 D5 D4 MSb Opcode (0Bh) Figure 12 Datasheet Address Dummy Byte D0 LSb Read Data Fast read operation 15 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional description 4.1.6 Special Sector Memory Access commands 4.1.6.1 Special Sector Write (SSWR, 42h) All writes to the 256-byte special begin with a WREN opcode with CS being asserted and deasserted. The next opcode is SSWR. The SSWR opcode is followed by a three-byte address containing the 8-bit sector address (A7– A0) of the first data byte to be written into the special sector memory. The upper 16 bits of the three-byte address are ignored. Subsequent bytes are data bytes, which are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks and keeps CS LOW. Once the internal address counter auto increments to XXXFFh, CS should toggle HIGH to terminate the ongoing SSWR operation. Every data byte to be written is transmitted on SI in 8-clock cycles with MSb first and the LSb last. The rising edge of CS terminates a write operation. The CY15X108QN special sector write operation is shown in Figure 13. Notes • If power is lost in the middle of the write operation, only the last completed byte will be written. • The special sector F-RAM memory guarantees to retain data integrity up to three cycles of standard reflow soldering. CS 0 1 2 3 4 5 6 7 0 1 2 3 A23 A22 A21 A20 4 20 21 22 23 0 1 2 3 4 5 6 D7 D6 D5 D4 D3 D2 D1 7 SCK 0 SI 1 0 0 0 0 1 0 A3 A2 A1 A0 MSb Hi-Z SO D0 LSb Hi-Z Opcode (42h) Address Write Data Figure 13 Special sector write (WREN not shown) operation 4.1.6.2 Special Sector Read (SSRD, 4Bh) After the falling edge of CS, the bus master can issue an SSRD opcode. Following the SSRD command is a three-byte address containing the 8-bit address (A7–A0) of the first byte of the special sector read operation. The upper 16 bits of the address are ignored. After the opcode and address are issued, the device drives out the read data on the next eight clocks. The SI input is ignored during read data bytes. Subsequent bytes are data bytes, which are read out sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks and CS is LOW. Once the internal address counter auto increments to XXXFFh, CS should toggle HIGH to terminate the ongoing SSRD operation. Every read data byte on SO is driven in 8-clock cycles with MSb first and the LSb last. The rising edge of CS terminates a special sector read operation and tristates the SO pin. The CY15X108QN special sector read operation is shown in Figure 14. Note The special sector F-RAM memory guarantees to retain data integrity up to three cycles of standard reflow soldering. CS 0 1 2 3 4 5 6 7 0 1 2 3 A22 A21 A20 4 20 21 22 23 0 1 2 3 4 5 6 D3 D2 D1 7 SCK SI SO 0 1 0 0 1 0 1 1 A23 A3 Hi-Z A2 A1 Hi-Z A0 D7 D6 D5 D4 MSb Opcode (4Bh) Figure 14 Datasheet Address D0 LSb Read Data Special sector read operation 16 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional description 4.1.7 Identification and Serial Number commands 4.1.7.1 Read Device ID (RDID, 9Fh) The CY15X108QN device can be interrogated for its manufacturer, product identification, and die revision. The RDID opcode 9Fh allows the user to read the 9-byte manufacturer ID and product ID, both of which are read-only bytes. The JEDEC-assigned manufacturer ID places the Ramtron identifier in bank 7; therefore, there are six bytes of the continuation code 7Fh followed by the single byte C2h. There are two bytes of product ID, which includes a family code, a density code, a sub code, and the product revision code. Table 6 shows 9-Byte Device ID field description. Refer to “Ordering information” on page 27 for 9-Byte device ID of an individual part. The CY15X108QN read device ID operation is shown in Figure 15. Note The least significant data byte (Byte 0) shifts out first and the most significant data byte (Byte 8) shifts out last. Table 6 9-byte device ID Device ID field description Manufacturer ID [71:16] Family [15:13] Density [12:9] Inrush [8] Sub type [7:5] Revision [4:3] Voltage [2] Frequency [1:0] 56-bit 3-bit 4-bit 1-bit 3-bit 2-bit 1-bit 2-bit Refer to “Ordering information” on page 27 for 9-Byte device ID of an individual part. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 60 61 62 63 64 65 66 67 68 69 70 71 SCK SI 1 0 0 1 1 1 1 MSb Hi-Z SO Hi-Z 1 D7 LSb D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 Byte 0 D1 D0 Byte 8 Opcode (9Fh) 9-Byte Device ID Figure 15 Read Device ID 4.1.7.2 Read Unique ID (RUID, 4Ch) The CY15X102QN device can be interrogated for unique ID which is a factory programmed, 64-bit number unique to each device. The RUID opcode, 4Ch allows to read the 8-byte, read only unique ID. The CY15X102QN read unique ID operation is shown in Figure 16. Notes • The least significant data byte (Byte 0) shifts out first and the most significant data byte (Byte 7) shifts out last. • The unique ID registers are guaranteed to retain data integrity of up to three cycles of the standard reflow soldering. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 52 53 54 55 56 57 58 59 60 61 62 63 SCK SI SO 0 1 0 0 1 1 Hi-Z 0 Hi-Z 0 MSb D7 LSb D6 D5 D4 D3 D2 D1 D0 D7 D6 Byte 0 Opcode (4Ch) Figure 16 Datasheet D5 D4 D3 D2 D1 D0 Byte 7 8-Byte Unique ID Read Unique ID 17 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional description 4.1.7.3 Write Serial Number (WRSN, C2h) The serial number is an 8-byte one-time programmable memory space provided to the user to uniquely identify a PC board or a system. A serial number typically consists of a two-byte Customer ID, followed by five bytes of a unique serial number and one byte of CRC check. However, the end application can define its own format for the 8-byte serial number. All writes to the Serial Number Register begin with a WREN opcode with CS being asserted and deasserted. The next opcode is WRSN. The WRSN instruction can be used in burst mode to write all the 8 bytes of serial number. After the last byte of the serial number is shifted in, CS must be driven high to complete the WRSN operation. The CY15X108QN write serial number operation is shown in Figure 17. Note The CRC checksum is not calculated by the device. The system firmware must calculate the CRC checksum on the 7-byte content and append the checksum to the 7-byte user-defined serial number before programming the 8-byte serial number into the serial number register. The factory default value for the 8-byte Serial Number is ‘0000000000000000h’. Table 7 8-byte serial number 16-bit customer identifier SN[63:56] 40-bit unique number SN[55:48] SN[47:40] SN[39:32] SN[31:24] 8-bit CRC SN[23:16] SN[15:8] SN[7:0] CS 0 1 2 3 4 5 6 7 0 1 2 3 D5 D4 4 52 53 54 55 56 57 58 59 60 61 62 63 SCK 1 SI 1 0 0 0 0 1 0 D7 D6 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 LSb MSb Hi-Z SO Hi-Z Opcode (C2h) Write 8-Byte Serial Number Figure 17 Write serial number (WREN not shown) operation 4.1.7.4 Read Serial Number (RDSN, C3h) The CY15X108QN device incorporates an 8-byte serial space provided to the user to uniquely identify the device. The serial number is read using the RDSN instruction. A serial number read may be performed in burst mode to read all the eight bytes at once. After the last byte of the serial number is read, the device loops back to the first byte of the serial number. An RDSN instruction can be issued by shifting the opcode for RDSN after CS goes LOW. The CY15X108QN read serial number operation is shown in Figure 18. Note The least significant data byte (Byte 0) shifts out first and the most significant data byte (Byte 7) shifts out last. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 52 53 54 55 56 57 58 59 60 61 62 63 SCK SI SO 1 1 0 0 0 0 Hi-Z 1 Hi-Z 1 MSb D7 LSb D6 D5 D4 D3 D2 D1 D0 D7 D6 Byte 0 Opcode (C3h) Figure 18 Datasheet D5 D4 D3 D2 D1 D0 Byte 7 8-Byte Serial Number Read serial number operation 18 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional description 4.1.8 Low Power Mode commands 4.1.8.1 Deep Power-down Mode (DPD, BAh) A power-saving Deep Power-Down mode is implemented on the CY15X108QN device. The device enters the Deep Power-Down mode after tENTDPD time after the DPD opcode BAh is clocked in and a rising edge of CS is applied. When in Deep Power-Down mode, the SCK and SI pins are ignored and SO will be Hi-Z, but the device continues to monitor the CS pin. A CS pulse-width of tCSDPD exits the DPD mode after tEXTDPD time. The CS pulse-width can be generated either by sending a dummy command cycle or toggling CS alone while SCK and I/Os are don’t care. The I/Os remain in hi-Z state during the wakeup from deep power down. Refer to Figure 19 for DPD entry and Figure 20 for DPD exit timing. Enters DPD tENTDPD CS 0 1 2 3 4 5 6 7 SCK SI 1 0 1 1 1 0 1 0 hi-Z SO Opcode (BAh) Figure 19 DPD entry timing tEXTDPD tCSDPD CS 0 1 2 SCK tSU X I/Os Figure 20 DPD exit timing 4.1.8.2 Hibernate Mode (HBN, B9h) A lowest power Hibernate mode is implemented on the CY15X108QN device. The device enters Hibernate mode after tENTHIB time after the HBN opcode B9h is clocked in and a rising edge of CS is applied. When in Hibernate mode, the SCK and SI pins are ignored and SO will be Hi-Z, but the device continues to monitor the CS pin. On the next falling edge of CS, the device will return to normal operation within tEXTHIB time. The SO pin remains in a Hi-Z state during the wakeup from hibernate period. The device does not necessarily respond to an opcode within the wakeup period. To exit the Hibernate mode, the controller may send a “dummy” read, for example, and wait for the remaining tEXTHIB time. Datasheet 19 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Functional description Enters Hibernate Mode tENTHIB Recovers from Hibernate Mode tEXTHIB CS 0 1 2 3 4 5 6 0 7 1 2 SCK tSU SI 1 0 1 1 1 0 0 1 hi-Z SO Opcode (B9h) Figure 21 Hibernate mode operation 4.1.8.3 Endurance The CY15X108QN devices are capable of being accessed at least 1015 times, reads or writes. An F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows and columns of 128K rows of 64-bit each. The entire row is internally accessed once, whether a single byte or all eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. Table 8 shows endurance calculations for a 64-byte repeating loop, which includes an opcode, a starting address, and a sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop. F-RAM read and write endurance is virtually unlimited at a 50-MHz clock rate. Table 8 Time to reach endurance limit for repeating 64-byte loop SCK freq. (MHz) Endurance cycles/sec Endurance cycles/year Years to reach 1015 limit 50 91,900 2.9 × 1012 345 20 10 5 Datasheet 36,520 18,380 9,190 1.16 × 10 12 864 5.79 × 10 11 1727 11 3454 2.90 × 10 20 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Maximum ratings 5 Maximum ratings Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage temperature –65 °C to +125 °C Maximum accumulated storage time: At 125 °C ambient temperature At 85 °C ambient temperature 1000 h 10 Years Maximum junction temperature 125 °C Supply voltage on VDD relative to VSS: CY15V108QN CY15B108QN –0.5 V to +2.4 V –0.5 V to +4.1 V Input voltage VIN  VDD + 0.5 V DC voltage applied to outputs in High-Z state –0.5 V to VDD + 0.5 V Transient voltage (< 20 ns) on any pin to ground potential –2.0 V to VDD + 2.0 V Package power dissipation capability (TA = 25 °C) 1.0 W Surface mount lead soldering temperature (3 seconds) +260 °C DC output current (1 output at a time, 1s duration) 15 mA Electrostatic discharge voltage human body model (JEDEC Std JESD22-A114-B) 2 kV Charged device model (JEDEC Std JESD22-C101-A) 500 V Latch-up current >140 mA 6 Device CY15V108QN CY15B108QN Datasheet Operating range Range Ambient temperature Industrial –40 °C to +85 °C 21 of 32 VDD 1.71 V to 1.89 V 1.8 V to 3.6 V 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial DC electrical characteristics 7 DC electrical characteristics Over the Operating range Parameter VDD IDD ISB IDPD Description Power supply VDD supply current VDD standby current Deep power-down current IHBN Hibernate mode current ILI Input leakage current on I/O pins except WP pin Input leakage current on WP pin CY15V108QN 1.71 Typ[2, 3] 1.80 CY15B108QN 1.80 3.30 3.60 Test conditions Min Max 1.89 VDD = 1.71 V to 1.89 V; SCK toggling between VDD – 0.2 V and VSS, other inputs VSS or VDD – 0.2 V. SO = Open fSCK = 1 MHz – 0.40 0.75 fSCK = 50 MHz – 2.8 3.7 VDD = 1.8 V to 3.6 V; SCK toggling between VDD – 0.2 V and VSS, other inputs VSS or VDD – 0.2 V. SO = Open. fSCK = 1 MHz – 0.50 1.0 fSCK = 50 MHz – 3.3 4.5 VDD = 1.71 V to 1.89 V; CS = VDD. All other inputs VSS or VDD. – 7.5 134 VDD = 1.8 V to 3.6 V; CS = VDD. All other inputs VSS or VDD. – 8 135 VDD = 1.71 V to 1.89 V; CS = VDD. All other inputs VSS or VDD. – 0.90 16.9 VDD = 1.8 V to 3.6 V; CS = VDD. All other inputs VSS or VDD. – 1.1 18.1 VDD = 1.71 V to 1.89 V; CS = VDD. All other inputs VSS or VDD. – 0.10 0.9 VDD = 1.8 V to 3.6 V; CS = VDD. All other inputs VSS or VDD. – 0.10 1.6 –1 – 1 –100 – 1 –1 – 1 Unit V mA µA µA µA VSS < VIN < VDD ILO Output leakage current VSS < VOUT < VDD VIH Input HIGH voltage – 0.7 × VDD – VDD + 0.3 VIL Input LOW voltage – –0.3 – 0.3 × VDD VOH1 Output HIGH voltage IOH = –1 mA, VDD = 2.7 V 2.4 – – VOH2 Output HIGH voltage IOH = –100 µA VDD – 0.2 – – µA V Notes 2. Typical values are at 25 °C, VDD = VDD (typ). 3. This parameter is guaranteed by characterization; not tested in production. Datasheet 22 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Data retention and endurance 7 DC electrical characteristics (continued) Over the Operating range Parameter Description Test conditions VOL1 Output LOW voltage IOL = 2 mA, VDD = 2.7 V VOL2 Output LOW voltage IOL = 150 µA Max – Typ[2, 3] – – – 0.2 Min 0.4 Unit V Notes 2. Typical values are at 25 °C, VDD = VDD (typ). 3. This parameter is guaranteed by characterization; not tested in production. 8 Data retention and endurance Parameter Description TDR Data retention NVC Endurance 9 Capacitance Test conditions TA = 85 °C TA = 65 °C Over operating temperature 10 151 1015 Max – – – Unit Cycles Max Unit Years For all packages. Parameter[4] Description CO Output pin capacitance (SO) CI Input pin capacitance 10 Thermal resistance Parameter[4] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test conditions 8 TA = 25 °C, f = 1 MHz, VDD = VDD (typ) Test conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 6 24-ball FBGA package pF Unit 46.4 °C/W 31.7 Note 4. This parameter is guaranteed by characterization; not tested in production. Datasheet 23 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial AC test conditions 11 AC test conditions Input pulse levels 10% and 90% of VDD Input rise and fall times 3 ns Input and output timing reference levels 0.5 × VDD Output load capacitance 30 pF 12 AC switching characteristics Over the Operating range Parameters[5] Parameter Alt. parameter 35 MHz Description 50 MHz Min Max Min Max fSCK tCH – SCK clock frequency 0 35 0 50 – Clock HIGH time 13 – 9 – tCL – Clock LOW time 13 – 9 – Clock LOW to Output low-Z 0 – 0 – tCSS tCSH – tCSU tCSH Chip select setup 5 – 5 – Chip select hold - SPI mode 0 5 – 5 – – Chip select hold - SPI mode 3 10 – 10 – tOD tODV Output disable time – 12 – 10 Output data valid time – 9 – 8 – tD Output hold time 1 – 1 – Deselect time 40 – 40 – tSU Data setup time 5 – 5 – tHD tH Data hold time 5 – 5 – tWPS tWHSL tSHWL WP setup time (w.r.t CS) 20 – 20 – WP hold time (w.r.t CS) 20 – 20 – tCLZ[6] tCSH1 tHZCS[7, 8] tCO tOH tCS tSD tWPH Unit MHz ns Notes 5. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 30-pF load capacitance shown in “AC test conditions” on page 24. 6. Guaranteed by design. 7. tHZCS is specified with a load capacitance of 5 pF. Transition is measured when the output enters a high-impedance state. 8. This parameter is guaranteed by characterization; not tested in production. Datasheet 24 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial AC switching characteristics tCS CS tCSS tCH tCL tCSH1 tCSH Mode 3 SCK Mode 0 tSD SI SO Figure 22 X tHD X VALID DATA IN tCO tCLZ Hi-Z tOH X tHZCS X DATA OUT Hi-Z Synchronous data timing (Mode 0 and Mode 3) tWPS tWPH CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 D7 D6 D5 D4 D3 D2 D1 D0 SCK SI 0 0 0 0 0 0 0 1 MSb SO Hi-Z Opcode (01h) Figure 23 Datasheet LSb Write Data Write Protect Timing during Write Status Register (WRSR) operation 25 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Power cycle timing 13 Power cycle timing Over the Operating range Parameters[9] Parameter tPU Alt. parameter Description Min Max Unit µs – Power-up VDD(min) to first access (CS LOW) 450 – – VDD power-up ramp rate 30 – – VDD power-down ramp rate 20 – tDP CS high to enter deep power-down (CS high to hibernate mode current) – 3 tCSDPD – CS pulse width to wake up from deep power-down mode 0.015 4  1/fSCK tEXTDPD tRDP Recovery time from deep power-down mode (CS low to ready for access) – 13 Time to enter hibernate (CS high to enter hibernate mode current) – 3 Recovery time from hibernate mode (CS low to ready for access) – 450 tVR[10] tVF[10, 11] tENTDPD[12] tENTHIB[13] – tEXTHIB[13] tREC VDD(low)[11] tPD[11] – Low VDD where initialization must occur 0.6 – – VDD(low) time when VDD(low) at 0.6 V 130 – – VDD(low) time when VDD(low) at VSS 70 – µs V µs VDD VDD VDD (max) No Device Access Allowed VDD (max) VDD (min) VDD (min) tVR µs/V tPU Device Access Allowed tVF tVR tPU Device Access Allowed VDD (low) tPD Time Figure 24 Time Power cycle timing Notes 9. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 30-pF load capacitance shown in “AC test conditions” on page 24. 10.Slope measured at any point on the VDD waveform. 11.This parameter is guaranteed by characterization; not tested in production. 12.Guaranteed by design. Refer to Figure 19 for Deep Power Down mode timing. 13.Guaranteed by design. Refer to Figure 21 for Hibernate mode timing. Datasheet 26 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Ordering information 14 Ordering information Ordering code CY15B108QN-50BKXI CY15B108QN-50BKXIT CY15V108QN-50BKXI CY15V108QN-50BKXIT Device ID Package diagram Package type Operating range 001-97209 24-ball FBGA Industrial (I) 7F7F7F7F7F7FC22E00 7F7F7F7F7F7FC22E04 All these parts are Pb-free. Contact your local Infineon sales representative for availability of these parts. 14.1 CY 15 Ordering code definitions B 108 Q N - 50 BK X I T Options: Blank = Standard; T = Tape and reel Temperature range: I = Industrial (-40 °C to +85 °C) X = Pb-free Package type: BK = 24-ball FBGA Frequency: 50 = 50 MHz N = No inrush current control Interface: Q = SPI F-RAM Density: 108 = 8-Mbit Voltage: B = 1.8 V to 3.6 V V = 1.71 V to 1.89 V 15 = F-RAM CY = CYPRESS™ (An Infineon Technologies company) Datasheet 27 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Package diagram 15 Package diagram TOP VIEW BOTTOM VIEW SIDE VIEW 4.00 BSC 8.00 BSC 4.00 BSC 6.00 BSC 1.00 BSC Ø0.40±0.05 0.20 MIN PIN A1 CORNER PIN A1 CORNER 1.20 MAX 0.10 C NOTES: 001-97209 *A 1. REFERENCE JEDEC # MO-216 2. ALL DIMENSIONS ARE IN MILLIMETERS Figure 25 Datasheet 24L FBGA 8  6  1.2 mm BK24A package outline, 001-97209 28 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Acronyms 16 Acronyms Table 9 Acronyms used in this document Acronym Description CPHA Clock phase CPOL Clock polarity EEPROM Electrically erasable programmable read-only memory EIA Electronic Industries Alliance FBGA Fine-pitch ball grid array F-RAM Ferroelectric random access memory FSPI Fast SPI I/O Input/output JEDEC Joint Electron Devices Engineering Council JESD JEDEC standards LSb Least significant bit MSb Most significant bit RoHS Restriction of hazardous substances SPI Serial peripheral interface Datasheet 29 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Document conventions 17 Document conventions 17.1 Units of measure Table 10 Units of measure Symbol Unit of measure °C degree Celsius Hz hertz kHz kilohertz k kilohm Mbit megabit MHz megahertz µA microampere µF microfarad µs microsecond mA milliampere ms millisecond ns nanosecond  ohm % percent pF picofarad V volt W watt Datasheet 30 of 32 002-32517 Rev. *B 2022-05-25 8Mb EXCELON™ LP Ferroelectric RAM (F-RAM) Serial (SPI), 1024K × 8, 50MHz, industrial Revision history Revision histor y Document version Date of release *B 2022-05-25 Datasheet Description of changes Publish to web. 31 of 32 002-32517 Rev. *B 2022-05-25 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2022-05-25 Published by Infineon Technologies AG 81726 Munich, Germany © 2022 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? Go to www.infineon.com/support Document reference 002-32517 Rev. *B IMPORTANT NOTICE The information given in this document shall in no For further information on the product, technology, event be regarded as a guarantee of conditions or delivery terms and conditions and prices please contact your nearest Infineon Technologies office characteristics (“Beschaffenheitsgarantie”). (www.infineon.com). With respect to any examples, hints or any typical values stated herein and/or any information WARNINGS regarding the application of the product, Infineon Due to technical requirements products may contain Technologies hereby disclaims any and all dangerous substances. For information on the types warranties and liabilities of any kind, including in question please contact your nearest Infineon without limitation warranties of non-infringement of Technologies office. intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
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