CY22392
Three-PLL General Purpose
Flash-Programmable Clock Generator
Three-PLL General Purpose Flash-Programmable Clock Generator
Features
■
Three Integrated Phase-locked Loops
■
Ultra Wide Divide Counters (8-bit Q, 11-bit P, and 7-bit Post
Divide)
■
Improved Linear Crystal Load Capacitors
■
Flash Programmability
■
Field-Programmable
■
Low-jitter, High-accuracy Outputs
■
Power Management Options (Shutdown, OE, Suspend)
■
Configurable Crystal Drive Strength
■
Frequency Select through three External LVTTL Inputs
■
3.3 V Operation
■
16-pin TSSOP and SOIC Packages
■
CyClocksRT™ Support
Benefits
■
■
Generates up to three unique frequencies on six outputs up to
200 MHz from an external source. Functional upgrade for
current CY2292 family.
Enables 0 ppm frequency generation and frequency
conversion under the most demanding applications.
■
Improves frequency accuracy over temperature, age, process,
and initial offset.
■
Nonvolatile programming enables easy customization, fast
turnaround, performance tweaking, design timing margin
testing, inventory control, lower part count, and more secure
product supply. In addition, any part in the family can also be
programmed multiple times, which reduces programming
errors and provides an easy upgrade path for existing designs.
■
In-house programming of samples and prototype quantities is
available using the CY3672 development kit. Production
quantities are available through Cypress Semiconductor’s
value added distribution partners or by using third party
programmers from BP Microsystems, HiLo Systems, and
others.
■
Performance
suitable
for
high-end
multimedia,
communications, industrial, A/D Converters, and consumer
applications.
■
Supports numerous low power application schemes and
reduces EMI by enabling unused outputs to be turned off.
■
Adjusts crystal drive strength for compatibility with virtually all
crystals.3-bit external frequency select options for PLL1, CLKA,
and CLKB.
■
Industry-standard supply voltage.Industry-standard packaging
saves on board space.Easy to use software support for design
entry.
Functional Description
For a complete list of related documentation, click here.
Logic Block Diagram
XTALIN
XTALOUT
XBUF
OSC.
CONFIGURATION
FLASH
PLL1
11 BIT P
8 BIT Q
SHUTDOWN/OE
PLL2
S0
11 BIT P
8 BIT Q
S1
S2/SUSPEND
4x4
Crosspoint
Switch
PLL3
11 BIT P
8 BIT Q
Cypress Semiconductor Corporation
Document Number: 38-07013 Rev. *M
•
198 Champion Court
•
Divider
/2,3, or 4
CLKE
Divider
7 BIT
CLKD
Divider
7 BIT
CLKC
Divider
7 BIT
CLKB
Divider
7 BIT
CLKA
San Jose, CA 95134-1709
•
408-943-2600
Revised February 2, 2018
CY22392
Contents
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 3
Operation ........................................................................... 4
Configurable PLLs ....................................................... 4
General Purpose Inputs .............................................. 4
Crystal Input ................................................................ 4
Output Configuration ................................................... 4
Power Saving Features ............................................... 4
Improving Jitter ............................................................ 5
Power Supply Sequencing .......................................... 5
CyberClocks™ Software .................................................. 5
Device Programming ........................................................ 5
Junction Temperature Limitations .................................. 5
Maximum Ratings ............................................................. 5
Operating Conditions ....................................................... 5
Electrical Characteristics ................................................. 6
Switching Characteristics ................................................ 6
Switching Waveforms ...................................................... 7
Document Number: 38-07013 Rev. *M
Test Circuit ........................................................................ 7
Ordering Information ........................................................ 8
Possible Configurations ............................................... 8
Ordering Code Definitions ........................................... 9
Package Diagrams .......................................................... 10
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC®Solutions ....................................................... 14
Cypress Developer Community ................................. 14
Technical Support ..................................................... 14
Page 2 of 14
CY22392
Pin Configurations
Figure 1. 16-pin TSSOP / 16-pin SOIC pinout
SHUTDOWN/OE
CLKC
1
16
VDD
2
15
S2/SUSPEND
AGND
3
14
AVDD
XTALIN
4
13
S1
XTALOUT
XBUF
5
12
6
11
S0
GND
CLKD
7
10
CLKA
CLKE
8
9
CLKB
Pin Definitions
Name
Pin Number
CLKC
1
Configurable clock output C
Description
VDD
2
Power supply
AGND
3
Analog Ground
XTALIN
4
Reference crystal input or external reference clock input
XTALOUT
5
Reference crystal feedback
XBUF
6
Buffered reference clock output
CLKD
7
Configurable clock output D
CLKE
8
Configurable clock output E
CLKB
9
Configurable clock output B
CLKA
10
Configurable clock output A
GND
11
Ground
S0
12
General Purpose Input for Frequency Control; bit 0
S1
13
General Purpose Input for Frequency Control; bit 1
AVDD
14
Analog Power Supply
S2/SUSPEND
15
General Purpose Input for Frequency Control; bit 2. Optionally Suspend mode control input.
SHUTDOWN/OE
16
Places outputs in three-state condition and shuts down chip when Low. Optionally, only places
outputs in tristate condition and does not shut down chip when Low.
Document Number: 38-07013 Rev. *M
Page 3 of 14
CY22392
Operation
applications that
requirements.
The CY22392 is an upgrade to the existing CY2292. The new
device has a wider frequency range, greater flexibility, improved
performance, and incorporates many features that reduce PLL
sensitivity to external system issues.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with a
resolution of 0.375 pF for a total crystal load range of 6 pF to
30 pF.
The device has three PLLs which, when combined with the
reference, enable up to four independent frequencies to be
output on up to six pins. These three PLLs are completely
programmable.
For driven clock inputs the input load capacitors may be
completely bypassed. This enables the clock chip to accept
driven frequency inputs up to 166 MHz. If the application requires
a driven input, then XTALOUT must be left floating.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL1 is sent to the
crosspoint switch. The output of PLL1 is also sent to a /2, /3, or
/4 synchronous post-divider that is output through CLKE. The
frequency of PLL1 can be changed by external CMOS inputs,
S0, S1, S2. See the following section on General Purpose Inputs
for more details.
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL2 is sent to the
crosspoint switch.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL3 is sent to the
cross-point switch.
General Purpose Inputs
S0, S1, and S2 are general purpose inputs that can be
programmed to enable eight different frequency settings.
Options that may be switched with these general purpose inputs
are as follows: the frequency of PLL1, the output divider of CLKB,
and the output divider of CLKA.
CLKA and CLKB both have 7-bit dividers that point to one of two
programmable settings (register 0 and register 1). Both clocks
share a single register control, so both must be set to register 0,
or both must be set to register 1.
For example, the part may be programmed to use S0, S1, and
S2 (0, 0, 0 to 1, 1, 1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be glitch
free.
Crystal Input
The input crystal oscillator is an important feature of this device
because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
enables maximum compatibility with crystals from various
manufacturers, processes, performances, and qualities.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors must not
be used for MPEG, POTS dial tone, communications, or other
Document Number: 38-07013 Rev. *M
are
sensitive
to
absolute
frequency
Output Configuration
Under normal operation there are four internal frequency
sources that may be routed through a programmable crosspoint
switch to any of the four programmable 7-bit output dividers. The
four sources are: reference, PLL1, PLL2, and PLL3. In addition,
many outputs have a unique capability for even greater flexibility.
The following is a description of each output.
CLKA’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post divider
derives its value from one of two programmable registers. Each
of the eight possible combinations of S0, S1, S2 controls which
of the two programmable registers is loaded into CLKA’s 7-bit
post divider. See the section General Purpose Inputs for more
information.
CLKB’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post divider
derives its value from one of two programmable registers. Each
of the eight possible combinations of S0, S1, and S2 controls
which of the two programmable registers is loaded into CLKA’s
7-bit post divider. See the section General Purpose Inputs for
more information.
CLKC’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post divider
derives its value from one programmable register.
CLKD’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post divider
derives its value from one programmable register.
CLKE’s output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4.
XBUF is simply the buffered reference.
The clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15 pF. While driving
multiple loads is possible with proper termination, it is generally
not recommended.
Power Saving Features
The SHUTDOWN/OE input tristates the outputs when pulled low.
If system shutdown is enabled, a Low on this pin also shuts off
the PLLs, counters, the reference oscillator, and all other active
components. The resulting current on the VDD pins is less than
5 A (typical). After leaving shutdown mode, the PLLs must
relock.
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs can be shut off in nearly any combination.
The only limitation is that if a PLL is shut off, all outputs derived
from it must also be shut off. Suspending a PLL shuts off all
Page 4 of 14
CY22392
Jitter Optimization Control is useful in mitigating problems
related to similar clocks switching at the same moment, causing
excess jitter. If one PLL is driving more than one output, the
negative phase of the PLL can be selected for one of the outputs
(CLKA–CLKD). This prevents the output edges from aligning,
enabling superior jitter performance.
unprogrammed, and must be programmed prior to installation on
a PCB. After a programming file (.jed) is created using
CyberClocks software, devices can be programmed in small
quantities using the CY3672 programmer and CY3698 [1]
adapter. Volume programming is available through Cypress
Semiconductor’s value added distribution partners or by using
third party programmers from BP Microsystems, HiLo Systems,
and others. For sufficiently large volumes, Cypress can supply
pre-programmed devices with a part number extension that is
configuration-specific.
Power Supply Sequencing
Junction Temperature Limitations
For parts with multiple VDD pins, there are no power supply
sequencing requirements. The part is not fully operational until
all VDD pins have been brought up to the voltages specified in
the Operating Conditions. All grounds must be connected to the
same ground plane.
It is possible to program the CY22392 such that the maximum
junction temperature rating is exceeded. The package JA is
115 C/W. Use the CyClocksRT power estimation feature to
verify that the programmed configuration meets the junction
temperature and package power dissipation maximum ratings.
CyberClocks™ Software
Maximum Ratings
The CyberClocks application enables users to configure this
device. Within CyberClocks, select the CyClocksRT tool. The
easy-to-use interface offers complete control of the many
features of this family including input frequency, PLL, output
frequencies, and different functional options. Data sheet
frequency range limitations are checked and performance tuning
is automatically applied. CyClocksRT also has a power
estimation feature that enables you to see the power
consumption of your specific configuration. Download a copy of
CyberClocks free on Cypress’s web site at www.cypress.com.
Install and run it on any PC running Windows.
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply Voltage .............................................–0.5 V to +7.0 V
associated logic, while suspending an output simply forces a
tristate condition.
Improving Jitter
Device Programming
Part numbers starting with CY22392F are ‘field programmable’
devices. Field programmable devices are shipped
DC Input Voltage ........................ –0.5 V to + (AVDD + 0.5 V)
Storage Temperature ............................... –65 C to +125 C
Junction Temperature ................................................ 125 C
Data Retention at Tj = 125 C ..............................> 10 years
Maximum Programming Cycles .......................................100
Package Power Dissipation ..................................... 350 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. 2000 V
Latch up (according to JEDEC 17) ..................... > ±200 mA
Operating Conditions
The following table lists the recommended operating conditions. [2]
Parameter
Description
VDD/AVDD
Supply Voltage
TA
Commercial Operating Temperature, Ambient
Min
Typ
Max
Unit
3.135
3.3
3.465
V
0
–
+70
C
–40
–
+85
C
CLOAD_OUT
Maximum Load Capacitance
–
–
15
pF
fREF
External Reference Crystal
Industrial Operating Temperature, Ambient
tPU
8
–
30
MHz
External Reference Clock
[3]
1
–
166
MHz
External Reference Clock
[3]
1
–
150
MHz
0.05
–
500
ms
, Commercial
, Industrial
Power up time for all VDD’s to reach minimum specified voltage (power
ramps must be monotonic)
Notes
1. Programming of only 16-pin TSSOP package is supported by CY3698. For programming support of 16-pin SOIC package, contact your local FAE.
2. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
3. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2.
Document Number: 38-07013 Rev. *M
Page 5 of 14
CY22392
Electrical Characteristics
Parameter
Description
Conditions
Output High Current
[4]
IOL
Output Low Current
[4]
CXTAL_MIN
Crystal Load Capacitance [4]
IOH
CXTAL_MAX
Crystal Load Capacitance
CLOAD_IN
Input Pin Capacitance
[4]
[4]
Min
Typ
Max
Unit
VOH = VDD – 0.5 V, VDD = 3.3 V
12
24
–
mA
VOL = 0.5 V, VDD = 3.3 V
12
24
–
mA
Capload at minimum setting
–
6
–
pF
Capload at maximum setting
–
30
–
pF
Except crystal pins
–
7
–
pF
VIH
High Level Input Voltage
CMOS levels,% of AVDD
70%
–
–
AVDD
VIL
Low Level Input Voltage
CMOS levels,% of AVDD
–
–
30%
AVDD
IIH
Input High Current
VIN = AVDD – 0.3 V
–
100 MHz or
divider = 1, measured at VDD/2
40%
50%
60%
IDDS
Total Power Supply Current in
Shutdown Mode
Switching Characteristics
Parameter
1/t1
t2
Name
Output Frequency
Output Duty Cycle
[4, 5]
[4, 6]
Description
t3
Rising Edge Slew Rate [4]
Output clock rise time, 20% to 80%
of VDD
0.75
1.4
–
V/ns
t4
Falling Edge Slew Rate [4]
Output clock fall time, 80% to 20%
of VDD
0.75
1.4
–
V/ns
t5
Output three-state Timing [4]
Time for output to enter or leave
three-state mode after
SHUTDOWN/OE switches
–
150
300
ns
t6
Clock Jitter [4, 7]
Peak-to-peak period jitter, CLK
outputs measured at VDD/2
–
400
–
ps
t7
Lock Time [4]
PLL Lock Time from Power up
–
1.0
3
ms
Notes
4. Guaranteed by design, not 100% tested.
5. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications.
6. Reference Output duty cycle depends on XTALIN duty cycle.
7. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
Document Number: 38-07013 Rev. *M
Page 6 of 14
CY22392
Switching Waveforms
Figure 2. All Outputs, Duty Cycle, and Rise/Fall Time
t1
t2
OUTPUT
t3
t4
Figure 3. Output Three-State Timing
OE
t5
t5
ALL
THREE-STATE
OUTPUTS
Figure 4. CLK Output Jitter
t6
CLK
OUTPUT
Figure 5. Frequency Change
.
SELECT
OLD SELECT
Fold
NEW SELECT STABLE
t7
Fnew
OUTPUT
Test Circuit
Figure 6. Test Circuit
AVDD
0.1 F
OUTPUTS
CLK out
CLOAD
VDD
0.1 F
GND
Document Number: 38-07013 Rev. *M
Page 7 of 14
CY22392
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
Pb-free
CY22392FXC
ZZ16
16-pin TSSOP
Commercial (TA = 0 C to 70 C)
3.3 V
CY22392FXCT
ZZ16
16-pin TSSOP – Tape and Reel
Commercial (TA = 0 C to 70 C)
3.3 V
CY22392FXI
ZZ16
16-pin TSSOP
Industrial (TA = –40 C to 85 C)
3.3 V
CY22392FXIT
ZZ16
16-pin TSSOP – Tape and Reel
Industrial (TA = –40 C to 85 C)
3.3 V
Programmer
CY3675-CLKMAKER1[8]
Only for TSSOP CY22392, CY22393, CY22394,
(ZZ16) package CY22395
Adapter Board for TSSOP16A
Devices
Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible
Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or Sales
Representative for more information.
Possible Configurations
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
Pb-free
CY22392ZXC-xxx [9]
ZZ16
16-pin TSSOP
Commercial (TA = 0 C to 70 C)
3.3 V
ZZ16
16-pin TSSOP – Tape and Reel
Commercial (TA = 0 C to 70 C)
3.3 V
ZZ16
16-pin TSSOP
Industrial (TA = –40 C to 85 C)
3.3 V
CY22392ZXI-xxxT
[9]
ZZ16
16-pin TSSOP – Tape and Reel
Industrial (TA = –40 C to 85 C)
3.3 V
CY22392SXC-xxx
[9]
SZ16
16-pin SOIC
Commercial (TA = 0 C to 70 C)
3.3 V
SZ16
16-pin SOIC – Tape and Reel
Commercial (TA = 0 C to 70 C)
3.3 V
SZ16
16-pin SOIC
Industrial (TA = –40 C to 85 C)
3.3 V
SZ16
16-pin SOIC – Tape and Reel
Industrial (TA = –40 C to 85 C)
3.3 V
CY22392ZXC-xxxT
[9]
CY22392ZXI-xxx [9]
CY22392SXC-xxxT
[9]
CY22392SXI-xxx [9]
CY22392ZSXI-xxxT
[9]
Notes
8. Programming of only 16-pin TSSOP package is supported. For programming support of 16-pin SOIC package, contact your local FAE.
9. The CY22392ZXC-xxx and CY22392ZXI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of
100 Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative.
Document Number: 38-07013 Rev. *M
Page 8 of 14
CY22392
Ordering Code Definitions
CY 22392 F
X
X
X - xxx
T
X = blank or T
T = Tape and Reel; blank = Tube
Dash Code (for factory programmed devices only)
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: X = blank or S
blank = 16-pin TSSOP, S= 16-pin SOIC
F = field programmable device
Base part number
Company ID: CY = Cypress
Document Number: 38-07013 Rev. *M
Page 9 of 14
CY22392
Package Diagrams
Figure 7. 16-pin TSSOP (4.40 mm Body) Z16.173/ZZ16.173 Package Outline, 51-85091
51-85091 *E
Figure 8. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068
51-85068 *E
Document Number: 38-07013 Rev. *M
Page 10 of 14
CY22392
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
EMI
Electromagnetic Interference
°C
degree Celsius
FET
Field-Effect Transistor
MHz
megahertz
FTG
Frequency Timing Generator
microampere
JEDEC
Joint Electron Devices Engineering Council
F
microfarad
LVTTL
Low Voltage Transistor-Transistor Logic
mA
milliampere
OSC
Oscillator
mm
millimeter
PCB
Printed Circuit Board
ms
millisecond
PLL
Phase Locked Loop
mW
milliwatt
TSSOP
Thin Shrink Small Outline Package
ns
nanosecond
%
percent
pF
picofarad
ppm
parts per million
ps
picosecond
V
volt
W
watt
Document Number: 38-07013 Rev. *M
Symbol
Unit of Measure
Page 11 of 14
CY22392
Document History Page
Document Title: CY22392, Three-PLL General Purpose Flash-Programmable Clock Generator
Document Number: 38-07013
Rev.
ECN
Orig. of
Change
Submission
Date
**
106738
TLG
07/03/2001
New data sheet.
*A
108515
JWK
08/23/2001
Changed status from Preliminary to Final.
Added Junction Temperature Limitations.
Updated Maximum Ratings:
Removed soldering temperature rating.
Updated Electrical Characteristics:
Splitted crystal load into two typical specs representing digital settings range.
Updated Switching Characteristics:
Changed maximum value of t5 parameter from 250 ns to 300 ns.
Changed typical value of t7 parameter from 0.3 ms to 1.0 ms.
*B
110052
CKN
12/09/2001
Updated Ordering Information:
Updated part numbers.
Added Note 9 and referred the same note in factory programmed MPNs.
*C
121864
RBI
12/14/2002
Updated Operating Conditions:
Added tPU parameter and its details.
*D
237811
RGL
06/25/2004
Updated Ordering Information:
Updated part numbers.
*E
2584052
AESA
10/10/2008
Updated Ordering Information:
Updated part numbers.
Replaced “Lead-Free” with “Pb-Free”.
Added Note “Not recommended for new designs.” and referred the same note
in non Pb-free part numbers.
Updated to new template.
*F
2740247
KVM /
PYRS
07/17/2009
Updated CyberClocks™ Software:
Updated description.
Added Device Programming.
Added Electrical Characteristics.
Updated Ordering Information:
Updated part numbers.
Replaced Z16 with ZZ16 in “Package Name” column for Pb-free devices.
*G
2897246
KVM
03/22/2010
Updated Ordering Information:
No change in part numbers.
Updated Note 9.
Removed Note “Not recommended for new designs. New designs should use
P.-free devices.”.
Added description before Possible Configurations.
Added Possible Configurations.
Updated Package Diagrams:
spec 51-85091 – Changed revision from *A to *B.
*H
3340710
PURU
08/09/2011
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Updated Package Diagrams:
spec 51-85091 – Changed revision from *B to *C.
Added Acronyms and Units of Measure.
Updated to new template.
Completing Sunset Review.
Document Number: 38-07013 Rev. *M
Description of Change
Page 12 of 14
CY22392
Document History Page (continued)
Document Title: CY22392, Three-PLL General Purpose Flash-Programmable Clock Generator
Document Number: 38-07013
Rev.
ECN
Orig. of
Change
Submission
Date
Description of Change
*I
3882659
PURU
01/24/2013
Updated Features:
Added 16-pin SOIC package details.
Updated Pin Configurations:
Updated caption of Figure 1 to include 16-pin SOIC package details.
Updated Device Programming:
Added Note 1 and referred the same Note for CY3698.
Updated Ordering Information:
Updated part numbers (Added new MPNs CY22392FSXC, CY22392FSXCT,
CY22392FSXI and CY22392FSXIT).
Updated Possible Configurations:
Updated part numbers (Added new MPNs CY22392SXC-xxx,
CY22392SXC-xxxT, CY22392SXI-xxx and CY22392SXI-xxxT).
Updated Ordering Code Definitions (To include 16-pin SOIC package details).
Updated Package Diagrams:
spec 51-85091 – Changed revision from *C to *D.
Added spec 51-85068 *E (for 16-pin SOIC package).
*J
4505589
TAVA
09/17/2014
Updated to new template.
Completing Sunset Review.
*K
4597235
TAVA
12/18/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85091 – Changed revision from *D to *E.
*L
5452399
TAVA
09/28/2016
Updated to new template.
Completing Sunset Review.
*M
6056485
PAWK
02/02/2018
Updated Ordering Information:
Updated part numbers.
Updated Note 8.
Updated to new template.
Document Number: 38-07013 Rev. *M
Page 13 of 14
CY22392
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
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© Cypress Semiconductor Corporation, 2001-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 38-07013 Rev. *M
CyClocksRT is a trademark of Cypress Semiconductor Corporation.
Revised February 2, 2018
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