CY25402/CY25422/CY25482
Two-PLL Programmable Clock Generator
with Spread Spectrum
Two-PLL Programmable Clock Generator with Spread Spectrum
Features
■
Two fully integrated phase locked loops (PLLs)
■
Input frequency range
❐ External crystal: 8 to 48 MHz
❐ External reference: 8 to 166 MHz clock
■
Three clock outputs with programmable drive strength
■
Glitch-free outputs while frequency switching
■
8-pin small outline integrated circuit (SOIC) package
■
Commercial and Industrial temperature ranges
Benefits
Reference clock input voltage range
❐ 2.5 V, 3.0 V, and 3.3 V for CY25482
❐ 1.8 V for CY25402 and CY25422
■
Wide operating output frequency range
❐ 3 to 166 MHz
■
Programmable[1] spread spectrum with center and down
spread option and lexmark and linear modulation profiles
■
■
VDD supply voltage options:
❐ 2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482
❐ 1.8 V for CY25422
■
Selectable output clock voltages independent of VDD:
❐ 2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482
❐ 1.8 V for CY25422
■
Frequency select feature with option to select four different
frequencies
■
Power-down, Output Enable, and SS ON/OFF controls
■
Low jitter, high accuracy outputs
■
Ability to synthesize nonstandard frequencies with Fractional-N
capability
■
Multiple high performance PLLs allow synthesis of unrelated
frequencies
■
Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
■
Application specific programmable EMI reduction using spread
spectrum for clocks
■
Programmable PLLs for system frequency margin tests
■
Meets critical timing requirements in complex system designs
■
Suitability for PC, consumer, portable, and networking
applications
■
Capable of zero parts per million (PPM) frequency synthesis
error
■
Uninterrupted system operation during clock frequency switch
■
Application compatibility in standard and low power systems
Functional Description
For a complete list of related documentation, click here.
Block Diagram
Crossbar
Switch
XIN/
EXCLKIN
XOUT
FS0
PLL 1
(SS)
OSC
Output
Dividers
MUX
and
and
Drive
PLL 2
(SS)
Control
CLK1
REFOUT
Strength
Logic
Control
FS1
CLK2
SSON
PD#/OE
Note
1. The devices mentioned in this data sheet are available as factory-programmable parts and not as field-programmable parts, since the associated programming
software is currently not available. Please visit www.cypress.com to create a Technical Support case, so Cypress can provide a programming file (.jed file) that matches
your requirements.
Cypress Semiconductor Corporation
Document Number: 001-12565 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 17, 2017
CY25402/CY25422/CY25482
Contents
Device Selector Guide ...................................................... 3
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 3
Pin Configuration ............................................................. 4
Pin Definitions .................................................................. 4
Pin Configuration ............................................................. 5
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Two Configurable PLLs ............................................... 6
Input Reference Clocks ............................................... 6
VDD Power Supply Options ........................................ 6
Output Source Selection ............................................. 6
Spread Spectrum Control ............................................ 6
Frequency Select ........................................................ 6
Glitch-Free Frequency Switch ..................................... 6
PD#/OE Mode ............................................................. 6
Output Drive Strength .................................................. 6
Generic Configuration and Custom Frequency ........... 6
Absolute Maximum Conditions ....................................... 7
Recommended Operating Conditions ............................ 7
DC Electrical Specifications ............................................ 8
Document Number: 001-12565 Rev. *J
AC Electrical Specifications ............................................ 9
Configuration Example .................................................... 9
Recommended Crystal Specification ........................... 10
Recommended Crystal Specification ........................... 10
Test and Measurement Setup ........................................ 10
Voltage and Timing Definitions ..................................... 11
Ordering Information ...................................................... 12
Possible Configurations ............................................. 12
Ordering Code Definitions ......................................... 13
Package Drawing and Dimensions ............................... 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC®Solutions ....................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Page 2 of 17
CY25402/CY25422/CY25482
Device Selector Guide
Device
Crystal Input
EXCKLKIN Input
VDD
CY25402
CY25482
Yes
1.8 V LVCMOS
2.5 V, 3.0 V, 3.3 V
No
2.5 V, 3.0 V, 3.3 V LVCMOS
2.5 V, 3.0 V, 3.3 V
CY25422
Yes
1.8 V LVCMOS
1.8 V
Pin Configuration
Figure 1. 8-pin SOIC pinout
CY25402
XIN/
EXCLKIN
1
VDD
2
CLK1
REFOUT/
FS0
8
XOUT
7
GND
3
6
CLK2/SSON
4
5
PD#/OE/FS1
CY25402
Pin Definitions
CY25402 (2.5 V, 3.0 V, or 3.3 V Supply)
Pin Number
Name
I/O
1
XIN/EXCLKIN
Input
Description
Crystal input or 1.8 V External clock input
2
VDD
Power
Power supply: 2.5 V, 3.0 V, or 3.3 V
3
CLK1
Output
Programmable clock output with spread spectrum
4
REFOUT/FS0 Output/Input Multifunction programmable pin: Reference clock output or frequency select pin
5
PD#/OE/FS1
6
CLK2/SSON
Input
Multifunction programmable pin: Power-down, output enable or Frequency select pin
Output/Input Multifunction programmable pin: Programmable clock output with spread spectrum
or Spread spectrum ON/OFF control pin
7
GND
Power
Power supply ground
8
XOUT
Output
Crystal output
Document Number: 001-12565 Rev. *J
Page 3 of 17
CY25402/CY25422/CY25482
Pin Configuration
Figure 2. 8-pin SOIC pinout
CY25422
XIN/
EXCLKIN
1
VDD
2
CLK1
3
6
CLK2/SSON
REFOUT/
FS0
4
5
PD#/OE/FS1
CY25422
8
XOUT
7
GND
Pin Definitions
CY25422 (1.8 V Supply)
Pin Number
Name
1
XIN/EXCLKIN
Input
2
VDD
Power
Power supply: 1.8 V
CLK1
Output
Programmable clock output with spread spectrum
3
I/O
Description
Crystal input or 1.8 V external clock input
4
REFOUT/FS0 Output/Input Multifunction programmable pin: reference clock output or frequency select pin
5
PD#/OE/FS1
6
CLK2/SSON
7
GND
Power
Power supply ground
8
XOUT
Output
Crystal output
Input
Multifunction programmable pin: power-down, output enable or frequency select pin
Output/Input Multifunction programmable pin: programmable clock output with spread spectrum
or spread spectrum ON/OFF control pin
Document Number: 001-12565 Rev. *J
Page 4 of 17
CY25402/CY25422/CY25482
Pin Configuration
Figure 3. 8-pin SOIC pinout
CY25482
8
DNU
7
GND
3
6
CLK2/SSON
4
5
PD#/OE/FS1
EXCLKIN
1
VDD
2
CLK1
REFOUT/
FS0
CY25482
Pin Definitions
CY25482 (2.5 V, 3.0 V, or 3.3 V Supply)
Pin Number
Name
1
EXCLKIN
Input
2
VDD
Power
Power Supply: 2.5 V, 3.0 V, or 3.3 V
CLK1
Output
Programmable clock output with spread spectrum
3
I/O
Description
2.5 V, 3.0 V, or 3.3 V external clock input
4
REFOUT/FS0 Output/Input Multifunction programmable pin: Reference clock output or frequency select pin
5
PD#/OE/FS1
6
CLK2/SSON
7
GND
Power
Power supply ground
8
DNU
Output
Do not use this pin
Input
Multifunction programmable pin: Power-down, output enable or frequency select pin
Output/Input Multifunction Programmable pin: Programmable clock output with spread spectrum
or spread spectrum ON/OFF control pin
Document Number: 001-12565 Rev. *J
Page 5 of 17
CY25402/CY25422/CY25482
Functional Overview
Two Configurable PLLs
The CY25402, CY25422, and CY25482 have two programmable
PLLs that can be used to generate output frequencies ranging
from 3 to 166 MHz. The advantage of having two PLLs is that a
single device generates two independent frequencies from a
single crystal.
Input Reference Clocks
The input reference clock can be either a crystal or a clock signal,
for CY25402 and CY25422 while just a clock signal for CY25482.
The input frequency range for crystal (XIN) is 8 MHz to 48 MHz
and that for external reference clock (EXCLKIN) is 8 MHz to 166
MHz. The voltage range of the reference clock input for CY25482
is 2.5 V/3.0 V/3.3 V while that for CY25402 and CY25422 is
1.8 V. This gives user an option for this device to be compatible
for different input clock voltage levels in the system.
VDD Power Supply Options
These devices have programmable power supply options. The
CY25402/CY25482 is a high voltage part that can be
programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V while
CY25422 is a low voltage part that can operate at 1.8 V.
Output Source Selection
These devices have programmable input sources for each of its
clock outputs. There are three available clock sources and these
clock sources are: XIN/EXCLKIN, PLL1, and PLL2. Output clock
source selection is done by using three out of three crossbar
switch. Thus, any one of these three available clock sources can
be arbitrarily selected for the clock outputs. This gives user a
flexibility to have two independent clock outputs.
REFOUT/FS0 and PD#/OE/FS1 which if programmed as
frequency select inputs, can be used to select among these
arbitrarily programmed frequency settings. Each output has
programmable output divider options.
Glitch-Free Frequency Switch
When the frequency select pin, FS(1:0) is used to switch
frequency, the outputs are glitch-free provided frequency is
switched using output dividers. This feature enables
uninterrupted system operation while clock frequency is being
switched.
PD#/OE Mode
Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to
operate as either frequency select (FS1), power down (PD#) or
output enable (OE) mode. PD# is a low-true input. If activated it
shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings.
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 5). Individual
clock outputs can be programmed to be sensitive to this OE pin.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Pin Definitions on page 4
shows the typical rise and fall times for different drive strength
settings.
Table 1. Output Drive Strength
Output Drive Strength
Rise/Fall Time (ns)
(Typical Value)
Low
6.8
Spread Spectrum Control
Mid Low
3.4
Both PLLs (PLL1 and PLL2) have spread spectrum capability for
EMI reduction in the system. The device uses a Cypress
proprietary PLL and spread spectrum clock (SSC) technology to
synthesize and modulate the frequency of the PLL. The spread
spectrum feature can be turned on or off using a multifunction
control pin (CLK2/SSON). It can be programmed to either center
spread range from ±0.125% to ±2.50% or down spread range
from –0.25% to –5.0% with lexmark or linear profile.
Mid High
2.0
High
1.0
Frequency Select
Each PLL can be programmed for up to four different
frequencies. There are two multifunction programmable pins,
Document Number: 001-12565 Rev. *J
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
devices, CY25402, CY25422, and CY25482 can be custom
programmed to any desired frequencies and listed features. For
customer specific programming, please contact local Cypress
field application engineer (FAE) or sales representative.
Page 6 of 17
CY25402/CY25422/CY25482
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply voltage for
CY25402/CY25482
–
–0.5
4.5
V
VDD
Supply voltage for CY25422
–
–0.5
2.6
V
VIN
Input voltage for
CY25402/CY25482
Relative to VSS
–0.5
VDD + 0.5
V
VIN
Input voltage for CY25422
Relative to VSS
–0.5
2.2
V
TS
Temperature, Storage
Non Functional
–65
+150
°C
ESDHBM
ESD protection (human body
model)
JEDEC EIA/JESD22-A114-E
2000
–
V
UL-94
Flammability rating
V-0 at1/8 in.
–
10
ppm
MSL
Moisture sensitivity level
SOIC package
3
Recommended Operating Conditions
Min
Typ
Max
Unit
VDD
Parameter
VDD Operating voltage for CY25402/CY25482
Description
2.25
–
3.60
V
VDD
VDD Operating voltage for CY25422
1.65
1.8
1.95
V
TAC
Commercial ambient temperature
0
–
+70
°C
TAI
Industrial ambient temperature
–40
--
+85
°C
CLOAD
Maximum load capacitance
–
–
15
pF
tPU
Power-up time for all VDD to reach minimum specified voltage (power
ramps must be monotonic)
0.05
–
500
ms
Document Number: 001-12565 Rev. *J
Page 7 of 17
CY25402/CY25422/CY25482
DC Electrical Specifications
Parameter
VOL
Description
Output low voltage
Conditions
IOL = 2 mA, drive strength = [00]
Min
Typ
Max
Unit
–
–
0.4
V
VDD – 0.4
–
–
V
IOL = 3 mA, drive strength = [01]
IOL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
VOH
Output high voltage
IOH = –2 mA, drive strength = [00]
IOH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
IOH = –12 mA, drive strength = [11]
VIL1
Input low voltage of PD#/OE,
FS0, FS1 and SSON
–
–
–
0.2 × VDD
V
VIL2
Input low voltage of EXCLKIN
–
–
–
0.18
V
VIH1
Input High Voltage of PD#/OE,
FS0, FS1 and SSON
–
0.8 × VDD
–
–
V
VIH2
Input high voltage of EXCLKIN for –
CY25402/CY25422
1.62
–
2.2
V
VIH3
Input high voltage of EXCLKIN for –
CY25482
0.8 × VDD
–
–
V
IIL
Input low current, PD#/OE/FS1
–
–
10
µA
IIH
Input high current, PD#/OE/FS1 VIN = VDD
–
–
10
µA
IILDN
Input low current, SSON and FS0 VIN = 0 V
pins
(Internal pull down resistor = 160k
typ.)
–
–
10
µA
IIHDN
Input high current, SSON and
FS0 pins
14
–
36
µA
RDN
Output clocks in off state by setting
Pull-down resistor of CLK1,
REFOUT/FS0 and CLK2/SSON PD# = Low
pins
100
160
250
k
IDD[2, 3]
Supply current for CY25422
PD# = High, No load
–
12
–
mA
Supply current for
CY25402/CY25482
PD# = High, No load
–
14
–
mA
Standby current
PD# = Low
–
3
–
µA
Input capacitance
SSON, PD#/OE/FS1 and FS0 pins
–
–
7
pF
IDDS[2]
CIN
[3]
VIN = 0 V
VIN = VDD
(Internal pull down resistor = 160k
typ.)
Notes
2. Guaranteed by design but not 100% tested.
3. Configuration dependent.
Document Number: 001-12565 Rev. *J
Page 8 of 17
CY25402/CY25422/CY25482
AC Electrical Specifications
Parameter
Description
Conditions
Min
Typ
Max
Unit
FIN (crystal)
Crystal Frequency, XIN
8
–
48
MHz
FIN (clock)
Input Clock Frequency
(EXCLKIN)
8
–
166
MHz
FCLK
Output Clock Frequency
3
–
166
MHz
DC
Output Duty Cycle, All Clocks
except Ref Out
Duty Cycle is defined in Figure 5 on
page 11; t1/t2, measured at 50% of
VDD
45
50
55
%
DC
Ref Out Duty Cycle
Ref In Min 45%, Max 55%
40
–
60
%
TRF1[4]
Output Rise/Fall Time
Measured from 20% to 80% of VDD,
as shown in Figure 6 on page 11,
CLOAD = 15 pF, drive strength [00]
–
6.8
–
ns
TRF2[4]
Output Rise/Fall Time
Measured from 20% to 80% of VDD,
as shown in Figure 6 on page 11,
CLOAD = 15 pF, drive strength [01]
–
3.4
–
ns
TRF3[4]
Output Rise/Fall Time
Measured from 20% to 80% of VDD,
as shown in Figure 6 on page 11,
CLOAD = 15 pF, drive strength [10]
–
2.0
–
ns
TRF4[4]
Output Rise/Fall Time
Measured from 20% to 80% of VDD,
as shown in Figure 6 on page 11,
CLOAD = 15 pF, drive strength [11]
–
1.0
–
ns
TCCJ[4, 5]
Cycle-to-cycle Jitter (peak)
Configuration dependent. See
Configuration Example
–
100
–
ps
TLOCK[5]
PLL Lock Time
Measured from 90% of the applied
power supply level
–
1
3
ms
Configuration Example
For C-C Jitter
Ref. Frequency (MHz)
CLK1 Output
CLK2 Output
Freq. (MHz)
C-C Jitter Typ (ps)
Freq. (MHz)
C-C Jitter Typ (ps)
14.3181
8.0
134
48
92
19.2
74.25
99
8
91
27
48
67
166
103
48
48
93
166
137
Notes
4. Guaranteed by design but not 100% tested.
5. Configuration dependent.
Document Number: 001-12565 Rev. *J
Page 9 of 17
CY25402/CY25422/CY25482
Recommended Crystal Specification
For SMD Package
Parameter
Description
Range 1
Range 2
Range 3
Unit
Fmin
Minimum frequency
8
14
28
MHz
Fmax
Maximum frequency
14
28
48
MHz
R1
Motional resistance (ESR)
135
50
30
C0
Shunt capacitance
4
4
2
pF
CL
Parallel load capacitance
18
14
12
pF
DL(max)
Maximum crystal drive level
300
300
300
µW
Range 1
Range 2
Range 3
Unit
Recommended Crystal Specification
For Thru-Hole Package
Parameter
Description
Fmin
Minimum frequency
8
14
24
MHz
Fmax
Maximum frequency
14
24
32
MHz
R1
Motional resistance (ESR)
90
50
30
C0
Shunt capacitance
7
7
7
pF
CL
Parallel load capacitance
DL(max)
Maximum crystal drive level
18
12
12
pF
1000
1000
1000
µW
Test and Measurement Setup
Figure 4. Test and Measurement Setup
V DD
0.1 F
DUT
Outputs
C LOAD
GND
Document Number: 001-12565 Rev. *J
Page 10 of 17
CY25402/CY25422/CY25482
Voltage and Timing Definitions
Figure 5. Duty Cycle Definition
t1
t2
V DD
50% of VDD
Clock
Output
0V
Figure 6. Rise Time = TRF, Fall Time = TRF
T
RF
T
RF
V DD
80% of V DD
Clock
Output
Document Number: 001-12565 Rev. *J
20% of VDD
0V
Page 11 of 17
CY25402/CY25422/CY25482
Ordering Information
Type [6]
Part Number
Package
Supply Voltage
Production Flow
Pb-free
CY25402FSXC
Field Programmable
8-pin SOIC
2.5 V, 3.0 V, or 3.3 V
Commercial, 0 °C to 70 °C
CY25402FSXCT
Field Programmable
8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V
Commercial, 0 °C to 70 °C
CY25422FSXC
Field Programmable
8-pin SOIC
1.8 V
Commercial, 0 °C to 70 °C
CY25422FSXCT
Field Programmable
8-pin SOIC – Tape and Reel 1.8 V
Commercial, 0 °C to 70 °C
CY25482FSXC
Field Programmable
8-pin SOIC
2.5 V, 3.0 V, or 3.3 V
Commercial, 0 °C to 70 °C
CY25482FSXCT
Field Programmable
8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V
Commercial, 0 °C to 70 °C
CY25402FSXI
Field Programmable
8-pin SOIC
2.5 V, 3.0 V, or 3.3 V
Industrial, –40 °C to +85 °C
CY25402FSXIT
Field Programmable
8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V
Industrial, –40 °C to +85 °C
CY25422FSXI
Field Programmable
8-pin SOIC
1.8 V
Industrial, –40 °C to +85 °C
CY25422FSXIT
Field Programmable
8-pin SOIC – Tape and Reel 1.8 V
Industrial, –40 °C to +85 °C
CY25482FSXI
Field Programmable
8-pin SOIC
2.5 V, 3.0 V, or 3.3 V
Industrial, –40 °C to +85 °C
CY25482FSXIT
Field Programmable
8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V
Industrial, –40 °C to +85 °C
Programmer
CY3675-CLKMAKER1
Programming kit
CY3675-SOIC8A
Socket Adapter Board, for programming CY25402, CY25403, CY25422, CY25423,
CY25482 and CY25483
Possible Configurations
Some product offerings are factory programmed customer specific devices with customized part numbers.The Possible Configurations
table shows the available device types, but not complete part numbers. Contact your local Cypress FAE of Sales Representative for
more information.
Part Number [7]
Type
Package
Supply Voltage
Production Flow
Pb-free
CY25402SXC-xxx
2.5 V, 3.0 V, or 3.3 V
Commercial, 0 °C to 70 °C
CY25402SXC-xxxT Factory Programmed
Factory Programmed
8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V
Commercial, 0 °C to 70 °C
CY25422SXC-xxx
8-pin SOIC
1.8 V
Commercial, 0 °C to 70 °C
CY25422SXC-xxxT Factory Programmed
8-pin SOIC – Tape and Reel 1.8 V
Commercial, 0 °C to 70 °C
CY25482SXC-xxx
8-pin SOIC
Factory Programmed
Factory Programmed
8-pin SOIC
2.5 V, 3.0 V, or 3.3 V
Commercial, 0 °C to 70 °C
CY25482SXC-xxxT Factory Programmed
8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V
Commercial, 0 °C to 70 °C
CY25402SXI-xxx
Factory Programmed
8-pin SOIC
2.5 V, 3.0 V, or 3.3 V
Industrial, –40 °C to +85 °C
CY25402SXI-xxxT
Factory Programmed
8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V
Industrial, –40 °C to +85 °C
CY25422SXI-xxx
Factory Programmed
8-pin SOIC
1.8 V
Industrial, –40 °C to +85 °C
CY25422SXI-xxxT
Factory Programmed
8-pin SOIC – Tape and Reel 1.8 V
Industrial, –40 °C to +85 °C
CY25482SXI-xxx
Factory Programmed
8-pin SOIC
2.5 V, 3.0 V, or 3.3 V
Industrial, –40 °C to +85 °C
CY25482SXI-xxxT
Factory Programmed
8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V
Industrial, –40 °C to +85 °C
Notes
6. The devices mentioned in this data sheet are available as factory-programmable parts and not as field-programmable parts, since the associated programming
software is currently not available. Please visit www.cypress.com to create a Technical Support case, so Cypress can provide a programming file (.jed file) that matches
your requirements.
7. xxx indicates Factory Programmable and are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative.
Document Number: 001-12565 Rev. *J
Page 12 of 17
CY25402/CY25422/CY25482
Ordering Code Definitions
CY 254x2
X
S
X
X - xxx X
X = blank or T
blank = Tube; T = Tape and Reel
Customer Specific Identification Code
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: S = 8-pin SOIC package
X = F or blank
F = Field Programmable; blank = Factory Programmed
Device Number: 254x2 = 25402 or 25422 or 25482
Company ID: CY = Cypress
Document Number: 001-12565 Rev. *J
Page 13 of 17
CY25402/CY25422/CY25482
Package Drawing and Dimensions
Figure 7. 8-pin SOIC (150 Mils) Package Outline, 51-85066
51-85066 *H
Document Number: 001-12565 Rev. *J
Page 14 of 17
CY25402/CY25422/CY25482
Acronyms
Acronym
Document Conventions
Description
Units of Measure
DL
Drive Level
DNU
Do Not Use
°C
degrees Celsius
DUT
Device Under Test
fF
femtofarad
EIA
Electronic Industries Alliance
MHz
megahertz
EMI
Electromagnetic Interference
s
microsecond
ESD
Electrostatic Discharge
W
microwatt
mA
milliampere
ms
millisecond
ns
nanosecond
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
V
volt
W
watt
FAE
Field Application Engineer
FS
Frequency Select
JEDEC
Joint Electron Devices Engineering Council
LVCMOS
Low Voltage Complementary Metal Oxide
Semiconductor
OE
Output Enable
OSC
Oscillator
PD
Power Down
PLL
Phase Locked Loop
PPM
Parts Per Million
SS
Spread Spectrum
SSC
Spread Spectrum Clock
SSON
Spread Spectrum On
Document Number: 001-12565 Rev. *J
Symbol
Unit of Measure
Page 15 of 17
CY25402/CY25422/CY25482
Document History Page
Document Title: CY25402/CY25422/CY25482, Two-PLL Programmable Clock Generator with Spread Spectrum
Document Number: 001-12565
Rev.
ECN No.
Issue Date
Orig. of
Change
**
690296
See ECN
RGL
*A
815788
See ECN
RGL
*B
1428744
See ECN
RGL /
AESA
Description of Change
New data sheet.
Minor Change: To post on web
Changed status from Preliminary to Final.
Added CY25482 part related information in all instances across the document.
Replaced “CLK2” with “REFOUT” in all instances across the document.
Updated Block Diagram.
Updated Functional Overview.
Updated Absolute Maximum Conditions.
Updated Recommended Operating Conditions.
Updated DC Electrical Specifications.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*C
2748211
08/10/09
TSAI
Posting to external web.
*D
2898568
06/02/10
KVM
Updated Ordering Information:
Updated part numbers.
Added Possible Configurations.
Moved ‘xxx’ parts to Possible Configurations table.
Updated Package Drawing and Dimensions:
spec 51-85066 – Changed revision from *C to *D.
Updated to new template.
*E
3110175
12/14/2010
BASH
Added Units of Measure.
Updated to new template.
*F
3235621
04/20/2011
CXQ
Updated Ordering Information:
Updated part numbers.
*G
4219507
12/13/2013
CINM
Updated Ordering Information:
Updated part numbers.
Updated Package Drawing and Dimensions:
spec 51-85066 – Changed revision from *D to *F.
Updated to new template.
Completing Sunset Review.
*H
4473684
08/25/2014
TAVA
Updated Features:
Added Note 1 and referred the same note next to “Programmable”.
Updated Ordering Information:
No change in part numbers.
Added Note 6 and referred the same note in “Type” column.
*I
4586478
12/03/2014
AJU
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*J
5590046
01/17/2017
TAVA
Updated Package Drawing and Dimensions:
spec 51-85066 – Changed revision from *F to *H.
Updated to new template.
Completing Sunset Review.
Document Number: 001-12565 Rev. *J
Page 16 of 17
CY25402/CY25422/CY25482
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2007-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
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are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 001-12565 Rev. *J
Revised January 17, 2017
Page 17 of 17