CY25482FSXIT

CY25402/CY25422/CY25482 Two-PLL Programmable Clock Generator with Spread Spectrum Two-PLL Programmable Clock Generator with Spread Spectrum Features ■ Two fully integrated phase-locked loops (PLLs) ■ Input frequency range ❐ External crystal: 8 to 48 MHz ❐ External reference: 8 to 166 MHz clock ■ Reference clock input voltage range ❐ 2.5 V, 3.0 V, and 3.3 V for CY25482 ❐ 1.8 V for CY25402 and CY25422 ■ ■ ■ 8-pin small outline integrated circuit (SOIC) package ■ Commercial and industrial temperature ranges ■ One-time programmability For programming support, contact Cypress technical support or send an e-mail to clocks@cypress.com Benefits Wide operating output frequency range ❐ 3 to 166 MHz Programmable[1] spread spectrum with center and down spread option and lexmark and linear modulation profiles ■ Multiple high-performance PLLs allow synthesis of unrelated frequencies ■ Nonvolatile programming for personalization of PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies ■ VDD supply voltage options: ❐ 2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482 ❐ 1.8 V for CY25422 Application specific programmable EMI reduction using spread spectrum for clocks ■ Programmable PLLs for system frequency margin tests Frequency select feature with option to select four different frequencies ■ Meets critical timing requirements in complex system designs ■ ■ ■ Power-down, Output Enable, and SS ON/OFF controls Suitability for PC, consumer, portable, and networking applications ■ Low jitter, high-accuracy outputs ■ Capable of zero parts per million (PPM) frequency synthesis error ■ Ability to synthesize nonstandard frequencies with fractional-N capability ■ Uninterrupted system operation during clock frequency switch Three clock outputs with programmable drive strength ■ Application compatibility in standard and low-power systems ■ ■ Glitch-free outputs while frequency switching ■ Functional Description For a complete list of related documentation, click here. Block Diagram XIN / EXCLKIN XOU T FS0 Crossbar Switch PLL 1 (SS) OSC Output CLK1 (SS) Dividers MU X and and Drive Control PLL 2 (SS) REFOUT (No SS) Strength Logic Control FS1 CLK2 (SS) SSON PD#/OE Note 1. The devices mentioned in this datasheet are available as factory-programmable parts and not as field-programmable parts, since the associated programming software is currently not available. Visit www.cypress.com to create a Technical Support case, so Cypress can provide a programming file (.jed file) that matches your requirements. Cypress Semiconductor Corporation Document Number: 001-12565 Rev. *M • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 31, 2017 CY25402/CY25422/CY25482 Contents Device Selector Guide ...................................................... 3 Pin Configuration ............................................................. 3 Pin Definitions .................................................................. 3 Pin Configuration ............................................................. 4 Pin Definitions .................................................................. 4 Pin Configuration ............................................................. 5 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Two Configurable PLLs ............................................... 6 Input Reference Clocks ............................................... 6 VDD Power Supply Options ........................................ 6 Output Source Selection ............................................. 6 Spread Spectrum Control ............................................ 6 Frequency Select ........................................................ 6 Glitch-Free Frequency Switch ..................................... 6 PD#/OE Mode ............................................................. 6 Output Drive Strength .................................................. 6 Generic Configuration and Custom Frequency ........... 6 Absolute Maximum Conditions ....................................... 7 Recommended Operating Conditions ............................ 7 DC Electrical Specifications ............................................ 8 Document Number: 001-12565 Rev. *M AC Electrical Specifications ............................................ 9 Configuration Example .................................................... 9 Recommended Crystal Specification ........................... 10 Recommended Crystal Specification ........................... 10 Test and Measurement Setup ........................................ 10 Voltage and Timing Definitions ..................................... 11 Ordering Information ...................................................... 12 Possible Configurations ............................................. 12 Ordering Code Definitions ......................................... 13 Package Drawing and Dimensions ............................... 14 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC® Solutions ...................................................... 18 Cypress Developer Community ................................. 18 Technical Support ..................................................... 18 Page 2 of 18 CY25402/CY25422/CY25482 Device Selector Guide Device Crystal Input EXCKLKIN Input VDD CY25402 CY25482 Yes 1.8 V LVCMOS 2.5 V, 3.0 V, 3.3 V No 2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V CY25422 Yes 1.8 V LVCMOS 1.8 V Pin Configuration Figure 1. 8-pin SOIC Pinout CY25402 XIN/ EXCLKIN 1 VDD 2 CLK1 REFOUT/ FS0 8 XOUT 7 GND 3 6 CLK2/SSON 4 5 PD#/OE/FS1 CY25402 Pin Definitions CY25402 (2.5 V, 3.0 V, or 3.3 V Supply) Pin Number Name I/O 1 XIN/EXCLKIN Input Description Crystal input or 1.8 V external clock input 2 VDD Power Power supply: 2.5 V, 3.0 V, or 3.3 V 3 CLK1 Output Programmable clock output with spread spectrum 4 REFOUT/FS0 Output/Input Multifunction programmable pin: reference clock output with no spread spectrum or frequency select pin 5 PD#/OE/FS1 Multifunction programmable pin: power-down, output enable or frequency select pin Input Multifunction programmable pin: programmable clock output with spread spectrum Output/Input or spread spectrum ON/OFF control pin 6 CLK2/SSON 7 GND Power Power supply ground 8 XOUT Output Crystal output Document Number: 001-12565 Rev. *M Page 3 of 18 CY25402/CY25422/CY25482 Pin Configuration Figure 2. 8-pin SOIC Pinout CY25422 XIN/ EXCLKIN 1 VDD 2 CLK1 3 6 CLK2/SSON REFOUT/ FS0 4 5 PD#/OE/FS1 CY25422 8 XOUT 7 GND Pin Definitions CY25422 (1.8 V Supply) Pin Number Name I/O 1 XIN/EXCLKIN Input 2 VDD Power 3 CLK1 Output Description Crystal input or 1.8 V external clock input Power supply: 1.8 V Programmable clock output with spread spectrum 4 REFOUT/FS0 Output/Input Multifunction programmable pin: reference clock output with no spread spectrum or frequency select pin 5 PD#/OE/FS1 Input Multifunction programmable pin: power-down, output enable or frequency select pin 6 CLK2/SSON Output/Input Multifunction programmable pin: programmable clock output with spread spectrum or spread spectrum ON/OFF control pin 7 GND Power Power supply ground 8 XOUT Output Crystal output Document Number: 001-12565 Rev. *M Page 4 of 18 CY25402/CY25422/CY25482 Pin Configuration Figure 3. 8-pin SOIC Pinout CY25482 8 DNU 7 GND 3 6 CLK2/SSON 4 5 PD#/OE/FS1 EXCLKIN 1 VDD 2 CLK1 REFOUT/ FS0 CY25482 Pin Definitions CY25482 (2.5 V, 3.0 V, or 3.3 V Supply) Pin Number Name I/O 1 EXCLKIN Input 2 VDD Power Power supply: 2.5 V, 3.0 V, or 3.3 V 3 CLK1 Output Programmable clock output with spread spectrum 4 REFOUT/FS0 Output/Input Multifunction programmable pin: reference clock output with no spread spectrum or frequency select pin 5 PD#/OE/FS1 Input Multifunction programmable pin: power-down, output enable, or frequency select pin 6 CLK2/SSON Output/Input Multifunction Programmable pin: programmable clock output with spread spectrum or spread spectrum ON/OFF control pin 7 GND Power Power supply ground 8 DNU Output Do not use this pin Document Number: 001-12565 Rev. *M Description 2.5 V, 3.0 V, or 3.3 V external clock input Page 5 of 18 CY25402/CY25422/CY25482 Functional Overview Two Configurable PLLs The CY25402, CY25422, and CY25482 have two programmable PLLs that can be used to generate output frequencies ranging from 3 to 166 MHz. The advantage of having two PLLs is that a single device generates two independent frequencies from a single crystal. Input Reference Clocks The input reference clock can be either a crystal or a clock signal, for CY25402 and CY25422 while just a clock signal for CY25482. The input frequency range for crystal (XIN) is 8 MHz to 48 MHz and that for external reference clock (EXCLKIN) is 8 MHz to 166 MHz. The voltage range of the reference clock input for CY25482 is 2.5 V/3.0 V/3.3 V while that for CY25402 and CY25422 is 1.8 V. This gives user an option for this device to be compatible for different input clock voltage levels in the system. VDD Power Supply Options These devices have programmable power supply options. The CY25402/CY25482 is a high voltage part that can be programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V while CY25422 is a low voltage part that can operate at 1.8 V. Output Source Selection These devices have programmable input sources for each of its clock outputs. There are three available clock sources and these clock sources are: XIN/EXCLKIN, PLL1, and PLL2. Output clock source selection is done by using three out of three crossbar switch. Thus, any one of these three available clock sources can be arbitrarily selected for the clock outputs. This gives user a flexibility to have two independent clock outputs. Glitch-Free Frequency Switch When the frequency select pin, FS(1:0) is used to switch frequency, the outputs are glitch-free provided frequency is switched using output dividers. This feature enables uninterrupted system operation while clock frequency is being switched. PD#/OE Mode Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to operate as either frequency select (FS1), power down (PD#) or output enable (OE) mode. PD# is a low-true input. If activated it shuts off the entire chip, resulting in minimum power consumption for the device. Setting this signal high brings the device in the operational mode with default register settings. When this pin is programmed as Output Enable (OE), clock outputs can be enabled or disabled using OE (pin 5). Individual clock outputs can be programmed to be sensitive to this OE pin. Output Drive Strength The DC drive strength of the individual clock output can be programmed for different values. Pin Definitions on page 4 shows the typical rise and fall times for different drive strength settings. Table 1. Output Drive Strength Output Drive Strength Rise/Fall Time (ns) (Typical Value) Low 6.8 Mid Low 3.4 Mid High 2.0 High 1.0 Spread Spectrum Control Generic Configuration and Custom Frequency Both PLLs (PLL1 and PLL2) have spread spectrum capability for EMI reduction in the system. The device uses a Cypress proprietary PLL and spread spectrum clock (SSC) technology to synthesize and modulate the frequency of the PLL. The spread spectrum feature can be turned on or off using a multifunction control pin (CLK2/SSON). It can be programmed to either center spread range from ±0.125% to ±2.50% or down spread range from –0.25% to –5.0% with lexmark or linear profile. There is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. The devices, CY25402, CY25422, and CY25482 can be custom programmed to any desired frequencies and listed features. For customer specific programming, contact your local Cypress field application engineer (FAE) or sales representative. Frequency Select Each PLL can be programmed for up to four different frequencies. There are two multifunction programmable pins, REFOUT/FS0 and PD#/OE/FS1 which if programmed as frequency select inputs, can be used to select among these arbitrarily programmed frequency settings. Each output has programmable output divider options. Document Number: 001-12565 Rev. *M Page 6 of 18 CY25402/CY25422/CY25482 Absolute Maximum Conditions Min Max Unit VDD Parameter Supply voltage for CY25402/CY25482 Description – Condition –0.5 4.5 V VDD Supply voltage for CY25422 – –0.5 2.6 V VIN Input voltage for CY25402/CY25482 Relative to VSS –0.5 VDD + 0.5 V VIN Input voltage for CY25422 Relative to VSS –0.5 2.2 V TS Temperature, storage Non Functional –65 +150 °C ESDHBM ESD protection (human body model) JEDEC EIA/JESD22-A114-E 2000 – V UL-94 Flammability rating V-0 at1/8 in. 10 ppm MSL Moisture sensitivity level SOIC package – 3 Recommended Operating Conditions Min Typ Max Unit VDD Parameter VDD Operating voltage for CY25402/CY25482 Description 2.25 – 3.60 V VDD VDD Operating voltage for CY25422 1.65 1.8 1.95 V TAC Commercial ambient temperature 0 – +70 °C TAI Industrial ambient temperature –40 -- +85 °C CLOAD Maximum load capacitance – – 15 pF tPU Power-up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) 0.05 – 500 ms Document Number: 001-12565 Rev. *M Page 7 of 18 CY25402/CY25422/CY25482 DC Electrical Specifications Parameter VOL Description Output low voltage Conditions IOL = 2 mA, drive strength = [00] Min Typ Max Unit – – 0.4 V VDD – 0.4 – – V IOL = 3 mA, drive strength = [01] IOL = 7 mA, drive strength = [10] IOL = 12 mA, drive strength = [11] VOH Output high voltage IOH = –2 mA, drive strength = [00] IOH = –3 mA, drive strength = [01] IOH = –7 mA, drive strength = [10] IOH = –12 mA, drive strength = [11] VIL1 Input low voltage of PD#/OE, FS0, FS1 – and SSON – – 0.2 × VDD V VIL2 Input low voltage of EXCLKIN for CY25402/CY25422 – – – 0.3 V VIL3 Input low voltage of EXCLKIN for CY25482 – – – 0.2 × VDD V VIH1 Input High Voltage of PD#/OE, FS0, FS1 – and SSON 0.8 × VDD – – V VIH2 Input high voltage of EXCLKIN for CY25402/CY25422 – 1.62 – 2.2 V VIH3 Input high voltage of EXCLKIN for CY25482 – 0.8 × VDD – – V IIL Input low current, PD#/OE/FS1 VIN = 0 V – – 10 µA IIH Input high current, PD#/OE/FS1 VIN = VDD – – 10 µA IILDN Input low current, SSON and FS0 pins VIN = 0 V (Internal pull down resistor = 160k typ.) – – 10 µA IIHDN Input high current, SSON and FS0 pins VIN = VDD (Internal pull down resistor = 160k typ.) 14 – 36 µA RDN Pull-down resistor of CLK1, REFOUT/FS0 and CLK2/SSON pins 100 160 250 k IDD[2, 3] Supply current for CY25422 PD# = High, No load – 12 – mA Supply current for CY25402/CY25482 PD# = High, No load – 14 – mA Standby current PD# = Low – 3 – µA Input capacitance SSON, PD#/OE/FS1 and FS0 pins – – 7 pF IDDS[2] CIN [3] Output clocks in off state by setting PD# = Low Notes 2. Guaranteed by design but not 100% tested. 3. Configuration dependent. Document Number: 001-12565 Rev. *M Page 8 of 18 CY25402/CY25422/CY25482 AC Electrical Specifications Parameter Description Conditions Min Typ Max Unit FIN (crystal) Crystal frequency, XIN 8 – 48 MHz FIN (clock) Input clock frequency (EXCLKIN) 8 – 166 MHz FCLK Output clock frequency 3 – 166 MHz DC Output duty cycle, all clocks except Ref Out Duty Ccycle is defined in Figure 5 on page 11; t1/t2, measured at 50% of VDD 45 50 55 % DC Ref Out duty cycle Ref In minimum 45%, maximum 55% 40 – 60 % TRF1[4] Output rise/fall time Measured from 20% to 80% of VDD, as shown in Figure 6 on page 11, CLOAD = 15 pF, drive strength [00] – 6.8 – ns TRF2[4] Output rise/fall time Measured from 20% to 80% of VDD, as shown in Figure 6 on page 11, CLOAD = 15 pF, drive strength [01] – 3.4 – ns TRF3[4] Output rise/fall time Measured from 20% to 80% of VDD, as shown in Figure 6 on page 11, CLOAD = 15 pF, drive strength [10] – 2.0 – ns TRF4[4] Output rise/fall time Measured from 20% to 80% of VDD, as shown in Figure 6 on page 11, CLOAD = 15 pF, drive strength [11] – 1.0 – ns TCCJ[4, 5] Cycle-to-cycle jitter (peak) Configuration dependent. See Configuration Example – 100 – ps TLOCK[5] PLL lock time Measured from 90% of the applied power supply level – 1 3 ms Configuration Example For C-C Jitter Ref. Frequency (MHz) CLK1 Output CLK2 Output Freq. (MHz) C-C Jitter Typ (ps) Freq. (MHz) C-C Jitter Typ (ps) 14.3181 8.0 134 48 92 19.2 74.25 99 8 91 27 48 67 166 103 48 48 93 166 137 Notes 4. Guaranteed by design but not 100% tested. 5. Configuration dependent. Document Number: 001-12565 Rev. *M Page 9 of 18 CY25402/CY25422/CY25482 Recommended Crystal Specification For SMD Package Parameter Description Range 1 Range 2 Range 3 Unit Fmin Minimum frequency 8 14 28 MHz Fmax Maximum frequency 14 28 48 MHz R1 Motional resistance (ESR) 135 50 30  C0 Shunt capacitance 4 4 2 pF CL Parallel load capacitance 18 14 12 pF DL(max) Maximum crystal drive level 300 300 300 µW Range 1 Range 2 Range 3 Unit Recommended Crystal Specification For Thru-Hole Package Parameter Description Fmin Minimum frequency 8 14 24 MHz Fmax Maximum frequency 14 24 32 MHz R1 Motional resistance (ESR) 90 50 30  C0 Shunt capacitance 7 7 7 pF CL Parallel load capacitance DL(max) Maximum crystal drive level 18 12 12 pF 1000 1000 1000 µW Test and Measurement Setup Figure 4. Test and Measurement Setup V DD 0.1 F DUT Outputs C LOAD GND Document Number: 001-12565 Rev. *M Page 10 of 18 CY25402/CY25422/CY25482 Voltage and Timing Definitions Figure 5. Duty Cycle Definition t1 t2 V DD 50% of VDD Clock Output 0V Figure 6. Rise Time = TRF, Fall Time = TRF T RF T RF V DD 80% of V DD Clock Output Document Number: 001-12565 Rev. *M 20% of VDD 0V Page 11 of 18 CY25402/CY25422/CY25482 Ordering Information Type[6] Part Number Package Supply Voltage Production Flow Pb-free CY25402SXI Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C CY25402SXIT Field Programmable 8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C CY25422FSXI Field Programmable 8-pin SOIC 1.8 V Industrial, –40 °C to +85 °C CY25422FSXIT Field Programmable 8-pin SOIC – Tape and Reel 1.8 V Industrial, –40 °C to +85 °C CY25482FSXI Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C CY25482FSXIT Field Programmable 8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C Programmer CY3675-CLKMAKER1 Programming kit CY3675-SOIC8A Socket adapter board for programming CY25402, CY25403, CY25422, CY25423, CY25482, and CY25483 Some product offerings are factory-programmed customer-specific devices with customized part numbers. The Possible Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales representative for more information. Possible Configurations Part Number[7] Type Package Supply Voltage Production Flow Pb-free CY25402SXC-xxx Factory Programmed 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C CY25402SXC-xxxT Factory Programmed 8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C CY25422SXC-xxx 8-pin SOIC 1.8 V Commercial, 0 °C to 70 °C CY25422SXC-xxxT Factory Programmed 8-pin SOIC – Tape and Reel 1.8 V Commercial, 0 °C to 70 °C CY25482SXC-xxx 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C CY25482SXC-xxxT Factory Programmed 8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C CY25402SXI-xxx Factory Programmed 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C CY25402SXI-xxxT Factory Programmed 8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C CY25422SXI-xxx Factory Programmed 8-pin SOIC 1.8 V Industrial, –40 °C to +85 °C CY25422SXI-xxxT Factory Programmed 8-pin SOIC – Tape and Reel 1.8 V Industrial, –40 °C to +85 °C CY25482SXI-xxx Factory Programmed 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C CY25482SXI-xxxT Factory Programmed 8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C Factory Programmed Factory Programmed 8-pin SOIC Notes 6. The devices mentioned in this datasheet are available as factory-programmable parts and not as field-programmable parts, since the associated programming software is currently not available. Visit www.cypress.com to create a Technical Support case, so Cypress can provide a programming file (.jed file) that matches your requirements. 7. xxx indicates Factory Programmable and are factory programmed configurations. For more details, contact your local Cypress FAE or sales representative. Document Number: 001-12565 Rev. *M Page 12 of 18 CY25402/CY25422/CY25482 Ordering Code Definitions CY 254x2 X S X X - xxx X X = blank or T blank = Tube; T = Tape and Reel Customer Specific Identification Code Temperature Range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: S = 8-pin SOIC package X = F or blank F = Field Programmable; blank = Factory Programmed Device Number: 254x2 = 25402 or 25422 or 25482 Company ID: CY = Cypress Document Number: 001-12565 Rev. *M Page 13 of 18 CY25402/CY25422/CY25482 Package Drawing and Dimensions Figure 7. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066 51-85066 *I Document Number: 001-12565 Rev. *M Page 14 of 18 CY25402/CY25422/CY25482 Acronyms Acronym Document Conventions Description Units of Measure DL Drive Level DNU Do Not Use °C degrees Celsius DUT Device Under Test fF femtofarad EIA Electronic Industries Alliance MHz megahertz EMI Electromagnetic Interference s microsecond ESD Electrostatic Discharge W microwatt FAE Field Application Engineer mA milliampere FS Frequency Select ms millisecond JEDEC Joint Electron Devices Engineering Council ns nanosecond Low Voltage Complementary Metal Oxide Semiconductor  ohm LVCMOS pF picofarad OE Output Enable ppm parts per million OSC Oscillator ps picosecond PD Power Down V volt PLL Phase-Locked Loop W watt PPM Parts Per Million SS Spread Spectrum SSC Spread Spectrum Clock SSON Spread Spectrum On Document Number: 001-12565 Rev. *M Symbol Unit of Measure Page 15 of 18 CY25402/CY25422/CY25482 Document History Page Document Title: CY25402/CY25422/CY25482, Two-PLL Programmable Clock Generator with Spread Spectrum Document Number: 001-12565 Rev. ECN No. Orig. of Change Submission Date ** 690296 RGL 01/17/2007 Description of Change New data sheet. *A 815788 RGL 03/02/2007 Minor Change: To post on web. *B 1428744 RGL / AESA 08/30/2007 Updated Document Title to read as “CY25402/CY25422/CY25482 Two PLL Programmable Clock Generator with Spread Spectrum”. Changed status from Preliminary to Final. Added CY25482 part related information in all instances across the document. Updated Block Diagram. Updated Pin Definitions: Updated details in “Description” column. Updated Functional Overview: Updated description and added sub-sections. Updated Absolute Maximum Conditions: Updated details corresponding to VDD and VIN parameters. Updated Recommended Operating Conditions: Updated details corresponding to VDD parameter. Updated DC Electrical Specifications: Updated almost entire table. Updated Ordering Information: Updated part numbers. Updated to new template. *C 2748211 TSAI 08/10/2009 Post to external web. *D 2898568 KVM 06/02/2010 Updated Ordering Information: Updated part numbers. Added Possible Configurations. Moved ‘xxx’ parts under Possible Configurations. Added Ordering Code Definitions. Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *C to *D. Added Acronyms. Updated to new template. *E 3110175 BASH 12/14/2010 Added Units of Measure. Updated to new template. *F 3235621 CXQ 04/20/2011 Updated Ordering Information: Updated part numbers. *G 4219507 CINM 12/13/2013 Updated Ordering Information: Updated part numbers. Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *D to *F. Updated to new template. Completing Sunset Review. *H 4473684 TAVA 08/25/2014 Updated Features: Added Note 1 and referred the same note next to “Programmable”. Updated Ordering Information: No change in part numbers. Added Note 6 and referred the same note in “Type” column. *I 4586478 AJU 12/03/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Document Number: 001-12565 Rev. *M Page 16 of 18 CY25402/CY25422/CY25482 Document History Page (continued) Document Title: CY25402/CY25422/CY25482, Two-PLL Programmable Clock Generator with Spread Spectrum Document Number: 001-12565 Rev. ECN No. Orig. of Change Submission Date *J 5590046 TAVA 01/17/2017 Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *F to *H. Updated to new template. Completing Sunset Review. *K 5726617 BPIN 05/18/2017 Updated Ordering Information: Updated part numbers. Updated to new template. *L 5778002 PSR 06/19/2017 Updated Features: Added one-time programmability. Updated Pin Definitions: Updated details in “Description” column corresponding to pin number 4. Updated Pin Definitions: Updated details in “Description” column corresponding to pin number 4. *M 5952857 XHT 10/31/2017 Updated DC Electrical Specifications: Updated details in “Description” and “Max” columns corresponding to VIL2 parameter. Added VIL3 parameter and its details. Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *H to *I. Completing Sunset Review. Document Number: 001-12565 Rev. *M Description of Change Page 17 of 18 CY25402/CY25422/CY25482 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-12565 Rev. *M Revised October 31, 2017 Page 18 of 18