CY51X7
High-Performance PLL Die for Oscillators
High-Performance PLL Die for Oscillators
Features
Functional Description
■
Low-noise PLL Die for integrated crystal applications
■
Differential clock output: Four frequencies selectable,
reconfigurable by I2C
■
Output frequency support from 15 MHz to 2.1 GHz
■
Fractional N PLL with fully integrated VCO
■
Works on third overtone (OT3) of a fixed-frequency crystal,
low-frequency
fundamental
(LFF),
high-frequency
fundamental (HFF) mode crystal, and low-frequency input
■
LVPECL, CML, HCSL, LVDS, and LVCMOS output standards
available
■
Compatible with 3.3 V, 2.5 V, and 1.8 V supply
■
150 fs typical integrated jitter performance (12 kHz to 20 MHz
frequency offsets) for output greater than 150 MHz
■
VCXO functionality provided with tunable Total Pull Range
(TPR) from ±50 ppm to ±275 ppm
■
Die size facilitates integration with several integrated crystal
package options
The CY51X7 is a Programmable PLL-based crystal oscillator
solution with flexible output frequency options. It is field and
factory programmable for any output frequency between 15 MHz
and 2.1 GHz. Four frequencies are independently programmable
on the differential output with the frequency select (FS) bits.
Additionally, other frequency options can be configured with the
I2C interface. Using advanced design technology, it provides
excellent jitter performance across the entire output frequency
range working reliably at supply voltages from 1.8 V to 3.3 V for
junction temperatures from –40 °C to 125 °C. This makes it
ideally suited for communications applications (for example,
OTN, SONET/SDH, xDSL, GbE, Networking, Wireless
Infrastructure), test and instrumentation applications, and
high-speed data converters. Additionally, the VCXO function
enables the use of CY51X7 in applications requiring a clock
source with voltage control and in discrete clocking solutions for
synchronous timing applications.
The CY51X7 die configuration can be created using
ClockWizard 2.1. For programming support, contact Cypress
Technical Support or send an email to clocks@cypress.com.
For a complete list of related documentation, click here.
Logic Block Diagram
VDD
GND
VDDO
CLK_P
XOUT
Crystal
Oscillator
Fractional - N
Output
Dividers
LC VCO Based PLL
Output
Drivers
CLK_N
CLK_SE
XIN
Digital Configuration and Control
I2C
Interface
NVM
SCL
FS[1:0]
Cypress Semiconductor Corporation
Document Number: 001-90233 Rev. *K
•
ADC + Digital Filtering Pathway
(for VCXO Function)
SDA
198 Champion Court
VC
•
OE
San Jose, CA 95134-1709
•
408-943-2600
Revised June 1, 2017
CY51X7
Contents
Die Pad Description .......................................................... 3
Die Pad Summary ............................................................. 3
Functional Overview ........................................................ 4
Programmable Features .............................................. 4
Architecture Overview ................................................. 4
Internal State Diagram ................................................ 4
Small/Large Changes .................................................. 5
Programming Support ................................................. 5
Frequency Configurations ........................................... 5
Programmable OE Polarity .......................................... 5
Programmable VCXO .................................................. 5
Power Supply Sequencing .......................................... 5
I2C Interface ................................................................ 5
Memory Map ............................................................... 6
Absolute Maximum Ratings ............................................ 7
Recommended Operating Conditions ............................ 7
DC Electrical Specifications ............................................ 7
DC Specifications for LVDS Output ................................ 8
DC Specifications for LVPECL Output ........................... 8
DC Specifications for CML Output .................................. 8
DC Specifications for HCSL Output ................................ 9
DC Specifications for LVCMOS Output .......................... 9
VCXO Specific Parameters .............................................. 9
AC Electrical Specifications for LVPECL,
LVDS, CML Outputs ....................................................... 10
Document Number: 001-90233 Rev. *K
AC Electrical Specifications for HCSL Output ............. 11
AC Electrical Specifications for LVCMOS Output ....... 11
HFF Crystal Specifications ............................................ 12
OT3 Crystal Specifications ............................................ 12
LFF Crystal Specifications ............................................ 12
LF Low Frequency Reference ....................................... 12
Timing Parameters ......................................................... 13
Input Clock Measurement Point .................................... 13
Phase Jitter Characteristics .......................................... 14
I2C Bus Timing Specifications ...................................... 14
Voltage and Timing Definitions ..................................... 15
Phase Noise Plots .......................................................... 17
Ordering Information ...................................................... 20
Ordering Code Definitions ......................................... 20
Packaging Information ................................................... 21
Acronyms ........................................................................ 22
Document Conventions ................................................. 22
Units of Measure ....................................................... 22
Document History Page ................................................. 23
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC® Solutions ...................................................... 25
Cypress Developer Community ................................. 25
Technical Support ..................................................... 25
Page 2 of 25
CY51X7
Die Pad Description
Horizontal Scribe
Note:
XOUT
XIN
GND
VDDA
SCL
FS0
Die Size: X = 919.5955 Pm
Y = 1399.4 Pm
GNDO
CLK_SE
CLK_P
CLK_N
VDDO
VC
SDA
FS1
OE
Vertical Scribe
FS0_BOT
FS1_BOT
SDA_BOT
SCL_BOT
Y
Scribe: Vertical = 79.8955 Pm
Horizontal = 80 Pm
CY Logo
X
Die Pad Summary
Pad coordinates are referenced from the seal ring edge (X = 0, Y = 0)
Name
Die Pad
X Coordinate (Pm) Y Coordinate (Pm)
Description
VC
1
86.8275
1234.157
VIN for VCXO
SDA
2
86.8275
1133.357
Serial data input/output for I2C
FS1
3
86.8275
1032.557
Frequency Select input 1 (100 k: pull-down)
OE
4
86.8275
931.7565
Output Enable input (configurable 200 k:pull-up/ pull-down
FS0_BOT
5
162.063
87.2235
Frequency Select 0 (Alternative) (100 k: pull-down)
FS1_BOT
6
262.8765
87.2235
Frequency Select 1 (Alternative) (100 k: pull-down)
SDA_BOT
7
363.663
87.2235
Serial data input/output (Alternative)
SCL_BOT
8
464.463
87.2235
Serial clock input for I2C (Alternative)
VDDO
9
714.627
73.0755
Power supply for output driver
CLK_N
10
714.627
173.8755
Complementary output
CLK_P
11
714.627
305.2755
True output
CLK_SE
12
714.627
393.4755
(Optional) LVCMOS clock output
GNDO
13
714.627
494.2755
Supply Ground for output driver
FS0
14
704.0025
1232.123
Frequency Select input 0 (100 k: pull-down)
SCL
15
603.2025
1232.123
Serial clock input for I2C
VDDA
16
502.4025
1232.123
Power supply for core
GND
17
401.6025
1232.123
Power supply ground
XIN
18
300.8025
1232.123
Crystal reference input
XOUT
19
200.0025
1232.123
Crystal reference output
Note: CLK_SE and (CLK_P, CLK_N) will not be available at the same time. VDDA should equal VDDO.
Document Number: 001-90233 Rev. *K
Page 3 of 25
CY51X7
Programmable Features
Figure 2 shows the conceptual internal memory structure that
consists of Common Device Configurations and Frequency
Information.
Table 1. Programmable Features
Figure 2. Memory Structure for Configurations
Functional Overview
Feature
FS0Profile
FS1Profile
FS2Profile
FS3Profile
VCXOFunction
VDD
I2C
OutputStandard
LOCK
InputReference
Description
Frequency Tuning
Frequency for the PLL
Oscillator tuning (load capacitance values)
Function
OE polarity
Power Supply
VDD (1.8, 2.5 or 3.3 V)
Enable/Disable VCXO
Kv polarity
VCXO
Total pull range
Frequency
Information
Common
Device
Configurations
Description of Settings for the Memory Structure
Modulation bandwidth
■
Profile[FS0-3]: Frequency information
■
VCXO function: VCXO enable/disable, TPR, modulation
bandwidth and Kv (Slope for VC vs. Frequency) information
■
VDD: 1.8 / 2.5 / 3.3 V range information
■
I2C: enable/disable, I2C address information
Architecture Overview
■
Output Standards: LVPECL, LVDS, CML, HCSL, LVCMOS
The CY51X7 is a high-performance programmable PLL die for
crystal oscillators supporting multiple functions, multiple output
standards, and four user selectable output frequencies. The
device has internal one-time programmable (OTP) nonvolatile
memory (NVM) that can be partitioned into Common Device
Configurations and Frequency Information (see Figure 2). The
Common Device Configurations do not change with output
frequency and consist of chip power supply, OE polarity, I2C
device address, input reference, output standards, and VCXO.
The OTP memory is based on eFuse and the CY51X7 also
contains volatile memory (shown as “NVMCopy” in Figure 1) that
stores an exact copy of the NVM at the release of reset on Power
ON. The chip settings depend on the contents of the volatile
memory and the output frequency depends on the
configurations, as explained in Figure 1. The volatile memory
can be accessed through the I2C bus and modified.
■
LOCK pattern: 2-bit pattern to indicate eFuse lock
■
Input reference: Crystal (OT3, HFF, LFF) or clock
Output
LVPECL, LVDS, HCSL, CML, LVCMOS
I2C address
Function
4 / 2 / 1 - default frequency
Reference
Crystal (HFF, OT3, LFF) or clock input
Figure 1. Conceptual Memory Structure
ProgrameFuse
Reset
“NVMCopy”
Volatile
“eFuse”
NonͲVolatile
M
U
X
Chip
Settings
Internal State Diagram
The CY51X7 contains a state machine, which controls the device
behavior. The state machine loads the “eFuse” contents to
“NVMCopy” after the reset as indicated in Figure 3 on page 5.
The eFuse memory contains a 2-bit pattern “XT-PATTERN”
associated with Crystal Blank Tuning.
The state machine enters one of the following states: “Crystal
Blank Tuning state”, “Command Wait state”, or “Active state”
according to the XT-PATTERN and/or LOCK. There are two
options for the unprogrammed device: one is the
XT-PATTERN = “00” or “11” (referred to as non-XT-PAT device
hereafter) and the other is XT-PATTERN = “01” or “10” (referred
to as XT-PAT device hereafter).
In case of a XT-PAT device, the state machine goes to “Crystal
Blank Tuning state” automatically. You may tune the Crystal
Blank without shifting any data to the device.
In the case of a non-XT-PAT device, the State Machine goes to
“Command Wait state” if the LOCK = “00”. In this state, you may
access all the registers and read/write the “NVMCopy” contents.
The following commands can be used in the “Command Wait
state”:
■
Program eFuse
■
Selectively Program eFuse
Copy eFuse to NVMCopy
■
Copy NVMCopy to NVMRegister
■
Loop Lock
■
Exit Command (applicable in the “Crystal Blank tuning state”)
❐
I2C
FS[0Ͳ1]
You may test the device functionality by issuing the “Loop Lock”
command to enter “Active state” without programming the LOCK.
Document Number: 001-90233 Rev. *K
Page 4 of 25
CY51X7
When the LOCK is programmed as “10” or “01”, the device goes
to the “Active state” and the output clock will be available after
completion of the power-on cycle.
In the “Active state”, you may change the output frequency by
applying “Small Change” or “Large Change” commands.
Figure 3. State Diagrams
ReleaseResetonPower
Copy“eFuse”to“NVMCopy”
XTͲPATTERN=“01”or“10”
Table 2. FS Setting
FS1
FS0
FS Setting
0
0
FS0
0
1
FS1
1
0
FS2
1
1
FS3
Programmable OE Polarity
XTͲPATTERN=“00”or“11”
CrystalBlanktuningstate
LOCK = "10" or "01"
LOCK=“10”
LOCK=“00”
Exitcommand
frequency configuration for FS[0–3] is provided in Table 4 on
page 6.
Programmable VCXO
LoopLock
Activestate
OutputClock
CommandWaitState
SmallChange
LargeChange
Small/Large Changes
Small change refers to the case where the frequency is changing
within ±500 ppm. The frequency information can be loaded
through I2C and the output frequency will change without any
glitch from its original frequency to the new frequency.
Note The small change functionality is not supported in the
Integer mode PLL. For more information, see AC Electrical
Specifications for LVPECL, LVDS, CML Outputs.
Large change refers to the case where the frequency is changing
more than ±500 ppm and is done through an I2C or FS state
change. The device will recalibrate and reconfigure the PLL and
the output will be unstable until this process is completed.
Programming Support
The CY51X7 is a software-configurable solution in which
Cypress provides a programming specification that defines all
necessary configuration bits. The customer uses this information
to develop programming software for use with their programmer
hardware.
Frequency Configurations
The FS[0-3] setting is done based on the logic levels on the FS0
and FS1 pins as indicated in the Table 2. The frequency
configuration consists of the desired output frequency
corresponding to each of the FS[0–3] setting. The Fractional-N
PLL is loaded with values required to generate the frequency for
each of these settings based on the input crystal frequency. The
Document Number: 001-90233 Rev. *K
The CY51X7 contains a bit for OE polarity setting (default is
active-low). You can choose active-high or active-low polarity for
the OE function. The output will be disabled when OE is
deasserted.
The device incorporates a proprietary technique for modulating
frequency by modifying VCO frequency according to the VC
control voltage. The pull profile is linear and accurate compared
to pulling the OT3/HFF reference. Also, the VCXO
characteristics are very stable and do not vary over temperature,
supply voltage, or process variations.
Kv (slope for frequency versus VC), TPR VC bandwidth, and
VCXO on/off are all programmable. Note that the VCXO
functionality is not supported in the Integer mode PLL.
Power Supply Sequencing
For start-up, the CY51X7 does not require any specific
sequencing and only needs a monotonic VDD ramp specified in
the datasheet. After the ramp up, VDD has to be maintained
within the limits specified for it in the Recommended Operating
Conditions. Brownout detection and protection has to be
implemented elsewhere in the system.
Other input signals, such as VC, FS0 or FS1, can power up
earlier or later than VDD. There are no timing requirements for
those input signals with reference to VDD. The device will operate
normally when all of the input signals are settled in the configured
state.
If a TCXO or external clock is fed into the XIN/XOUT inputs, a
stable input has to be present before start of the VDD ramp-up to
the specified level. This is because the on-chip frequency
calibration process starts at Power ON and requires a stable
reference input to be available at the start of the process.
I2C Interface
The CY51X7 supports two-wire serial interface and I2C in Fast
Mode (400 kbps) and 7-bit addressing. The device address is
programmable and is 55h by default. It supports single-byte
access only. The first I2C access to the device has to be made
5 ms (minimum) after VDD reaches its minimum specified
voltage.
Page 5 of 25
CY51X7
Memory Map
Table 3. Common Configurations
Memory Address
50h-57h
Table 5. Miscellaneous Information
Description
Device configurations
Table 4. FSx: Frequency Configurations
Memory Address
Description
10h, 20h, 30h, 40h
DIVO
11h, 21h, 31h, 41h
DIVO, DIVN_INT
12h, 22h, 32h, 42h
ICP,DIVN_INT, PLL_MODE
13h, 23h, 33h, 43h
DIVN_FRAC_L
14h, 24h, 34h, 44h
DIVN_FRAC_M
15h, 25h, 35h, 45h
DIVN_FRAC_H
1xh = FS0, 2xh = FS1,
3xh = FS2, 4xh = FS3
Document Number: 001-90233 Rev. *K
Memory Address
Description
00h (Read Only)
Device ID (= 51h)
D4h–D6h
User configurable information
Write all the contents created by the Configuration tool. Partial
updates to the device is not allowed.
Access to locations other than those described here may cause
fatal error in device operation.
–
Page 6 of 25
CY51X7
Programming temperature ........................... 0 qC to +125 qC
Programming Voltage .........................................2.5V ±0.1 V
Supply Current for eFuse Programming ..................... 50 mA
Data retention at TJ = 125 qC ...............................> 10 years
Maximum programming cycles ............................................1
ESD HBM (JEDEC JS-001-2012) ............................ 2000 V
ESD MM (JEDEC JESD22-A115B) ............................. 200 V
Latch-up current .................................................... ± 140 mA
Absolute Maximum Ratings
Exceeding maximum ratings[1] may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage to ground potential .............–0.5 V to + 3.8 V
Input voltage ...............................................–0.5 V to + 3.8 V
Storage temperature (non-condensing) ... –55 qC to +150 qC
Junction temperature ............................... –40 qC to +125 qC
Recommended Operating Conditions
Parameter
VDD, VDDO
fRES
TPLLHOLD
Description
Supply voltage, 1.8-V operating range, 1.8 V ± 5%
Supply voltage, 2.5-V operating range, 2.5 V ± 10%
Supply voltage, 3.3-V operating range, 3.3 V ± 10%
Frequency resolution
PLL Hold Temperature Range
Min
1.71
2.25
2.97
–
Max
1.89
2.75
3.63
2
125
Unit
V
V
V
ppb
qC
Unit
DC Electrical Specifications
Parameter
IDD[2]
Description
Test Conditions
Min
Typ
Max
Supply current[3], LVPECL
VDD = 3.3 V, 2.5 V,
50 : to VTT (VDDO – 2.0 V), with common
mode current
–
93
106
Supply current[3], LVPECL
VDD = 3.3 V, 2.5 V,
50 : to VTT (VDDO – 2.0 V), without
common mode current[4]
–
81
94
Supply current[3], LVDS
VDD = 3.3 V, 2.5 V, 1.8 V,
100 : between CLKP and CLKN
–
69
81
Supply current[3], HCSL
VDD = 3.3 V, 2.5 V, 1.8 V,
33 : and 49.9 : to GND
–
80
93
Supply current[3], CML
VDD = 3.3 V, 2.5 V, 1.8 V,
50 : to VDDO
–
73
86
Supply current[3], CMOS
VDD = 3.3 V, 2.5 V, 1.8 V,
0 pF load, 33.33 MHz
–
58
70
Supply current[3], CMOS
VDD = 3.3 V, 2.5 V, 1.8 V,
10 pF load, 33.33 MHz
–
66
78
Supply current, PLL only
VDD = 3.3 V, 2.5 V, 1.8 V
–
59
70
mA
IIH
Input high current
Logic input, Input = VDD
–
30
50
μA
IIL
Input low current
Logic input, Input = GND
–
30
50
μA
VIH[5]
VIL[5]
Input high voltage
OE, FS, SCL, SDA logic level = 1
0.7 × VDD
–
–
V
Input low voltage
OE, FS, SCL, SDA logic level = 0
–
–
0.3 × VDD
V
VIN
Input voltage level
All input, relative to GND
–0.5
–
3.8
V
RP
Internal pull-up resistance
OE, configured active High
–
200
–
k:
RD
Internal pull-down resistance
OE, configured active Low
–
200
–
k:
FS0, FS1 pins
–
100
–
k:
Notes
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation
of the device at these or at any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to
Absolute-Maximum-Rated conditions for extended periods may affect device reliability or cause permanent device damage.
2. IDD is the total supply current and is measured with VDD and VDDO shorted together.
3. Maximum current 3 mA lesser with HFF Crystal.
4. In ClockWizard 2.1, setting the output standard to LVPECL2 configures the output to "LVPECL without common mode current". Refer to AN210253 for LVPECL
terminations for different use case configurations.
5. I2C operation applicable for VDD of 1.8 V and 2.5 V only.
Document Number: 001-90233 Rev. *K
Page 7 of 25
CY51X7
DC Specifications for LVDS Output
(VDDO = 1.8 V, 2.5 V, or 3.3 V range)
Parameter
VOCM
[6]
Description
Output common-mode voltage
'VOCM
Change in VOCM between
complementary output states
IOZ
Output leakage current
Conditions
Min
Typ
Max
Units
1.125
1.200
1.375
V
–
–
–
50
mV
Output off, VOUT = 0.75 V to 1.75V
–20
–
20
PA
VDDO = 2.5-V or 3.3-V range
DC Specifications for LVPECL Output
(VDDO = 2.5 V or 3.3 V range, with common mode current)
Typ
Max
Units
VOH
Parameter
Output high voltage
Description
R-term = 50 : to VTT (VDDO – 2.0 V) VDDO – 1.165
Conditions
Min
–
VDDO – 0.800
V
VOL
Output low voltage
R-term = 50 : to VTT (VDDO – 2.0 V)
–
VDDO – 1.55
V
Max
Units
VDDO
V
VDDO – 0.32
V
VDDO – 2.0
DC Specifications for CML Output
(VDDO = 1.8 V, 2.5 V, or 3.3 V range)
Parameter
Description
Conditions
VOH
Output high voltage
R-term = 50 : to VDDO
VOL
Output low voltage
R-term = 50 : to VDDO
Min
Typ
VDDO – 0.085 VDDO – 0.01
VDDO – 0.6
VDDO – 0.4
Note
6. Requires external AC coupling for VDDO = 1.8-V range, as indicated in Figure 8. The common-mode voltage of 1.2V has to be generated and applied externally.
Document Number: 001-90233 Rev. *K
Page 8 of 25
CY51X7
DC Specifications for HCSL Output
(VDDO = 1.8 V, 2.5 V, or 3.3 V range)
Parameter
Description
Conditions
Min
Typ
Max
Units
VMAX[7]
Max output high voltage
Measurement taken from
single-ended waveform
–
–
1150
mV
VMIN[7]
Min output low voltage
Measurement taken from
single-ended waveform
–300
–
–
mV
VOHDIFF
Differential output high voltage
Measurement taken from differential waveform
150
–
–
mV
VOLDIFF
Differential output low voltage
Measurement taken from differential waveform
–
–
–150
mV
VCROSS[7]
Absolute crossing point voltage
Measurement taken from
single-ended waveform
250
–
600
mV
VCROSSDELTA[7]
Variation of VCROSS over all rising Measurement taken from
clock edges
single-ended waveform
–
–
140
mV
Min
Typ
Max
Units
100-PA load
VDDO – 0.2
–
–
4-mA load, VDD = 1.8 V and 2.5 V
VDDO – 0.4
–
–
4-mA load, VDD = 3.3 V
VDDO – 0.3
–
–
100-PA load
–
–
0.2
4-mA load
–
–
0.3
DC Specifications for LVCMOS Output
Parameter[7]
VOH
VOL
Description
Output high voltage
Output low voltage
Condition
V
V
VCXO Specific Parameters
Parameter[7]
Description
Condition
Min
Typ
Max
Units
± 50
–
± 275
ppm
Deviation from BSL line
–5
–
5
%
–10
–
10
%
5
10
20
kHz
0
–
VDD
V
TPR
Total pull range
VC range 0.1 × VDD to 0.9 × VDD
KBSL
Best-fit straight line (BSL)
linearity
KINC
Incremental linearity
Kv slope deviation
KBW
Bandwidth of Kv modulation
Programmable
KRANGE
voltage range on the control port
permissible
VCTYP
Nominal center VC control
voltage
RVCIN[8]
Input resistance for VC
VRANGE
Input voltage range
–
VDD configuration = 1.8 V
–
0.9
–
V
VDD configuration = 2.5 V
–
1.25
–
V
VDD configuration = 3.3 V
–
1.65
–
V
5
–
–
M:
0.1 × VDD
–
0.9 × VDD
V
–
Range of input possible at control
port
Notes
7. Parameters are guaranteed by design and characterization. Not 100% tested in production.
8. RVCIN is 100% tested.
Document Number: 001-90233 Rev. *K
Page 9 of 25
CY51X7
AC Electrical Specifications for LVPECL, LVDS, CML Outputs
(VDD = 3.3 V and 2.5 V for LVPECL, with common mode current, and VDD = 3.3 V, 2.5 V, and 1.8 V for LVDS and CML outputs)
Parameter[9]
Description
Details/Conditions
Min
Typ
Max
Unit
Clock Output Frequency
LVPECL, CML, LVDS output
standards
15
–
2100
MHz
LVPECL Output Rise/Fall Time
20% to 80% of AC levels.
Measured at 156.25 MHz for PECL
outputs.
–
–
350
ps
CML Output Rise/Fall Time
20% to 80% of AC levels.
Measured at 156.25 MHz for CML
outputs.
–
–
350
ps
LVDS Output Rise/Fall Time
20% to 80% of AC levels.
Measured at 156.25 MHz for LVDS
outputs.
–
–
350
ps
tODC
Output Duty Cycle
Measured at differential 50% level,
156.25 MHz.
45
50
55
%
VP
LVDS output differential peak
15 MHz to 700 MHz
247
–
454
mV
VP
LVDS output differential peak
700 MHz to 2100 MHz
150
–
454
mV
'VP
Change in VP between
complementary output states
–
–
50
mV
fOUT
tRF
VP
–
450
–
–
mV
350
–
–
mV
VP
LVPECL output differential peak fOUT = 325 MHz to 700 MHz
fOUT = 700 MHz to 2100 MHz
250
–
–
mv
VP
CML output differential peak
fOUT = 15 MHz to 700 MHz
250
–
600
mV
VP
CML output differential peak
fOUT = 700 MHz to 2100 MHz
200
–
600
mV
tCCJ
Cycle to Cycle Jitter
pk, measured at differential signal,
156.25 MHz, over 10k cycles,
100 MHz–130 MHz crystal
–
–
50
ps
tPJ
Period Jitter
pk-pk, measured at differential
signal, 156.25 MHz, over 10k
cycles, 100 MHz–130 MHz crystal
–
–
50
ps
JRMS
RMS Phase Jitter
fOUT = 156.25 MHz, 12 kHz–20
MHz offset, non-VCXO mode
–
150
250
fs
VP
fOUT = 15 MHz to 325 MHz
Non-VCXO Mode
PN1k
Phase Noise, 1 kHz Offset
100-130 MHz crystal reference,
fOUT = 156.25 MHz
–
–
-113
dBc/
Hz
PN10k
Phase Noise, 10 kHz Offset
100-130 MHz crystal reference,
fOUT = 156.25 MHz
–
–
-127
dBc/
Hz
PN100k
Phase Noise, 100 kHz Offset
100-130 MHz crystal reference,
fOUT = 156.25 MHz
–
–
-135
dBc/
Hz
PN1M
Phase Noise, 1MHz Offset
100-130 MHz crystal reference,
fOUT = 156.25 MHz
–
–
-144
dBc/
Hz
PN10M
Phase Noise, 10 MHz Offset
100-130MHz crystal reference,
fOUT = 156.25 MHz
–
–
–152
dBc/
Hz
PN-SPUR
Spur
At frequency offsets equal to and
greater than the update rate of the
PLL
–
–
–65
dBc/
Hz
Note
9. Parameters are guaranteed by design and characterization. Not 100% tested in production.
Document Number: 001-90233 Rev. *K
Page 10 of 25
CY51X7
AC Electrical Specifications for HCSL Output
Parameter[10]
Min
Typ
Max
Units
fOUT
Output frequency
Description
HCSL
Test Conditions
15
–
700
MHz
ER
Rising edge rate
Measured taken from differential
waveform, –150 mV to +150 mV
0.6
–
5.7 [11]
V/ns
EF
Falling edge rate
Measured taken from differential
waveform, –150 mV to +150 mV
0.6
–
5.7 [11]
V/ns
tSTABLE
Time before voltage ring back
(VRB) is allowed
Measured taken from differential
waveform, –150 mV to +150 mV
500
–
–
ps
R-F_MATCHING Rise-Fall matching
Measured taken from
single-ended waveform, rising
edge rate to falling edge rate
matching, 100 MHz
–100
–
100
ps
tDC
Output duty cycle
Measured taken from differential
waveform, fOUT = 100 MHz
45
–
55
%
tCCJ
Cycle to cycle Jitter
Measured taken from differential
waveform, 100 MHz
–
–
50
ps
JRMSPCIE
Random jitter, PCIE
Specification 3.0
100 MHz–130 MHz crystal
–
–
1
ps
(RMS
)
Min
Typ
Max
Unit
15
–
250
MHz
Measured at 1/2 VDDO, loaded,
fOUT < 100 MHz
45
–
55
%
Measured at 1/2 VDDO, loaded,
fOUT > 100 MHz
40
–
60
%
VDDO = 1.8 V, 20%–80%
–
–
2
ns
VDDO = 2.5 V, 20%–80%
–
–
1.5
ns
VDDO = 3.3 V, 20%–80%
–
–
1.2
ns
–
–
50
ps
–
–
100
ps
AC Electrical Specifications for LVCMOS Output
(Load: 10 pF < 100 MHz, 7.5 pF < 150 MHz, 5 pF > 150 MHz)
Parameter[10]
fOUT
tDC
tRFCMOS
Description
Test Conditions
Output frequency
Output duty cycle
Rise/Fall time
tCCJ
Cycle to cycle Jitter
pk, Measured at 1/2VDDO
over 10k cycle,
fOUT = 156.25 MHz
tPJ
Period Jitter
pk, Measured at 1/2VDDO
over 10k cycle,
fOUT = 156.25 MHz
Notes
10. Parameters are guaranteed by design and characterization. Not 100% tested in production.
11. Edge rates are higher than 4 V/ns due to jitter performance requirements.
Document Number: 001-90233 Rev. *K
Page 11 of 25
CY51X7
HFF Crystal Specifications
Parameter[12]
Description
Test Conditions
Min
Typ
Max
Unit
fXTAL
Crystal frequency range
–
100
–
130
MHz
C0
Crystal shunt capacitance
–
–
–
2
pF
CL
Crystal load capacitance
–
–
5
–
pF
ESR
Crystal equivalent series
resistance
–
20
–
:
DL
Drive level
–
–
–
200
PW
Test Conditions
Min
Typ
Max
Units
–
100
–
130
MHz
2
ESR = Rm (1 + C0/CL) ^ 2
Rm = Crystal motional resistance
OT3 Crystal Specifications
Parameter[12]
fXTAL
Description
Crystal frequency range
C0
Crystal shunt capacitance
–
–
–
CL
Crystal load capacitance
–
–
5
ESR
Crystal equivalent series
resistance
–
60
90
:
DL
Drive level
–
–
–
200
PW
Test Conditions
Min
Typ
Max
Units
ESR = Rm (1 + C0/CL) ^ 2
Rm = Crystal motional resistance
pF
pF
LFF Crystal Specifications
Parameter[12]
Description
fXTAL
Crystal frequency range
–
50
–
60
MHz
C0
Crystal shunt capacitance
–
–
–
2
pF
CL
Crystal load capacitance
–
–
–
8
pF
ESR
Crystal equivalent series
resistance
–
–
90
W
DL
Drive level
–
–
200
PW
Test Conditions
Min
Typ
Max
Units
–
50
–
60
MHz
ESR = Rm (1 + C0/CL) ^ 2
Rm = Crystal motional resistance
–
LF Low Frequency Reference
(TCXO reference input)
Parameter[12]
Description
fIN
Input frequency
tDC
Input duty cycle
Measured at 1/2 input swing
40
–
60
%
VPP
pk-pk input swing
AC coupled input
0.8
–
1.2
V
VIL
Input low voltage
DC coupled input
–
–
0.2
V
VIH
Input high voltage
DC coupled input
0.8
–
1.2
V
tR
Input rise time
20%–80% of input
–
–
1.5
ns
tF
Input fall time
20%–80% of input
–
–
1.5
ns
PN10K
Input phase noise
10-kHz offset
–
–
–151
dBc/H
z
PN100K
Input phase noise
100-kHz offset
–
–
–155
dBc/H
z
PN1M
Input phase noise
1-MHz offset
–
–
–156
dBc/H
z
Note
12. Parameters are guaranteed by design and characterization. Not 100% tested in production.
Document Number: 001-90233 Rev. *K
Page 12 of 25
CY51X7
Timing Parameters
Parameter[13]
Min
Max
Unit
0.01
3000
ms
Time from minimum specified power supply to 2000 V” with “2000 V” in value corresponding to “ESD HBM”.
Replaced “> 200 V” with “200 V” in value corresponding to “ESD MM”.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated to new template.
Updated Functional Overview:
Updated Frequency Configurations:
Added Table 2.
Updated DC Electrical Specifications:
Removed Note “Parameters are guaranteed by design and characterization.
Not 100% tested in production.” and its reference.
Updated details in “Test Conditions” column corresponding to IDD parameter.
Updated DC Specifications for HCSL Output:
Referred Note 7 in VMAX, VMIN, VCROSS and VCROSSDELTA parameters.
Updated VCXO Specific Parameters:
Added Note 8 and referred the same note in “RVCIN” parameter.
Updated AC Electrical Specifications for LVCMOS Output:
Referred Note 10 in “Parameter” column.
Updated HFF Crystal Specifications:
Added Note 12 and referred the same note in “Parameter” column.
Updated OT3 Crystal Specifications:
Referred Note 12 in “Parameter” column.
Updated LFF Crystal Specifications:
Referred Note 12 in “Parameter” column.
Updated LF Low Frequency Reference:
Referred Note 12 in “Parameter” column.
Updated Phase Jitter Characteristics:
Added Note 15 and referred the same note in “Parameter” column.
Updated I2C Bus Timing Specifications:
Referred Note 12 in “Parameter” column.
Updated Voltage and Timing Definitions:
Added Figure 9.
Added Note 17 and referred the same note in Figure 9.
Updated Ordering Information:
Updated part numbers.
Updated Note 18.
Added Note 19 and referred the same note in “CY5117-1X07I”.
Added Packaging Information.
Updated to new template.
*F
5429121
09/07/2016
Description of Change
*G
5518357
11/15/2016
MGPL /
PSR
*H
5537710
11/30/2016
TAVA
Updated Ordering Code Definitions under Ordering Information.
PSR
Added links to ClockWizard 2.1 and technical support, and added reference to
related documentation in Functional Description.
Updated LVPECL specs in DC Electrical Specifications.
Added note clarifying voltage range in AC Electrical Specifications for LVPECL,
LVDS, CML Outputs.
Updated Ordering Information.
*I
5613574
02/03/2017
Document Number: 001-90233 Rev. *K
Page 23 of 25
CY51X7
Document History Page (continued)
Document Title: CY51X7, High-Performance PLL Die for Oscillators
Document Number: 001-90233
Rev.
ECN No.
Submission
Date
Orig. of
Change
*J
5682054
04/03/2017
PSR
Updated the template.
Replaced the Waffle tray diagram with the Cypress drawing 51-52100.
Added Clock Tree Services to Sales, Solutions, and Legal Information.
*K
5755392
06/01/2017
PSR
Updated Cypress logo and Sales information.
Updated VCXO Specific Parameters.
Updated Figure 18 (spec 51-52100 *F to *G) in Packaging Information.
Document Number: 001-90233 Rev. *K
Description of Change
Page 24 of 25
CY51X7
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
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Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2013-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-90233 Rev. *K
Revised June 1, 2017
Page 25 of 25
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