CY62157E MoBL®
8-Mbit (512K x 16) Static RAM
8-Mbit (512K x16) Static RAM
is ideal for providing More Battery Life (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
into standby mode when deselected (CE1 HIGH or CE2 LOW or
both BHE and BLE are HIGH). The input or output pins (I/O0
through I/O15) are placed in a high impedance state when:
Features
■
Very high speed: 45 ns
❐ Industrial: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
■
Wide voltage range: 4.5V–5.5V
■
Ultra low standby power
❐ Typical standby current: 2 A
❐ Maximum standby current: 8 A (Industrial)
■
Deselected (CE1HIGH or CE2 LOW)
■
Outputs are disabled (OE HIGH)
■
Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
■
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■
Ultra low standby power
■
Write operation is active (CE1 LOW, CE2 HIGH and WE LOW)
■
Easy memory expansion with CE1, CE2 and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
package
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A18). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A18).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See the “Truth Table” on
page 10 for a complete description of read and write modes.
Functional Description
[1]
The CY62157E is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
Logic Block Diagram
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CE2
512K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
CE1
A17
A18
A15
A16
BLE
A14
BHE
BHE
A11
A12
A13
Power Down
Circuit
SENSE AMPS
DATA IN DRIVERS
WE
CE2
OE
BLE
CE1
Note
1. For best practice recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05695 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 20, 2010
[+] Feedback
CY62157E MoBL®
Contents
Product Portfolio .............................................................. 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ....................................................................... 4
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 5
Data Retention Waveform................................................. 5
Thermal Resistance .......................................................... 5
Switching Characteristics ................................................ 6
Document #: 38-05695 Rev. *G
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 2 of 15
[+] Feedback
CY62157E MoBL®
Product Portfolio
Power Dissipation
Product
Speed
(ns)
VCC Range (V)
Range
Operating ICC, (mA)
f = 1 MHz
Min
Typ[2]
Max
Standby, ISB2
(A)
f = fmax
Typ[2]
Max
Typ[2]
Max
Typ[2]
Max
CY62157ELL
Industrial
4.5
5.0
5.5
45
1.8
3
18
25
2
8
CY62157ELL
Automotive
4.5
5.0
5.5
55
1.8
4
18
35
2
30
Pin Configuration
The following pictures show the TSOP II and VFBGA pinouts.[3, 4]
VFBGA
TSOP II
Top View
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A18
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
A12
A13
Top View
4
3
1
2
BLE
OE
A0
I/O8
BHE
I/O9
5
6
A1
A2
CE2
A
A3
A4
CE1
I/O0
B
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
Vcc
D
VCC
I/O12
NC
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
3. NC pins are not connected on the die.
4. The 44-pin TSOP II package has only one chip enable (CE) pin.
Document #: 38-05695 Rev. *G
Page 3 of 15
[+] Feedback
CY62157E MoBL®
DC Input Voltage[5, 6] ........................................–0.5V to 6.0V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage .......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current .................................................... > 200 mA
Operating Range
Supply Voltage to Ground
Potential ...........................................................–0.5V to 6.0V
DC Voltage Applied to Outputs
in High-Z State[5, 6] ...........................................–0.5V to 6.0V
Device
Range
Ambient
Temperature
VCC[7]
CY62157ELL
Industrial
–40°C to +85°C
4.5V to 5.5V
Automotive –40°C to +125°C
Electrical Characteristics
Over the Operating Range
Parameter
Description
45 ns (Industrial)
Test Conditions
Min
Typ[8]
Max
VOH
Output HIGH
Voltage
IOH = –1 mA
2.4
VOL
Output LOW
Voltage
IOL = 2.1 mA
VIH
Input HIGH
Voltage
VCC = 4.5V to 5.5V
2.2
VCC + 0.5
VIL
Input LOW
Voltage
VCC = 4.5V to 5.5V
–0.5
IIX
Input Leakage
Current
GND < VI < VCC
IOZ
Output Leakage GND < VO < VCC, Output Disabled
Current
ICC
VCC Operating
Supply
Current
f = fmax = 1/tRC VCC = VCC(max)
IOUT = 0 mA
f = 1 MHz
CMOS levels
ISB1
Automatic CE
Power Down
Current —
CMOS Inputs
ISB2 [9]
Automatic CE
Power Down
Current —
CMOS Inputs
55 ns (Automotive)
Min
Typ[8]
Unit
Max
2.4
V
0.4
0.4
V
2.2
VCC + 0.5
V
0.8
–0.5
0.8
V
–1
+1
–4
+4
A
–1
+1
–4
+4
A
mA
18
25
18
35
1.8
3
1.8
4
CE1 > VCC 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V, VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = VCC(max)
2
8
2
30
A
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCC(max)
2
8
2
30
A
Capacitance[10]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Notes
5. VIL(min) = –2.0V for pulse durations less than 20 ns for I < 30 mA.
6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
9. Chip enables (CE1 and CE2) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05695 Rev. *G
Page 4 of 15
[+] Feedback
CY62157E MoBL®
Thermal Resistance [11]
TSOP II
VFBGA
Unit
JA
Parameter
Thermal Resistance Still Air, soldered on a 3 × 4.5 inch,
(Junction to Ambient) two-layer printed circuit board
Description
Test Conditions
77
72
°C/W
JC
Thermal Resistance
(Junction to Case)
13
8.86
°C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
VCC
OUTPUT
R1
3V
30 pF
10%
GND
Rise Time = 1 V/ns
R2
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
R1
R2
RTH
VTH
Values
1800
990
639
1.77
Unit
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
[11]
Conditions
Typ [12]
Max
2
VCC=2V, CE1> VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Chip Deselect to Data
Retention Time
tR [13]
Min
Operation Recovery Time
Unit
V
A
Industrial
8
Automotive
30
0
ns
tRC
ns
Data Retention Waveform[14]
Figure 2. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 2V
VCC(min)
tR
CE1 or
BHE.BLE
or
CE2
Notes
11. Tested initially and after any design or process changes that may affect these parameters.
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document #: 38-05695 Rev. *G
Page 5 of 15
[+] Feedback
CY62157E MoBL®
Switching Characteristics
Over the Operating Range[15, 16]
Parameter
Description
45 ns (Industrial)
Min
Max
55 ns (Automotive)
Min
Max
Unit
Read Cycle
tRC
45
Read Cycle Time
55
45
ns
55
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW and CE2 HIGH to Data Valid
45
55
ns
tDOE
OE LOW to Data Valid
22
25
ns
20
ns
LOW-Z[17]
tLZOE
OE LOW to
tHZOE
OE HIGH to High-Z[17, 18]
tLZCE
CE1 LOW and CE2 HIGH to Low-Z[17]
tHZCE
CE1 HIGH and CE2 LOW to
10
10
5
10
High-Z[17, 18]
ns
5
18
ns
10
18
ns
ns
20
ns
tPU
CE1 LOW and CE2 HIGH to Power Up
tPD
CE1 HIGH and CE2 LOW to Power Down
45
55
ns
tDBE
BLE/BHE LOW to Data Valid
45
55
ns
tLZBE
tHZBE
BLE/BHE LOW to
Low-Z[17]
BLE/BHE HIGH to
HIGH-Z[17, 18]
0
0
10
ns
10
18
ns
20
ns
Write Cycle[19]
tWC
Write Cycle Time
45
55
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
35
40
ns
tAW
Address Setup to Write End
35
40
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Setup to Write Start
0
0
ns
tPWE
WE Pulse Width
35
40
ns
tBW
BLE/BHE LOW to Write End
35
40
ns
tSD
Data Setup to Write End
25
25
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
tLZWE
WE LOW to
High-Z[17, 18]
WE HIGH to
Low-Z[17]
18
10
20
10
ns
ns
Notes
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 5.
16. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
17. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
19. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH. All signals must be active to initiate a
write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
Document #: 38-05695 Rev. *G
Page 6 of 15
[+] Feedback
CY62157E MoBL®
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[20, 21]
Figure 3. Read Cycle No. 1
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[21, 22]
Figure 4. Read Cycle No. 2
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
20. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.
21. WE is HIGH for read cycle.
22. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05695 Rev. *G
Page 7 of 15
[+] Feedback
CY62157E MoBL®
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[23, 24, 25]
Figure 5. Write Cycle No. 1
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
tHD
OE
DATA I/O
tSD
NOTE 26
VALID DATA
tHZOE
Write Cycle No. 2 (CE1 or CE2 Controlled)[23, 24, 25]
Figure 6. Write Cycle No. 2
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 26
tHD
VALID DATA
tHZOE
Notes
23. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH. All signals must be active to initiate a
write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
24. Data I/O is high impedance if OE = VIH.
25. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
26. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 38-05695 Rev. *G
Page 8 of 15
[+] Feedback
CY62157E MoBL®
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[27]
Figure 7. Write Cycle No. 3
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA I/O
NOTE 28
tHD
VALID DATA
tLZWE
tHZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[27]
Figure 8. Write Cycle No. 4
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 28
tHD
VALID DATA
Notes
27. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
28. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 38-05695 Rev. *G
Page 9 of 15
[+] Feedback
CY62157E MoBL®
Truth Table
CE1
WE
OE
BHE
BLE
[29]
Mode
Power
X
X
X
X
High-Z
Deselect/Power Down
Standby (ISB)
L
X
X
X
X
High-Z
Deselect/Power Down
Standby (ISB)
X[29]
X[29]
X
X
H
H
High-Z
Deselect/Power Down
Standby (ISB)
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
High-Z (I/O8–I/O15)
Read
Active (ICC)
L
H
H
L
L
H
High-Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
L
H
H
H
L
H
High-Z
Output Disabled
Active (ICC)
L
H
H
H
H
L
High-Z
Output Disabled
Active (ICC)
L
H
H
H
L
L
High-Z
Output Disabled
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (I/O0–I/O7);
High-Z (I/O8–I/O15)
Write
Active (ICC)
L
H
L
X
L
H
High-Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
H
[29]
X
CE2
X
Inputs/Outputs
Note
29. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document #: 38-05695 Rev. *G
Page 10 of 15
[+] Feedback
CY62157E MoBL®
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
45
CY62157ELL-45ZSXI
51-85087
44-pin Thin Small Outline Package Type II (Pb-free)
Industrial
55
CY62157ELL-55ZSXE
51-85087
44-pin Thin Small Outline Package Type II (Pb-free)
Automotive
CY62157ELL-55BVXE
51-85150
48-ball Very Fine Pitch Ball Grid Array (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 5
7
E
LL xx
xxx
I
Temperature Range: I = Industrial, A = Automotive-A, E = Automotive-E
ZSX = 44-pin TSOP II (Pb-free), BVX = 48-ball VFBGA (Pb-free) Pinout - 1
xx = Speed Grade
Low Power
E = Process Technology 90 nm
Buswidth = × 6
Density = 8-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document #: 38-05695 Rev. *G
Page 11 of 15
[+] Feedback
CY62157E MoBL®
Package Diagrams
Figure 9. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
51-85150 *F
Document #: 38-05695 Rev. *G
Page 12 of 15
[+] Feedback
CY62157E MoBL®
Package Diagrams (continued)
Figure 10. 44-Pin TSOP II, 51-85087
PIN 1 I.D.
11.938 (0.470)
11.735 (0.462)
10.262 (0.404)
10.058 (0.396)
1
22
Z Z Z
Z X Z
AA
44
23
BOTTOM VIEW
TOP VIEW
0.800 BSC
(0.0315)
0.400(0.016)
0.300 (0.012)
EJECTOR MARK
(OPTIONAL)
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
BASE PLANE
10.262 (0.404)
10.058 (0.396)
0.10 (.004)
18.517 (0.729)
18.313 (0.721)
0.150 (0.0059)
0.050 (0.0020)
1.194 (0.047)
0.991 (0.039)
DIMENSION IN MM (INCH)
MAX
MIN.
Document #: 38-05695 Rev. *G
0.210 (0.0083)
0.120 (0.0047)
0°-5°
SEATING
PLANE
0.597 (0.0235)
0.406 (0.0160)
51-85087-*C
Page 13 of 15
[+] Feedback
CY62157E MoBL®
Document History Page
Document Title: CY62157E MoBL®, 8-Mbit (512K x 16) Static RAM
Document Number: 38-05695
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
291273
See ECN
PCI
New data sheet
*A
457689
See ECN
NXR
Added Automotive Product
Removed Industrial Product
Removed 35 ns and 45 ns speed bins
Removed “L” bin
Updated AC Test Loads table
Corrected tR in Data Retention Characteristics from 100 s to tRC ns
Updated the Ordering Information and replaced the Package Name column
with Package Diagram
*B
467033
See ECN
NXR
Added Industrial Product (Final Information)
Removed 48 ball VFBGA package and its relevant information
Changed the ICC(typ) value of Automotive from 2 mA to 1.8 mA for f = 1MHz
Changed the ISB2(typ) value of Automotive from 5 A to 1.8 A
Modified footnote #4 to include current limit
Updated the Ordering Information table
*C
569114
See ECN
VKN
Added 48 ball VFBGA package
Updated Logic Block Diagram
Added footnote #3
Updated the Ordering Information table
*D
925501
See ECN
VKN
Added footnote #9 related to ISB2 and ICCDR
Added footnote #14 related AC timing parameters
*E
1045801
See ECN
VKN
Converted Automotive specs from preliminary to final
*F
2934396
06/03/10
VKN
Added footnote #23 related to chip enable
Updated package diagrams
Updated template.
*G
3110053
12/14/2010
PRAS
Document #: 38-05695 Rev. *G
Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
Page 14 of 15
[+] Feedback
CY62157E MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05695 Rev. *G
Revised December 20, 2010
Page 15 of 15
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback
工商网监
湘ICP备2023018690号
