CY7C63310/CY7C638xx
enCoRe™ II
Low Speed USB Peripheral Controller
enCoRe™ II Low Speed USB Peripheral Controller
Features
■
■
USB 2.0-USB-IF certified (TID # 40000085)
■
enCoRe™ II USB - ‘enhanced Component Reduction’
■
■
■
■
Up to 20 GPIO pins
❐
2 mA source current on all GPIO pins. Configurable 8 or
50 mA/pin current sink on designated pins.
Crystalless oscillator with support for an external clock. The
internal oscillator eliminates the need for an external crystal
or resonator.
❐
Each GPIO port supports high impedance inputs,
configurable pull-up, open drain output, CMOS/TTL inputs,
and CMOS output
❐
Two internal 3.3 V regulators and an internal USB Pull-up
resistor
❐
Maskable interrupts on all I/O pins
❐
Configurable I/O for real world interface without external
components
USB Specification compliance
❐
Conforms to USB Specification, Version 2.0
❐
Conforms to USB HID Specification, Version 1.1
❐
Supports one low speed USB device address
❐
Supports one control endpoint and two data endpoints
❐
Integrated USB transceiver with dedicated 3.3 V regulator for
USB signalling and D– pull-up.
■
A dedicated 3.3 V regulator for the USB PHY. Aids in signalling
and D– line pull-up
■
125 mA 3.3 V voltage regulator powers external 3.3 V devices
■
3.3 V I/O pins
■
Enhanced 8-bit microcontroller
❐
■
❐
❐
❐
■
GPIO ports
Harvard architecture
M8C CPU speed is up to 24 MHz or sourced by an external
clock signal
■
Internal memory
❐
Up to 256 bytes of RAM
❐
Up to eight Kbytes of flash including EEROM emulation
Interface can auto configure to operate as PS/2 or USB
❐
No external components for switching between PS/2 and
USB modes
❐
No General Purpose I/O (GPIO) pins required to manage
dual mode capability
Low power consumption
❐
Typically 10 mA at 6 MHz
❐
10 A sleep
In system reprogrammability
❐
Allows easy firmware update
Cypress Semiconductor Corporation
Document Number: 38-08035 Rev. *T
•
■
❐
4 I/O pins with 3.3 V logic levels
❐
Each 3.3 V pin supports high impedance input, internal
pull-up, open drain output or traditional CMOS output
SPI serial communication
❐
Master or slave operation
❐
Configurable up to 4 Mbps transfers in the master mode
❐
Supports half duplex single data line mode for optical sensors
2-channel 8-bit or 1-channel 16-bit capture timer registers.
Capture timer registers store both rising and falling edge times.
❐
Two registers each for two input pins
❐
Separate registers for rising and falling edge capture
❐
Simplifies the interface to RF inputs for wireless applications
Internal low power wakeup timer during suspend mode:
❐
Periodic wakeup with no external components
■
12-bit Programmable Interval Timer with interrupts
■
Advanced development tools based on Cypress PSoC® tools
■
Watchdog timer (WDT)
■
Low-voltage detection with user configurable threshold
voltages
■
Operating voltage from 4.0 V to 5.5 V DC
■
Operating temperature from 0 °C–70 °C
■
Available in 18-pin PDIP; 16, 18, and 24-pin SOIC; 24-pin
QSOP, and 24-pin and 32-pin QFN Sawn packages
■
Industry standard programmer support
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 27, 2017
CY7C63310/CY7C638xx
Applications
❐
The CY7C63310/CY7C638xx is targeted for the following
applications:
■
PC HID devices
❐
■
■
Mice (optomechanical, optical, trackball)
Gaming
❐
Joysticks
Game pad
General purpose
❐
Barcode scanners
❐
POS terminal
❐
Consumer electronics
❐
Toys
❐
Remote controls
❐
Security dongles
Logic Block Diagram
3.3V
Regulator
Low-Speed
USB/PS2
Transceiver
and Pull up
Low-Speed
USB SIE
Interrupt
Control
4 3.3 V I/O /
SPI Pins
Up to 14
Extended
IO Pins
Up to 6
GPIO
pins
Wakeup
Timer
Internal
24 MHz
Oscillator
M8C CPU
Clock
Control
RAM
Up to 256
Byte
Flash
Up to 8K
Byte
12-bit Timer
16-bit Free
running
timer
External Clock
Watchdog
Timer
Vdd
POR /
Low-Voltage
Detect
Document Number: 38-08035 Rev. *T
Page 2 of 92
CY7C63310/CY7C638xx
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right enCoRe II device for your design, and to help
you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the product webpage
http://www.cypress.com/?id=182.
■
■
■
■
Overview: USB Portfolio, USB Roadmap.
USB Low Speed Product Selectors: enCoRe II, PRoC-LP,
PRoC-LPstar.
Application notes: Cypress offers a large number of USB
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with FX3 are:
❐ AN6062 - enCoRe™ to enCoRe II Conversion.
❐ AN6075 - enCoRe™ II USB Bootloader.
❐ AN15482 - Using Capture Timers in enCoRe™ II and
enCoRe II LV Devices.
■
User Module Datasheets:
❐ User Module Datasheet: USB DEVICE DATASHEET, USB V
1.90 (CY7C639/638/633XX, CYRF69XX3).
❐ User Module Datasheet: 12-Bit Programmable Interval Timer
Datasheet, PITIMER12 V 1.1
(CY7C639/638/633/601/602XX, CYRF69XX3).
❐ User Module Datasheet: 1 Millisecond Interval Timer
Datasheet, MSTIMER V 1.2 (CY7C639/638/633/602/601XX,
CYRF69XX3).
❐ User Module Datasheet: SPI Master Datasheet SPIM V 1.30
(CY7C639/638/633/602/601xx, CYRF69xx3).
❐ User Module Datasheet: EEPROM Datasheet E2PROM V
0.40 (CY7C633/638/639/601/602xx, CYRF69xx3).
❐ User Module Datasheet: CyFi™ Star Network Protocol Stack
Datasheet CYFISNP V 2.00 (CY7C601/602xx, CYRF69x13,
CYRF89235, CYRF89435).
❐ User Module Datasheet: SPI-based CyFi™ Transceiver Data
Sheet CYFISPI (CY7C638x3, CY7C601/602xx,
CYRF69103, CYRF69213).
■
Development Kits:
❐ CY3216 Modular Programmer Kit.
❐ CY3655 enCoRe™ II Development Kit.
■
Reference Designs:
❐ CY4623 Mouse Reference Design.
■
Models: IBIS.
Code Examples:
❐ CE58786 - Implementing Pin Specific Interrupts in enCoRe™
II / enCoRe II LV.
PSoC Designer
PSoC Designer is the revolutionary Integrated Design Environment (IDE) that you can use to customize PSoC to meet your specific
application requirements. PSoC Designer software accelerates system bring-up and time-to-market. Develop your applications using
a library of pre-characterized analog and digital peripherals in a drag-and-drop design environment. Then, customize your design
leveraging the dynamically generated API libraries of code. Finally, debug and test your designs with the integrated debug environment
including in-circuit emulation and standard software debug features.
■
Application Editor GUI for device and User Module configuration and dynamic reconfiguration
■
Extensive User Module Catalog
■
Integrated source code editor (C and Assembly)
■
Free C compiler with no size restrictions or time limits
■
Built-in Debugger
■
Integrated Circuit Emulation (ICE)
■
Built-in Support for Communication Interfaces:
❐ Hardware and software I2C slaves and masters
❐ Low/Full-speed USB 2.0
❐ Up to 4 full-duplex UARTs, SPI master and slave, and Wireless
Document Number: 38-08035 Rev. *T
Page 3 of 92
CY7C63310/CY7C638xx
Contents
Introduction ....................................................................... 5
Conventions ...................................................................... 5
Pinouts .............................................................................. 6
Pin Descriptions ............................................................... 8
CPU Architecture .............................................................. 9
CPU Registers ................................................................. 10
Flags Register ........................................................... 10
Addressing Modes ..................................................... 11
Instruction Set Summary ............................................... 14
Memory Organization ..................................................... 15
Flash Program Memory Organization ....................... 15
Data Memory Organization ....................................... 16
Flash .......................................................................... 16
SROM ........................................................................ 16
SROM Function Descriptions .................................... 17
Clocking .......................................................................... 21
Clock Architecture Description .................................. 23
CPU Clock During Sleep Mode ...................................... 29
Reset ................................................................................ 30
Power on Reset ......................................................... 31
Watchdog Timer Reset .............................................. 31
Sleep Mode ...................................................................... 31
Sleep Sequence ........................................................ 32
Wake up Sequence ................................................... 32
Low Power in Sleep Mode ......................................... 33
Low Voltage Detect Control ........................................... 34
General Purpose I/O (GPIO) Ports ................................ 36
Port Data Registers ................................................... 36
GPIO Port Configuration ........................................... 38
Serial Peripheral Interface (SPI) .................................... 43
SPI Data Register ...................................................... 43
SPI Configure Register .............................................. 44
SPI Interface Pins ...................................................... 45
Timer Registers .............................................................. 46
Registers ................................................................... 46
Interrupt Controller ......................................................... 54
Architectural Description ........................................... 54
Interrupt Processing .................................................. 55
Document Number: 38-08035 Rev. *T
Interrupt Trigger Conditions ....................................... 55
Interrupt Latency ....................................................... 55
Interrupt Registers ..................................................... 56
Regulator Output ............................................................ 61
VREG Control ............................................................ 61
USB/PS2 Transceiver ..................................................... 62
USB Transceiver Configuration ................................. 62
USB Serial Interface Engine (SIE) ................................. 62
USB Device ..................................................................... 63
USB Device Address ................................................. 63
Endpoint 0, 1, and 2 Count ........................................ 63
Endpoint 0 Mode ....................................................... 64
Endpoint 1 and 2 Mode ............................................. 65
USB Mode Tables ........................................................... 67
Mode Column ............................................................ 67
Encoding Column ...................................................... 67
SETUP, IN, and OUT Columns ................................. 67
Details of Mode for Differing Traffic Conditions .......... 67
Register Summary .......................................................... 70
Voltage versus CPU Frequency Characteristics ......... 73
Absolute Maximum Ratings .......................................... 74
DC Characteristics ......................................................... 74
AC Characteristics ......................................................... 76
Ordering Information ...................................................... 82
Ordering Code Definitions ......................................... 82
Package Handling ........................................................... 82
Package Diagrams .......................................................... 83
Acronyms ........................................................................ 87
Document Conventions ................................................. 87
Units of Measure ....................................................... 87
Document History Page ................................................. 88
Sales, Solutions, and Legal Information ...................... 92
Worldwide Sales and Design Support ....................... 92
Products .................................................................... 92
PSoC® Solutions ...................................................... 92
Cypress Developer Community ................................. 92
Technical Support ..................................................... 92
Page 4 of 92
CY7C63310/CY7C638xx
Introduction
Cypress has reinvented its leadership position in the low speed
USB market with a new family of innovative microcontrollers.
Introducing enCoRe II USB - ‘enhanced Component Reduction.’
Cypress has leveraged its design expertise in USB solutions to
advance its family of low speed USB microcontrollers, which
enable peripheral developers to design new products with a
minimum number of components. The enCoRe II USB
technology builds on the enCoRe family. The enCoRe family has
an integrated oscillator that eliminates the external crystal or
resonator, reducing overall cost. Also integrated into this chip are
other external components commonly found in low speed USB
applications, such as pull-up resistors, wakeup circuitry, and a
3.3 V regulator. Integrating these components reduces the
overall system cost.
The enCoRe II is an 8-bit flash programmable microcontroller
with an integrated low speed USB interface. The instruction set
is optimized specifically for USB and PS/2 operations, although
the microcontrollers may be used for a variety of other embedded
applications.
The enCoRe II features up to 20 GPIO pins to support USB,
PS/2, and other applications. The IO pins are grouped into four
ports (Port 0 to 3). The pins on Port 0 and Port 1 may each be
configured individually while the pins on Ports 2 and 3 are
configured only as a group. Each GPIO port supports high
impedance inputs, configurable pull-up, open drain output,
CMOS/TTL inputs, and CMOS output with up to five pins that
support a programmable drive strength of up to 50 mA sink
current. GPIO Port 1 features four pins that interface at a voltage
level of 3.3V. Additionally, each IO pin may be used to generate
a GPIO interrupt to the microcontroller. Each GPIO port has its
own GPIO interrupt vector; in addition, GPIO Port 0 has three
dedicated pins that have independent interrupt vectors
(P0.2–P0.4).
The enCoRe II features an internal oscillator. With the presence
of USB traffic, the internal oscillator may be set to precisely tune
to USB timing requirements (24 MHz ±1.5%). Optionally, an
external 12 MHz or 24 MHz clock is used to provide a higher
precision reference for USB operation. The clock generator
provides the 12 MHz and 24 MHz clocks that remain internal to
the microcontroller. The enCoRe II also has a 12-bit
programmable interval timer and a 16-bit Free Running Timer
with Capture Timer registers. In addition, the enCoRe II includes
a Watchdog timer and a vectored interrupt controller.
The enCoRe II has up to eight Kbytes of flash for user code and
up to 256 bytes of RAM for stack space and user variables.
The power on reset circuit detects logic when power is applied
to the device, resets the logic to a known state, and begins
executing instructions at flash address 0x0000. When power
falls below a programmable trip voltage, it generates a reset or
may be configured to generate an interrupt. There is a low
voltage detect circuit that detects when VCC drops below a
programmable trip voltage. It is configurable to generate an LVD
interrupt to inform the processor about the low voltage event.
Document Number: 38-08035 Rev. *T
POR and LVD share the same interrupt. There is no separate
interrupt for each. The Watchdog timer may be used to ensure
the firmware never gets stalled in an infinite loop.
The microcontroller supports 22 maskable interrupts in the
vectored interrupt controller. Interrupt sources include a USB bus
reset, LVR/POR, a programmable interval timer, a 1.024 ms
output from the free-running timer, three USB endpoints, two
capture timers, four GPIO Ports, three Port 0 pins, two SPI, a
16-bit free running timer wrap, an internal sleep timer, and a bus
active interrupt. The sleep timer causes periodic interrupts when
enabled. The USB endpoints interrupt after a USB transaction
complete is on the bus. The capture timers interrupt when a new
timer value is saved because of a selected GPIO edge event. A
total of seven GPIO interrupts support both TTL or CMOS
thresholds. For additional flexibility on the edge sensitive GPIO
pins, the interrupt polarity is programmed as rising or falling.
The free-running 16-bit timer provides two interrupt sources: the
1.024 ms outputs and the free running counter wrap interrupt.
The programmable interval timer provides up to 1 sec
resolution and provides an interrupt every time it expires. These
timers are used to measure the duration of an event under
firmware control by reading the desired timer at the start and at
the end of an event, then calculating the difference between the
two values. The two 8-bit capture timer registers save a
programmable 8-bit range of the free-running timer when a GPIO
edge occurs on the two capture pins (P0.5, P0.6). The two 8-bit
captures may be ganged into a single 16-bit capture.
The enCoRe II includes an integrated USB serial interface
engine (SIE) that allows the chip to easily interface to a USB
host. The hardware supports one USB device address with three
endpoints.
The USB D+ and D– pins are optionally used as PS/2 SCLK and
SDATA signals so that products are designed to respond to
either USB or PS/2 modes of operation. The PS/2 operation is
supported with internal 5 K pull-up resistors on P1.0 (D+) and
P1.1 (D–), and an interrupt to signal the start of PS/2 activity. In
USB mode, the integrated 1.5 Kpull-up resistor on D– may be
controlled under firmware. No external components are
necessary for dual USB and PS/2 systems, and no GPIO pins
need to be dedicated to switching between modes.
The enCoRe II supports in system programming by using the D+
and D– pins as the serial programming mode interface. The
programming protocol is not USB.
Conventions
In this data sheet, bit positions in the registers are shaded to
indicate which members of the enCoRe II family implement the
bits.
Available in all enCoRe II family members
CY7C638(1/2/3)3 only
Page 5 of 92
CY7C63310/CY7C638xx
Pinouts
Figure 1. Pin Diagrams
Top View
CY7C63801, CY7C63310
16-Pin SOIC
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
P0.1
P0.0
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P1.3/SSEL
P1.2
VCC
P1.1/D–
P1.0/D+
CY7C63803
16-Pin SOIC
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
P0.1
P0.0
VSS
CY7C63813
18-Pin PDIP
SSEL/P1.3
SCLK/P1.4
SMOSI/P1.5
SMISO/P1.6
P1.7
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P1.2/VREG
VCC
P1.1/D–
P1.0/D+
VSS
P0.0
P0.1
P0.2/INT0
P0.3/INT1
CY7C63823
24-Pin QSOP
NC
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
P0.1
P0.0
P2.1
P2.0
NC
1
2
3
4
5
6
7
8
9
10
11
12
Document Number: 38-08035 Rev. *T
24
23
22
21
20
19
18
17
16
15
14
13
P1.7
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P3.1
P3.0
P1.3/SSEL
P1.2/VREG
VCC
P1.1/D–
P1.0/D+
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P1.3/SSEL
P1.2/VREG
VCC
P1.1/D–
P1.0/D+
CY7C63813
18-Pin SOIC
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
P0.1
P0.0
VSS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P1.7
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P1.3/SSEL
P1.2/VREG
VCC
P1.1/D–
P1.0/D+
CY7C63823
24-Pin SOIC
NC
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
P0.1
P0.0
P2.1
P2.0
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
NC
P1.7
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P3.1
P3.0
P1.3/SSEL
P1.2/VREG
VCC
P1.1/D–
P1.0/D+
Page 6 of 92
CY7C63310/CY7C638xx
24
23
NC
NC
NC
22
211 NC
20
NC
19
NC
Figure 2. CY7C63803 24-Pin QFN
NC
1
TIO0/P0.5
2
INT2/P0.4
INT1/P0.3
INT0/P0.2
4
15
5
14
P0.1
6
13
P1.5/MOSI
P1.4/SCLK
P1.3/SSEL
P1.2/VREG
VCC
P1.1 D-
18
17
11
12
9
10
7
16
P0.0
NC
NC
NC
VSS
P1.0 D+
8
QFN
3
P1.6/MISO
P1.7
NC
NC
NC
NC
NC
P0.7
Figure 3. CY7C63833 32-Pin Sawn QFN
32 31 30 29 28 27 26 25
P0.6/TIO1
1
24
P1.5/SMOSI
P0.5/TIO0
2
23
P1.4/SCLK
P3.1
P0.4/INT2
3
22
P0.3/INT1
4
21
P3.0
P0.2/INT0
5
20
P1.3/SSEL
P0.1
6
19
P0.0
7
18
P2.1
8
17
NC
P1.2/VREG
NC
Document Number: 38-08035 Rev. *T
Vdd
P1.1/D-
Vss
P1.0/D+
NC
NC
NC
P2.0
9 10 11 12 13 14 15 16
Page 7 of 92
CY7C63310/CY7C638xx
Pin Descriptions
32
QFN
24
QFN
24
QSOP
24
SOIC
18
SIOC
18
PDIP
16
SOIC
Name
21
–
19
18
–
–
–
P3.0
22
–
20
19
–
–
–
P3.1
9
–
11
11
–
–
–
P2.0
8
–
10
10
–
–
–
P2.1
14
12
14
13
10
15
9
P1.0/D+
GPIO Port 1 bit 0/USB D+ [1]/ISSP-SCLK If this pin is used
as a General Purpose output, it draws current. This pin must
be configured as an input to reduce current draw.
15
13
15
14
11
16
10
P1.1/D–
GPIO Port 1 bit 1/USB D– [1]/ISSP-SDATA If this pin is used
as a General Purpose output, it draws current. This pin must
be configured as an input to reduce current draw.
18
15
17
16
13
18
12
P1.2/VREG GPIO Port 1 bit 2. Configured individually.
3.3V if regulator is enabled. (The 3.3 V regulator is not available
in the CY7C63310 and CY7C63801.) A 1-F min, 2-F max
capacitor is required on Vreg output.
20
16
18
17
14
1
13
P1.3/SSEL GPIO Port 1 bit 3. Configured individually.
Alternate function is SSEL signal of the SPI bus TTL voltage
thresholds. Although Vreg is not available with the
CY7C63310, 3.3 V I/O is still available.
23
17
21
20
15
2
14
P1.4/SCLK GPIO Port 1 bit 4. Configured individually.
Alternate function is SCLK signal of the SPI bus TTL voltage
thresholds. Although Vreg is not available with the
CY7C63310, 3.3 V I/O is still available.
24
18
22
21
16
3
15
P1.5/SMOSI GPIO Port 1 bit 5. Configured individually.
Alternate function is SMOSI signal of the SPI bus TTL voltage
thresholds. Although Vreg is not available with the
CY7C63310, 3.3 V I/O is still available.
25
–
23
22
17
4
16
P1.6/SMISO GPIO Port 1 bit 6. Configured individually.
Alternate function is SMISO signal of the SPI bus TTL voltage
thresholds. Although Vreg is not available with the
CY7C63310, 3.3 V I/O is still available.
26
–
24
23
18
5
–
P1.7
GPIO Port 1 bit 7. Configured individually.
TTL voltage threshold.
7
7
9
9
8
13
7
P0.0
GPIO Port 0 bit 0. Configured individually.
External clock input when configured as Clock In.
6
6
8
8
7
12
6
P0.1
GPIO Port 0 bit 1. Configured individually.
Clock output when configured as Clock Out.
5
5
7
7
6
11
5
P0.2/INT0 GPIO Port 0 bit 2. Configured individually.
Optional rising edge interrupt INT0.
4
4
6
6
5
10
4
P0.3/INT1 GPIO Port 0 bit 3. Configured individually.
Optional rising edge interrupt INT1.
3
3
5
5
4
9
3
P0.4/INT2 GPIO Port 0 bit 4. Configured individually.
Optional rising edge interrupt INT2.
Description
GPIO Port 3. Configured as a group (byte).
GPIO Port 2. Configured as a group (byte).
Note
1. P1.0(D+) and P1.1(D–) pins must be in I/O mode when used as GPIO and in Isb mode.
Document Number: 38-08035 Rev. *T
Page 8 of 92
CY7C63310/CY7C638xx
Pin Descriptions (continued)
32
QFN
24
QFN
24
QSOP
24
SOIC
18
SIOC
18
PDIP
16
SOIC
2
2
4
4
3
8
2
P0.5/TIO0 GPIO Port 0 bit 5. Configured individually
Alternate function Timer capture inputs or Timer output TIO0
1
–
3
3
2
7
1
P0.6/TIO1 GPIO Port 0 bit 6. Configured individually
Alternate function Timer capture inputs or Timer output TIO1
32
–
2
2
1
6
–
P0.7
10
8
1
1
–
–
–
NC
No connect
Name
Description
GPIO Port 0 bit 7. Configured individually
Not present in the 16 pin SOIC package
11
9
12
24
–
–
–
NC
No connect
12
10
–
–
–
–
–
NC
No connect
17
20
–
–
–
–
–
NC
No connect
19
21
–
–
–
–
–
NC
No connect
27
22
–
–
–
–
–
NC
No connect
28
23
–
–
–
–
–
NC
No connect
29
24
–
–
–
–
–
NC
No connect
30
–
–
–
–
–
–
NC
No connect
31
–
–
–
–
–
–
NC
No connect
16
14
16
15
12
17
11
Vcc
Supply
13
11
13
12
9
14
8
VSS
Ground
CPU Architecture
This family of microcontrollers is based on a high performance,
8-bit, Harvard architecture microprocessor. Five registers control
the primary operation of the CPU core. These registers are
affected by various instructions, but are not directly accessible
through the register space by the user.
Table 1. CPU Registers and Register Names
CPU Register
Flags
Register Name
CPU_F
Program Counter
CPU_PC
Accumulator
CPU_A
Stack Pointer
CPU_SP
Index
CPU_X
The Stack Pointer Register (CPU_SP) holds the address of the
current top of the stack in the data memory space. It is affected
by the PUSH, POP, LCALL, CALL, RETI, and RET instructions,
which manage the software stack. It is also affected by the SWAP
and ADD instructions.
The Flag Register (CPU_F) has three status bits: Zero Flag bit
[1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global
Interrupt Enable bit [0] globally enables or disables interrupts.
The user cannot manipulate the Supervisory State status bit [3].
The flags are affected by arithmetic, logic, and shift operations.
The manner in which each flag is changed is dependent upon
the instruction being executed, such as AND, OR, XOR, and
others. See Table 18 on page 14.
The 16-bit Program Counter Register (CPU_PC) allows direct
addressing of the full 8 Kbytes of program memory space.
The Accumulator Register (CPU_A) is the general purpose
register, which holds the results of instructions that specify any
of the source addressing modes.
The Index Register (CPU_X) holds an offset value that is used
in the indexed addressing modes. Typically, this is used to
address a block of data within the data memory space.
Document Number: 38-08035 Rev. *T
Page 9 of 92
CY7C63310/CY7C638xx
CPU Registers
The CPU registers in enCoRe II devices are in two banks with 256 registers in each bank. Bit[4]/XI/O bit in the CPU Flags register
must be set/cleared to select between the two register banks Table 2 on page 10.
Flags Register
The Flags Register is set or reset only with logical instruction.
Table 2. CPU Flags Register (CPU_F) [R/W]
Bit #
7
Field
6
5
Reserved
4
3
2
1
0
XIO
Super
Carry
Zero
Global IE
Read/Write
–
–
–
R/W
R
RW
RW
RW
Default
0
0
0
0
0
0
1
0
Bit [7:5]: Reserved
Bit 4: XIO
Set by the user to select between the register banks
0 = Bank 0
1 = Bank 1
Bit 3: Super
Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user.)
0 = User Code
1 = Supervisor Code
Bit 2: Carry
Set by the CPU to indicate whether there has been a carry in the previous logical/arithmetic operation.
0 = No Carry
1 = Carry
Bit 1: Zero
Set by the CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation.
0 = Not Equal to Zero
1 = Equal to Zero
Bit 0: Global IE
Determines whether all interrupts are enabled or disabled
0 = Disabled
1 = Enabled
Note CPU_F register is only readable with the explicit register address 0xF7. The OR F, expr and AND F, expr instructions must
be used to set and clear the CPU_F bits.
Table 3. CPU Accumulator Register (CPU_A)
Bit #
7
6
5
Field
4
3
2
1
0
CPU Accumulator [7:0]
Read/Write
–
–
–
–
–
–
–
–
Default
0
0
0
0
0
0
0
0
Bit [7:0]: CPU Accumulator [7:0]
8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode.
Document Number: 38-08035 Rev. *T
Page 10 of 92
CY7C63310/CY7C638xx
Table 4. CPU X Register (CPU_X)
Bit #
7
6
5
4
Field
3
2
1
0
X [7:0]
Read/Write
–
–
–
–
–
–
–
–
Default
0
0
0
0
0
0
0
0
2
1
0
Bit [7:0]: X [7:0]
8-bit data value holds an index for any instruction that uses an indexed addressing mode.
Table 5. CPU Stack Pointer Register (CPU_SP)
Bit #
7
6
5
4
Field
3
Stack Pointer [7:0]
Read/Write
–
–
–
–
–
–
–
–
Default
0
0
0
0
0
0
0
0
4
3
2
1
0
Bit [7:0]: Stack Pointer [7:0]
8-bit data value holds a pointer to the current top of the stack.
Table 6. CPU Program Counter High Register (CPU_PCH)
Bit #
7
6
5
Field
Program Counter [15:8]
Read/Write
–
–
–
–
–
–
–
–
Default
0
0
0
0
0
0
0
0
4
3
2
1
0
Bit [7:0]: Program Counter [15:8]
8-bit data value holds the higher byte of the program counter.
Table 7. CPU Program Counter Low Register (CPU_PCL)
Bit #
7
6
5
Field
Program Counter [7:0]
Read/Write
–
–
–
–
–
–
–
–
Default
0
0
0
0
0
0
0
0
Bit [7:0]: Program Counter [7:0]
8-bit data value holds the lower byte of the program counter.
Addressing Modes
Examples
Source Immediate
ADD
A
7
The immediate value of 7 is added with the
Accumulator and the result is placed in the
Accumulator.
MOV
X
8
The immediate value of 8 is moved to the X
register.
AND
F
9
The immediate value of 9 is logically ANDed with
the F register and the result is placed in the F
register.
The result of an instruction using this addressing mode is placed
in the A register, the F register, the SP register, or the X register,
which is specified as part of the instruction opcode. Operand 1
is an immediate value that serves as a source for the instruction.
Arithmetic instructions require two sources; the second source is
the A or the X register specified in the opcode. Instructions using
this addressing mode are two bytes in length.
Table 8. Source Immediate
Opcode
Instruction
Operand 1
Immediate Value
Document Number: 38-08035 Rev. *T
Page 11 of 92
CY7C63310/CY7C638xx
Source Direct
Destination Direct
The result of an instruction using this addressing mode is placed
in either the A register or the X register, which is specified as part
of the instruction opcode. Operand 1 is an address that points to
a location in the RAM memory space or the register space that
is the source of the instruction. Arithmetic instructions require
two sources; the second source is the A register or X register
specified in the opcode. Instructions using this addressing mode
are two bytes in length.
The result of an instruction using this addressing mode is placed
within the RAM memory space or the register space. Operand 1
is an address that points to the location of the result. The source
for the instruction is either the A register or the X register, which
is specified as part of the instruction opcode. Arithmetic
instructions require two sources; the second source is the
location specified by Operand 1. Instructions using this
addressing mode are two bytes in length.
Table 9. Source Direct
Table 11. Destination Direct
Opcode
Instruction
Operand 1
Source address
Opcode
Operand 1
Instruction
Destination address
Examples
Examples
ADD
A
[7]
The value in the RAM memory location at
address 7 is added with the Accumulator,
and the result is placed in the Accumulator.
MOV
X
REG[8]
The value in the register space at address
8 is moved to the X register.
ADD
[7]
A
The value in the memory location at
address 7 is added with the Accumulator, and the result is placed in the
memory location at address 7. The
Accumulator is unchanged.
MOV
REG[8]
A
The Accumulator is moved to the
register space location at address 8.
The Accumulator is unchanged.
Source Indexed
The result of an instruction using this addressing mode is placed
in either the A register or the X register, which is specified as part
of the instruction opcode. Operand 1 is added to the X register
forming an address that points to a location in the RAM memory
space or the register space that is the source of the instruction.
Arithmetic instructions require two sources; the second source is
the A register or X register specified in the opcode. Instructions
using this addressing mode are two bytes in length.
Table 10. Source Indexed
Opcode
Instruction
Operand 1
MOV
A
X
The result of an instruction using this addressing mode is placed
within the RAM memory space or the register space. Operand 1
is added to the X register forming the address that points to the
location of the result. The source for the instruction is the A
register. Arithmetic instructions require two sources; the second
source is the location specified by Operand 1 added with the X
register. Instructions using this addressing mode are two bytes
in length.
Table 12. Destination Indexed
Source index
Opcode
Operand 1
Instruction
Examples
ADD
Destination Indexed
[X+7]
REG[X+8]
The value in the memory location at
address X + 7 is added with the
Accumulator, and the result is placed
in the Accumulator.
The value in the register space at
address X + 8 is moved to the X
register.
Document Number: 38-08035 Rev. *T
Destination index
Example
ADD
[X+7]
A
The value in the; memory location at
address X+7 is added with the Accumulator, and the result is placed in the
memory location at address x+7. The
Accumulator is unchanged.
Page 12 of 92
CY7C63310/CY7C638xx
Destination Direct Source Immediate
.
The result of an instruction using this addressing mode is placed
within the RAM memory space or the register space. Operand 1
is the address of the result. The source of the instruction is
Operand 2, which is an immediate value. Arithmetic instructions
require two sources; the second source is the location specified
by Operand 1. Instructions using this addressing mode are three
bytes in length.
Table 15. Destination Direct Source Direct
Opcode
Operand 1
Instruction
Destination address
Instruction
Operand 1
Destination address
Operand 2
Immediate Value
Examples
ADD [7]
5
The value in the memory location at address
7 is added to the immediate value of 5, and
the result is placed in the memory location at
address 7.
MOV REG[8]
6
The immediate value of 6 is moved into the
register space location at address 8.
Source address
Example
MOV
[7]
[8]
The value in the memory location at address 8
is moved to the memory location at address 7.
Table 13. Destination Direct Source Immediate
Opcode
Operand 2
Source Indirect Post Increment
The result of an instruction using this addressing mode is placed
in the Accumulator. Operand 1 is an address pointing to a
location within the memory space, which contains an address
(the indirect address) for the source of the instruction. The
indirect address is incremented as part of the instruction
execution. This addressing mode is only valid on the MVI
instruction. The instruction using this addressing mode is two
bytes in length. Refer to the PSoC Designer: Assembly
Language User Guide for further details on MVI instruction.
Table 16. Source Indirect Post Increment
Destination Indexed Source Immediate
The result of an instruction using this addressing mode is placed
within the RAM memory space or the register space. Operand 1
is added to the X register to form the address of the result. The
source of the instruction is Operand 2, which is an immediate
value. Arithmetic instructions require two sources; the second
source is the location specified by Operand 1 added with the X
register. Instructions using this addressing mode are three bytes
in length.
Opcode
Operand 1
Instruction
Source address address
Example
MVI
A
[8]
The value in the memory location at address
8 is an indirect address. The memory location
pointed to by the indirect address is moved
into the Accumulator. The indirect address is
then incremented.
Table 14. Destination Indexed Source Immediate
Opcode
Instruction
Operand 1
Destination index
Operand 2
Immediate value
Examples
ADD
[X+7]
5
The value in the memory location at
address X+7 is added with the
immediate value of 5, and the result
is placed in the memory location at
address X+7.
MOV
REG[X+8]
6
The immediate value of 6 is moved
into the location in the register space
at address X+8.
Destination Direct Source Direct
The result of an instruction using this addressing mode is placed
within the RAM memory. Operand 1 is the address of the result.
Operand 2 is an address that points to a location in the RAM
memory that is the source for the instruction. This addressing
mode is only valid on the MOV instruction. The instruction using
this addressing mode is three bytes in length.
Document Number: 38-08035 Rev. *T
Destination Indirect Post Increment
The result of an instruction using this addressing mode is placed
within the memory space. Operand 1 is an address pointing to a
location within the memory space, which contains an address
(the indirect address) for the destination of the instruction. The
indirect address is incremented as part of the instruction
execution. The source for the instruction is the Accumulator. This
addressing mode is only valid on the MVI instruction. The
instruction using this addressing mode is two bytes in length.
Table 17. Destination Indirect Post Increment
Opcode
Operand 1
Instruction
Destination address address
Example
MVI
[8]
A
The value in the memory location at
address 8 is an indirect address. The
Accumulator is moved into the memory
location pointed to by the indirect
address. The indirect address is then
incremented.
Page 13 of 92
CY7C63310/CY7C638xx
Instruction Set Summary
Opcode Hex
Cycles
8
2 OR [X+expr], A
Z
5A
5
2 MOV [expr], X
–
2 ADD A, expr
C, Z
2E
9
3 OR [expr], expr
Z
5B
4
1 MOV A, X
Z
6
2 ADD A, [expr]
C, Z
2F
10
3 OR [X+expr], expr
Z
5C
4
1 MOV X, A
–
7
2 ADD A, [X+expr]
C, Z
30
9
1 HALT
–
5D
6
2 MOV A, reg[expr]
Z
04
7
2 ADD [expr], A
C, Z
31
4
2 XOR A, expr
Z
5E
7
2 MOV A, reg[X+expr]
Z
05
8
2 ADD [X+expr], A
C, Z
32
6
2 XOR A, [expr]
Z
5F
10
3 MOV [expr], [expr]
–
06
9
3 ADD [expr], expr
C, Z
33
7
2 XOR A, [X+expr]
Z
60
5
2 MOV reg[expr], A
–
07 10
3 ADD [X+expr], expr
C, Z
34
7
2 XOR [expr], A
Z
61
6
2 MOV reg[X+expr], A
–
08
4
1 PUSH A
–
35
8
2 XOR [X+expr], A
Z
62
8
3 MOV reg[expr], expr
–
09
4
2 ADC A, expr
C, Z
36
9
3 XOR [expr], expr
Z
63
9
3 MOV reg[X+expr], expr
0A
6
2 ADC A, [expr]
C, Z
37
10
3 XOR [X+expr], expr
Z
64
4
1 ASL A
C, Z
–
1 SSC
01
4
02
03
Instruction Format
Bytes
Cycles
2D
Instruction Format
00 15
Bytes
Opcode Hex
Flags
–
Bytes
Flags
Cycles
Opcode Hex
The instruction set is summarized in Table 18 numerically and serves as a quick reference. If more information is needed, the
Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the
Cypress web site at http://www.cypress.com/?docID=15538).
Table 18. Instruction Set Summary Sorted Numerically by Opcode Order [2, 3]
Instruction Format
Flags
–
0B
7
2 ADC A, [X+expr]
C, Z
38
5
2 ADD SP, expr
65
7
2 ASL [expr]
C, Z
0C
7
2 ADC [expr], A
C, Z
39
5
2 CMP A, expr
66
8
2 ASL [X+expr]
C, Z
0D
8
2 ADC [X+expr], A
C, Z
3A
7
2 CMP A, [expr]
67
4
1 ASR A
C, Z
0E
9
3 ADC [expr], expr
C, Z
3B
8
2 CMP A, [X+expr]
68
7
2 ASR [expr]
C, Z
0F 10
3 ADC [X+expr], expr
C, Z
3C
8
3 CMP [expr], expr
69
8
2 ASR [X+expr]
C, Z
10
4
1 PUSH X
–
3D
9
3 CMP [X+expr], expr
6A
4
1 RLC A
C, Z
11
4
2 SUB A, expr
C, Z
3E
10
2 MVI A, [ [expr]++]
Z
6B
7
2 RLC [expr]
C, Z
12
6
2 SUB A, [expr]
C, Z
3F
10
2 MVI [ [expr]++], A
–
6C
8
2 RLC [X+expr]
C, Z
13
7
2 SUB A, [X+expr]
C, Z
40
4
1 NOP
–
6D
4
1 RRC A
C, Z
14
7
2 SUB [expr], A
C, Z
41
9
3 AND reg[expr], expr
Z
6E
7
2 RRC [expr]
C, Z
15
8
2 SUB [X+expr], A
C, Z
42
10
3 AND reg[X+expr], expr
Z
6F
8
2 RRC [X+expr]
C, Z
16
9
3 SUB [expr], expr
C, Z
43
9
3 OR reg[expr], expr
Z
70
4
2 AND F, expr
C, Z
17 10
3 SUB [X+expr], expr
C, Z
44
10
3 OR reg[X+expr], expr
Z
71
4
2 OR F, expr
C, Z
18
5
1 POP A
Z
45
9
3 XOR reg[expr], expr
Z
72
4
2 XOR F, expr
C, Z
19
4
2 SBB A, expr
C, Z
46
10
3 XOR reg[X+expr], expr
Z
73
4
1 CPL A
Z
1A
6
2 SBB A, [expr]
C, Z
47
8
3 TST [expr], expr
Z
74
4
1 INC A
C, Z
if (A=B) Z=1
if (A10
x
x
junk
Ignore
0011
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