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FUJITSU SEMICONDUCTOR
Data Sheet
FME-MB88121-1.48E
Automotive Solutions
CMOS
FlexRay ASSP
MB88121/MB88121A/MB88121B/MB88121C
■ DESCRIPTION
The MB88121 Series FlexRay ASSP (application specific standard product) facilitates to add FlexRay connectivity
to 8-bit, 16-bit and 32-bit microcontrollers that do not comprise embedded FlexRay protocol cores. The device
features a FlexRay communication controller based on the ERAY*1 IP core provided by Bosch. The most recent
FlexRay communication controller complies to the protocol definition 2.1 of the FlexRay consortium. Fujitsu intends
to update the communications controller when new protocol definitions are released. Please, refer to the chapter
‘product lineup’ for a cross reference between device version and protocol version supported. Several parallel
and serial interfaces provide connectivity to a vast number of host processors.
All types of host interfaces are selectable by mode pins that supersede any programming by the user. The
configurable parallel host interface connects to most 16-bit and 32-bit microcontrollers while SPI offers serial
interfacing options. A DMA support unit avoids that the application on the host processor has to wait until the
input buffer becomes available for writing.
The version suffix ’B/C’ of the ASSP is operated from a single 3.3V or 5.0 V supply and includes an on board
voltage regulator that provides 1.8 V to the internal core. This creates a major advantage in terms of EMI and
power consumption.
The internal PLL clock frequency multiplier provides an internal 80 MHz clock from an external 4 MHz, 5 MHz,
8 MHz, 10 MHz, 16 MHz*2 or 20 MHz*2 clock. Alternatively the user may choose to drive the clock input with a
square wave signal from the host processor.
*1 : License of Robert Bosch GmbH
*2 : MB88121C only
rev 1.48
29/Jan/2013
MB88121
FlexRay ASSP
■ PACKAGE
64-pin Plastic LQFP
(FPT-64P-M03/M24)
The device is offered in a standard 64-pin quad flatpack package with a pin pitch of 0.5 mm.
■ FEATURES
• FlexRay communication controller based on ERAY*1 IP core from Bosch
• Data rates of up to 10 Mbit/s on each channel
• Up to 128 message buffers configurable
• 8 Kbyte of Message RAM for storage of e.g. 128 message buffers with max. 48 byte data section or up to
30 message buffers with 254 byte data section
• Configuration of message buffers with different payload lengths possible
• One configurable receive FIFO
• Each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive FIFO
• Host access to message buffers via Input and Output Buffer
Input Buffer: Holds message to be transferred to the Message RAM
Output Buffer: Holds message read from the Message RAM
• Filtering for slot counter, cycle counter, and channel
• Maskable module interrupts
• Network Management supported
• Configurable parallel host interface
• SPI interface (8 Mbit/s) (MB88121B/C only)
• DMA support unit (MB88121A/B/C only)
• 0.18μm CMOS Process Technology
• Single voltage supply (5.0 V / 3.3 V), internal voltage regulator for 1.9 V core voltage offering low EMI and low
power consumption (MB88121B/C only)
• Package : 64-pin*2 plastic LQFP;
*1 : License of Robert Bosch GmbH
*2: Other packages such as 48-pin plastic LQFP featuring only SPI host interface are under consideration.
2
rev 1.48
29/Jan/2013
MB88121
FlexRay ASSP
■ PRODUCT LINEUP
Part Number
Parameter
System clock
Technology
Operating voltage
range
Temperature range
MB88121
MB88121A
Direct clock input: 80MHz (or 40MHz
for 5Mbit/s).
On-chip PLL (evaluation pending):
External clock 10 MHz, internal clock
80 MHz (50% duty cycle).
Parallel host interface
Low voltage interrupt
(tbd)
On-chip PLL
(jitter evaluation
pending)
External clock input
4/5/8/10 MHz
Direct clock input:
80MHz.
On-chip PLL
(jitter evaluation
pending)
External clock input
4/5/8/10/16/20 MHz
0.18μm CMOS with on-chip voltage regulator for internal power supply.
5.0V±0.5V, 3.3V±0.3V, 1.8V±0.15V
3.0 V - 5.5 V
TA = −40 ° C to +85 ° C
TA = −40 ° C to +105
°C
TA = −40 ° C to +125
°C
LQFP-64
2.0
2.1
V2.1
Configurable parallel host interface
Configurable parallel host interface compatcompatible with Fujitsu 32-bit FR miible with Fujitsu 16-bit 16FX and 32-bit FR
crocontrollers.
microcontrollers.
Maximum frequency 33MHz (target)
SPI interface
DMA support unit
MB88121C
0.18μm CMOS with triple voltage
supply
(5.0V, 3.3V, 1,8V).
Package
FlexRay Protocol version
MB88121B
-
Configurable clocking schemes and bit direction.
Generates DMA request signal for host processor for writing the
input buffer. Thus the possibility that the input buffer is busy
does not produce any waiting time at the host that can issue other tasks during the buffer writing.
-
-
Generates an interrupt when internal or external operating voltage drops below certain
limits.
.
rev 1.48
29/Jan/2013
3
MB88121
FlexRay ASSP
■ PIN ASSIGNMENTS
1. Pin assignment in 16 bit multiplexed parallel mode (MB88121B/C only)
VSS
INT1
INT2
INT4
INT3
MBSU_RX1/NC
MBSU_TX1/NC
MBSU_TX2/NC
D15
MBSU_RX2/NC
D14
VCC
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS
49
32
VCC
D13
50
31
DMA_REQ
D12
51
30
MDE0
D11
52
29
MDE1
AD10
53
28
MDE2
AD9
54
27
RDY
AD8
55
26
TXDB
AD7
56
25
TXENB
AD6
57
24
RXDB
AD5
58
23
MT
AD4
59
22
ALE/AS
AD3
60
21
WR
AD2
61
20
RD
AD1
62
19
CS
AD0
63
18
C
MD2
64
17
VSS
VCC
BCLK
CYCS
RXDA
TXENA
INT0
TXDA
STPW
SDS
CYCS0
RST
MD0
MD1
X0
X1
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(FPT-64P-M03/M24)
4
rev 1.48
29/Jan/2013
MB88121
FlexRay ASSP
2. Pin assignment in 16 bit non-multiplexed parallel mode
VSS
INT1
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
VCC
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS
49
32
VCC/VCC33
D13
50
31
DMA_REQ
D12
51
30
MDE0
D11
52
29
MDE1
D10
53
28
MDE2
D9
54
27
RDY
D8
55
26
TXDB
D7
56
25
TXENB
D6
57
24
RXDB
D5
58
23
MT/NC
D4
59
22
INT2
D3
60
21
WR
D2
61
20
RD
D1
62
19
CS
D0
63
18
C/VCC18
MD2
64
17
VSS
VCC
BCLK
CYCS/NC
RXDA
TXENA
TXDA
INT0
STPW/VSS
CYCS0/VCC18
SDS/NC
RST
MD0
MD1
X0
X1
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(FPT-64P-M03/M24)
rev 1.48
29/Jan/2013
5
MB88121
FlexRay ASSP
3. Pin assignment in SPI mode (MB88121B/C only)
VSS
INT1
MBSU_TX1/NC
SCK
MBSU_RX1/NC
SDI
SDO
MBSU_TX2/NC
VCC
MBSU_RX2/NC
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
50
31
51
30
MDE0
52
29
MDE1
MDS2
53
28
MDE2
MDS1
54
27
MDS0
55
26
TXDB
56
25
TXENB
57
24
RXDB
INT2
58
23
MT
INT3
59
22
INT4
60
21
61
20
62
19
CS
63
18
C
64
17
VSS
VSS
MD2
VCC
VCC
RXDA
CYCS
TXDA
TXENA
STPW
INT0
SDS
CYCS0
RST
MD0
X0
MD1
X1
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(FPT-64P-M03/M24)
6
rev 1.48
29/Jan/2013
MB88121
FlexRay ASSP
■ PIN DESCRIPTION
Pin No.
Pin name
Circuit type
Function
1, 17, 33,
49
VSS
⎯
These are power supply ground (0 V) input pins
16, 48
VCC
⎯
MB88121B/C: These are power supply (3.3 - 5.0 V) input pins.
MB88121(A): These are power supply (5.0 V) input pins
32
VCC/VCC33
⎯
MB88121B/C: This is a power supply (3.3 - 5.0 V) input pin.
MB88121(A): 3.3V supply voltage for the level converters.
⎯
MB88121B/C: This is the power supply stabilization capacitor pin.
It should be connected to higher than or equal to 0.1 μF ceramic
capacitor.
MB88121(A): 1.8V core supply input pin.
18
C/VCC18
2
X1
3
X0
4-5
MD1 - MD0
A
Input pins for the mode selection.
6
RST
A
Reset input pin.
7
SDS/NC
B/-
MB88121B/C: Debug pin: Start of dynamic segment, when function is disabled, this pin outputs ‘L’-Level
MB88121(A): Do not connect!
8
CYCS0/VCC18
B/-
MB88121B/C: Debug pin: Cycle 0 start output, when function is
disabled, this pin outputs ‘L’-Level
MB88121(A): 1.8V core supply input pin.
9
STPWT/VSS
C/-
MB88121B/C: Stop Watch Trigger Input pin
MB88121(A): Power supply ground (0 V) input pin.
10
INT0
B
Output pin for the Interrupt 0 output.
11
TXDA
B
Output pin for the data transmitter output channel A.
12
TXENA
B
Output pin for the transmission enable output channel A.
13
RXDA
A
Input pin for the data receiver input channel A.
14
CYCS/NC
B/-
15
BCLK
D
A
19
20
CS
RD
21
-
Oscillation input pin. If external clock is used, it is connected here.
MB88121B/C: Debug pin: Cycle start output, when function is disabled, this pin outputs ‘L’-Level
MB88121(A): Do not connect!
Input pin for the Bus Clock input.
This function is enabled in all parallel modes.
This pin is unused in SPI mode.
A
Input pin for the chip select input.
A
Input pin for the read enable input.
This function is enabled in all parallel modes.
WR
Oscillation output pin.
This pin is unused in SPI mode.
A
Input pin for the write enable input.
This function is enabled in all parallel modes.
This pin is unused in SPI mode.
rev 1.48
29/Jan/2013
7
MB88121
Pin No.
22
FlexRay ASSP
Pin name
Circuit type
ALE
Input pin for the address latch enable input (high active).
This function is enabled in the multiplexed parallel modes for
16FX and for other devices to be defined later.
AS
Input pin for the address strobe input (low active).
This function is enabled in the multiplexed parallel modes. Timing
meets FR core devices (460 series) and other devices.
C
Output pin for the Interrupt 2 output.
This function is enabled in 16-bit non-multiplexed parallel mode.
INT2
-
This pin is Hi-Z in in SPI mode.
MB88121B/C: Debug pin; Macrotick start output, when function is
disabled, this pin outputs ‘L’-Level
MB88121(A): Do not connect!
23
MT/NC
B/-
24
RXDB
A
Input pin for the data receiver input channel B.
25
TXENB
B
Output pin for the transmission enable output channel B.
26
TXDB
B
Output pin for the data transmitter output channel B.
B
Output pin for the ready output.
This function is enabled in all parallel modes.
27
RDY
-
28-30
31
34
This pin is Hi-Z in SPI mode.
MDE2 - MDE0
A
Input pins for the extended mode selection.
DMA_REQ
B
Output pin for the DMA request output (MB88121A/B/C only).
On MB88121, this pin outputs “L” level.
This function is enabled in all parallel modes
-
B
This pin is Hi-Z in SPI mode.
INT1
B
Output pin for the Interrupt 1 output.
Input pin for the address bus.
This function is enabled in 16-bit non-multiplexed parallel mode.
A10
35
INT2
C
-
36
INT3
Input pin for the address bus.
This function is enabled in 16-bit non-multiplexed parallel mode.
C
-
Input pin for the address bus.
This function is enabled in 16-bit non-multiplexed multiplexed
parallel mode.
C
INT4
-
Output pin for the Interrupt 3 output.
This function is enabled in 16-bit multiplexed parallel mode.
This pin is Hi-Z in SPI mode.
A8
37
Output pin for the Interrupt 2 output.
This function is enabled in 16-bit multiplexed parallel mode.
This pin is Hi-Z in SPI mode.
A9
8
Function
Output pin for the Interrupt 4 output
This function is enabled in 16-bit multiplexed parallel mode
This pin is Hi-Z inSPI mode.
rev 1.48
29/Jan/2013
MB88121
Pin No.
FlexRay ASSP
Pin name
Circuit type
Input pins for the address bus.
This function is enabled in 16-bit non-multiplexed parallel mode.
A7
MBSU_TX1
MB88121B/C: Debug pin, when function is disabled, this pin outputs ‘L’-Level
MB88121(A): Not supported.
This function is enabled in 16-bit multiplexed parallel and SPI
mode.
A6
Input pins for the address bus.
This function is enabled in 16-bit non-multiplexed parallel mode.
38
C
39
C
MBSU_RX1
SCK
A
-
SDI
Input pin for the address bus.
This function is enabled in 16-bit non-multiplexed parallel modes.
A
-
SDO
Input pin for the address bus.
This function is enabled in 16-bit non-multiplexed parallel modes.
C
-
Output pin for the serial data output.
When CS is “H“ SDO is High-Z.
This function is enabled in SPI mode.
This pin is Hi-Z in 16-bit multiplexed parallel modes.
A2
43
Input pin for the serial data input.
This function is enabled in SPI mode.
This pin is unused in 16-bit multiplexed parallel modes.
A3
42
Input pin for the serial clock input.
This function is enabled in SPI mode.
This pin is unused in 16-bit multiplexed parallel modes.
A4
41
MB88121B/C: Debug pin, when function is disabled, this pin outputs ‘L’-Level
MB88121(A): Not supported.
This function is enabled in 16-bit multiplexed parallel and SPI
mode.
Input pin for the address bus.
This function is enabled 16-bit non-multiplexed parallel modes.
A5
40
Function
A
Input pin for the address bus.
This function is enabled in 16-bit non-multiplexed parallel modes.
-
This pin is unused in 16-bit multiplexed parallel mode and in SPI
mode.
A1
Input pin for the address bus.
This function is enabled in 16-bit non-multiplexed parallel modes.
44
C
MBSU_TX2
MB88121B/C: Debug pin, when function is disabled, this pin outputs ‘L’-Level
MB88121(A): Not supported.
This function is enabled in 16-bit multiplexed parallel and SPI
mode.
rev 1.48
29/Jan/2013
9
MB88121
Pin No.
FlexRay ASSP
Pin name
Circuit type
Input pin for the address bus.
This function is enabled in 16-bit non-multiplexed parallel modes.
A0
MBSU_RX2
MB88121B/C: Debug pin, when function is disabled, this pin outputs ‘L’-Level
MB88121(A): Not supported.
This function is enabled in 16-bit multiplexed parallel and SPI
mode.
D15 - D14
I/O pins for the data bus.
This function is enabled in 16-bit multiplexed and non-multiplexed
parallel modes.
45
46 - 47
C
C
-
50 - 52
D13 - D11
These pins are Hi-Z in SPI mode.
C
-
D10 - D8
I/O pins for the address/data bus.
This function is enabled in 16-bit multiplexed parallel mode.
C
I/O pins for the address/data bus.
This function is enabled in 16-bit multiplexed parallel mode.
AD7 - AD6
D7 - D6
C
-
61 - 63
D5 - D3
I/O pins for the address/data bus.
This function is enabled in 16-bit multiplexed parallel mode.
C
10
I/O pins for the data bus.
This function is enabled in 16-bit non-multiplexed parallel mode.
INT2 - INT4
Output pins for the Interrupt 2 - 4 outputs.
This function is enabled in SPI mode.
AD3 - AD0
I/O pins for the address/data bus.
This function is enabled in 16-bit multiplexed parallel mode.
D2 - D0
C
64
I/O pins for the data bus.
This function is enabled in 16-bit non-multiplexed parallel mode.
These pins are Hi-Z in SPI mode.
AD5 - AD3
58 - 60
I/O pins for the data bus.
This function is enabled in 16-bit non-multiplexed parallel mode.
Input pins for specific settings of serial interfaces. This function is
only enabled when serial mode was selected by MD / MDE.
MDS2 - MDS0
56 - 57
I/O pins for the data bus.
This function is enabled in 16-bit multiplexed and non-multiplexed
parallel modes.
These pins are Hi-Z in SPI mode.
AD10 - AD8
53 - 55
Function
MD2
I/O pins for the data bus.
This function is enabled in 16-bit non-multiplexed parallel mode.
These pins are Hi-Z in SPI mode.
A
Input pin for the mode selection.
rev 1.48
29/Jan/2013
MB88121
FlexRay ASSP
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• CMOS hysteresis input
CMOS HYS
R
A
Input enable signal
• CMOS output
VCC
P-ch
N-ch
B
CMOS HYS
R
R
Automotive
HYS
• CMOS output
VCC
• CMOS hysteresis input with input
enable signal
P-ch
N-ch
C
R
CMOS HYS
R
Input enable signal Automotive
HYS
X1
Clock input
P-ch
• Oscillation feedback resistor :
1 MΩ approx.
N-ch
X0
D
Standby control signal
rev 1.48
29/Jan/2013
11
MB88121
FlexRay ASSP
■ PIN FUNCTIONS VS. MODES
Pin No.
16bit mux mode
(MB88121B/C only)
1
VSS
2
X1
3
X0
4
MD1
5
MD0
6
RST
7
MB88121B/C: SDS; MB88121(A):NC
8
MB88121B/C: CYCS0 ; MB88121(A): VCC18
9
MB88121B/C: STPWT; MB88121(A): VSS
10
INT0
11
TXDA
12
TXENA
13
RXDA
14
MB88121B/C: CYCS; MB88121(A): NC
15
BCLK
-
16
VCC
17
VSS
18
MB88121B/C: C; MB88121(A): VCC18
19
CS
20
RD
-
21
WR
-
22
ALE/AS
INT2
-
23
MB88121B/C: MT; MB88121(A): NC
24
RXDB
25
TXENB
26
TXDB
27
12
SPI mode
(MB88121B/C only)
16bit non mux mode
RDY
-
28
MDE2
29
MDE1
30
MDE0
31
DMA_REQ
-
32
MB88121B/C: VCC; MB88121(A): VCC33
33
VSS
rev 1.48
29/Jan/2013
MB88121
Pin No.
FlexRay ASSP
16bit mux mode
(MB88121B/C only)
16bit non mux mode
34
SPI mode
(MB88121B/C only)
INT1
35
INT2
A10
-
36
INT3
A9
-
37
INT4
A8
-
38
MBSU_TX1
A7
MBSU_TX1;
39
MBSU_RX1;
A6
MBSU_RX1;
40
-
A5
SCK
41
-
A4
SDI
42
-
A3
SDO
43
-
A2
-
44
MBSU_TX2;
A1
MBSU_TX2
45
MBSU_RX2;
A0
MBSU_RX2
46
D15
-
47
D14
-
48
VCC
49
VSS
50
D13
-
51
D12
-
52
D11
-
53
AD10
D10
MDS2
54
AD9
D9
MDS1
55
AD8
D8
MDS0
56
AD7
D7
-
57
AD6
D6
-
58
AD5
D5
INT2
59
AD4
D4
INT3
60
AD3
D3
INT4
61
AD2
D2
-
62
AD1
D1
-
63
AD0
D0
-
64
MD2
rev 1.48
29/Jan/2013
13
MB88121
FlexRay ASSP
■ MODE SELECTION
MD2
MD1
MD0
Mode
0
X
X
Reserved(Set-prohibitd)
1
1
0
0
0
1
16-bit
(Oscillator)
16-bit*2
(External Clock Input)
*1
1
1
0
Serial
1
1
1
Reserved(Set-prohibitd)
MDE2
MDE1
MDE0
Mode Expansion
0
0
0
FR (460)*1
0
0
1
16FX*1
0
1
0
0
1
1
1
0
0
FR (460)
1
0
1
16FX*2
1
1
0
FR (360)
1
1
1
0
0
0
FR (460)
0
0
1
16FX
0
1
0
0
1
1
1
0
0
FR (460)
1
0
1
16FX
1
1
0
FR (360)
1
1
1
reserved
(Set-prohibitd)
mux
reserved
(Set-prohibitd)
non mux
reserved
(Set-prohibitd)
reserved
(Set-prohibitd)
mux
reserved
(Set-prohibitd)
non mux
reserved
(Set-prohibitd)
Refer to tables for
- frequency selection
- serial type selection
X
X
X
The table above describes the encoding of host interface options by mode pins. Basically these mode pins
(MD[2:0]) select between the different bus types, parallel or serial, and in case of parallel type, their width. For
32-bit modes, the swapping of low word with high word for non-Intel style access is implicit part of the selected
mode. The multiplex style for 16-bit modes is encoded in the mode expansion bits MDE[2:0].
The selection of the serial interface is encoded in MDE[2:0]. Implicitly type and operating frequency are encoded
as well here. The specific settings of the selected serial interface are encasuplated in the special mode expansion
pins MDS[2:0], that become available for MD[2:0] = 110B (select serial) only.
*1: MB88121B/C only
*2: MB88121C only
14
rev 1.48
29/Jan/2013
MB88121
FlexRay ASSP
■ Used Clock for X0/X1
Input frequency of X0 and X1 is described Table below.
Oscillator
100
4MHz/5MHz/8MHz
External Clock
-
MD[2:0]
101
4MHz/5MHz/8MHz/
10MHz/16MHz/20MHz/
80MHz
110
4MHz/5MHz/8MHz
4MHz/5MHz/8MHz/
10MHz
rev 1.48
29/Jan/2013
15
MB88121
FlexRay ASSP
■ FREQUENCY SELECTION IN SERIAL MODE
When operating the device via serial interface, the frequency set up according the table below needs to match
the externally supplied clock.
MDE2 MDE1
Frequency
0
0
4 MHz
0
1
5 MHz
1
0
8 MHz
1
1
10 MHz
■ SERIAL INTERFACE TYPE SELECTION
The table below applies when MD[2:0] = 110B.
MDE0 Serial interface type
0
SPI (tbd)
1
Reserved
■ SPI SETTINGS
The table below applies when MD[2:0] = 110B and MDE0 = 0.
MDS2 MDS1 MDS0
16
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Specific SPI Mode Settings
MDS2=LSBFE: Bit Direction
1: Data is transferred least significant bit first.
0: Data is transferred most significant bit first.
MDS1=CPOL: Clock Polarity
1: Active-low clock. In idle state SCK is high.
0: Active-high clock. In idle state SCK is low.
MDS0=CPHA: Clock Phase
1: Sampling of data occurs at even edges of SCK.
0: Sampling of data occurs at odd edges of SCK.
rev 1.48
29/Jan/2013
MB88121
FlexRay ASSP
■ HANDLING DEVICES
Special care is required for the following when handling the device :
• Preventing latch-up
• Stabilization of supply voltage
• Treatment of unused pins
• Using external clock
• Power supply pins (VCC/VSS)
• Pull-up/down resistors
• Crystal Oscillator Circuit
• Notes on Energization
• Caution on Operation with PLL
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
2. Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operating range. Therefore, the VCC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at
commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient
of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
3. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
Unused inputs that feature an internal pull up resistor, or unused inputs that have been disabled by a particular
operational mode can be left open. Make sure that at least one condition is explicitly mentioned for the respective
pin.
4. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90390 Series
MB88121(A/B/C)
X0
X1
5. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch up.
rev 1.48
29/Jan/2013
17
MB88121
FlexRay ASSP
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 μF as a bypass capacitor between
VCC and VSS in the vicinity of VCC and VSS pins of the device.
VCC
VSS
VCC
VSS
VSS
VCC
MB90390
MB88121(A/B/C)
Series
VCC
VSS
VSS
VCC
6. Pull-up/down resistors
MB88121(A/B/C) does not provide internal pull-up/down resistors unless explicitely mentioned in the pin list.
Use external components where needed.
7. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
8. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 µs
or more (0.2 V to 2.7 V) .
9. Caution on Operation with PLL
As the device operates with an internal PLL clock, it attempts to be working with the self-oscillating circuit even
when there is no external oscillator present or when the external clock input stopped. Performance of this
operation, however, cannot be guaranteed.
10. Interrupt pin Assignment
The MB88121/A/B/C series supports interrupt pins. In the differrent operation interface modes the interrupt pin
assignment is different.
18
rev 1.48
29/Jan/2013
MB88121
FlexRay ASSP
For 16-bit none multiplexed mode (MD[2:0] = 1,0,0; MDE[2:0] = 1,x,x) the interrupt pin assignment is:
Pin name
Internal E-Ray signal
Description
Signal is activate if Interrupt line 0 is activated via ILE
Register (ILE.0 = 1).
INT0
eray_int0
All E-Ray interrupts set to Interrupt line0 and activated
will be signaled via this pin (EILS, SILS EIES, SIES Register).
Signal is activate if Interrupt line 1 is activated via ILE
Register(ILE.1 = 1)
INT1
INT2
eray_int1
Timer 0 or Timer 1 interrupt,
Low voltage detection
All E-Ray interrupts set to Interrupt line1 and activated
will be signaled via this pin. (EILS, SILS EIES, SIES Register).
Timer0 and Timer 1 interrupts are signaled via this pins.
They are logical or combined
In case of low voltage detection it is indicated by INT2
For 16-bit multiplexed mode (MD[2:0] = 1,0,0; MDE[2:0] = 0,x,x) and SPI mode (MD[2:0] = 1,1,0) the interrupt
pin assignment is:
Pin name
Internal E-Ray signal
Description
Signal is activate if Interrupt line is activated via ILE
Register (ILE.0 = 1).
INT0
eray_int0
All E-Ray interrupts set to Interrupt line0 and activated
will be signaled via this pin (EILS, SILS EIES, SIES
Register).
Signal is activate if Interrupt line is activated via ILE
Register(ILE.1 = 1)
INT1
eray_int1
All E-Ray interrupts set to Interrupt line1 and activated
will be signaled via this pin. (EILS, SILS EIES, SIES
Register).
INT2
Timer Interrupt 0
Timer0 Interrupt is signaled via this pins.
INT3
Timer interrupt 1
Timer1 Interrupt is signaled via this pins.
INT4
Low voltage detection
In case of low voltage detection it is indicated by INT4
pin.
rev 1.48
29/Jan/2013
19
MB88121
FlexRay ASSP
11. Pin level at interrupt pins
In case that the interrupt pin is enabled following level is output
Level
Description
0
default value, no interrupt request is pending
1
Interrupt request is pending
The output changes to Low-Level when the corresponding flag in the E-Reay register is cleared.
For timer0 and timer1 interrupt pin(s) the High level is output only a dedicated time and set back to Low-Level.
See E-Ray User Manual for details. It is recommended to use egde detection at host side for these pins.
12. Data Accessing of MB88121 series
The MB88121 series includes a parallel bus Interface using 16-bit data width. However the internal Communication Controller requires a 32-bit data access. Therefore always access the MB88121 using 32-bit data access.
The Bus Interface expect two 16-bit data transfer from the Host MCU.
The order of the transfer is important, otherwise data can be lost.
First 16-bit write cycle must be the lower, the second 16-bit write cycle the higher 16-bit address of the 32-bit
address. As soon as data is written to the higher 16-bit Address, the Communication Controller is writing the
32-bit value to the address.
Example:
Write access to Input buffer: First 32-bit register WRDS1: (Address: 0x400 - 0x403)
Value of WRDS1 register: 0x0000 0000
First 16-bit write cycle via Bus interface to address 0x400-401: Value: 1234
Value of WRDS1 register: 0x0000 0000
Second 16 bit write cycle via Bus Interface to address 0x402 - 0x403: Value 5678
32-bit data written to WRDS1 address.
Value of WRDS1 register: 0x1234 5678
20
rev 1.48
29/Jan/2013
MB88121
FlexRay ASSP
■ BLOCK DIAGRAM
To FlexRay
Transceivers
MB88121/MB88121A/MB88121B/MB88121C
PORT A
RAM A
PORT B
RAM B
CPU Interface
To Host CPU
MB88121/A/B/C
Global Time
Management
Network
Management
Error
Handling
Input Buffer
Message
Handler
Output Buffer
Clock
Control
DMA
Support*1
Startup
Logic
Message
RAM
Interrupt
Logic
*1: DMA support is only available on MB88121A/B/C
rev 1.48
29/Jan/2013
21
MB88121
FlexRay ASSP
■ HOST INTERFACES
Connection to Host CPU in 16-bit multiplexed Mode (MB88121B/C only)
Host CPU
MB88121B/C
AD[10:0]
AD[10:0]
VCC
D[15:11]
BCLK
4
VCC
VSS
BCLK
ALE/AS
ALE/AS
RD
RD
WR
WR
CS
CS
DMA_REQ
6
MD[2:0]
DMA_REQ
RDY
INT[4:0]
VSS
D[15:11]
3
RDY
5
MDE[2:0]
INT[4:0]
RST
3
3
Physical
Layer A/B
I/F Mode Selection
Mode Expansion
C
X0
X1
or square wave input
Reset
*1: DMA_REQ can only be used if RDY is not used, e.g. with automatic wait states.
The initial function of the RDY/DMA_REQ pin is RDY.
22
rev 1.48
29/Jan/2013
MB88121
FlexRay ASSP
Connection to Host CPU in 16-bit non-multiplexed Mode
Host CPU
MB88121(A/B/C)
A[10:0]
A[10:0]
VCC
VSS
D[15:0]
D[15:0]
BCLK
4
BCLK
RD
RD
WR
WR
CS
CS
6
MD[2:0]
DMA_REQ*1
DMA_REQ
RDY
INT[2:0]
3
RDY
3
MDE[2:0]
INT[2:0]
RST
3
3
VCC
VSS
Physical
Layer A/B
I/F Mode Selection
Mode Expansion
C
X0
X1
or square wave input
Reset
*1: MB88121A/B/C only
rev 1.48
29/Jan/2013
23
MB88121
FlexRay ASSP
Connection to Host CPU in SPI Mode (MB88121B/C only)
Host CPU
MB88121B/C
VCC
VSS
CS
4
VCC
VSS
CS
SCK
SCK
SDO
SDI
SDI
SDO
6
MD[2:0]
MDE[2:0]
INT[4:0]
3
5
INT[4:0]
MDS[2:0]
3
3
3
Physical
Layer A/B
I/F Mode Selection
Mode Expansion
Serial Mode Settings
C
RST
X0
X1
or square wave input
Reset
24
rev 1.48
29/Jan/2013
MB88121
FlexRay ASSP
■ I/O MAP
Address
Symbol
Name
Reset
Access
Customer Registers
0x0000
VER
Version Information Register
0x0004
CCNT
Clock Control Register
0x0008
CUS2
0x000C
reserved
Customer 2 Register (DBGS & DMAS)
-
reserved
INT
Interrupt Register
MB88121: 0410 7905
MB88121A: 0420 7906
MB88121B: 0430 79FF
MB88121C: 0440 79FF
0000 0000
MB88121:
0000 0000
MB88121A/B/C:0000 0000
MB88121(A): 0000 0000
MB88121B/C: 0000 0000
r
r/w
r
r/w
r
r/w
Special Registers
0x0010
-
reserved (1) (don’t write)
MB88121:
0000 0000
MB88121A/B/C: 0000 0300
r
0x0014
-
reserved (1) (don’t write)
0000 0000
r
0x0018
-
reserved (1)
0000 0000
r
0x001C
LCK
Lock Register
0000 0000
r/w
Interrupt Registers
0x0020
EIR
Error Interrupt Register
0000 0000
r/w
0x0024
SIR
Status Interrupt Register
0000 0000
r/w
0x0028
EILS
Error Interrupt Line Select
0000 0000
r/w
0x002C
SILS
Status Interrupt Line Select
MB88121:
0303 7FFF
MB88121A/B/C: 0303 FFFF
r/w
0x0030
EIES
Error Interrupt Enable Set
0000 0000
r/w
0x0034
EIER
Error Interrupt Enable Reset
0000 0000
r/w
0x0038
SIES
Status Interrupt Enable Set
0000 0000
r/w
0x003C
SIER
Status Interrupt Enable Reset
0000 0000
r/w
0x0040
ILE
Interrupt Line Enable
0000 0000
r/w
0x0044
T0C
Timer 0 Configuration
0000 0000
r/w
0x0048
T1C
Timer 1 Configuration
0002 0000
r/w
STPW
Stop Watch Register
STPW1
Stop Watch Register 1
-
reserved
STPW2
Stop Watch Register 2
-
reserved (11)
0x004C
0x0050
0x0054 0x007C
MB88121/A: 0000 0000
MB88121B/C: 0000 0000
r/w
MB88121/A: 0000 0000
MB88121B/C: 0000 0000
r
0000 0000
rev 1.48
29/Jan/2013
r
25
MB88121
FlexRay ASSP
(Continued)
Address
Symbol
Name
Reset
Access
CC Control Registers
0x0080
SUCC
SUC Configuration Register 1
MB88121:
0C40 0000
MB88121A/B/C: 0C40 1000
r/w
0x0084
SUCC2
SUC Configuration Register 2
MB88121:
0100 05A4
MB88121A/B/C: 0100 0504
r/w
0x0088
SUCC3
SUC Configuration Register 3
0000 0011
r/w
0x008C
NEMC
NEM Configuration Register
0000 0000
r/w
0x0090
PRTC1
PRT Configuration Register 1
MB88121:
084C 0005
MB88121A/B/C: 084C 0633
r/w
0x0094
PRTC2
PRT Configuration Register 2
MB88121: 0F2D 0E0E
MB88121A/B/C:0F2D 0A0E
r/w
0x0098
MHDC
MHD Configuration Register
MB88121:
0001 0000
MB88121A/B/C: 0000 0000
r/w
0x009C
-
reserved (1)
0000 0000
r
0x00A0
GTUC1
GTU Configuration Register 1
MB88121:
0000 02D0
MB88121A/B/C: 0000 0280
r/w
0x00A4
GTUC2
GTU Configuration Register 2
MB88121:
0002 000C
MB88121A/B/C: 0002 000A
r/w
0x00A8
GTUC3
GTU Configuration Register 3
MB88121:
0001 0000
MB88121A/B/C: 0202 0000
r/w
0x00AC
GTUC4
GTU Configuration Register 4
MB88121:
000A 0009
MB88121A/B/C: 0008 0007
r/w
0x00B0
GTUC5
GTU Configuration Register 5
MB88121:
0A01 0000
MB88121A/B/C: 0E00 0000
r/w
0x00B4
GTUC6
GTU Configuration Register 6
0002 0000
r/w
0x00B8
GTUC7
GTU Configuration Register 7
MB88121:
0002 0005
MB88121A/B/C: 0002 0004
r/w
0x00BC
GTUC8
GTU Configuration Register 8
0000 0002
r/w
0x00C0
GTUC9
GTU Configuration Register 9
MB88121:
0001 0101
MB88121A/B/C: 0000 0101
r/w
0x00C4
GTUC10
GTU Configuration Register 10
MB88121:
0002 0001
MB88121A/B/C: 0002 0005
r/w
0x00C8
GTUC11
GTU Configuration Register 11
0000 0000
r/w
-
reserved (13)
0000 0000
r
0x00CC 0x00FC
26
rev 1.48
29/Jan/2013
MB88121
Address
Symbol
FlexRay ASSP
Name
Reset
Access
CC Status Registers
0x0100
CCSV
CC Status Vector
MB88121:
0000 4000
MB88121A/B/C: 0010 4000
r
0x0104
CCEV
CC Error Vector
0000 0000
r
-
reserved (2)
0000 0000
r
0x0110
SCV
Slot Counter Value
MB88121:
03FF 03FF
MB88121A/B/C: 0000 0000
r
0x0114
MTCCV
Macrotick and Cycle Counter Value
0000 0000
r
0x0118
RCV
Rate Correction Value
0000 0000
r
0x011C
OCV
Offset Correction Value
0000 0000
r
0x0120
SFS
Sync Frame Status
0000 0000
r
0x0124
SWNIT
Symbol Window and NIT Status
0000 0000
r
0x0128
ACS
Aggregated Channel Status
0000 0000
r/w
0x012C
-
reserved (1)
0000 0000
r
ESIDn
Even Sync ID [1 ...15]
0000 0000
r
-
reserved (1)
0000 0000
r
OSIDn
Odd Sync ID [1 ...15]
0000 0000
r
-
reserved (1)
0000 0000
r
NMVn
Network Management Vector [1... 3]
0000 0000
r
-
reserved (81)
0000 0000
r
0x0108 0x010C
0x0130 0x0168
0x016C
0x0170 0x01A8
0x01AC
0x01B0 0x01B8
0x01BC 0x02FC
Message Buffer Control Registers
0x0300
MRC
Message RAM Configuration
MB88121:
0080 0000
MB88121A/B/C: 0180 0000
r/w
0x0304
FRF
FIFO Rejection Filter
0180 0000
r/w
0x0308
FRFM
FIFO Rejection Filter Mask
0000 0000
r/w
0x030C
FCL
reserved (1)
MB88121/A: 0000 0000
MB88121B/C: 0000 0080
r
FIFO critical level
rev 1.48
29/Jan/2013
r/w
27
MB88121
Address
Symbol
FlexRay ASSP
Name
Reset
Access
Message Handler Status
0000 0000
r/w
reserved
MB88121:
0000 0000
MB88121A/B/C: 0000 0000
r
Message Buffer Status Registers
0x0310
MHDS
0x0314
LDTS
Last Dynamic Transmit Slot
r
-
reserved
FSR
FIFO Status Register
0x031C
MHDF
Message Handler Constraints Flags
0x0320
TXRQ1
Transmission Request 1
0000 0000
r
0x0324
TXRQ2
Transmission Request 2
0000 0000
r
0x0328
TXRQ3
Transmission Request 3
0000 0000
r
0x032C
TXRQ4
Transmission Request 4
0000 0000
r
0x0330
NDAT1
New Data 1
0000 0000
r
0x0334
NDAT2
New Data 2
0000 0000
r
0x0338
NDAT3
New Data 3
0000 0000
r
0x033C
NDAT4
New Data 4
0000 0000
r
0x0340
MBSC1
Message Buffer Status Changed 1
0000 0000
r
0x0344
MBSC2
Message Buffer Status Changed 2
0000 0000
r
0x0348
MBSC3
Message Buffer Status Changed 3
0000 0000
r
0x034C
MBSC4
Message Buffer Status Changed 4
0000 0000
r
-
reserved (40)
0000 0000
r
0x0318
0x0350 0x03EC
reserveds
MB88121/A: 0000 0000
MB88121B/C: 0000 0000
MB88121/A: 0000 0000
MB88121B/C: 0000 0000
r
r
r/w
Identification Registers
0x03F0
CREL
0x03F4
ENDN
Endian Register
-
reserved
0x03F8 0x03FC
reserved
Core Release Endian Register
reserved
MB88121/A: 0000 0000
MB88121B: 0726 0412
MB88121C: 1027 1031
r
MB88121/A: 0000 0000
MB88121B/C: 8765 4321
r
0000 0000
r
(Continued)
28
rev 1.48
29/Jan/2013
MB88121
FlexRay ASSP
(Continued)
Address
Symbol
Name
Reset
Access
Input Buffer
0x0400 -
WRDSn
Write Data Section [1...64]
0000 0000
r/w
0x0500
WRHS1
Write Header Section 1
0000 0000
r/w
0x0504
WRHS2
Write Header Section 2
0000 0000
r/w
0x0508
WRHS3
Write Header Section 3
0000 0000
r/w
0x050C
-
reserved (1)
0000 0000
r/w
0x0510
IBCM
Input Buffer Command Mask
0000 0000
r/w
0x0514
IBCR
Input Buffer Command Request
0000 0000
r/w
-
reserved (58)
0000 0000
r
0x04FC
0x0518 0x05FC
Output Buffer
0x0600 -
RDDSn
Read Data Section [1 ...64]
0000 0000
r
0x0700
RDHS1
Read Header Section 1
0000 0000
r
0x0704
RDHS2
Read Header Section 2
0000 0000
r
0x0708
RDHS3
Read Header Section 3
0000 0000
r
0x070C
MBS
Message Buffer Status
0000 0000
r
0x0710
OBCM
Output Buffer Command Mask
0000 0000
r/w
0x0714
OBCR
Output Buffer Command Request
0000 0000
r/w
0000 0000
r
0x06FC
0x0718 -
0x07FC
• Explanation on read/write
r/w: Readable and Writable
r: Read only
w: Write only
reserved (58)
Note : Any write access to reserved addresses in I/O map may result in unexpected behaviour. A read access to
reserved address results in reading “X”.
rev 1.48
29/Jan/2013
29
MB88121
FlexRay ASSP
■ VERSION INFORMATION REGISTER (VER)
Address
0x0000
31
24
23
16
15
8
7
0
VID[7:0]
INV[7:0]
CIV[7:0]
ECR[7:0]
R
R
R
R
Initial value
MB88121: 0x04107905
MB88121A 0x04207906
MB88121B: 0x043079FF
MB88121C: 0x044079FF
bit7 - bit0
ECR[7:0]
FlexRay IP Version
0x05
PreBeta2update
0x06
Beta
0xFF
Rev. 1.0 RC1 and above *)
bit15 - bit8
CIV[7:0]
0x79
LSI Number
MB88121/A/B/C
bit23 - bit16
INV[7:0]
LSI Version
0x10
MB88121
0x20
MB88121A
0x30
MB88121B
0x40
MB88121C
bit31 - bit24
VID[7:0]
0x04
R: Read only
*) look up CREL register for detailed IP version when reading 0xFF in ECR string
Bit
Name
Function
VID: JEDEC Vendor ID Code
The JEDEC Vendor ID Code is shown. The
value of MB88121, MB88121A , MB88121B
and MB88121C is 0x04. Writing is invalid.
bit23 - bit16
INV: LSI Version
The LSI Version information is shown. The
value of MB88121 is 0x10, the value of
MB88121A is 0x20 and the value of
MB88121B is 0x30 and the value of
MB88121C is 0x40. Writing is invalid.
bit15 - bit8
CIV: LSI Number
The LSI Number information is shown. The
value of MB88121, MB88121A , MB88121B
and MB88121C is 0x79. Writing is invalid.
ECR: FlexRay IP Version
The FlexRay IP Version information is shown.
The value of MB88121 is 0x05, the value of
MB88121A is 0x06. All other the value is
0xFF, the CREL register contains the IP version. Writing is invalid.
bit31 - bit24
bit7 - bit0
30
JEDEC Vendor ID
MB88121/A/B/C
rev 1.48
29/Jan/2013
MB88121
FlexRay ASSP
■ CLOCK CONTROL REGISTER (CCNT)
The CLOCK CONTROL Register (except SRST[1:0]) is writeable in DEFAULT_CONFIG (CCSV[5:0] = 00 0000)
or CONFIG state (CCSV[5:0] = 00 1111), only. SRST[1:0] is always writeable.
Address
0x0004
31
14
RSV
R/W
13
12
11
10
SRST[1:0] PMUL[2] RSV
R/W
R/W
R/W
9 8
6
7
5
4
3
2
1
0
RSV STOP RCLK PMUL[1:0] SSEL PON
SDIV[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0x00000000
R/W
bit0
PON
PLL Oscillator Enable
0
Stop PLL oscillator
1
Enable PLL oscillator
bit1
SSEL
System Clock Selection
0
Select the oscillation clock (X0/X1)
1
Select the PLL clock
bit11,bit3 - bit2
PMUL[2:0]
PLL Multiplier Selection
0
0
0
X0/X1 (4MHz) x 20 (80MHz)
0
0
1
X0/X1 (5MHz) x 16 (80MHz)
0
1
0
X0/X1 (8MHz) x 10 (80MHz)
0
1
1
X0/X1 (10MHz) x 8 (80MHz)
1
0
0
X0/X1 (16MHz) x 5 (80MHz)
0
1
X0/X1 (20MHz) x 4 (80MHz)
1
bit4
RCLK
RAM Clock Selection (MB88121A/B only)
0
Select System Clock
1
Select System Clock divided by 2
bit5
STOP
Clock Stop
0
Supply the system clock for FlexRay Controller
1
Stop the system clock for FlexRay Controller
bit8 - bit7
SDIV[1:0]
Division for system clock (MB88121A/B only)
0
0
System clock is divided by 1
0
1
System clock is divided by 2
1
0
System clock is divided by 4
1
1
System clock is divided by 8
bit13 - bit12
SRST[1:0]
Software Reset
See after sheet
bit31 - bit14, bit10 - bit9, bit6
Read only
R:
R/W: Read/Write
RSV
Reserved
These bits are reserved. Always write “0”. “0” is read.
rev 1.48
29/Jan/2013
31
MB88121
Bit
FlexRay ASSP
Name
bit31 - bit14 RSV: Reserved
bit13 - bit12 SRST[1:0]
bit10 - bit 9 RSV Reserved
bit8 - bit7
SDIV[1:0]:
Division for system
clock
Function
These bits are reserved. “0” is read. Write “0”.
These bits initialize Communication Controller. When "00", "01",
"10", "11" are written to these bits continuously, Communication
Controller is initialized.
First : write "00" to SRST[1:0]
Second: Write "01" to SRST[1:0]
Third : Write "10" to SRST[1:0]
Forth : Write "11" to SRST[1:0]
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