Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
PSoC® Programmable System-on-Chip™
PSoC® Programmable System-on-Chip™
Features
■
■
❐
Powerful Harvard-architecture processor
❐ M8C processor speeds up to 24 MHz
❐ Low power at high speed
❐ Operating voltage: 2.4 V to 5.25 V
❐ Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐ Industrial temperature range: –40 °C to +85 °C
❐
■
Versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O combinations
❐ Capacitive sensing application capability
■
Additional system resources
2 [2]
❐I C
master, slave, and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection (LVD)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
Advanced peripherals (PSoC® blocks)
❐ Four analog Type E PSoC blocks provide:
• Two comparators with digital-to-analog converter (DAC)
references
• Single or dual 10-bit 28 channel analog-to-digital
converters (ADC)
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse width modulators
(PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Full-duplex universal asynchronous receiver transmitter
(UART), serial peripheral interface (SPI) master or slave
• Connectable to all general purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
■
Flexible on-chip memory
❐ 8 KB flash program storage 50,000 erase/write cycles
❐ 512 bytes static random access memory (SRAM) data
storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
■
Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured, in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128-KB trace memory
■
Precision, programmable clocking
[1]
❐ Internal ±2.5% 24- / 48-MHz main oscillator
❐ Internal oscillator for watchdog and sleep
■
Programmable pin configurations
❐ 25-mA sink, 10-mA source on all GPIOs
❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
Up to eight analog inputs on GPIOs
Configurable interrupt on all GPIOs
Logic Block Diagram
Errata: For information on silicon errata, see “Errata” on page 50. Details include trigger conditions, devices affected, and proposed workaround.
Notes
1. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.
2. Errata: The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is transitioning in to or out of sleep
mode.
Cypress Semiconductor Corporation
Document Number: 38-12025 Rev. AJ
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 31, 2019
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
More Information
Cypress provides a wealth of data at www.cypress.com to help
you to select the right PSoC device for your design, and to help
you to quickly and effectively integrate the device into your
design. For a comprehensive list of resources, see the
knowledge base article, How to Design with PSoC® 1,
PowerPSoC®, and PLC – KBA88292. Following is an
abbreviated list for PSoC 1:
■
Overview: PSoC Portfolio, PSoC Roadmap
■
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
■
In addition, PSoC Designer includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 1 are:
®
❐ Getting Started with PSoC 1 – AN75320.
®
❐ PSoC 1 - Getting Started with GPIO – AN2094.
®
❐ PSoC 1 Analog Structure and Configuration – AN74170.
®
❐ PSoC 1 Switched Capacitor Analog Blocks – AN2041.
❐ Selecting Analog Ground and Reference – AN2219.
Note: For CY8C21x34B devices related Application note please
click here.
■
■
Development Kits:
❐ CY3210-PSoCEval1 supports all PSoC 1 Mixed-Signal Array
families, including automotive, except CY8C25/26xxx
devices. The kit includes an LCD module, potentiometer,
LEDs, and breadboarding space.
❐ CY3214-PSoCEvalUSB features a development board for
the CY8C24x94 PSoC device. Special features of the board
include USB and CapSense development and debugging
support.
Note: For CY8C21x34B devices related Development Kits
please click here.
The MiniProg1 and MiniProg3 devices provide interfaces for
flash programming and debug.
PSoC Designer
PSoC Designer is a free Windows-based Integrated Design
Environment (IDE). Develop your applications using a library of
pre-characterized analog and digital peripherals in a
drag-and-drop design environment. Then, customize your
design leveraging the dynamically generated API libraries of
code. Figure 1 shows PSoC Designer windows. Note: This is not
the default view.
1. Global Resources – all device hardware settings.
2. Parameters – the parameters of the currently selected User
Modules.
3. Pinout – information related to device pins.
4. Chip-Level Editor – a diagram of the resources available on
the selected chip.
5. Datasheet – the datasheet for the currently selected UM
6. User Modules – all available User Modules for the selected
device.
7. Device Resource Meter – device resource usage for the
current project configuration.
8. Workspace – a tree level diagram of files associated with the
project.
9. Output – output from project build and debug operations.
Note: For detailed information on PSoC Designer, go to
PSoC® Designer > Help > Documentation >
Designer Specific Documents > IDE User Guide.
Figure 1. PSoC Designer Layout
Document Number: 38-12025 Rev. AJ
Page 2 of 60
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Contents
PSoC Functional Overview .............................................. 4
The PSoC Core ........................................................... 4
The Digital System ...................................................... 4
The Analog System ..................................................... 5
Additional System Resources ..................................... 5
PSoC Device Characteristics ...................................... 6
Getting Started .................................................................. 6
Application Notes ........................................................ 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library .......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 8
Select User Modules ................................................... 8
Configure User Modules .............................................. 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug ....................................... 8
Pin Information ................................................................. 9
16-pin Part Pinout ........................................................ 9
CY8C21234 16-pin SOIC Pin Definitions .................... 9
20-pin Part Pinout ...................................................... 10
CY8C21334 20-pin SSOP Pin Definitions ................. 10
28-pin Part Pinout ...................................................... 11
CY8C21534 28-pin SSOP Pin Definitions ................. 11
32-pin Part Pinout ...................................................... 12
CY8C21434/CY8C21634
32-pin QFN Pin Definitions ............................................... 14
56-pin Part Pinout ...................................................... 15
CY8C21001 56-pin SSOP Pin Definitions ................. 15
Register Reference ......................................................... 17
Register Conventions ................................................ 17
Register Mapping Tables .......................................... 17
Document Number: 38-12025 Rev. AJ
Absolute Maximum Ratings .......................................... 20
Operating Temperature .................................................. 20
Electrical Specifications ................................................ 21
DC Electrical Characteristics ..................................... 21
AC Electrical Characteristics ..................................... 27
Packaging Information ................................................... 35
Thermal Impedances ................................................. 39
Solder Reflow Specifications ..................................... 39
Development Tool Selection ......................................... 40
Software .................................................................... 40
Development Kits ...................................................... 40
Evaluation Tools ........................................................ 40
Device Programmers ................................................. 41
Accessories (Emulation and Programming) .............. 41
Ordering Information ...................................................... 42
Ordering Code Definitions ......................................... 43
Acronyms ........................................................................ 44
Reference Documents .................................................... 44
Document Conventions ................................................. 45
Units of Measure ....................................................... 45
Numeric Conventions ................................................ 45
Glossary .......................................................................... 45
Errata ............................................................................... 50
Part Numbers Affected .............................................. 50
CY8C21X34 Qualification Status .............................. 50
CY8C21X34 Errata Summary ................................... 51
Document History Page ................................................. 52
Sales, Solutions, and Legal Information ...................... 60
Worldwide Sales and Design Support ....................... 60
Products .................................................................... 60
PSoC® Solutions ...................................................... 60
Cypress Developer Community ................................. 60
Technical Support ..................................................... 60
Page 3 of 60
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The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple
traditional MCU-based system components with one low-cost
single-chip programmable component. A PSoC device includes
configurable blocks of analog and digital logic, and
programmable interconnect. This architecture makes it possible
for you to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast central processing unit (CPU), flash program memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts.
The PSoC architecture, shown in Figure 2, consists of four main
areas: the core, the system resources, the digital system, and
the analog system. Configurable global bus resources allow
combining all of the device resources into a complete custom
system. Each CY8C21x34 PSoC device includes four digital
blocks and four analog blocks. Depending on the PSoC
package, up to 28 GPIOs are also included. The GPIOs provide
access to the global digital and analog interconnects.
The PSoC Core
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and internal main
oscillator (IMO) and internal low speed oscillator (ILO). The CPU
core, called the M8C, is a powerful processor with speeds up to
24 MHz [3]. The M8C is a four-million instructions per second
(MIPS) 8-bit Harvard-architecture microprocessor.
System resources provide these additional capabilities:
■
Digital clocks for increased flexibility
■
I2C [4] functionality to implement an I2C master and slave
■
An internal voltage reference, multi-master, that provides an
absolute value of 1.3 V to a number of PSoC subsystems
■
A SMP that generates normal operating voltages from a single
battery cell
■
Various system resets supported by the M8C
The Digital System
The digital system consists of four digital PSoC blocks. Each
block is an 8-bit resource that is used alone or combined with
other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which
are called user modules. Digital peripheral configurations
include:
■
PWMs (8- to 32-bit)
■
PWMs with dead band (8- to 32-bit)
■
Counters (8- to 32-bit)
■
Timers (8- to 32-bit)
■
UART 8- with selectable parity
■
Serial peripheral interface (SPI) master and slave
■
I2C slave and multi-master [4]
■
CRC/generator (8-bit)
■
IrDA
■
PRS generators (8-bit to 32-bit)
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 6.
Figure 2. Digital System Block Diagram
Port 3
Port 0
Digital Clocks To System Bus
From Core
To Analog
System
DIGITAL SYSTEM
The digital system consists of an array of digital PSoC blocks that
may be configured into any number of digital peripherals. The
digital blocks are connected to the GPIOs through a series of
global buses. These buses can route any signal to any pin,
freeing designs from the constraints of a fixed peripheral
controller.
The analog system consists of four analog PSoC blocks,
supporting comparators, and analog-to-digital conversion up to
10 bits of precision.
Port 1
Port 2
Row Input
Configuration
Digital PSoC Block Array
4
Row 0
DBB00
DBB01
DCB02
DCB03
4
8
Row Output
Configuration
PSoC Functional Overview
8
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Notes
3. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.
4. Errata: The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is transitioning in to or out of
sleep mode.
Document Number: 38-12025 Rev. AJ
Page 4 of 60
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The Analog System
The Analog Multiplexer System
The analog system consists of four configurable blocks that allow
for the creation of complex analog signal flows. Analog
peripherals are very flexible and can be customized to support
specific application requirements. Some of the common PSoC
analog functions for this device (most available as user modules)
are:
The analog mux bus can connect to every GPIO pin. Pins may
be connected to the bus individually or in any combination. The
bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. An additional 8:1
analog input multiplexer provides a second path to bring Port 0
pins to the analog array.
Switch-control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
ADCs (single or dual, with 8-bit or 10-bit resolution)
■
Pin-to-pin comparator
■
Single-ended comparators (up to two) with absolute (1.3 V)
reference or 8-bit DAC reference
■
Track pad, finger sensing
1.3-V reference (as a system resource)
■
Chip-wide mux that allows analog input from any I/O pin
■
Crosspoint connection between any I/O pin combinations
■
In most PSoC devices, analog blocks are provided in columns of
three, which includes one continuous time (CT) and two switched
capacitor (SC) blocks. The CY8C21x34 devices provide limited
functionality Type E analog blocks. Each column contains one
CT Type E block and one SC Type E block. Refer to the PSoC
Technical Reference Manual for detailed information on the
CY8C21x34’s Type E analog blocks.
Figure 3. Analog System Block Diagram
Array Input
Configuration
Additional System Resources
System resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch-mode pump,
low-voltage detection, and power-on-reset (POR).
■
■
ACI0[1:0]
LVD interrupts can signal the application of falling voltage
levels, while the advanced POR circuit eliminates the need for
a system supervisor.
■
An internal 1.3-V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
An integrated switch-mode pump generates normal operating
voltages from a single 1.2-V battery cell, providing a low cost
boost converter.
■
Versatile analog multiplexer system.
X
X
X
ACOL1MUX
X
Analog Mux Bus
X
Array
ACE00
ACE01
ASE10
ASE11
The I2C [5] module provides 100- and 400-kHz communication
over two wires. Slave, master, and multi-master modes are all
supported.
■
ACI1[1:0]
All I/O
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
Note
5. Errata: The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is transitioning in to or out of sleep
mode.
Document Number: 38-12025 Rev. AJ
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PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is
highlighted in Table 1.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Analog
Outputs Columns
Analog
Blocks
SRAM
Size
Flash
Size
CY8C29x66
up to 64
4
16
up to 12
4
4
12
2K
32K
CY8C28xxx
up to 44
up to 3
up to 12
up to 44
up to 4
up to 6
up to
12 + 4[6]
1K
16K
CY8C27x43
up to 44
2
8
up to 12
4
4
12
256
16K
CY8C24x94
up to 56
1
4
up to 48
2
2
CY8C24x23A
up to 24
1
4
up to 12
2
2
6
1K
16K
6
256
4K
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
CY8C22x45
up to 38
2
8
up to 38
0
4
6[6]
1K
16K
CY8C21x45
up to 24
1
4
up to 24
0
4
6[6]
512
8K
CY8C21x34
up to 28
1
4
up to 28
0
2
4[6]
512
8K
CY8C21x23
up to 16
1
4
up to 8
0
2
4[6]
256
4K
CY8C20x34
up to 28
0
0
up to 28
0
0
3[6,7]
512
8K
0
3[6,7]
up to 2K
up to 32K
CY8C20xx6
up to 36
0
0
up to 36
0
Getting Started
covers a wide variety of topics and skill levels to assist you in
your designs.
For in-depth information, along with detailed programming
details, see the PSoC® Technical Reference Manual.
CYPros Consultants
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Notes
6. Limited analog functionality.
7. Two analog blocks and one CapSense®.
Document Number: 38-12025 Rev. AJ
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Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and are
linked with other software modules to get absolute addressing.
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
■
Integrated source-code editor (C and assembly)
Debugger
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also allows you to create a trace buffer of registers and memory
locations of interest.
Built-in support for communication interfaces:
2 [8] slaves and masters
❐ Hardware and software I C
❐ Full-speed USB 2.0
❐ Up
to
four
full-duplex
universal
asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
■
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are ADCs, DACs, amplifiers, and filters. Configure
the user modules for your chosen application and connect them
to each other and to the proper pins. Then generate your project.
This prepopulates your project with APIs and libraries that you
can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this allows you to use more than 100 percent
of PSoC’s resources for an application.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an online support Forum
to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
Note
8. Errata: The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is transitioning in to or out of sleep
mode.
Document Number: 38-12025 Rev. AJ
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process is summarized in four steps:
specifications. Each datasheet describes the use of each user
module parameter, and other information you may need to
successfully implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
1. Select User Modules.
Generate, Verify, and Debug
2. Configure User Modules.
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run-time and interrupt service routines that
you can adapt as needed.
3. Organize and Connect.
4. Generate, Verify, and Debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each 8 bits of resolution. The user module parameters permit
you to establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus. All the user modules are documented in
datasheets that may be viewed directly in PSoC Designer or on
the Cypress website. These user module datasheets explain the
internal operation of the user module and provide performance
Document Number: 38-12025 Rev. AJ
A complete code development environment allows you to
develop and customize your applications in either C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging
capabilities rival those of systems costing many times more. In
addition to traditional single-step, run-to-breakpoint, and
watch-variable features, the debug interface provides a large
trace buffer and allows you to define complex breakpoint events.
These include monitoring address and data bus values, memory
locations, and external signals.
Page 8 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
Pin Information
The CY8C21x34 PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with
a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, SMP, and XRES are not capable of
Digital I/O.
16-pin Part Pinout
Figure 4. CY8C21234 16-pin PSoC Device
A, I, M, P0[7]
1
16
VDD
A, I, M, P0[5]
2
15
P0[6], A, I, M
A, I, M, P0[3]
3
14
P0[4], A, I, M
A, I, M, P0[1]
4
13
P0[2], A, I, M
SMP
5
12
P0[0], A, I, M
VSS
6
11
P1[4], EXTCLK, M
M, I2C SCL, P1[1]
7
10
P1[2], M
VSS
8
9
SOIC
P1[0], I2C SDA, M
CY8C21234 16-pin SOIC Pin Definitions
Pin No.
Type
Digital
Name
Analog
Description
1
I/O
I, M
P0[7]
Analog column mux input
2
I/O
I, M
P0[5]
Analog column mux input
3
I/O
I, M
P0[3]
Analog column mux input, integrating input
4
I/O
I, M
P0[1]
Analog column mux input, integrating input
5
Power
SMP
Switch-mode pump (SMP) connection to required external components
6
Power
VSS
Ground connection [9]
7
I/O
P1[1]
I2C serial clock (SCL), ISSP-SCLK[10]
8
Power
VSS
Ground connection [9]
9
I/O
M
P1[0]
I2C serial data (SDA), ISSP-SDATA[10]
10
I/O
M
P1[2]
11
I/O
M
P1[4]
Optional external clock input (EXTCLK)
12
I/O
I, M
P0[0]
Analog column mux input
13
I/O
I, M
P0[2]
Analog column mux input
14
I/O
I, M
P0[4]
Analog column mux input
15
I/O
I, M
P0[6]
Analog column mux input
16
Power
VDD
Supply voltage
M
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Notes
9. All VSS pins should be brought out to one common GND plane.
10. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12025 Rev. AJ
Page 9 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
20-pin Part Pinout
Figure 5. CY8C21334 20-pin PSoC Device
A, I, M, P0[7]
1
20
VDD
A, I, M, P0[5]
2
19
P0[6], A, I, M
A, I, M, P0[3]
3
18
P0[4], A, I, M
A, I, M, P0[1]
4
17
P0[2], A, I, M
VSS
5
16
P0[0], A, I, M
M, I2C SCL, P1[7]
6
15
XRES
M, I2C SDA, P1[5]
7
14
P1[6], M
M, P1[3]
8
13
P1[4], EXTCLK, M
M, I2C SCL, P1[1]
9
12
P1[2], M
VSS
10
11
P1[0], I2C SDA, M
SSOP
CY8C21334 20-pin SSOP Pin Definitions
Pin No.
Type
Digital
Name
Analog
Description
1
I/O
I, M
P0[7]
Analog column mux input
2
I/O
I, M
P0[5]
Analog column mux input
3
I/O
I, M
P0[3]
Analog column mux input, integrating input
4
I/O
I, M
P0[1]
Analog column mux input, integrating input
5
Power
VSS
Ground connection [11]
6
I/O
M
P1[7]
I2C SCL
7
I/O
M
P1[5]
I2C SDA
8
I/O
M
P1[3]
9
I/O
M
P1[1]
I2C SCL, ISSP-SCLK[12]
10
Power
VSS
Ground connection [11]
11
I/O
M
P1[0]
I2C SDA, ISSP-SDATA[12]
12
I/O
M
P1[2]
13
I/O
M
P1[4]
14
I/O
M
P1[6]
15
Input
16
I/O
17
I/O
18
Optional external clock input (EXTCLK)
XRES
Active high external reset with internal pull-down
I, M
P0[0]
Analog column mux input
I, M
P0[2]
Analog column mux input
I/O
I, M
P0[4]
Analog column mux input
19
I/O
I, M
P0[6]
Analog column mux input
20
Power
VDD
Supply voltage
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Notes
11. All VSS pins should be brought out to one common GND plane.
12. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12025 Rev. AJ
Page 10 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
28-pin Part Pinout
Figure 6. CY8C21534 28-pin PSoC Device
A, I, M, P0[7]
1
28
VDD
A, I, M, P0[5]
2
27
P0[6], A, I, M
A, I, M, P0[3]
3
26
P0[4], A, I, M
A, I, M, P0[1]
4
25
P0[2], A, I, M
M, P2[7]
5
24
P0[0], A, I, M
M, P2[5]
6
23
P2[6], M
M, P2[3]
7
22
P2[4], M
M, P2[1]
8
21
P2[2], M
VSS
9
20
P2[0], M
M, I2C SCL, P1[7]
10
19
XRES
M, I2C SDA, P1[5]
11
18
P1[6], M
M, P1[3]
12
17
P1[4], EXTCLK, M
M, I2C SCL, P1[1]
13
16
P1[2], M
VSS
14
15
P1[0], I2C SDA, M
SSOP
CY8C21534 28-pin SSOP Pin Definitions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Type
Digital
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
Analog
I, M
I, M
I, M
I, M
M
M
I, M
I, M
M
M
M
M
M
M
M
M
I, M
I, M
M
M
I, M
I, M
I, M
I, M
Name
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
VSS
P1[7]
P1[5]
P1[3]
P1[1]
VSS
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
VDD
Description
Analog column mux input
Analog column mux input and column output
Analog column mux input and column output, integrating input
Analog column mux input, integrating input
Direct switched capacitor block input
Direct switched capacitor block input
Ground connection [13]
I2C SCL
I2C SDA
I2C SCL, ISSP-SCLK[14]
Ground connection [13]
I2C SDA, ISSP-SDATA[14]
Optional external clock input (EXTCLK)
Active high external reset with internal pull-down
Direct switched capacitor block input
Direct switched capacitor block input
Analog column mux input
Analog column mux input
Analog column mux input
Analog column mux input
Supply voltage
LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input.
Notes
13. All VSS pins should be brought out to one common GND plane.
14. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12025 Rev. AJ
Page 11 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
32-pin Part Pinout
Figure 7. CY8C21434 32-pin PSoC Device
Figure 8. CY8C21634 32-pin PSoC Device
Document Number: 38-12025 Rev. AJ
Page 12 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QFN
(Top View)
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
M, I2C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
9
10
11
12
13
14
15
16
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
M, P3[3]
M, P3[1]
M, I2C SCL, P1[7]
32
31
30
29
28
27
26
25
Vss
P0[3], A, I, M
P0[5], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
Figure 9. CY8C21434 32-pin Sawn PSoC Device Sawn
1
2
3
4
5
6
7
8
QFN
(Top View)
24
23
22
21
20
19
18
17
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
M, I2C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
9
10
11
12
13
14
15
16
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
SMP
Vss
M, I2C SCL, P1[7]
32
31
30
29
28
27
26
25
Vss
P0[3], A, I, M
P0[5], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
Figure 10. CY8C21634 32-pin Sawn PSoC Device Sawn
Document Number: 38-12025 Rev. AJ
Page 13 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
CY8C21434/CY8C21634 32-pin QFN Pin Definitions
Pin No. [15]
Type
Digital
Analog
Name
1
I/O
I, M
P0[1]
2
I/O
M
P2[7]
3
I/O
M
P2[5]
4
I/O
M
P2[3]
5
I/O
M
P2[1]
6
I/O
M
P3[3]
6
Power
7
I/O
7
Power
8
I/O
9
Description
Analog column mux input, integrating input
In CY8C21434 part
SMP
SMP connection to required external components in CY8C21634 part
P3[1]
In CY8C21434 part
VSS
Ground connection in CY8C21634 part [16]
M
P1[7]
I2C SCL
I/O
M
P1[5]
I2C SDA
10
I/O
M
P1[3]
11
I/O
M
P1[1]
I2C SCL, ISSP-SCLK[17]
12
Power
VSS
Ground connection [16]
13
I/O
M
P1[0]
I2C SDA, ISSP-SDATA[17]
14
I/O
M
P1[2]
15
I/O
M
P1[4]
16
I/O
M
P1[6]
17
Input
18
I/O
M
P3[0]
19
I/O
M
P3[2]
20
I/O
M
P2[0]
21
I/O
M
P2[2]
22
I/O
M
P2[4]
23
I/O
M
P2[6]
24
I/O
I, M
P0[0]
Analog column mux input
25
I/O
I, M
P0[2]
Analog column mux input
26
I/O
I, M
P0[4]
Analog column mux input
27
I/O
I, M
P0[6]
Analog column mux input
28
Power
VDD
Supply voltage
29
I/O
I, M
P0[7]
Analog column mux input
30
I/O
I, M
P0[5]
Analog column mux input
31
I/O
I, M
P0[3]
Analog column mux input, integrating input
32
Power
VSS
Ground connection [16]
M
XRES
Optional external clock input (EXTCLK)
Active high external reset with internal pull-down
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Notes
15. The center pad on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must
be electrically floated and not connected to any other signal.
16. All VSS pins should be brought out to one common GND plane.
17. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12025 Rev. AJ
Page 14 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
56-pin Part Pinout
The 56-pin SSOP part is for the CY8C21001 on-chip debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Figure 10. CY8C21001 56-pin PSoC Device
V ss
P 0[7]
P 0[5]
P 0[3]
P 0[1]
P 2[7]
P 2[5]
P 2[3]
P 2[1]
NC
NC
NC
NC
OCDE
OCDO
SMP
V ss
V ss
P 3[3]
P 3[1]
NC
NC
I2C S C L, P 1[7]
I2C S D A , P 1[5]
NC
P 1[3]
S C LK , I2C S C L, P 1[1]
V ss
A I,
A I,
A I,
A I,
1
2
56
55
3
4
5
6
7
8
9
10
54
53
52
51
18
19
20
21
22
23
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
24
25
33
32
26
27
28
31
30
11
12
13
14
15
16
17
SS O P
29
V dd
P 0[6],
P 0[4],
P 0[2],
P 0[0],
P 2[6]
AI
AI
AI
AI
P 2[4]
P 2[2]
P 2[0]
NC
NC
P 3[2]
P 3[0]
C C LK
H C LK
XR E S
NC
NC
NC
NC
NC
NC
P 1[6]
P 1[4], E XTC LK
P 1[2]
P 1[0], I2C S D A , S D A TA
NC
NC
CY8C21001 56-pin SSOP Pin Definitions
Type
Pin No.
Digital
Pin Name
Analog
Description
VSS
Ground connection [18]
I
P0[7]
Analog column mux input
I/O
I
P0[5]
Analog column mux input and column output
I/O
I
P0[3]
Analog column mux input and column output
5
I/O
I
P0[1]
Analog column mux input
6
I/O
7
I/O
8
I/O
I
9
I/O
I
1
Power
2
I/O
3
4
P2[7]
P2[5]
P2[3]
Direct switched capacitor block input
P2[1]
Direct switched capacitor block input
10
NC
No connection. Pin must be left floating
11
NC
No connection. Pin must be left floating
12
NC
No connection. Pin must be left floating
13
NC
No connection. Pin must be left floating
14
OCD
OCDE
OCD even data I/O
15
OCD
OCDO
OCD odd data output
16
Power
SMP
SMP connection to required external components
17
Power
VSS
Ground connection [18]
18
Power
VSS
Ground connection [18]
19
I/O
P3[3]
Document Number: 38-12025 Rev. AJ
Page 15 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
CY8C21001 56-pin SSOP Pin Definitions (continued)
Type
Pin No.
20
Digital
Pin Name
Analog
I/O
Description
P3[1]
21
NC
No connection. Pin must be left floating
22
NC
No connection. Pin must be left floating
23
I/O
P1[7]
I2C SCL
24
I/O
P1[5]
I2C SDA
25
NC
No connection. Pin must be left floating
26
I/O
P1[3]
IFMTEST
27
I/O
P1[1]
I2C SCL, ISSP-SCLK[19]
28
Power
VSS
Ground connection [18]
29
NC
No connection. Pin must be left floating
30
NC
No connection. Pin must be left floating
31
I/O
P1[0]
I2C SDA, ISSP-SDATA[19]
32
I/O
P1[2]
VFMTEST
33
I/O
P1[4]
Optional external clock input (EXTCLK)
34
I/O
P1[6]
35
NC
No connection. Pin must be left floating
36
NC
No connection. Pin must be left floating
37
NC
No connection. Pin must be left floating
38
NC
No connection. Pin must be left floating
39
NC
No connection. Pin must be left floating
40
NC
No connection. Pin must be left floating
41
Input
XRES
Active high external reset with internal pull-down
42
OCD
HCLK
OCD high-speed clock output
43
OCD
CCLK
OCD CPU clock output
44
I/O
P3[0]
45
I/O
P3[2]
46
47
NC
No connection. Pin must be left floating
NC
No connection. Pin must be left floating
48
I/O
I
P2[0]
49
I/O
I
50
I/O
51
I/O
52
I/O
I
P0[0]
Analog column mux input
53
I/O
I
P0[2]
Analog column mux input and column output
54
I/O
I
P0[4]
Analog column mux input and column output
55
I/O
I
P0[6]
Analog column mux input
56
Power
VDD
Supply voltage
P2[2]
P2[4]
P2[6]
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
Notes
18. All VSS pins should be brought out to one common GND plane.
19. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12025 Rev. AJ
Page 16 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
Register Reference
This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, see the PSoC Technical Reference
Manual.
Register Conventions
The register conventions specific to this section are listed in Table 2.
Table 2. Register Conventions
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Register Mapping Tables
The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into
two banks, Bank 0 and Bank 1. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the
XOI bit is set to 1, the user is in Bank 1.
Note In the following register mapping tables, blank fields are reserved and must not be accessed.
Document Number: 38-12025 Rev. AJ
Page 17 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
Table 3. Register Map 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
Addr (0,Hex) Access
Name
00
RW
01
RW
02
RW
03
RW
04
RW
05
RW
06
RW
07
RW
08
RW
09
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
AMUXCFG
DBB00DR2
22
RW
PWM_CR
DBB00CR0
23
#
DBB01DR0
24
#
CMP_CR0
DBB01DR1
25
W
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
DCB02DR0
28
#
ADC0_CR
DCB02DR1
29
W
ADC1_CR
DCB02DR2
2A
RW
DCB02CR0
2B
#
DCB03DR0
2C
#
TMP_DR0
DCB03DR1
2D
W
TMP_DR1
DCB03DR2
2E
RW
TMP_DR2
DCB03CR0
2F
#
TMP_DR3
30
31
32
ACE00CR1
33
ACE00CR2
34
35
36
ACE01CR1
37
ACE01CR2
38
39
3A
3B
3C
3D
3E
3F
Blank fields are reserved and must not be accessed.
Document Number: 38-12025 Rev. AJ
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
#
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASE10CR0
Addr (0,Hex)
80
81
82
83
ASE11CR0
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
RW
Name
RW
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_CR0
DEC_CR1
RW
RW
RW
RW
RW
RW
RW
CPU_F
DAC_D
CPU_SCR1
CPU_SCR0
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RW
RW
RL
RW
#
#
Page 18 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
Table 4. Register Map 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
Addr (1,Hex) Access
Name
00
RW
01
RW
02
RW
03
RW
04
RW
05
RW
06
RW
07
RW
08
RW
09
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
DBB00FN
20
RW
CLK_CR0
DBB00IN
21
RW
CLK_CR1
DBB00OU
22
RW
ABF_CR0
23
AMD_CR0
DBB01FN
24
RW
CMP_GO_EN
DBB01IN
25
RW
DBB01OU
26
RW
AMD_CR1
27
ALT_CR0
DCB02FN
28
RW
DCB02IN
29
RW
DCB02OU
2A
RW
2B
CLK_CR3
DCB03FN
2C
RW
TMP_DR0
DCB03IN
2D
RW
TMP_DR1
DCB03OU
2E
RW
TMP_DR2
2F
TMP_DR3
30
31
32
ACE00CR1
33
ACE00CR2
34
35
36
ACE01CR1
37
ACE01CR2
38
39
3A
3B
3C
3D
3E
3F
Blank fields are reserved and must not be accessed.
Document Number: 38-12025 Rev. AJ
Addr (1,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASE10CR0
Addr (1,Hex)
80
81
82
83
ASE11CR0
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
RW
Name
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
ADC0_TR
ADC1_TR
IMO_TR
ILO_TR
BDG_TR
ECO_TR
RW
RW
RW
RW
RW
RW
RW
CPU_F
FLS_PR1
DAC_CR
CPU_SCR1
CPU_SCR0
Addr (1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
W
W
RW
W
RL
RW
RW
#
#
Page 19 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
TBAKETEMP Bake temperature
Min
Typ
Max
Units
Notes
–55
25
+100
°C
Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25 °C ± 25 °C.
Extended duration storage
temperatures above 65 °C
degrade reliability.
–
125
See
package
label
°C
See
package
label
–
72
Hours
–40
–
+85
°C
tBAKETIME
Bake time
TA
Ambient temperature with power applied
VDD
Supply voltage on VDD relative to VSS
–0.5
–
+6.0
V
VIO
DC input voltage
VSS – 0.5
–
VDD + 0.5
V
VIOZ
DC voltage applied to tri-state
VSS – 0.5
–
VDD + 0.5
V
IMIO
Maximum current into any port pin
–25
–
+50
mA
ESD
Electrostatic discharge voltage
2000
–
–
V
LU
Latch-up current
–
–
200
mA
Human body model ESD.
Operating Temperature
Min
Typ
Max
Units
TA
Symbol
Ambient temperature
Description
–40
–
+85
°C
TJ
Junction temperature
–40
–
+100
°C
Document Number: 38-12025 Rev. AJ
Notes
The temperature rise from ambient to
junction is package specific. See
Table 29 on page 39. You must limit
the power consumption to comply
with this requirement.
Page 20 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For up-to-date electrical specifications,
visit the Cypress web site at http://www.cypress.com.
Specifications are valid for –40 C TA 85 C and TJ 100 C as specified, except where noted.
Refer to Table 16 on page 27 for the electrical specifications for the IMO using SLIMO mode.
Figure 11. Voltage versus CPU Frequency
Figure 12. IMO Frequency Trim Options
Vdd Voltage
lid ng
Va ati
er ion
Op eg
R
4.75
SLIMO Mode = 0
5.25
Vdd Voltage
5.25
4.75
3.60
3.00
3.00
2.40
2.40
93 kHz
12 MHz
3 MHz
24 MHz
93 kHz
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=1
6 MHz
12 MHz
24 MHz
IMO Frequency
CPU Frequency
DC Electrical Characteristics
DC Chip-Level Specifications
Table 5 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 5. DC Chip-level Specifications
Symbol
Description
VDD
Supply voltage
IDD
Supply current, IMO = 24 MHz
Min
2.40
–
Typ
–
3
Max
5.25
4
Units
Notes
V See Table 13 on page 25
mA Conditions are VDD = 5.0 V,
TA = 25 °C, CPU = 3 MHz,
48 MHz disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz
mA Conditions are VDD = 3.3 V,
TA = 25 °C, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz
mA Conditions are VDD = 2.55 V,
TA = 25 °C, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz
µA VDD = 2.55 V, 0 °C TA 40 °C
IDD3
Supply current, IMO = 6 MHz using
SLIMO mode.
–
1.2
2
IDD27
Supply current, IMO = 6 MHz using
SLIMO mode.
–
1.1
1.5
ISB27
–
2.6
4
–
2.8
5
µA
VDD = 3.3 V, –40 °C TA 85 °C
VREF
Sleep (mode) current with POR, LVD,
sleep timer, WDT, and internal slow
oscillator active. Mid temperature range.
Sleep (mode) current with POR, LVD,
Sleep Timer, WDT, and internal slow
oscillator active.
Reference voltage (Bandgap)
1.28
1.30
1.32
V
VREF27
Reference voltage (Bandgap)
1.16
1.30
1.33
V
Trimmed for appropriate VDD
VDD = 3.0 V to 5.25 V
Trimmed for appropriate VDD
VDD = 2.4 V to 3.0 V
AGND
Analog ground
ISB
Document Number: 38-12025 Rev. AJ
VREF – 0.003 VREF VREF + 0.003
V
Page 21 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
DC General-Purpose I/O Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 6. 5-V and 3.3-V DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
4
5.6
8
k
Pull-down resistor
4
5.6
8
k
High output level
VDD – 1.0
–
–
V
IOH = 10 mA, VDD = 4.75 to 5.25 V
(8 total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])
VOL
Low output level
–
–
0.75
V
IOL = 25 mA, VDD = 4.75 to 5.25 V
(8 total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5]))
IOH
High level source current
10
–
–
mA
VOH = VDD – 1.0 V, see the limitations
of the total current in the note for VOH
IOL
Low level sink current
25
–
–
mA
VOL = 0.75 V, see the limitations of the
total current in the note for VOL
VIL
Input low level
–
–
0.8
V
VDD = 3.0 to 5.25
V
VDD = 3.0 to 5.25
–
mV
RPU
Pull-up resistor
RPD
VOH
Notes
VIH
Input high level
2.1
–
VH
Input hysteresis
–
60
IIL
Input leakage (absolute value)
–
1
–
nA
Gross tested to 1 µA
CIN
Capacitive load on pins as input
–
3.5
10
pF
Package and pin dependent
Temp = 25 °C
COUT
Capacitive load on pins as output
–
3.5
10
pF
Package and pin dependent
Temp = 25 °C
Min
Typ
Max
Units
4
5.6
8
k
Table 7. 2.7-V DC GPIO Specifications
Symbol
Description
Notes
RPU
Pull-up resistor
RPD
Pull-down resistor
4
5.6
8
k
VOH
High output level
VDD – 0.4
–
–
V
IOH = 2.5 mA (6.25 Typ), VDD = 2.4 to
3.0 V (16 mA maximum, 50 mA Typ
combined IOH budget)
VOL
Low output level
–
–
0.75
V
IOL = 10 mA, VDD = 2.4 to 3.0 V
(90 mA maximum combined IOL
budget)
IOH
High level source current
2.5
–
–
mA
VOH = VDD – 0.4 V, see the limitations
of the total current in the note for VOH
IOL
Low level sink current
10
–
–
mA
VOL = 0.75 V, see the limitations of the
total current in the note for VOL
VIL
Input low level
–
–
0.75
V
VDD = 2.4 to 3.0
VIH
Input high level
2.0
–
–
V
VDD = 2.4 to 3.0
VH
Input hysteresis
–
90
–
mV
IIL
Input leakage (absolute value)
–
1
–
nA
Gross tested to 1 µA
CIN
Capacitive load on pins as input
–
3.5
10
pF
Package and pin dependent
Temp = 25 °C
COUT
Capacitive load on pins as output
–
3.5
10
pF
Package and pin dependent
Temp = 25 °C
Document Number: 38-12025 Rev. AJ
Page 22 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
DC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 8. 5-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
Min
Typ
Max
Units
–
2.5
15
mV
Notes
TCVOSOA Average input offset voltage drift
–
10
–
µV/°C
IEBOA
Input leakage current (Port 0 analog pins
7-to-1)
–
200
–
pA
IEBOA00
Input leakage current (Port 0, Pin 0 analog pin)
–
50
–
nA
Gross tested to 1 µA
CINOA
Input capacitance (Port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
VCMOA
Common mode voltage range
0.0
–
VDD – 1.0
V
GOLOA
Open loop gain
–
80
–
dB
ISOA
Amplifier supply current
–
10
30
µA
Min
Typ
Max
Units
–
2.5
15
mV
–
10
–
µV/°C
Gross tested to 1 µA
Table 9. 3.3-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
TCVOSOA Average input offset voltage drift
Notes
IEBOA
Input leakage current (Port 0 analog pins)
–
200
–
pA
Gross tested to 1 µA
IEBOA00
Input leakage current (Port 0, Pin 0 analog pin)
–
50
–
nA
Gross tested to 1 µA
CINOA
Input capacitance (Port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
VCMOA
Common mode voltage range
0
–
VDD –
1.0
V
GOLOA
Open loop gain
–
80
–
dB
ISOA
Amplifier supply current
–
10
30
µA
Min
Typ
Max
Units
–
2.5
15
mV
Table 10. 2.7-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
TCVOSOA Average input offset voltage drift
–
10
–
µV/°C
IEBOA
Input leakage current (Port 0 analog pins)
–
200
–
pA
Notes
Gross tested to 1 µA
IEBOA00
Input leakage current (Port 0, Pin 0 analog pin)
–
50
–
nA
Gross tested to 1 µA
CINOA
Input capacitance (Port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
VCMOA
Common mode voltage range
0
–
VDD –
1.0
V
GOLOA
Open loop gain
–
80
–
dB
ISOA
Amplifier supply current
–
10
30
µA
Document Number: 38-12025 Rev. AJ
Page 23 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
DC Switch Mode Pump Specifications
Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Figure 13. Basic Switch Mode Pump Circuit
D1
Vdd
V PUMP
L1
V BAT
+
SMP
Battery
C1
PSoC
Vss
Table 11. DC Switch Mode Pump (SMP) Specifications
Symbol
VPUMP5V
Description
5 V output voltage from pump
Min
4.75
Typ
5.0
Max
5.25
VPUMP3V
3.3 V output voltage from pump
3.00
3.25
3.60
VPUMP2V
2.6 V output voltage from pump
2.45
2.55
2.80
IPUMP
VBAT5V
Available output current
VBAT = 1.8 V, VPUMP = 5.0 V
VBAT = 1.5 V, VPUMP = 3.25 V
VBAT = 1.3 V, VPUMP = 2.55 V
Input voltage range from battery
5
8
8
1.8
–
–
–
–
–
–
–
5.0
VBAT3V
Input voltage range from battery
1.0
–
3.3
VBAT2V
Input voltage range from battery
1.0
–
2.8
VBATSTART
Minimum input voltage from battery to start
pump
1.2
–
–
VPUMP_Line
Line regulation (over Vi range)
–
5
–
VPUMP_Load
Load regulation
–
5
–
–
100
–
VPUMP_Ripple Output voltage ripple (depends on cap/load)
Units
Notes
V
Configured as in Note 20
Average, neglecting ripple
SMP trip voltage is set to 5.0 V
V
Configured as in Note 20
Average, neglecting ripple.
SMP trip voltage is set to 3.25 V
V
Configured as in Note 20
Average, neglecting ripple.
SMP trip voltage is set to 2.55 V
Configured as in Note 20
mA SMP trip voltage is set to 5.0 V
mA SMP trip voltage is set to 3.25 V
mA SMP trip voltage is set to 2.55 V
V
Configured as in Note 20
SMP trip voltage is set to 5.0 V
V
Configured as in Note 20
SMP trip voltage is set to 3.25 V
V
Configured as in Note 20
SMP trip voltage is set to 2.55 V
V
Configured as in Note 20
0 C TA 100. 1.25 V at
TA = –40 °C
%VO Configured as in Note 20
VO is the “VDD Value for PUMP
Trip” specified by the VM[2:0]
setting in the DC POR and LVD
Specification, Table 13 on page 25
%VO Configured as in Note 20
VO is the “VDD Value for PUMP
Trip” specified by the VM[2:0]
setting in the DC POR and LVD
Specification, Table 13 on page 25
mVpp Configured as in Note 20
Load is 5 mA
Note
20. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 13 on page 24.
Document Number: 38-12025 Rev. AJ
Page 24 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
Table 11. DC Switch Mode Pump (SMP) Specifications (continued)
E3
Symbol
Efficiency
Description
Min
35
Typ
50
Max
–
E2
Efficiency
35
80
–
FPUMP
DCPUMP
Switching frequency
Switching duty cycle
–
–
1.3
50
–
–
Units
Notes
%
Configured as in Note 20
Load is 5 mA. SMP trip voltage is
set to 3.25 V
%
For I load = 1mA, VPUMP = 2.55 V,
VBAT = 1.3 V,
10 µH inductor, 1 µF capacitor, and
Schottky diode
MHz
%
DC Analog Mux Bus Specifications
Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 12. DC Analog Mux Bus Specifications
Min
Typ
Max
Units
RSW
Symbol
Switch resistance to common analog bus
Description
–
–
400
800
RVDD
Resistance of initialization switch to VDD
–
–
800
Notes
VDD 2.7 V
2.4 V VDD 2.7 V
DC POR and LVD Specifications
Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 13. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
–
–
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
VDD must be greater than or equal
to 2.5 V during startup, the reset
from the XRES pin, or reset from
watchdog
VPPOR0
VPPOR1
VPPOR2
VDD value for PPOR trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VDD value for LVD trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.51[21]
2.99[22]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
V
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
VDD value for pump trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.45
2.96
3.03
3.18
4.54
4.62
4.71
4.89
2.55
3.02
3.10
3.25
4.64
4.73
4.82
5.00
2.62[23]
3.09
3.16
3.32[24]
4.74
4.83
4.92
5.12
V
V
V
V
V
V
V
V
Notes
21. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.
22. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.
23. Always greater than 50 mV above VLVD0.
24. Always greater than 50 mV above VLVD3.
Document Number: 38-12025 Rev. AJ
Page 25 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
DC Programming Specifications
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 14. DC Programming Specifications
Min
Typ
Max
Units
VDDP
Symbol
VDD for programming and erase
Description
4.5
5
5.5
V
This specification applies to the
functional requirements of
external programmer tools
VDDLV
Low VDD for verify
2.4
2.5
2.6
V
This specification applies to the
functional requirements of
external programmer tools
VDDHV
High VDD for verify
5.1
5.2
5.3
V
This specification applies to the
functional requirements of
external programmer tools
5.25
V
This specification applies to this
device when it is executing
internal flash writes
VDDIWRITE Supply voltage for flash write operation
2.7
Notes
IDDP
Supply current during programming or verify
–
5
25
mA
VILP
Input low voltage during programming or
verify
–
–
0.8
V
VIHP
Input high voltage during programming or
verify
2.2
–
–
V
IILP
Input current when applying VILP to P1[0] or
P1[1] during programming or verify
–
–
0.2
mA
Driving internal pull-down resistor
IIHP
Input current when applying VIHP to P1[0] or
P1[1] during programming or verify
–
–
1.5
mA
Driving internal pull-down resistor
VOLV
Output low voltage during programming or
verify
–
–
VSS + 0.75
V
VOHV
Output high voltage during programming or
verify
VDD – 1.0
–
VDD
V
50,000[25]
–
–
–
Erase/write cycles per block
1,800,000
–
–
–
Erase/write cycles
10
–
–
Years
FlashENPB Flash endurance (per block)
(total)[26]
FlashENT
Flash endurance
FlashDR
Flash data retention
DC I2C Specifications
Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 15. DC I2C Specifications[27]
Symbol
VILI2C
VIHI2C
Description
Input low level
Input high level
Min
Typ
Max
Units
–
–
0.7 × VDD
Notes
–
0.3 × VDD
V
2.4 V VDD 3.6 V
–
0.25 × VDD
V
4.75 V VDD 5.25 V
–
–
V
2.4 V VDD 5.25 V
Notes
25. The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V,
and 4.75 V to 5.25 V.
26. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36×2
blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and ensure that no
single block ever sees more than 50,000 cycles). For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result
to the temperature argument before writing. Refer to the Flash APIs application note AN2015 (Design Aids - Reading and Writing PSoC® Flash) for more information.
27. All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs.
Document Number: 38-12025 Rev. AJ
Page 26 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
AC Electrical Characteristics
AC Chip-Level Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 16. 5-V and 3.3-V AC Chip-Level Specifications
Min
Typ
Max
Units
Notes
FIMO24 [28]
Symbol
IMO frequency for 24 MHz
Description
23.4
24
24.6[29,30]
MHz
Trimmed for 5 V or 3.3 V
operation using factory trim
values. See Figure 12 on
page 21. SLIMO mode = 0
FIMO6 [28]
IMO frequency for 6 MHz
5.52
6
6.48 [29,30]
MHz
Trimmed for 5 V or 3.3 V
operation using factory trim
values. See Figure 12 on
page 21. SLIMO mode = 1
FCPU1
CPU frequency (5 V nominal)
0.091
24
24.6[29]
MHz
24 MHz only for
SLIMO mode = 0
FCPU2
CPU frequency (3.3 V nominal)
0.091
12
12.3[30]
MHz
SLIMO mode = 0
FBLK5
Digital PSoC block
V nominal)
0
48
49.2[29,31]
MHz
Refer to AC Digital Block
Specifications on page 30
FBLK33
Digital PSoC block frequency (3.3 V nominal)
0
24
24.6[31]
MHz
F32K1
ILO frequency
15
32
64
kHz
F32K_U
ILO untrimmed frequency
5
–
100
kHz
tXRST
External reset pulse width
10
–
–
s
DC24M
24 MHz duty cycle
40
50
60
%
DCILO
ILO duty cycle
20
50
80
%
Step24M
24 MHz trim step size
–
50
–
kHz
Fout48M
48 MHz output frequency
46.8
48.0
49.2[29,30]
MHz
FMAX
Maximum frequency of signal on row input or
row output.
–
–
12.3
MHz
SRPOWER_UP Power supply slew rate
–
–
250
V/ms
tPOWERUP
Time from end of POR to CPU executing
code
–
16
100
ms
tjit_IMO
24-MHz IMO cycle-to-cycle jitter (RMS)[32]
–
200
700
ps
24-MHz IMO long term N cycle-to-cycle jitter
(RMS)[32]
–
300
900
ps
24-MHz IMO period jitter (RMS)[32]
–
100
400
ps
frequency0(5
After a reset and before the
M8C starts to run, the ILO is
not trimmed. See the system
resets section of the PSoC
Technical Reference Manual
for details on this timing
Trimmed. Using factory trim
values
VDD slew rate during
power-up
Power-up from 0 V. See the
System Resets section of the
PSoC Technical Reference
Manual
N = 32
Notes
28. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.
29. 4.75 V < VDD < 5.25 V.
30. 3.0 V < VDD < 3.6 V. See application note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3 V.
31. See the individual user module datasheets for information on maximum frequencies for user modules.
32. Refer to Cypress Jitter Specifications Application Note AN5054 “Understanding Datasheet Jitter Specifications for Cypress Timing Products” at
www.cypress.com under Application Notes for more information.
Document Number: 38-12025 Rev. AJ
Page 27 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
Table 17. 2.7-V AC Chip-Level Specifications
Min
Typ
Max
Units
Notes
FIMO12 [33]
Symbol
IMO frequency for 12 MHz
Description
11.04
120
12.96 [34, 35]
MHz
Trimmed for 2.7 V operation
using factory trim values.
See Figure 12 on page 21.
SLIMO mode = 1
FIMO6 [33]
IMO frequency for 6 MHz
5.52
6
6.48 [34, 35]
MHz
Trimmed for 2.7 V operation
using factory trim values.
See Figure 12 on page 21.
SLIMO mode = 1
FCPU1
CPU frequency (2.7 V nominal)
0.093
3
3.15[34]
MHz
12 MHz only for
SLIMO mode = 0
FBLK27
Digital PSoC block frequency (2.7 V nominal)
0
12
12.5[34,35]
MHz
Refer to AC Digital Block
Specifications on page 30
F32K1
ILO frequency
8
32
96
kHz
F32K_U
ILO untrimmed frequency
5
–
100
kHz
tXRST
External reset pulse width
10
–
–
µs
DCILO
IILO duty cycle
20
50
80
%
FMAX
Maximum frequency of signal on row input or
row output.
–
–
12.3
MHz
SRPOWER_UP Power supply slew rate
–
–
250
V/ms
tPOWERUP
Time from end of POR to CPU executing
code
–
16
100
ms
tjit_IMO
12 MHz IMO cycle-to-cycle jitter (RMS)[36]
–
400
1000
ps
12 MHz IMO long term N cycle-to-cycle jitter
(RMS)[36]
–
600
1300
ps
12 MHz IMO period jitter (RMS)[36]
–
100
500
ps
After a reset and before the
M8C starts to run, the ILO is
not trimmed. See the System
Resets section of the PSoC
Technical Reference Manual
for details on this timing
VDD slew rate during
power-up
Power-up from 0 V. See the
System Resets section of the
PSoC Technical Reference
Manual.
N = 32
Notes
33. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.
34. 2.4 V < VDD < 3.0 V.
35. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” available at http://www.cypress.com for information on
maximum frequency for user modules.
36. Refer to Cypress Jitter Specifications Application Note AN5054 “Understanding Datasheet Jitter Specifications for Cypress Timing Products” at
www.cypress.com under Application Notes for more information.
Document Number: 38-12025 Rev. AJ
Page 28 of 60
CY8C21634/CY8C21534/CY8C21434
CY8C21334/CY8C21234
AC General Purpose I/O Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 18. 5-V and 3.3-V AC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Normal strong mode
FGPIO
GPIO operating frequency
0
–
12
MHz
TRiseF
Rise time, normal strong mode, Cload = 50 pF
3
–
18
ns
VDD = 4.5 to 5.25 V, 10% to 90%
TFallF
Fall time, normal strong mode, Cload = 50 pF
2
–
18
ns
VDD = 4.5 to 5.25 V, 10% to 90%
TRiseS
Rise time, slow strong mode, Cload = 50 pF
7
27
–
ns
VDD = 3 to 5.25 V, 10% to 90%
TFallS
Fall time, slow strong mode, Cload = 50 pF
7
22
–
ns
VDD = 3 to 5.25 V, 10% to 90%
Table 19. 2.7 V AC GPIO Specifications
Min
Typ
Max
Units
Notes
FGPIO
Symbol
GPIO operating frequency
Description
0
–
3
MHz
Normal strong mode
TRiseF
Rise time, normal strong mode, Cload = 50 pF
6
–
50
ns
VDD = 2.4 to 3.0 V, 10% to 90%
TFallF
Fall time, normal strong mode, Cload = 50 pF
6
–
50
ns
VDD = 2.4 to 3.0 V, 10% to 90%
TRiseS
Rise time, slow strong mode, Cload = 50 pF
18
40
120
ns
VDD = 2.4 to 3.0 V, 10% to 90%
TFallS
Fall time, slow strong mode, Cload = 50 pF
18
40
120
ns
VDD = 2.4 to 3.0 V, 10% to 90%
Figure 14. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 20. AC Operational Amplifier Specifications
Symbol
TCOMP
Description
Comparator mode response time, 50 mV
overdrive
Document Number: 38-12025 Rev. AJ
Min
Typ
Max
Units
–
–
100
200
ns
ns
Notes
VDD 3.0 V
2.4 V < VDD
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