Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY8C29466/CY8C29566
CY8C29666/CY8C29866
PSoC® Programmable System-on-Chip™
PSoC® Programmable System-on-Chip™
Features
■
■
■
■
■
❐
Powerful Harvard-architecture processor
❐ M8C processor speeds to 24 MHz
❐ Two 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Operating voltage: 3.0 V to 5.25 V
❐ Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐ Industrial temperature range: –40 °C to +85 °C
❐
Four 40 mA analog outputs on GPIOs
Configurable interrupt on all GPIOs
■
Additional system resources
2
❐ I C slave, master, and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection (LVD)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
■
Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured in-circuit emulator (ICE) and
programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
❐ Complex events
❐ C compilers, assembler, and linker
(PSoC®
Advanced peripherals
blocks)
❐ 12 rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
❐ 16 digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Up to four full-duplex universal asynchronous receiver
transmitters (UARTs)
• Multiple serial peripheral interface (SPI) masters or slaves
• Can connect to all general-purpose I/O (GPIO) pins
❐ Create complex peripherals by combining blocks
Logic Block Diagram
Port
7
Port
6
Port
5
Port
4
Port
3
Port
2
Port
1
Port 0 with
Analog Drivers
PSoC
CORE
System Bus
Global Digital Interconnect
SRAM
2 KB
Precision, programmable clocking
[1] 24- / 48-MHz main oscillator
❐ Internal ±5%
❐ 24- / 48-MHz with optional 32.768 kHz crystal
❐ Optional external oscillator, up to 24 MHz
❐ Internal oscillator for watchdog and sleep
Global Analog Interconnect
SROM
Flash 32KB
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Flexible on-chip memory
❐ 32 KB flash program storage 50,000 erase/write cycles
❐ 2 KB static random access memory (SRAM) data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ Electrically erasable programmable read-only memory
(EEPROM) emulation in flash
DIGITAL SYSTEM
ANALOG SYSTEM
Digital
Block
Array
Programmable pin configurations
❐ 25-mA sink, 10-mA source on all GPIOs
❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐ Eight standard analog inputs on GPIOs, plus four additional
analog inputs with restricted routing
Digital
Clocks
Multiply
Accum.
Analog
Ref.
Analog
Block
Array
Analog
Input
Muxing
POR and LVD
Decimator
I2 C
System Resets
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Errata: For information on silicon errata, see “Errata” on page 63. Details include trigger conditions, devices affected, and proposed workaround.
Note
1. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see Errata on page 63.
Cypress Semiconductor Corporation
Document Number: 38-12013 Rev. AD
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 29, 2020
CY8C29466/CY8C29566
CY8C29666/CY8C29866
More Information
Note: For CY8C29X66 devices related Development Kits please
click here.
Cypress provides a wealth of data at www.cypress.com to help
you to select the right PSoC device for your design, and to help
you to quickly and effectively integrate the device into your
design. For a comprehensive list of resources, see the
knowledge base article “How to Design with PSoC® 1,
PowerPSoC®, and PLC – KBA88292”. Following is an
abbreviated list for PSoC 1:
The MiniProg1 and MiniProg3 devices provide interfaces for
flash programming and debug.
■
Overview: PSoC Portfolio, PSoC Roadmap
■
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
■
In addition, PSoC Designer includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 1 are:
®
❐ Getting Started with PSoC 1 – AN75320.
®
❐ PSoC 1 - Getting Started with GPIO – AN2094.
®
❐ PSoC 1 Analog Structure and Configuration – AN74170.
®
❐ PSoC 1 Switched Capacitor Analog Blocks – AN2041.
❐ Selecting Analog Ground and Reference – AN2219.
Note: For CY8C29X66 devices related Application note please
click here.
■
■
Development Kits:
❐ CY3210-PSoCEval1 supports all PSoC 1 Mixed-Signal Array
families, including automotive, except CY8C25/26xxx
devices. The kit includes an LCD module, potentiometer,
LEDs, and breadboarding space.
❐ CY3214-PSoCEvalUSB features a development board for
the CY8C24x94 PSoC device. Special features of the board
include USB and CapSense development and debugging
support.
PSoC Designer
PSoC Designer is a free Windows-based Integrated Design
Environment (IDE). Develop your applications using a library of
pre-characterized analog and digital peripherals in a
drag-and-drop design environment. Then, customize your
design leveraging the dynamically generated API libraries of
code. Figure 1 shows PSoC Designer windows. Note: This is not
the default view.
1. Global Resources – all device hardware settings.
2. Parameters – the parameters of the currently selected User
Modules.
3. Pinout – information related to device pins.
4. Chip-Level Editor – a diagram of the resources available on
the selected chip.
5. Datasheet – the datasheet for the currently selected UM
6. User Modules – all available User Modules for the selected
device.
7. Device Resource Meter – device resource usage for the
current project configuration.
8. Workspace – a tree level diagram of files associated with the
project.
9. Output – output from project build and debug operations.
Note: For detailed information on PSoC Designer, go to
PSoC® Designer > Help > Documentation >
Designer Specific Documents > IDE User Guide.
Figure 1. PSoC Designer Layout
Document Number: 38-12013 Rev. AD
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Contents
PSoC Functional Overview .............................................. 4
PSoC Core .................................................................. 4
Digital System ............................................................. 4
Analog System ............................................................ 5
Additional System Resources ..................................... 6
PSoC Device Characteristics ...................................... 6
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 8
Select User Modules ................................................... 8
Configure User Modules .............................................. 8
Organize and Connect ................................................ 9
Generate, Verify, and Debug ....................................... 9
Pinouts ............................................................................ 10
28-Pin Part Pinout ..................................................... 10
44-Pin Part Pinout ..................................................... 11
48-Pin Part Pinout ..................................................... 12
100-Pin Part Pinout ................................................... 14
100-Pin Part Pinout (On-Chip Debug) ....................... 16
Register Reference ......................................................... 18
Register Conventions ................................................ 18
Register Mapping Tables .......................................... 18
Electrical Specifications ................................................ 21
Absolute Maximum Ratings ....................................... 21
Operating Temperature ............................................. 22
DC Electrical Characteristics ..................................... 22
AC Electrical Characteristics ..................................... 38
Packaging Information ................................................... 47
Packaging Dimensions .............................................. 47
Document Number: 38-12013 Rev. AD
Thermal Impedances ................................................. 51
Capacitance on Crystal Pins ..................................... 51
Solder Reflow Specifications ..................................... 51
Development Tool Selection ......................................... 52
Software .................................................................... 52
Development Kits ...................................................... 52
Evaluation Tools ........................................................ 52
Device Programmers ................................................. 53
Accessories (Emulation and Programming) ................ 53
Ordering Information ...................................................... 54
Ordering Code Definitions ......................................... 54
Acronyms ........................................................................ 55
Reference Documents .................................................... 55
Document Conventions ............................................. 56
Units of Measure ....................................................... 56
Numeric Conventions ................................................ 56
Glossary .......................................................................... 56
Errata ............................................................................... 61
Part Numbers Affected .............................................. 61
Qualification Status ................................................... 61
Errata Summary ........................................................ 61
Document History Page ................................................. 63
Sales, Solutions, and Legal Information ...................... 67
Worldwide Sales and Design Support ....................... 67
Products .................................................................... 67
PSoC® Solutions ...................................................... 67
Cypress Developer Community ................................. 67
Technical Support ..................................................... 67
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The digital system is composed of 16 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8-, 16-, 24-, and 32-bit peripherals,
which are called user modules.
Figure 2. Digital System Block Diagram
Port7
DIGITAL SYSTEM
Row Input
Configuration
Digital PSoC Block Array
Row0
DBB00
DBB01
DCB02
4
DCB03
4
8
8
Row Input
Configuration
8
Row1
DBB10
DBB11
DCB12
4
DCB13
4
Row2
DBB20
DBB21
DCB22
4
DCB23
4
Row3
DBB30
DBB31
DCB32
4
DCB33
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
8
Row Output
Configuration
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz internal main oscillator (IMO) accurate to
5% [2] over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low-power
32 kHz internal low speed oscillator (ILO) is provided for the
sleep timer and WDT. If crystal accuracy is desired, the
32.768 kHz external crystal oscillator (ECO) is available for use
as a real-time clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a system
resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
To Analog
System
Row Output
Configuration
Memory uses 32 KB of flash for program storage, 2 KB of SRAM
for data storage, and up to 2 KB of EEPROM emulated using the
flash. Program flash uses four protection levels on blocks of 64
bytes, allowing customized software information protection (IP).
To System Bus
Port0
Row Output
Configuration
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a 4 million instructions per second (MIPS)
8-bit Harvard-architecture microprocessor. The CPU uses an
interrupt controller with 17 vectors, to simplify programming of
real-time embedded events. Program execution is timed and
protected using the included sleep and watchdog timers (WDT).
Port1
Port2
Row Output
Configuration
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIOs.
Port3
Port4
Digital Clocks
From Core
The PSoC architecture, as illustrated in the Logic Block Diagram
on page 1, consists of four main areas: PSoC core, digital
system, analog system, and system resources. Configurable
global busing allows all of the device resources to be combined
into a complete custom system. The PSoC CY8C29x66 family
can have up to five I/O ports that connect to the global digital and
analog interconnects, providing access to 8 digital blocks and
12 analog blocks.
PSoC Core
Port5
Port6
Row Input
Configuration
The PSoC family consists of many Programmable
System-on-Chip controller devices. These devices are designed
to replace multiple traditional microcontroller unit (MCU)-based
system components with one, low-cost single-chip programmable device. PSoC devices include configurable blocks of
analog and digital logic, as well as programmable interconnects.
This architecture allows you to create customized peripheral
configurations that match the requirements of each individual
application. Additionally, a fast central processing unit (CPU),
flash program memory, SRAM data memory, and configurable
I/O are included in a range of convenient pinouts and packages.
Digital System
Row Input
Configuration
PSoC Functional Overview
GOE[7:0]
GOO[7:0]
PSoC GPIOs provide connection to the CPU, and digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
Note
2. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see Errata on page 63.
Document Number: 38-12013 Rev. AD
Page 4 of 69
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Digital peripheral configurations include:
■
DTMF Dialer
■
PWMs (8- and 16-bit)
■
Modulators
■
PWMs with dead band (8- and 16-bit)
■
Correlators
■
Counters (8- to 32-bit)
■
Peak detectors
■
Timers (8- to 32-bit)
■
Many other topologies possible
■
UART 8-bit with selectable parity (up to 2)
■
SPI slave and master (up to 2)
Analog blocks are provided in columns of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks, as shown in Figure 3.
■
I2C slave and multi-master (one available as a system
resource)
■
CRC generator (8- to 32-bit)
■
IrDA (up to 2)
■
PRS generators (8- to 32-bit)
Figure 3. Analog System Block Diagram
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
P0[1]
P0[0]
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device
Characteristics” on page 6.
P2[1]
AGNDIn RefIn
P0[7]
P2[3]
■
ADCs (up to 4, with 6- to 14-bit resolution; selectable as
incremental, delta sigma, and SAR)
■
Filters (2-, 4-, 6-, and 8-pole band pass, low pass, and notch)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
■
Comparators (up to 4, with 16 selectable thresholds)
■
DACs (up to 4, with 6-bit to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6-bit to 9-bit resolution)
■
High current output drivers (four with 30-mA drive as a core
resource)
■
P2[4]
P2[2]
P2[0]
Analog System
The analog system is composed of 12 configurable blocks, each
containing an opamp circuit that allows the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are:
P2[6]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
ACB00
ACB01
ACB02
ACB03
ASC10
ASD11
ASC12
ASD13
ASD20
ASC21
ASD22
ASC23
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
1.3-V reference (as a system resource)
Document Number: 38-12013 Rev. AD
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Additional System Resources
System resources, some of which were previously listed, provide
additional capability useful to complete systems. Additional
resources include a multiplier, decimator, switch mode pump,
low-voltage detection, and power-on-reset (POR).
■
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of delta
sigma ADCs.
2
■ The I C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■ LVD interrupts can signal the application of falling voltage
levels, while the advanced POR circuit eliminates the need for
a system supervisor.
■ An internal 1.3 V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■ An integrated switch-mode pump (SMP) generates normal
operating voltages from a single 1.2 V battery cell, providing a
low cost boost converter.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
Multiply accumulate (MAC) provides a fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific PSoC device groups.The PSoC device covered by this
datasheet is highlighted.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
CY8C29x66
up to 64
4
16
up to 12
4
4
12
2K
32 K
CY8C28xxx
up to 44
up to 3
up to 12
up to 44
up to 4
up to 6
up to
12 + 4[3]
1K
16 K
CY8C27x43
up to 44
2
8
up to 12
4
4
12
256
16 K
CY8C24x94
up to 56
1
4
up to 48
2
2
6
1K
16 K
CY8C24x23A
up to 24
1
4
up to 12
2
2
6
256
4K
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
CY8C22x45
up to 38
2
8
up to 38
0
4
6[3]
1K
16 K
CY8C21x45
up to 24
1
4
up to 24
0
4
6[3]
512
8K
CY8C21x34
up to 28
1
4
up to 28
0
2
4[3]
512
8K
[3]
256
4K
CY8C21x23
up to 16
1
4
up to 8
0
2
CY8C20x34
up to 28
0
0
up to 28
0
0
3[3,4]
4
512
8K
CY8C20xx6
up to 36
0
0
up to 36
0
0
3[3,4]
up to 2 K
up to 32 K
Notes
3. Limited analog functionality.
4. Two analog blocks and one CapSense®.
Document Number: 38-12013 Rev. AD
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Development Tools
PSoC Designer™ is the revolutionary Integrated Design
Environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
■
Integrated source-code editor (C and assembly)
Debugger
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also allows you to create a trace buffer of registers and memory
locations of interest.
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up
to
four
full-duplex
universal
asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
■
PSoC Designer Software Subsystems
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this allows you to use more than 100 percent
of PSoC's resources for an application.
Document Number: 38-12013 Rev. AD
In-Circuit Emulator
A low-cost, high-functionality In-Circuit Emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
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Designing with PSoC Designer
The development process for the PSoC® device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process is summarized in four steps:
1. Select User Modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
Document Number: 38-12013 Rev. AD
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a pulse
width modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the user module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
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Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
Document Number: 38-12013 Rev. AD
A complete code development environment allows you to
develop and customize your applications in either C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging
capabilities rival those of systems costing many times more. In
addition to traditional single-step, run-to-breakpoint and
watch-variable features, the debug interface provides a large
trace buffer and allows you to define complex breakpoint events
that include monitoring address and data bus values, memory
locations and external signals.
Page 9 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Pinouts
The CY8C29x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital I/O. However, VSS, VDD, SMP, and XRES are not capable of Digital I/O.
28-Pin Part Pinout
Table 2. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No.
Type
Digital
Analog
Pin
Name
Description
1
I/O
I
P0[7]
Analog column mux input
2
I/O
I/O
P0[5]
Analog column mux input and column output
3
I/O
I/O
P0[3]
Analog column mux input and column output
4
I/O
I
P0[1]
Analog column mux input
5
I/O
6
I/O
7
I/O
8
I/O
9
P2[7]
P2[5]
I
P2[3]
Direct switched capacitor block input
I
P2[1]
Direct switched capacitor block input
SMP
Switch mode pump (SMP) connection to
external components required
Power
10
I/O
P1[7]
I2C serial clock (SCL)
11
I/O
P1[5]
I2C serial data (SDA)
12
I/O
P1[3]
13
I/O
P1[1]
14
Power
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK[5]
VSS
Ground connection
15
I/O
P1[0]
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA[5]
16
I/O
P1[2]
17
I/O
P1[4]
18
I/O
P1[6]
19
Input
XRES
Active high external reset with internal
pull-down
Direct switched capacitor block input
I/O
I
P2[0]
21
I/O
I
P2[2]
Direct switched capacitor block input
22
I/O
P2[4]
External analog ground (AGND)
23
I/O
P2[6]
External voltage reference (VREF)
24
I/O
I
P0[0]
Analog column mux input
25
I/O
I/O
P0[2]
Analog column mux input and column output
26
I/O
I/O
P0[4]
Analog column mux input and column output
27
I/O
I
P0[6]
Analog column mux input
VDD
Supply voltage
Power
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PDIP
SSOP
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VREF
P2[4], External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2CSDA
Optional external clock input (EXTCLK)
20
28
Figure 4. CY8C29466 28-Pin PSoC Device
LEGEND: A = Analog, I = Input, and O = Output.
Note
5. These are the ISSP pins, which are not High Z at Power On Reset (POR). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12013 Rev. AD
Page 10 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
44-Pin Part Pinout
Table 3. 44-Pin Part Pinout (TQFP)
Analog
Pin
Name
Description
I/O
2
I/O
I
P2[3]
Direct switched capacitor block input
3
I/O
I
P2[1]
Direct switched capacitor block input
4
I/O
P4[7]
5
I/O
P4[5]
6
I/O
P4[3]
7
I/O
SMP
Switch mode pump (SMP) connection to
external components required
9
I/O
P3[7]
10
I/O
P3[5]
11
I/O
P3[3]
12
I/O
P3[1]
13
I/O
P1[7]
I2C SCL
14
I/O
P1[5]
I2C SDA
15
I/O
P1[3]
16
I/O
P1[1]
17
Power
Crystal (XTALin), I2C SCL, ISSP-SCLK[6]
VSS
Ground connection
18
I/O
P1[0]
Crystal (XTALout), I2C SDA, ISSP-SDATA[6]
19
I/O
P1[2]
20
I/O
P1[4]
21
I/O
P1[6]
22
I/O
P3[0]
23
I/O
P3[2]
24
I/O
P3[4]
25
I/O
26
Optional EXTCLK
P3[6]
Input
XRES
Active high external reset with internal
pull-down
27
I/O
P4[0]
28
I/O
P4[2]
29
I/O
P4[4]
30
I/O
31
I/O
I
P2[0]
Direct switched capacitor block input
32
I/O
I
P2[2]
Direct switched capacitor block input
33
I/O
P2[4]
External analog ground (AGND)
34
I/O
P2[6]
External voltage reference (VREF)
35
I/O
I
P0[0]
Analog column mux input
36
I/O
I/O
P0[2]
Analog column mux input and column output
37
I/O
I/O
P0[4]
Analog column mux input and column output
38
I/O
I
P0[6]
Analog column mux input
39
44
43
42
41
40
39
38
37
36
35
34
P4[1]
Power
P2[5]
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
1
2
3
4
5
6
7
8
9
10
11
TQFP
12
13
14
15
16
17
18
19
20
21
22
8
P2[5]
P2[7]
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
VDD
1
Figure 5. CY8C29566 44-Pin PSoC Device
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VREF
Type
Digital
33 P2[4], External AGND
32 P2[2], A, I
31 P2[0], A, I
30 P4[6]
29 P4[4]
28 P4[2]
27 P4[0]
26 XRES
25 P3[6]
24 P3[4]
23 P3[2]
P3[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
VSS
I2CSDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
P3[0]
Pin
No.
P4[6]
Power
VDD
Supply voltage
40
I/O
I
P0[7]
Analog column mux input
41
I/O
I/O
P0[5]
Analog column mux input and column output
42
I/O
I/O
P0[3]
Analog column mux input and column output
43
I/O
I
P0[1]
Analog column mux input
44
I/O
P2[7]
LEGEND: A = Analog, I = Input, and O = Output.
Note
6. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12013 Rev. AD
Page 11 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
48-Pin Part Pinout
Table 4. 48-Pin Part Pinout (SSOP)
Pin
No.
Type
Digital
Analog
Pin
Name
Description
1
I/O
I
P0[7]
Analog column mux input
2
I/O
I/O
P0[5]
Analog column mux input and column output
3
I/O
I/O
P0[3]
Analog column mux input and column output
4
I/O
I
P0[1]
Analog column mux input
5
I/O
6
I/O
7
I/O
I
P2[3]
Direct switched capacitor block input
8
I/O
I
P2[1]
Direct switched capacitor block input
9
I/O
P4[7]
10
I/O
P4[5]
11
I/O
P4[3]
12
I/O
13
P2[7]
P2[5]
P4[1]
Power
SMP
Switch mode pump (SMP) connection to
external components required
14
I/O
P3[7]
15
I/O
P3[5]
16
I/O
P3[3]
17
I/O
P3[1]
18
I/O
P5[3]
19
I/O
P5[1]
20
I/O
P1[7]
I2C SCL
21
I/O
P1[5]
I2C SDA
22
I/O
P1[3]
23
I/O
24
P1[1]
Power
VSS
25
I/O
P1[0]
26
I/O
P1[2]
27
I/O
P1[4]
28
I/O
P1[6]
29
I/O
P5[0]
30
I/O
P5[2]
31
I/O
P3[0]
32
I/O
P3[2]
33
I/O
P3[4]
34
I/O
35
Crystal (XTALin), I2C SCL, ISSP-SCLK[7]
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VREF
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[2]
P5[0]
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Ground connection
Crystal (XTALout), I2C SDA, ISSP-SDATA[7]
Optional EXTCLK
P3[6]
Input
XRES
Active high external reset with internal
pull-down
36
I/O
P4[0]
37
I/O
P4[2]
38
I/O
P4[4]
39
I/O
40
I/O
I
P2[0]
Direct switched capacitor block input
41
I/O
I
P2[2]
Direct switched capacitor block input
42
I/O
P2[4]
External Analog Ground (AGND)
43
I/O
P2[6]
External Voltage Reference (VREF)
44
I/O
I
P0[0]
Analog column mux input
45
I/O
I/O
P0[2]
Analog column mux input and column output
46
I/O
I/O
P0[4]
Analog column mux input and column output
47
I/O
I
P0[6]
Analog column mux input
VDD
Supply voltage
48
Figure 6. CY8C29666 48-Pin PSoC Device
P4[6]
Power
LEGEND: A = Analog, I = Input, and O = Output.
Note
7. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12013 Rev. AD
Page 12 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Table 5. 48-Pin Part Pinout (QFN) [9]
I
P2[3]
Direct switched capacitor block input
I/O
I
P2[1]
Direct switched capacitor block input
3
I/O
P4[7]
4
I/O
P4[5]
5
I/O
P4[3]
6
I/O
7
P4[1]
Power
SMP
Switch mode pump (SMP) connection to
external components required
8
I/O
P3[7]
9
I/O
P3[5]
10
I/O
P3[3]
11
I/O
P3[1]
12
I/O
P5[3]
13
I/O
P5[1]
14
I/O
P1[7]
I2C SCL
15
I/O
P1[5]
I2C SDA
16
I/O
P1[3]
17
I/O
P1[1]
18
Power
VSS
19
I/O
P1[0]
20
I/O
P1[2]
21
I/O
P1[4]
22
I/O
P1[6]
23
I/O
P5[0]
24
I/O
P5[2]
25
I/O
P3[0]
26
I/O
P3[2]
27
I/O
P3[4]
28
I/O
29
Crystal (XTALin), I2C SCL, ISSP-SCLK[8]
Ground connection
Crystal (XTALout), I2C SDA, ISSP-SDATA[8]
Optional EXTCLK
1
2
3
4
5
6
7
8
9
10
11
12
QFN
(Top View)
36
35
34
33
32
31
30
29
28
27
26
25
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P3[6]
Input
XRES
Active high external reset with internal
pull-down
30
I/O
P4[0]
31
I/O
P4[2]
32
I/O
P4[4]
33
I/O
34
I/O
I
P2[0]
Direct switched capacitor block input
35
I/O
I
P2[2]
Direct switched capacitor block input
36
I/O
P2[4]
External analog ground (AGND)
37
I/O
P2[6]
External voltage reference (VREF)
38
I/O
I
P0[0]
Analog column mux input
39
I/O
I/O
P0[2]
Analog column mux input and column output
40
I/O
I/O
P0[4]
Analog column mux input and column output
41
I/O
I
P0[6]
Analog column mux input
42
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
38
37
I/O
2
42
41
40
39
1
Figure 7. CY8C29666 48-Pin PSoC Device
P2[5]
P2[7]
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
VDD
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VREF
Description
48
47
46
45
44
43
Pin
Name
Analog
13
14
I2C SDA, P1[5] 15
P1[3] 16
I2C SCL, XTALin, P1[1] 17
VSS
18
I2C SDA, XTALout, P1[0] 19
P1[2] 20
EXTCLK, P1[4] 21
P1[6] 22
P5[0] 23
P5[2] 24
Type
Digital
P5[1]
I2C SCL, P1[7]
Pin
No.
P4[6]
Power
VDD
Supply voltage
43
I/O
I
P0[7]
Analog column mux input
44
I/O
I/O
P0[5]
Analog column mux input and column output
45
I/O
I/O
P0[3]
Analog column mux input and column output
46
I/O
I
P0[1]
Analog column mux input
47
I/O
P2[7]
48
I/O
P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
Notes
8. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
9. The QFN package has a center pad that must be connected to ground (VSS).
Document Number: 38-12013 Rev. AD
Page 13 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
100-Pin Part Pinout
Table 6. 100-Pin Part Pinout (TQFP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
Type
Digital Analog
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I
I
I
Power
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Name
NC
NC
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
NC
NC
SMP
VSS
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
NC
NC
NC
P1[5]
P1[3]
P1[1]
NC
VDD
NC
VSS
NC
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
NC
NC
NC
Description
No connection. Pin must be left floating
No connection. Pin must be left floating
Analog column mux input
Direct switched capacitor block input
Direct switched capacitor block input
No connection. Pin must be left floating
No connection. Pin must be left floating
Switch mode pump (SMP) connection to
external components required
Ground connection [10]
I2C SCL
No connection. Pin must be left floating
No connection. Pin must be left floating
No connection. Pin must be left floating
I2C SDA
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK[11]
No connection. Pin must be left floating
Supply voltage
No connection. Pin must be left floating
Ground connection [10]
No connection. Pin must be left floating
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA[11]
Optional EXTCLK
No connection. Pin must be left floating
No connection. Pin must be left floating
No connection. Pin must be left floating
Pin
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Type
Digital Analog
Name
NC
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
NC
NC
XRES
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
I/O
I/O
Description
No connection. Pin must be left floating
No connection. Pin must be left floating
No connection. Pin must be left floating
Active high external reset with internal
pull-down
P4[0]
P4[2]
Power
I/O
I/O
I/O
I/O
I/O
I
I
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
Power
Power
Power
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
VSS
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
NC
P2[6]
NC
P0[0]
NC
NC
P0[2]
NC
P0[4]
NC
Ground connection [10]
Direct switched capacitor block input
Direct switched capacitor block input
External Analog Ground (AGND)
No connection. Pin must be left floating
External Voltage Reference (VREF)
No connection. Pin must be left floating
Analog column mux input
No connection. Pin must be left floating
No connection. Pin must be left floating
Analog column mux input and column output
No connection. Pin must be left floating
Analog column mux input and column output
No connection. Pin must be left floating
P0[6]
VDD
VDD
VSS
VSS
P6[0]
P6[1]
P6[2]
P6[3]
P6[4]
P6[5]
P6[6]
P6[7]
NC
Analog column mux input
Supply voltage
Supply voltage
Ground connection [10]
Ground connection [10]
P0[7]
NC
P0[5]
NC
P0[3]
NC
Analog column mux input
No connection. Pin must be left floating
Analog column mux input and column output
No connection. Pin must be left floating
Analog column mux input and column output
No connection. Pin must be left floating
No connection. Pin must be left floating
LEGEND: A = Analog, I = Input, and O = Output.
Notes
10. All VSS pins should be brought out to one common GND plane.
11. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12013 Rev. AD
Page 14 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
VDD
VDD
P0[6], A, I
NC
P0[4], A, IO
NC
P0[2], A, IO
NC
87
86
85
84
83
82
81
80
79
78
77
76
P6[7]
P6[6]
P6[5]
P6[4]
P6[3]
P6[2]
P6[1]
P6[0]
VSS
VSS
TQFP
Document Number: 38-12013 Rev. AD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
P0[0], A, I
NC
P2[6], External VREF
NC
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
VSS
P4[2]
P4[0]
XRES
NC
NC
P3[6]
P3[4]
P3[2]
P3[0]
P5[6]
P5[4]
P5[2]
P5[0]
NC
NC
NC
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
XTALout, I2C SDA, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
NC
NC
NC
I2C SDA, P1[5]
P1[3]
XTALin, I2C SCL, P1[1]
NC
VDD
NC
VSS
NC
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
NC
NC
SMP
VSS
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
I2C SCL, P1[7]
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
100
99
98
97
96
95
94
93
92
91
90
89
88
NC
P0[3], A, IO
NC
P0[5], A, IO
NC
P0[7], A, I
NC
Figure 8. CY8C29866 100-Pin PSoC Device
Page 15 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is for the CY8C29000 On-Chip Debug (OCD) PSoC device.
Note OCD parts are only used for in-circuit debugging. OCD parts are NOT available for production.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
Power
NC
NC
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
OCDE
OCDO
SMP
Description
No internal connection
No internal connection
Analog column mux input
Direct switched capacitor block input
Direct switched capacitor block input
OCD even data I/O
OCD odd data output
Switch Mode Pump (SMP) connection to required
external components
Ground connection [12]
Pin
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
I/O
I/O
Analog
Name
Digital
Analog
Pin
No.
Digital
Table 7. 100-Pin OCD Part Pinout (TQFP)
Name
NC
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
HCLK
CCLK
XRES
P4[0]
P4[2]
15
Power
VSS
65
Power
VSS
16
I/O
P3[7]
66
I/O
P4[4]
17
I/O
P3[5]
67
I/O
P4[6]
18
I/O
P3[3]
68
I/O I
P2[0]
19
I/O
P3[1]
69
I/O I
P2[2]
20
I/O
P5[7]
70
I/O
P2[4]
21
I/O
P5[5]
71
NC
22
I/O
P5[3]
72
I/O
P2[6]
23
I/O
P5[1]
73
NC
24
I/O
P1[7]
I2C SCL
74
I/O I
P0[0]
25
NC
No internal connection
75
NC
26
NC
No internal connection
76
NC
27
NC
No internal connection
77
I/O I/O
P0[2]
28
I/O
P1[5]
I2C SDA
78
NC
29
I/O
P1[3]
IFMTEST
79
I/O I/O
P0[4]
30
I/O
P1[1][13] Crystal (XTALin), I2C SCL, TC SCLK.
80
NC
31
NC
No internal connection
81
I/O I
P0[6]
32
Power
VDD
Supply voltage
82
Power
VDD
33
NC
No internal connection
83
Power
VDD
34
Power
VSS
Ground connection [12]
84
Power
VSS
35
NC
No internal connection
85
Power
VSS
36
I/O
P7[7]
86
I/O
P6[0]
37
I/O
P7[6]
87
I/O
P6[1]
38
I/O
P7[5]
88
I/O
P6[2]
39
I/O
P7[4]
89
I/O
P6[3]
40
I/O
P7[3]
90
I/O
P6[4]
41
I/O
P7[2]
91
I/O
P6[5]
42
I/O
P7[1]
92
I/O
P6[6]
43
I/O
P7[0]
93
I/O
P6[7]
44
I/O
P1[0]*
Crystal (XTALout), I2C SDA, TC SDATA
94
NC
45
I/O
P1[2]
VFMTEST
95
I/O
I
P0[7]
46
I/O
P1[4]
Optional External Clock Input (EXTCLK)
96
NC
47
I/O
P1[6]
97
I/O
I/O P0[5]
48
NC
No internal connection
98
NC
49
NC
No internal connection
99
I/O
I/O P0[3]
50
NC
No internal connection
100
NC
LEGEND A = Analog, I = Input, O = Output, NC = No connection. Pin must be left floating, TC/TM: Test.
Description
No internal connection
OCD high speed clock output
OCD CPU clock output
Active high pin reset with internal pull-down
Ground connection [12]
Direct switched capacitor block input
Direct switched capacitor block input
External Analog Ground (AGND) input
No internal connection
External Voltage Reference (VREF) input
No internal connection
Analog column mux input
No internal connection
No internal connection
Analog column mux input and column output
No internal connection
Analog column mux input and column output, VREF
No internal connection
Analog column mux input
Supply voltage
Supply voltage
Ground connection [12]
Ground connection [12]
No internal connection
Analog column mux input
No internal connection
Analog column mux input and column output
No internal connection
Analog column mux input and column output
No internal connection
Notes
12. All VSS pins should be brought out to one common GND plane.
13. ISSP pin which is not High-Z at POR.
Document Number: 38-12013 Rev. AD
Page 16 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
77
76
P6[0]
VSS
VSS
VDD
VDD
P0[6], AI
NC
P0[4], AIO
NC
P0[2], AIO
NC
87
86
85
84
83
82
81
80
79
78
90
89
88
P6[7]
P6[6]
P6[5]
P6[4]
P6[3]
P6[2]
P6[1]
98
97
96
95
94
93
92
91
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
OCD TQFP
NC
P0[0] , AI
NC
P2[6] , External VREF
NC
P2[4] , External AGND
P2[2] , AI
P2[0] , AI
P4[6]
P4[4]
VSS
P4[2]
P4[0]
XRES
CCLK
HCLK
P3[6]
P3[4]
P3[2]
P3[0]
P5[6]
P5[4]
P5[2]
P5[0]
NC
NC
NC
XTALout, I2C SDA, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
NC
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Document Number: 38-12013 Rev. AD
NC
VSS
NC
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
54
53
52
51
26
27
28
29
30
31
32
33
34
35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
I2C SDA, P1[5]
P1[3]
XTALin, I2C SCL, P1[1]
NC
VDD
NC
NC
AI , P0[1]
P2[7]
P2[5]
AI , P2[3]
AI , P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
OCDE
OCDO
SMP
Vss
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
I2 C SCL, P1[7]
NC
100
99
NC
P0[3], AIO
NC
P0[5], AIO
NC
P0[7], AI
NC
Figure 9. CY8C29000 OCD (Not for Production)
Page 17 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Register Reference
This section lists the registers of the CY8C29x66 PSoC device. For detailed register information, refer to the
PSoC Programmable System-on-Chip Technical Reference Manual.
Register Conventions
The register conventions specific to this section are listed in Table 8.
Table 8. Register Conventions
Convention
R
W
L
C
#
Description
Read register or bit(s)
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
Register Mapping Tables
The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into
two banks. The XOI bit in the flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user
is in Bank 1.
Note In the register mapping tables, blank fields are reserved and should not be accessed.
Document Number: 38-12013 Rev. AD
Page 18 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Table 9. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2
PRT6DR
PRT6IE
PRT6GS
PRT6DM2
PRT7DR
PRT7IE
PRT7GS
PRT7DM2
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
DBB10DR0
DBB10DR1
DBB10DR2
DBB10CR0
DBB11DR0
DBB11DR1
DBB11DR2
DBB11CR0
DCB12DR0
DCB12DR1
DCB12DR2
DCB12CR0
DCB13DR0
DCB13DR1
DCB13DR2
DCB13CR0
Addr (0,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
Name
DBB20DR0
DBB20DR1
DBB20DR2
DBB20CR0
DBB21DR0
DBB21DR1
DBB21DR2
DBB21CR0
DCB22DR0
DCB22DR1
DCB22DR2
DCB22CR0
DCB23DR0
DCB23DR1
DCB23DR2
DCB23CR0
DBB30DR0
DBB30DR1
DBB30DR2
DBB30CR0
DBB31DR0
DBB31DR1
DBB31DR2
DBB31CR0
DCB32DR0
DCB32DR1
DCB32DR2
DCB32CR0
DCB33DR0
DCB33DR1
DCB33DR2
DCB33CR0
AMX_IN
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
ACB02CR3
ACB02CR0
ACB02CR1
ACB02CR2
ACB03CR3
ACB03CR0
ACB03CR1
ACB03CR2
Blank fields are Reserved and should not be accessed.
Document Number: 38-12013 Rev. AD
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
MUL1_X
MUL1_Y
MUL1_DH
MUL1_DL
ACC1_DR1
ACC1_DR0
ACC1_DR3
ACC1_DR2
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RDI1RI
RDI1SYN
RDI1IS
RDI1LT0
RDI1LT1
RDI1RO0
RDI1RO1
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RDI2RI
RDI2SYN
RDI2IS
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
RDI3RI
RDI3SYN
RDI3IS
RDI3LT0
RDI3LT1
RDI3RO0
RDI3RO1
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
CPU_F
RW
RW
RW
RW
RW
RW
RW
CPU_SCR1
CPU_SCR0
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
# Access is bit specific.
Page 19 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Table 10. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
PRT6DM0
PRT6DM1
PRT6IC0
PRT6IC1
PRT7DM0
PRT7DM1
PRT7IC0
PRT7IC1
DBB00FN
DBB00IN
DBB00OU
Addr (1,Hex) Access
Name
00
RW
DBB20FN
01
RW
DBB20IN
02
RW
DBB20OU
03
RW
04
RW
DBB21FN
05
RW
DBB21IN
06
RW
DBB21OU
07
RW
08
RW
DCB22FN
09
RW
DCB22IN
0A
RW
DCB22OU
0B
RW
0C
RW
DCB23FN
0D
RW
DCB23IN
0E
RW
DCB23OU
0F
RW
10
RW
DBB30FN
11
RW
DBB30IN
12
RW
DBB30OU
13
RW
14
RW
DBB31FN
15
RW
DBB31IN
16
RW
DBB31OU
17
RW
18
RW
DCB32FN
19
RW
DCB32IN
1A
RW
DCB32OU
1B
RW
1C
RW
DCB33FN
1D
RW
DCB33IN
1E
RW
DCB33OU
1F
RW
20
RW
CLK_CR0
21
RW
CLK_CR1
22
RW
ABF_CR0
23
AMD_CR0
DBB01FN
24
RW
DBB01IN
25
RW
DBB01OU
26
RW
AMD_CR1
27
ALT_CR0
DCB02FN
28
RW
ALT_CR1
DCB02IN
29
RW
CLK_CR2
DCB02OU
2A
RW
2B
DCB03FN
2C
RW
TMP_DR0
DCB03IN
2D
RW
TMP_DR1
DCB03OU
2E
RW
TMP_DR2
2F
TMP_DR3
DBB10FN
30
RW
ACB00CR3
DBB10IN
31
RW
ACB00CR0
DBB10OU
32
RW
ACB00CR1
33
ACB00CR2
DBB11FN
34
RW
ACB01CR3
DBB11IN
35
RW
ACB01CR0
DBB11OU
36
RW
ACB01CR1
37
ACB01CR2
DCB12FN
38
RW
ACB02CR3
DCB12IN
39
RW
ACB02CR0
DCB12OU
3A
RW
ACB02CR1
3B
ACB02CR2
DCB13FN
3C
RW
ACB03CR3
DCB13IN
3D
RW
ACB03CR0
DCB13OU
3E
RW
ACB03CR1
3F
ACB03CR2
Blank fields are Reserved and should not be accessed.
Document Number: 38-12013 Rev. AD
Addr (1,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
Addr (1,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RDI2RI
RDI2SYN
RDI2IS
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
RDI3RI
RDI3SYN
RDI3IS
RDI3LT0
RDI3LT1
RDI3RO0
RDI3RO1
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
DEC_CR2
IMO_TR
ILO_TR
BDG_TR
ECO_TR
RW
RW
RW
RW
RW
RW
RW
CPU_F
RW
RW
RW
RW
RW
RW
RW
FLS_PR1
CPU_SCR1
CPU_SCR0
Addr (1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
W
W
RW
W
RL
RW
#
#
Page 20 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C29x66 PSoC device. For the most up-to-date electrical
specifications, confirm that you have the most recent datasheet by going to the web at http://www.cypress.com.
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Refer to Table 29 for the electrical specifications
on the internal main oscillator (IMO) using SLIMO mode.
Figure 10. Voltage versus CPU Frequency
Figure 11. IMO Frequency Options
5.25
4.75
Vdd Voltage
Vdd Voltage
l id g
V a a tin
n
r
pe g io
Re
O
4.75
SLIMO Mode = 0
5.25
3.60
3.00
3.00
9 3 kHz
12 MHz
2 4 MHz
9 3 kHz
S L IM O
M o d e =1
S L IM O
M o d e =0
S L IM O
M o d e =1
S L IM O
M o d e =0
1 2 MHz
6 MHz
2 4 MHz
IM O F r e q u e n cy
C PU F r e q u e n c y
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 11. Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Unit
Notes
–55
25
+100
°C
Higher storage temperatures
reduce data retention time.
Recommended storage temperature is +25 °C ± 25 °C. Extended
duration storage temperatures
higher than 65 °C degrade
reliability.
–
125
See
package
label
°C
See
package
label
–
72
Hours
TSTG
Storage temperature
TBAKETEMP
Bake temperature
TBAKETIME
Bake time
TA
Ambient temperature with power applied
–40
–
+85
°C
VDD
Supply voltage on VDD relative to VSS
–0.5
–
+6.0
V
VIO
DC input voltage
VSS – 0.5
–
VDD + 0.5
V
VIOZ
DC voltage applied to tristate
VSS – 0.5
–
VDD + 0.5
V
IMIO
Maximum current into any port pin
–25
–
+50
mA
IMAIO
Maximum current into any port pin configured as
analog driver
–50
–
+50
mA
ESD
Electrostatic discharge voltage
2000
–
–
V
LU
Latch-up current
–
–
200
mA
Document Number: 38-12013 Rev. AD
Human body model ESD.
Page 21 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Operating Temperature
Table 12. Operating Temperature
Symbol
TA
TJ
Description
Ambient temperature
Junction temperature
Min
–40
–40
Typ
–
–
Max
+85
+100
Unit
°C
°C
Notes
The temperature rise from
ambient to junction is package
specific. See “Thermal
Impedances” on page 53. You
must limit the power
consumption to comply with this
requirement.
DC Electrical Characteristics
DC Chip-Level Specifications
Table 13 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 13. DC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Unit
Notes
s
V
See DC POR, SMP, and LVD Specifications on page
38.
mA Conditions are 5.0 V, TA = 25 °C, CPU = 3 MHz,
SYSCLK doubler disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz.
mA Conditions are VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz,
SYSCLK doubler disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz.
mA Conditions are VDD = 3.3 V, TA = 25 °C, CPU = 0.75
MHz, SYSCLK doubler disabled,
VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz.
µA Conditions are with internal slow speed oscillator,
VDD = 3.3 V, –40 C TA 55 °C.
µA Conditions are with internal slow speed oscillator,
VDD = 3.3 V, 55 °C < TA 85 °C.
µA Conditions are with properly loaded, 1 µW max,
32.768 kHz crystal. VDD = 3.3 V, –40 °C TA 55 °C.
VDD [14]
Supply voltage
3.00
–
5.25
IDD
Supply current
–
8
14
IDD3
Supply current
–
5
9
IDDP
Supply current when IMO = 6 MHz using SLIMO
mode.
–
2
3
ISB
Sleep (Mode) current with POR, LVD, sleep
–
timer, WDT, and internal slow oscillator active.
Sleep (Mode) current with POR, LVD, sleep
–
timer, WDT, and internal slow oscillator active.
Sleep (Mode) current with POR, LVD, sleep
–
timer, WDT, internal slow oscillator, and 32 kHz
crystal oscillator active.
Sleep (Mode) current with POR, LVD, sleep
–
timer, WDT, and 32 kHz crystal oscillator active.
Reference voltage (Bandgap)
1.28
3
10
4
25
4
12
5
27
µA
1.3
1.32
V
ISBH
ISBXTL
ISBXTLH
VREF
Conditions are with properly loaded, 1 µW max,
32.768 kHz crystal. VDD = 3.3 V, 55 °C < TA 85 °C.
Trimmed for appropriate VDD.
Note
14. Errata: When VDD of the device is pulled below ground just before power-on; the first read from each 8K Flash bank may be corrupted apart from flash bank 0. This
an be solved by doing a dummy read from each flash bank prior to use of the Flash banks. For more information, see Errata on page 63.
Document Number: 38-12013 Rev. AD
Page 22 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
DC GPIO Specifications
Table 14 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 14. DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Unit
4
5.6
8
k
Pull-down resistor
4
5.6
8
k
High output level
VDD – 1.0
–
–
V
IOH = 10 mA, VDD = 4.75 to 5.25 V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
80 mA maximum combined IOH budget.
VOL
Low output level
–
–
0.75
V
IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
150 mA maximum combined IOL budget.
IOH
High level source current
10
–
–
mA
VOH = VDD – 1.0 V, see the limitations of the total
current in the note for VOH
IOL
Low level sink current
25
–
–
mA
VOL = 0.75 V, see the limitations of the total
current in the note for VOL
VIL
Input low level
–
–
0.8
V
VDD = 3.0 to 5.25
VIH
Input high level
2.1
–
–
V
VDD = 3.0 to 5.25
VH
Input hysteresis
–
60
–
mV
IIL
Input leakage (absolute value)
–
1
–
nA
Gross tested to 1 µA.
CIN
Capacitive load on pins as input
–
3.5
10
pF
Package and pin dependent. Temp = 25 °C.
COUT
Capacitive load on pins as output
–
3.5
10
pF
Package and pin dependent. Temp = 25 °C.
RPU
Pull-up resistor
RPD
VOH
Document Number: 38-12013 Rev. AD
Notes
Page 23 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
DC Operational Amplifier Specifications
Table 15 and Table 16 list guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V
and 3.3 V at 25 °C and are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5 V at
25 °C and are for design guidance only.
Table 15. 5-V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Unit
–
–
–
–
–
–
1.6
1.6
1.6
1.6
1.6
1.6
10
10
10
10
10
10
mV
mV
mV
mV
mV
mV
–
4
23
µV/°C
–
200
–
pA
Gross tested to 1 µA
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
0
–
VDD
V
Common mode voltage range (Power = High,
Opamp bias = High)
0.5
–
VDD – 0.5
V
The common-mode input voltage range
is measured through an analog output
buffer.
The specification includes the
limitations imposed by the
characteristics of the analog output
buffer.
Common mode rejection ratio
60
–
–
dB
VOSOA
Input offset voltage (absolute value)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
TCVOSOA
Average input offset voltage drift
I
EBOA
Input leakage current (port 0 analog pins)
CINOA
Input capacitance (port 0 analog pins)
V
Common mode voltage range (All cases,
except Power = High, Opamp bias = High)
CMOA
CMRROA
GOLOA Open loop gain
80
–
–
dB
VOHIGHOA
High output voltage swing (internal signals)
VDD – 0.01
–
–
V
VOLOWOA
Low output voltage swing (internal signals)
–
–
0.1
V
ISOA
Supply current (including associated
AGND buffer)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
µA
µA
µA
µA
µA
µA
Supply voltage rejection ratio
67
80
–
dB
PSRROA
Document Number: 38-12013 Rev. AD
Notes
VSS VIN (VDD – 2.25) or
(VDD – 1.25 V) VIN VDD.
Page 24 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Table 16. 3.3-V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Unit
VOSOA
Input offset voltage (absolute value)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
–
–
–
–
–
–
1.4
1.4
1.4
1.4
1.4
–
10
10
10
10
10
–
mV
mV
mV
mV
mV
mV
TCVOSOA
Average input offset voltage drift
–
7
40
µV/°C
I
Notes
Power = High, Opamp bias = High
setting is not allowed for 3.3 V VDD
operation.
EBOA
Input leakage current (port 0 analog pins)
–
200
–
pA
Gross tested to 1 µA.
CINOA
Input capacitance (port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
V
Common mode voltage range
0
–
VDD
V
The common-mode input voltage range
is measured through an analog output
buffer.
The specification includes the limitations
imposed by the characteristics of the
analog output buffer.
CMOA
CMRROA
Common mode rejection ratio
60
–
–
dB
GOLOA
Open loop gain
80
–
–
dB
VOHIGHOA
High output voltage swing (internal signals)
VDD – 0.01
–
–
V
VOLOWOA
Low output voltage swing (internal signals)
–
–
0.01
V
ISOA
Supply current
(including associated AGND buffer)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
–
–
–
–
–
–
150
300
600
1200
2400
–
200
400
800
1600
3200
–
µA
µA
µA
µA
µA
µA
Supply voltage rejection ratio
54
80
–
dB
PSRROA
Power = High, Opamp bias = High
setting is not allowed for 3.3 V VDD
operation.
VSS VIN (VDD – 2.25) or
(VDD – 1.25 V) VIN VDD
DC Low-Power Comparator Specifications
Table 17 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C
TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V at 25 °C and are for design guidance only.
Table 17. DC Low-Power Comparator Specifications
Symbol
Description
VREFLPC
Low-power comparator (LPC) reference voltage range
ISLPC
LPC supply current
VOSLPC
LPC voltage offset
Document Number: 38-12013 Rev. AD
Min
Typ
Max
Unit
0.2
–
VDD – 1
V
–
10
40
µA
–
2.5
30
mV
Page 25 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
DC Analog Output Buffer Specifications
Table 18 and Table 19 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 18. 5-V DC Analog Output Buffer Specifications
Symbol
Description
VOSOB
Input offset voltage (absolute value)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
TCVOSOB
Average input offset voltage drift
VCMOB
Common-mode input voltage range
ROUTOB
Output resistance
Power = Low
Power = High
VOHIGHOB
Min
Typ
Max
Unit
–
–
–
–
3.2
3.2
3.2
3.2
18
18
18
18
mV
mV
mV
mV
–
5.5
26
µV/°C
0.5
–
VDD – 1.0
V
–
–
–
–
1
1
High output voltage swing
(Load = 32 ohms to VDD/2)
Power = Low
Power = High
0.5 × VDD + 1.3
0.5 × VDD + 1.3
–
–
–
–
V
V
Low output voltage swing
(Load = 32 ohms to VDD/2)
Power = Low
Power = High
–
–
–
–
0.5 × VDD – 1.3
0.5 × VDD – 1.3
V
V
ISOB
Supply current including bias cell (no load)
Power = Low
Power = High
–
–
1.1
2.6
2
5
mA
mA
PSRROB
Supply voltage rejection ratio
40
64
CL
Load capacitance
–
–
VOLOWOB
Document Number: 38-12013 Rev. AD
Notes
dB
200
pF
This specification
applies to the
external circuit
driven by the analog
output buffer.
Page 26 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Table 19. 3.3-V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Unit
VOSOB
Input offset voltage (absolute value)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
–
–
–
–
3.2
3.2
6
6
20
20
25
25
mV
mV
mV
mV
TCVOSOB
Average input offset voltage drift
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
–
–
–
–
8
8
12
12
32
32
41
41
µV/°C
µV/°C
µV/°C
µV/°C
VCMOB
Common-mode input voltage range
0.5
–
VDD – 1.0
V
ROUTOB
Output resistance
Power = Low
Power = High
–
–
–
–
10
10
W
W
VOHIGHOB
High output voltage swing
(Load = 32 ohms to VDD/2)
Power = Low
Power = High
0.5 × VDD + 1.0
0.5 × VDD + 1.0
–
–
–
–
V
V
Low output voltage swing
(Load = 32 ohms to VDD/2)
Power = Low
Power = High
–
–
–
–
0.5 × VDD – 1.0
0.5 × VDD – 1.0
V
V
ISOB
Supply current including bias cell (no load)
Power = Low
Power = High
–
–
0.8
2.0
1
5
mA
mA
PSRROB
Supply voltage rejection ratio
60
64
–
dB
CL
Load capacitance
–
–
200
pF
VOLOWOB
Document Number: 38-12013 Rev. AD
Notes
High power setting
is not
recommended.
High power setting
is not
recommended.
This specification
applies to the
external circuit
driven by the
analog output
buffer.
Page 27 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
DC Switch Mode Pump Specifications
Table 20 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 20. DC Switch Mode Pump (SMP) Specifications
Min
Typ
Max
Unit
Notes
VPUMP 5 V
Symbol
5 V output voltage at VDD from
pump
Description
4.75
5.0
5.25
V
Configured as in Note 15. Average,
neglecting ripple. SMP trip voltage
is set to 5.0 V
VPUMP 3 V
3 V output voltage at VDD from
pump
3.00
3.25
3.60
V
Configured as in Note 15. Average,
neglecting ripple. SMP trip voltage
is set to 3.25 V
IPUMP
Available output current
VBAT = 1.5 V, VPUMP = 3.25 V
VBAT = 1.8 V, VPUMP = 5.0 V
8
5
–
–
–
–
mA
mA
VBAT5 V
Input voltage range from battery
1.8
–
5.0
V
Configured as in Note 15. SMP trip
voltage is set to 5.0 V
VBAT3 V
Input voltage range from battery
1.0
–
3.3
V
Configured as in Note 15. SMP trip
voltage is set to 3.25 V
VBATSTART
Minimum input voltage from battery
to start pump
1.2
–
–
V
Configured as in Note 15.0 °C TA
100. 1.25 V at TA = –40 °C
VPUMP_Line
Line regulation (over VBAT range)
–
5
–
%VO
Configured as in Note 15. VO is the
“VDD Value for PUMP Trip” specified
by the VM[2:0] setting in the DC
POR and LVD Specification,
Table 26, “DC POR, SMP, and LVD
Specifications,” on page 38
VPUMP_Load
Load regulation
–
5
–
%VO
Configured as in Note 15. VO is the
“VDD Value for PUMP Trip” specified
by the VM[2:0] setting in Table 26,
“DC POR, SMP, and LVD Specifications,” on page 38
VPUMP_Ripple Output voltage ripple (depends on
capacitor/load)
–
100
–
mVpp
Configured as in Note 15. Load is
5 mA
E3
Efficiency
35
50
–
%
Configured as in Note 15. Load is
5 mA. SMP trip voltage is set to
3.25 V
FPUMP
Switching frequency
–
1.4
–
MHz
DCPUMP
Switching duty cycle
–
50
–
%
Configured as in Note 15
SMP trip voltage is set to 3.25 V
SMP trip voltage is set to 5.0 V
Note
15. L1 = 2 µH inductor, C1 = 10 µF capacitor, D1 = Schottky diode. See Figure 12.
Document Number: 38-12013 Rev. AD
Page 28 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Figure 12. Basic Switch Mode Pump Circuit
D1
Vdd
L1
V BAT
+
V PUMP
C1
SMP
Battery
PSoC
Vss
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
The guaranteed specifications for RefHI and RefLO are measured through the analog continuous time PSoC blocks. The power levels
for RefHI and RefLO refer to the analog reference control register. AGND is measured at P2[4] in AGND bypass mode. Each analog
continuous time PSoC block adds a maximum of 10 mV additional offset error to guaranteed AGND specifications from the local
AGND buffer. Reference control power can be set to medium or high unless otherwise noted.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the analog reference. Some coupling of
the digital signal may appear on the AGND.
Table 21. 5-V DC Analog Reference Specifications
Reference
ARF_CR[5:3]
Reference Power
Settings
Symbol
Reference
Description
Min
RefPower = High
Opamp bias = High
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.228
VDD/2 + 1.290 VDD/2 + 1.352
VAGND
AGND
VDD/2
VDD/2 – 0.078
VDD/2 – 0.007
VDD/2 + 0.063
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.336
VDD/2 – 1.295
VDD/2 – 1.250
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.224
VDD/2 + 1.293 VDD/2 + 1.356
V
VAGND
AGND
VDD/2
VDD/2 – 0.056
VDD/2 – 0.005
VDD/2 + 0.043
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.338
VDD/2 – 1.298
VDD/2 – 1.255
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.226
VDD/2 + 1.293 VDD/2 + 1.356
V
VAGND
AGND
VDD/2
VDD/2 – 0.057
VDD/2 – 0.006
VDD/2 + 0.044
V
RefPower = High
Opamp bias = Low
0b000
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Typ
Max
Unit
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.337
VDD/2 – 1.298
VDD/2 – 1.256
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.226
VDD/2 + 1.294 VDD/2 + 1.359
V
VAGND
AGND
VDD/2
VDD/2 – 0.047
VDD/2 – 0.004
VDD/2 + 0.035
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.338
VDD/2 – 1.299
VDD/2 – 1.258
V
Document Number: 38-12013 Rev. AD
Page 29 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Table 21. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
Symbol
Reference
RefPower = High
Opamp bias = High
VREFHI
Ref High
RefPower = High
Opamp bias = Low
0b001
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b010
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Description
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
Min
Typ
Max
Unit
P2[4] + P2[6] –
0.085
P2[4] + P2[6] –
0.016
P2[4] + P2[6]
+ 0.044
V
P2[4]
P2[4]
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.010
0.055
V
VREFHI
Ref High
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] + P2[6] –
0.077
P2[4] + P2[6] –
0.010
P2[4] + P2[6]
+ 0.051
V
P2[4]
P2[4]
P2[4]
P2[4]
–
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.005
0.039
V
VREFHI
Ref High
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] + P2[6] –
0.070
P2[4] + P2[6] –
0.010
P2[4] + P2[6]
+ 0.050
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.005
0.039
V
VREFHI
Ref High
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] + P2[6] –
0.070
P2[4] + P2[6] –
0.007
P2[4] + P2[6]
+ 0.054
V
P2[4]
P2[4]
P2[4]
P2[4]
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
VREFHI
Ref High
VDD
VAGND
AGND
P2[4]
VDD/2
P2[4]
P2[4]
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.002
0.032
–
–
V
VDD – 0.037
VDD – 0.009
VDD
V
VDD/2 – 0.061
VDD/2 – 0.006
VDD/2 + 0.047
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.007
VSS + 0.028
V
VREFHI
Ref High
VDD
VDD – 0.039
VDD – 0.006
VDD
V
VAGND
AGND
VDD/2 – 0.049
VDD/2 – 0.005
VDD/2 + 0.036
V
VDD/2
VREFLO
Ref Low
VSS
VSS
VSS + 0.005
VSS + 0.019
V
VREFHI
Ref High
VDD
VDD – 0.037
VDD – 0.007
VDD
V
VAGND
AGND
VDD/2 – 0.054
VDD/2 – 0.005
VDD/2 + 0.041
V
VDD/2
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.024
V
VREFHI
Ref High
VDD
VDD – 0.042
VDD – 0.005
VDD
V
VDD/2 – 0.046
VDD/2 – 0.004
VDD/2 + 0.034
V
VSS
VSS + 0.004
VSS + 0.017
V
VAGND
AGND
VREFLO
Ref Low
Document Number: 38-12013 Rev. AD
VDD/2
VSS
Page 30 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Table 21. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
Symbol
Reference
RefPower = High
Opamp bias = High
VREFHI
Ref High
RefPower = High
Opamp bias = Low
0b011
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b100
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Description
Min
Typ
Max
Unit
3 × Bandgap
3.788
3.891
3.986
V
VAGND
AGND
2 × Bandgap
2.500
2.604
2.699
V
VREFLO
Ref Low
Bandgap
1.257
1.306
1.359
V
VREFHI
Ref High
3 × Bandgap
3.792
3.893
3.982
V
2 × Bandgap
2.518
2.602
2.692
V
Bandgap
1.256
1.302
1.354
V
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
3 × Bandgap
3.795
3.894
3.993
V
VAGND
AGND
2 × Bandgap
2.516
2.603
2.698
V
VREFLO
Ref Low
Bandgap
1.256
1.303
1.353
V
VREFHI
Ref High
3 × Bandgap
3.792
3.895
3.986
V
VAGND
AGND
2 × Bandgap
2.522
2.602
2.685
V
VREFLO
Ref Low
Bandgap
1.255
1.301
1.350
V
VREFHI
Ref High
2 × Bandgap +
P2[6] (P2[6] =
1.3 V)
2.495 + P2[6]
2.586 + P2[6]
2.657 + P2[6]
V
VAGND
AGND
2.502
2.604
2.719
V
VREFLO
Ref Low
2 × Bandgap –
P2[6] (P2[6] =
1.3 V)
2.531 – P2[6]
2.611 – P2[6]
2.681 – P2[6]
V
VREFHI
Ref High
2 × Bandgap +
P2[6] (P2[6] =
1.3 V)
2.500 + P2[6]
2.591 + P2[6]
2.662 + P2[6]
V
2 × Bandgap
VAGND
AGND
2.519
2.602
2.693
V
VREFLO
Ref Low
2 × Bandgap –
P2[6] (P2[6] =
1.3 V)
2.530 – P2[6]
2.605 – P2[6]
2.666 – P2[6]
V
VREFHI
Ref High
2 × Bandgap +
P2[6] (P2[6] =
1.3 V)
2.503 + P2[6]
2.592 + P2[6]
2.662 + P2[6]
V
2 × Bandgap
VAGND
AGND
2.517
2.603
2.698
V
VREFLO
Ref Low
2 × Bandgap –
P2[6] (P2[6] =
1.3 V)
2.529 – P2[6]
2.606 – P2[6]
2.665 – P2[6]
V
VREFHI
Ref High
2 × Bandgap +
P2[6] (P2[6] =
1.3 V)
2.505 + P2[6]
2.594 + P2[6]
2.665 + P2[6]
V
VAGND
AGND
2.525
2.602
2.685
V
VREFLO
Ref Low
2.528 – P2[6]
2.603 – P2[6]
2.661 – P2[6]
V
Document Number: 38-12013 Rev. AD
2 × Bandgap
2 × Bandgap
2 × Bandgap –
P2[6] (P2[6] =
1.3 V)
Page 31 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Table 21. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
Symbol
Reference
RefPower = High
Opamp bias = High
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
RefPower = High
Opamp bias = Low
0b101
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b110
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b111
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Description
Min
Typ
Max
Unit
P2[4] + 1.222
P2[4] + 1.290
P2[4] + 1.343
V
P2[4]
P2[4]
P2[4]
–
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.331
P2[4] – 1.295
P2[4] – 1.254
V
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.226
P2[4] + 1.293
P2[4] + 1.347
V
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4]
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4]
P2[4] – 1.331
P2[4] – 1.298
P2[4] – 1.259
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.227
P2[4] + 1.294
P2[4] + 1.347
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4]
P2[4] – 1.331
P2[4] – 1.298
P2[4] – 1.259
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.228
P2[4] + 1.295
P2[4] + 1.349
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – 1.332
P2[4] – 1.299
P2[4] – 1.260
V
VREFHI
Ref High
VAGND
AGND
P2[4]
P2[4] – Bandgap
(P2[4] = VDD/2)
2 × Bandgap
2.535
2.598
2.644
V
Bandgap
1.227
1.305
1.398
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.009
VSS + 0.038
V
VREFHI
Ref High
2 × Bandgap
2.530
2.598
2.643
V
VAGND
AGND
Bandgap
1.244
1.303
1.370
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.005
VSS + 0.024
V
VREFHI
Ref High
2 × Bandgap
2.532
2.598
2.644
V
VAGND
AGND
Bandgap
1.239
1.304
1.380
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.026
V
VREFHI
Ref High
2 × Bandgap
2.528
2.598
2.645
V
Bandgap
1.249
1.302
1.362
V
VSS
VSS + 0.004
VSS + 0.018
V
4.155
4.234
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.041
1.6 × Bandgap
1.998
2.083
2.183
V
VSS
VSS + 0.010
VSS + 0.038
V
4.153
4.236
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.047
1.6 × Bandgap
2.012
2.082
2.157
V
VSS
VSS + 0.006
VSS + 0.024
V
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
3.2 × Bandgap
4.049
4.154
4.238
V
VAGND
AGND
1.6 × Bandgap
2.008
2.083
2.165
V
VREFLO
Ref Low
VSS
VSS + 0.006
VSS + 0.026
V
VREFHI
Ref High
3.2 × Bandgap
4.047
4.154
4.238
V
VAGND
AGND
1.6 × Bandgap
2.016
2.081
2.150
V
VREFLO
Ref Low
VSS
VSS + 0.004
VSS + 0.018
V
Document Number: 38-12013 Rev. AD
VSS
VSS
VSS
Page 32 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Table 22. 3.3-V DC Analog Reference Specifications
Reference
ARF_CR[5:3]
Reference Power
Settings
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b000
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Symbol Reference
Description
Min
Typ
Max
Unit
VDD/2 + BandGap
VDD/2 +
1.225
VDD/2 +
1.292
VDD/2 +
1.361
V
VDD/2
VDD/2 –
0.067
VDD/2 –
0.002
VDD/2 +
0.063
V
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VDD/2 – BandGap
VDD/2 –
1.35
VDD/2 –
1.293
VDD/2 –
1.210
V
VREFHI
Ref High
VDD/2 + BandGap
VDD/2 +
1.218
VDD/2 +
1.294
VDD/2 +
1.370
V
VAGND
AGND
VDD/2
VDD/2 –
0.038
VDD/2 –
0.001
VDD/2 +
0.035
V
VREFLO
Ref Low
VDD/2 – BandGap
VDD/2 –
1.329
VDD/2 –
1.296
VDD/2 –
1.259
V
VREFHI
Ref High
VDD/2 + BandGap
VDD/2 +
1.221
VDD/2 +
1.294
VDD/2 +
1.366
V
VAGND
AGND
VDD/2
VDD/2 –
0.050
VDD/2 –
0.002
VDD/2 +
0.046
V
VREFLO
Ref Low
VDD/2 – BandGap
VDD/2 –
1.331
VDD/2 –
1.296
VDD/2 –
1.260
V
VREFHI
Ref High
VDD/2 + BandGap
VDD/2 +
1.226
VDD/2 +
1.295
VDD/2 +
1.365
V
VAGND
AGND
VDD/2
VDD/2 –
0.028
VDD/2 –
0.001
VDD/2 +
0.025
V
VREFLO
Ref Low
VDD/2 – BandGap
VDD/2 –
1.329
VDD/2 –
1.297
VDD/2 –
1.262
V
Document Number: 38-12013 Rev. AD
Page 33 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Table 22. 3.3-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b001
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Symbol Reference
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
Description
Min
Typ
Max
Unit
P2[4]+P2[6]
(P2[4] = VDD/2,
P2[6] =
0.5 V)
P2[4] +
P2[6] –
0.098
P2[4] +
P2[6] –
0.018
P2[4] +
P2[6] +
0.055
V
P2[4]
P2[4]
P2[4]
P2[4]
–
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] =
0.5 V)
P2[4] –
P2[6] –
0.055
P2[4] –
P2[6] +
0.013
P2[4] –
P2[6] +
0.086
V
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] =
0.5 V)
P2[4] +
P2[6] –
0.082
P2[4] +
P2[6] –
0.011
P2[4] +
P2[6] +
0.050
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] =
0.5 V)
P2[4] –
P2[6] –
0.037
P2[4] –
P2[6] +
0.006
P2[4] –
P2[6] +
0.054
V
VREFHI
Ref High
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] =
0.5 V)
P2[4] +
P2[6] –
0.079
P2[4] +
P2[6] –
0.012
P2[4] +
P2[6] +
0.047
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4]–P2[6]
(P2[4] = VDD/2,
P2[6] =
0.5 V)
P2[4] –
P2[6] –
0.038
P2[4] –
P2[6] +
0.006
P2[4] –
P2[6] +
0.057
V
VREFHI
Ref High
P2[4]+P2[6]
(P2[4] = VDD/2,
P2[6] =
0.5 V)
P2[4] +
P2[6] –
0.080
P2[4] +
P2[6] –
0.008
P2[4] +
P2[6] +
0.055
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4]–P2[6]
(P2[4] = VDD/2,
P2[6] =
0.5 V)
P2[4] –
P2[6] –
0.032
P2[4] –
P2[6] +
0.003
P2[4] –
P2[6] +
0.042
V
Document Number: 38-12013 Rev. AD
Page 34 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Table 22. 3.3-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b010
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Symbol Reference
VREFHI
Ref High
VAGND
AGND
Description
Min
Typ
Max
Unit
VDD
VDD – 0.06
VDD – 0.010 VDD
V
VDD/2
VDD/2 –
0.05
VDD/2 –
0.002
V
Vss + 0.009 Vss + 0.056 V
VDD/2 +
0.040
VREFLO
Ref Low
Vss
Vss
VREFHI
Ref High
VDD
VDD – 0.060 VDD – 0.006 VDD
V
VAGND
AGND
VDD/2
VDD/2 –
0.028
VDD/2 –
0.001
V
VREFLO
Ref Low
Vss
Vss
Vss + 0.005 Vss + 0.034 V
VREFHI
Ref High
VDD
VDD – 0.058 VDD – 0.008 VDD
V
VAGND
AGND
VDD/2
VDD/2 –
0.037
VDD/2 –
0.002
V
VREFLO
Ref Low
Vss
Vss
Vss + 0.007 Vss + 0.046 V
VREFHI
Ref High
VDD
VAGND
AGND
VDD/2
VDD – 0.057 VDD – 0.006 VDD
VDD/2 –
VDD/2 –
VDD/2 +
0.025
0.001
0.022
VREFLO
Ref Low
Vss
Vss
VDD/2 +
0.025
VDD/2 +
0.033
V
V
Vss + 0.004 Vss + 0.030 V
0b011
All power settings.
Not allowed for 3.3 V
–
–
–
–
–
–
–
0b100
All power settings.
Not allowed for 3.3 V
–
–
–
–
–
–
–
Document Number: 38-12013 Rev. AD
Page 35 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Table 22. 3.3-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b101
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b110
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
0b111
Symbol Reference
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
Description
Min
Typ
Max
Unit
P2[4] + BandGap (P2[4] =
VDD/2)
P2[4] +
1.213
P2[4] +
1.291
P2[4] +
1.367
V
P2[4]
P2[4]
P2[4]
P2[4]
V
P2[4] – BandGap (P2[4] =
VDD/2)
P2[4] –
1.333
P2[4] –
1.294
P2[4] –
1.208
V
P2[4] + BandGap (P2[4] =
VDD/2)
P2[4] +
1.217
P2[4] +
1.294
P2[4] +
1.368
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
V
VREFLO
Ref Low
P2[4] – BandGap (P2[4] =
VDD/2)
P2[4] –
1.320
P2[4] –
1.296
P2[4] –
1.261
V
VREFHI
Ref High
P2[4] + BandGap (P2[4] =
VDD/2)
P2[4] +
1.217
P2[4] +
1.294
P2[4] +
1.369
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
V
VREFLO
Ref Low
P2[4] – BandGap (P2[4] =
VDD/2)
P2[4] –
1.322
P2[4] –
1.297
P2[4] –
1.262
V
VREFHI
Ref High
P2[4] + BandGap (P2[4] =
VDD/2)
P2[4] +
1.219
P2[4] +
1.295
P2[4] + 1.37 V
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
V
VREFLO
Ref Low
P2[4] – BandGap (P2[4] =
VDD/2)
P2[4] –
1.324
P2[4] –
1.297
P2[4] –
1.262
V
VREFHI
Ref High
2 × BandGap
2.507
2.598
2.698
V
1.424
V
VAGND
AGND
BandGap
1.203
1.307
VREFLO
Ref Low
Vss
Vss
Vss + 0.012 Vss + 0.067 V
VREFHI
Ref High
2 × BandGap
2.516
2.598
2.683
V
VAGND
AGND
BandGap
1.241
1.303
1.376
V
VREFLO
Ref Low
Vss
Vss
Vss + 0.007 Vss + 0.040 V
VREFHI
Ref High
2 × BandGap
2.510
2.599
2.693
V
VAGND
AGND
BandGap
1.240
1.305
1.374
V
VREFLO
Ref Low
Vss
Vss
Vss + 0.008 Vss + 0.048 V
VREFHI
Ref High
2 × BandGap
2.515
2.598
2.683
V
VAGND
AGND
BandGap
1.258
1.302
1.355
V
VREFLO
Ref Low
Vss
Vss
Vss + 0.005 Vss + 0.03
–
–
All power settings.
Not allowed for 3.3 V.
Document Number: 38-12013 Rev. AD
–
–
–
–
V
–
Page 36 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
DC Analog External Reference Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 23. 5-V DC Analog External Reference Specifications
Reference
Min
Typ
Max
Unit
Ref Low = P2[4] – P2[6] (P2[4] = VCC/2, P2[6] = 1.3 V)
1.12
1.221
1.28
V
AGND
AGND = P2[4] (P2[4] = VCC/2)
2.487
2.499
2.513
V
Ref High
Ref Low = P2[4] + P2[6] (P2[4] = VCC/2, P2[6] = 1.3 V)
3.67
3.759
3.93
V
Ref Low
Description
Table 24. 3.3-V DC Analog External Reference Specifications
Reference
Min
Typ
Max
Unit
Ref Low = P2[4] – P2[6] (P2[4] = VCC/2, P2[6] = 1.3 V)
0.29
0.371
0.41
V
AGND
AGND = P2[4] (P2[4] = VCC/2)
1.642
1.649
1.658
V
Ref High
Ref Low = P2[4] + P2[6] (P2[4] = VCC/2, P2[6] = 1.3 V)
–
2.916
–
V
Ref Low
Description
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 25. DC Analog PSoC Block Specifications
Symbol
RCT
CSC
Description
Resistor unit value (continuous time)
Capacitor unit value (switch cap)
Document Number: 38-12013 Rev. AD
Min
–
–
Typ
12.2
80
Max
–
–
Unit
k
fF
Notes
Page 37 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
DC POR, SMP, and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature
ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0
V to 3.6 V and –40 °C TA 85 °C, respectively. Typical
parameters apply to 5 V and 3.3 V at 25 °C and are for
design guidance only.
Table 26. DC POR, SMP, and LVD Specifications
Symbol
VPPOR0R
VPPOR1R
VPPOR2R
VPPOR0
VPPOR1
VPPOR2
VPH0
VPH1
VPH2
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
Description
VDD value for PPOR trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VDD value for PPOR trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
PPOR hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VDD value for LVD trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
VDD value for SMP trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
–
2.91
4.39
4.55
–
V
V
V
–
2.82
4.39
4.55
–
V
V
V
–
–
–
92
0
0
–
–
–
mV
mV
mV
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98[16]
3.08
3.20
4.08
4.57
4.74[17]
4.82
4.91
V
V
V
V
V
V
V
V
2.96
3.03
3.18
4.11
4.55
4.63
4.72
4.90
3.02
3.10
3.25
4.19
4.64
4.73
4.82
5.00
3.08
3.16
3.32
4.28
4.74
4.82
4.91
5.10
V
V
V
V
V
V
V
V
Notes
Notes
16. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
17. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 38-12013 Rev. AD
Page 38 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 27. DC Programming Specifications
Symbol
VDDP
VDDLV
VDDHV
Description
Min
Typ
Units
Notes
4.5
5
5.5
V
This specification applies
to the functional
requirements of external
programmer tools.
3
3.1
3.2
V
This specification applies
to the functional
requirements of external
programmer tools.
5.3
V
This specification applies
to the functional
requirements of external
programmer tools.
5.25
V
This specification applies
to this device when it is
executing internal flash
writes.
Low VDD for verify
High VDD for verify
5.1
VDDIWRITE
Max
VDD for programming and erase
5.2
Supply voltage for flash write operation
3.15
IDDP
Supply current during programming or verify
–
10
30
mA
VILP
Input low voltage during programming or verify
–
–
0.8
V
VIHP
Input high voltage during programming or verify
2.2
–
–
V
IILP
Input current when applying Vilp to P1[0] or P1[1]
during programming or verify
–
–
0.2
mA
Driving internal pull-down
resistor
IIHP
Input current when applying Vihp to P1[0] or P1[1]
during programming or verify
–
–
1.5
mA
Driving internal pull-down
resistor
VOLV
Output low voltage during programming or verify
–
–
VSS + 0.75
V
VOHV
Output high voltage during programming or verify
VDD – 1.0
–
VDD
V
[18]
–
–
–
Erase/write cycles per
block
Erase/write cycles
FlashENPB
Flash endurance (per block)
50,000
FlashENT
Flash endurance (total)[19]
1,800,000
–
–
–
FlashDR
Flash data retention
10
–
–
Years
DC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 28. DC I2C Specifications
Min
Typ
Max
Units
VILI2C[20]
Parameter
Input low level
Description
–
–
0.3 × VDD
V
Notes
–
–
0.25 × VDD
V
4.75 V VDD 5.25 V
VIHI2C[20]
Input high level
0.7 × VDD
–
–
V
3.0 V VDD 5.25 V
VOLI2C
Output low level
–
–
0.4
V
at sink current of 3 mA
–
–
0.6
V
at sink current of 6 mA
3.0 V VDD 3.6 V
Notes
18. The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V.
19. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each,
36 × 2 blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and that no
single block ever sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs application note Design Aids – Reading and Writing PSoC® Flash – AN2015 for more information.
20. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO specifications sections.The I2C GPIO pins also meet the mentioned specs.
Document Number: 38-12013 Rev. AD
Page 39 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Note See the individual user module datasheets for information on maximum frequencies for user modules.
Table 29. AC Chip-Level Specifications
Symbol
FIMO24
[21]
Description
Internal main oscillator (IMO)
frequency for 24 MHz
Min
Typ
Max
[22,23]
Units
Notes
22.8
24
25.2
MHz Trimmed for 5 V or 3.3 V operation using
factory trim values. See Figure 11 on page
21. SLIMO Mode = 0.
5.5
6
6.5[22,23]
MHz Trimmed for 5 V or 3.3 V operation using
factory trim values. See Figure 11 on page
21. SLIMO Mode = 1.
FIMO6
IMO frequency for 6 MHz
FCPU1
CPU frequency (5 V Nominal)
0.0914
24
25.2[22]
MHz SLIMO Mode = 0.
FCPU2
CPU frequency (3.3 V Nominal)
0.0914
12
12.6[23]
MHz SLIMO Mode = 0.
F48M
Digital PSoC block frequency
0
48
F24M
Digital PSoC block frequency
0
24
25.2 [24]
MHz
F32K1
Internal low speed oscillator
frequency
15
32
64
kHz
F32K2
External crystal oscillator
–
32.768
–
kHz
Accuracy is capacitor and crystal
dependent. 50% duty cycle
F32K_U
Internal low speed oscillator (ILO)
untrimmed frequency
5
–
100
kHz
After a reset and before the M8C starts to
run, the ILO is not trimmed. See the System
Resets section of the PSoC Technical
Reference Manual for details on this timing
FPLL
PLL frequency
–
23.986
–
TPLLSLEW
PLL lock time
0.5
–
10
ms
TPLLSLEWLOW
PLL lock time for low gain setting
0.5
–
50
ms
TOS
External crystal oscillator startup to
1%
–
250
500
ms
TOSACC
External crystal oscillator startup to
100 ppm
–
300
600
ms
TXRST
External reset pulse width
10
–
–
s
DC24M
24 MHz duty cycle
40
50
60
%
DCILO
Internal low speed oscillator duty
cycle
20
50
80
%
Step24M
24 MHz trim step size
–
50
–
kHz
[22, 23]
MHz Trimmed. Using factory trim values
Fout48M
48 MHz output frequency
FMAX
Maximum frequency of signal on
row input or row output.
45.6
48.0
–
–
50.4
[22,24]
50.4
12.3
MHz Refer to AC Digital Block Specifications on
page 45.
MHz A multiple (x732) of crystal frequency
The crystal oscillator frequency is within
100 ppm of its final value by the end of the
TOSACC period. Correct operation assumes
a properly loaded 1 µW maximum drive
level 32.768 kHz crystal.
3.0 V VDD 5.5 V, –40 °C TA 85 °C.
MHz
Notes
21. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see Errata on page 63.
22. 4.75 V < VDD < 5.25 V.
23. 3.0 V < VDD < 3.6 V. See application note Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V.
24. See the individual user module datasheets for information on maximum frequencies for user modules
Document Number: 38-12013 Rev. AD
Page 40 of 69
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CY8C29666/CY8C29866
Table 29. AC Chip-Level Specifications (continued)
Min
Typ
Max
Units
SRPOWER_UP
Symbol
Power supply slew rate
–
–
250
TPOWERUP [25]
Time from end of POR to CPU
executing code
–
16
100
V/ms VDD slew rate during power-up
ms Power-up from 0 V. See the System Resets
section of the PSoC Technical Reference
Manual
tjit_IMO[26]
24 MHz IMO cycle-to-cycle jitter
(RMS)
–
200
700
24 MHz IMO long term N
cycle-to-cycle jitter (RMS)
–
300
900
24 MHz IMO period jitter (RMS)
–
100
400
24 MHz IMO cycle-to-cycle jitter
(RMS)
–
200
800
24 MHz IMO long term N
cycle-to-cycle jitter (RMS)
–
300
1200
24 MHz IMO period jitter (RMS)
–
100
700
tjit_PLL
[26]
Description
Notes
ps
N = 32
ps
N = 32
Figure 13. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 14. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 15. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Notes
25. Errata: When VDD of the device is pulled below ground just before power-on; the first read from each 8K Flash bank may be corrupted apart from Flash bank 0. This
can be solved by doing a dummy read from each Flash bank prior to use of the Flash banks. For more information, see Errata on page 63.
26. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 38-12013 Rev. AD
Page 41 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
AC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 30. AC GPIO Specifications
Symbol
FGPIO
tRiseF
tFallF
tRiseS
tFallS
Description
GPIO operating frequency
Rise time, normal strong mode, Cload = 50 pF
Fall time, normal strong mode, Cload = 50 pF
Rise time, slow strong mode, Cload = 50 pF
Fall time, slow strong mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12.3
18
18
–
–
Unit
MHz
ns
ns
ns
ns
Notes
Normal strong mode
VDD = 4.75 to 5.25 V, 10% to 90%
VDD = 4.75 to 5.25 V, 10% to 90%
VDD = 3 to 5.25 V, 10% to 90%
VDD = 3 to 5.25 V, 10% to 90%
Figure 16. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the analog continuous time PSoC block.
Power = High and Opamp bias = High is not supported at 3.3 V.
Table 31. 5-V AC Operational Amplifier Specifications
Symbol
tROA
tSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising settling time to 0.1% for a 1 V step (10 pF load, unity gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = High
Falling settling time to 0.1% for a 1 V step (10 pF load, unity gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = High
Rising slew rate (20% to 80%) of a 1 V step (10 pF load, unity gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = High
Falling slew rate (20% to 80%) of a 1 V step (10 pF load, unity gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = High
Gain bandwidth product
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = High
Noise at 1 kHz (Power = Medium, Opamp bias = High)
Document Number: 38-12013 Rev. AD
Min
Typ
Max
Unit
–
–
–
–
–
–
3.9
0.72
0.62
µs
µs
µs
–
–
–
–
–
–
5.9
0.92
0.72
µs
µs
µs
0.15
1.7
6.5
–
–
–
–
–
–
V/µs
V/µs
V/µs
0.01
0.5
4.0
–
–
–
–
–
–
V/µs
V/µs
V/µs
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
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Table 32. 3.3-V AC Operational Amplifier Specifications
Symbol
tROA
tSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising settling time to 0.1% of a 1 V Step (10 pF load, unity gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Falling settling time to 0.1% of a 1 V Step (10 pF load, unity gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Rising slew rate (20% to 80%) of a 1 V Step (10 pF load, unity gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Falling slew rate (20% to 80%) of a 1 V Step (10 pF load, unity gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Gain bandwidth product
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Noise at 1 kHz (Power = Medium, Opamp bias = High)
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
µs
µs
–
–
–
–
5.41
0.72
µs
µs
0.31
2.7
–
–
–
–
V/µs
V/µs
0.24
1.8
0.67
2.8
–
–
–
–
–
–
–
–
V/µs
V/µs
MHz
MHz
–
100
–
nV/rt-Hz
Figure 17. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 38-12013 Rev. AD
0.01
0.1
Freq (kHz)
1
10
100
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Analog Reference Noise spectrum:
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 K resistance and the external capacitor.
Figure 18. Typical AGND Noise with P2[4] Bypass
AGND = 1.6 × Vbg
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Note: The capacitor values shown in Figure 18 are in µF.
AC Low-Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical
parameters apply to 5 V at 25 °C and are for design guidance only.
Table 33. AC Low-Power Comparator Specifications
Symbol
tRLPC
Description
LPC response time
Document Number: 38-12013 Rev. AD
Min Typ Max Unit
–
–
50
µs
Notes
50 mV overdrive comparator reference set within
VREFLPC
Page 44 of 69
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AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 34. AC Digital Block Specifications
Function
All functions
Timer
Description
Min
Typ
Max
Unit
VDD 4.75 V
–
–
50.4
MHz
VDD < 4.75 V
–
–
25.2
MHz
–
–
50.4
MHz
Input clock frequency
No capture, VDD 4.75 V
No capture, VDD < 4.75 V
–
–
25.2
MHz
With capture
–
–
25.2
MHz
50[27]
–
–
ns
No enable input, VDD 4.75 V
–
–
50.4
MHz
No enable input, VDD < 4.75 V
–
–
25.2
MHz
With enable input
–
–
25.2
MHz
50[27]
–
–
ns
20
Capture pulse width
Counter
Input clock frequency
Enable input pulse width
Dead Band
Notes
Block input clock frequency
Kill pulse width
Asynchronous restart mode
–
–
ns
Synchronous restart mode
50
[27]
–
–
ns
Disable mode
50[27]
–
–
ns
VDD 4.75 V
–
–
50.4
MHz
VDD < 4.75 V
–
–
25.2
MHz
VDD 4.75 V
–
–
50.4
MHz
VDD < 4.75 V
–
–
25.2
MHz
Input clock frequency
CRCPRS
(PRS Mode)
Input clock frequency
CRCPRS
(CRC Mode)
Input clock frequency
–
–
25.2
MHz
SPIM
Input clock frequency
–
–
8.2
MHz
The SPI serial clock (SCLK) frequency is equal to the
input clock frequency divided by 2
SPIS
Input clock (SCLK) frequency
–
–
4.1
MHz
The input clock is the SPI SCLK in SPIS mode
Width of SS_negated between
transmissions
50[27]
–
–
ns
Transmitter
Receiver
Input clock frequency
VDD 4.75 V, 2 stop bits
–
–
50.4
MHz
VDD 4.75 V, 1 stop bit
–
–
25.2
MHz
VDD < 4.75 V
–
–
25.2
MHz
VDD 4.75 V, 2 stop bits
–
–
50.4
MHz
VDD 4.75 V, 1 stop bit
–
–
25.2
MHz
VDD < 4.75 V
–
–
25.2
MHz
Input clock frequency
The baud rate is equal to the input clock frequency
divided by 8
The baud rate is equal to the input clock frequency
divided by 8
Note
27. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 38-12013 Rev. AD
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AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 35. 5-V AC Analog Output Buffer Specifications
Symbol
tROB
tSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising settling time to 0.1%, 1 V Step, 100 pF load
Power = Low
Power = High
Falling settling time to 0.1%, 1 V step, 100 pF load
Power = Low
Power = High
Rising slew rate (20% to 80%), 1 V step, 100 pF load
Power = Low
Power = High
Falling slew rate (80% to 20%), 1 V step, 100 pF load
Power = Low
Power = High
Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load
Power = Low
Power = High
Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load
Power = Low
Power = High
Min
Typ
Max
Unit
–
–
–
–
4
4
µs
µs
–
–
–
–
3.4
3.4
µs
µs
0.5
0.5
–
–
–
–
V/µs
V/µs
0.55
0.55
–
–
–
–
V/µs
V/µs
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Min
Typ
Max
Unit
–
–
–
–
4.7
4.7
µs
µs
–
–
–
–
4
4
µs
µs
0.36
0.36
–
–
–
–
V/µs
V/µs
0.40
0.40
–
–
–
–
V/µs
V/µs
0.7
0.7
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Table 36. 3.3-V AC Analog Output Buffer Specifications
Symbol
tROB
tSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising settling time to 0.1%, 1 V Step, 100 pF load
Power = Low
Power = High
Falling settling time to 0.1%, 1 V Step, 100 pF load
Power = Low
Power = High
Rising slew rate (20% to 80%), 1 V Step, 100 pF load
Power = Low
Power = High
Falling slew rate (80% to 20%), 1 V Step, 100 pF load
Power = Low
Power = High
Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load
Power = Low
Power = High
Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load
Power = Low
Power = High
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 37. 5-V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Unit
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High period
20.6
–
5300
ns
–
Low period
20.6
–
–
ns
–
Power-up IMO to switch
150
–
–
µs
Document Number: 38-12013 Rev. AD
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Table 38. 3.3-V AC External Clock Specifications
Symbol
Min
Typ
Max
Unit
Frequency with CPU clock divide by 1
0.093
–
12.3
MHz
FOSCEXT
Frequency with CPU clock divide by 2 or greater
0.186
–
24.6
MHz
–
High period with CPU clock divide by 1
41.7
–
5300
ns
–
Low period with CPU clock divide by 1
41.7
–
–
ns
–
Power-up IMO to switch
150
–
–
µs
FOSCEXT
Description
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 39. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Unit
1
–
20
ns
–
Fall time of SCLK
1
–
20
ns
–
Data setup time to falling edge of SCLK
40
–
–
ns
–
tHSCLK
Data hold time from falling edge of SCLK
40
–
–
ns
–
FSCLK
Frequency of SCLK
0
–
8
MHz
–
tERASEB
Flash erase time (block)
–
10
–
ms
–
tWRITE
Flash block write time
–
40
–
ms
–
tDSCLK
Data out delay from falling edge of SCLK
–
–
45
ns
VDD 3.6
tDSCLK3
Data out delay from falling edge of SCLK
–
–
50
ns
3.0 VDD 3.6
tERASEALL
Flash erase time (Bulk)
–
80
–
ms
Erase all blocks and
protection fields at once
tPROGRAM_HOT
Flash block erase + Flash block write time
–
–
100[28]
ms
0 °C Tj 100 °C
tPROGRAM_COLD
Flash block erase + Flash block write time
–
–
200[28]
ms
–40 °C Tj 0 °C
tRSCLK
Rise time of SCLK
tFSCLK
tSSCLK
Notes
Note
28. For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs application note Design Aids – Reading and Writing PSoC® Flash – AN2015 for more information.
Document Number: 38-12013 Rev. AD
Page 47 of 69
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AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 40. AC Characteristics of the I2C SDA and SCL Pins
Symbol
Standard Mode
Description
Fast Mode
Unit
Min
Max
Min
Max
0
100
0
400
kHz
FSCLI2C
SCL clock frequency
THDSTAI2C
Hold time (repeated) START condition. After this period, the first clock
pulse is generated.
4.0
–
0.6
–
µs
TLOWI2C
LOW period of the SCL clock
4.7
–
1.3
–
µs
THIGHI2C
HIGH period of the SCL clock
4.0
–
0.6
–
µs
TSUSTAI2C
Setup time for a repeated START condition
4.7
–
0.6
–
µs
THDDATI2C
Data hold time
0
–
0
–
µs
TSUDATI2C
Data setup time
250
–
100[29]
–
ns
TSUSTOI2C
Setup time for STOP condition
4.0
–
0.6
–
µs
TBUFI2C
Bus free time between a STOP and START condition
4.7
–
1.3
–
µs
TSPI2C
Pulse width of spikes are suppressed by the input filter.
–
–
0
50
ns
Figure 19. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
TSUDATI2C
THDSTAI2C
TSPI2C
THDDATI2CTSUSTAI2C
TBUFI2C
I2C_SCL
THIGHI2C TLOWI2C
S
START Condition
TSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
Note
29. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT >= 250 ns must then be met. This is the automatic case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released.
Document Number: 38-12013 Rev. AD
Page 48 of 69
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Packaging Information
This section illustrates the packaging specifications for the CY8C29x66 PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Packaging Dimensions
Figure 20. 28-pin PDIP (300 Mils) Package Outline, 51-85014
51-85014 *G
Document Number: 38-12013 Rev. AD
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Figure 21. 28-pin SSOP (210 Mils) Package Outline, 51-85079
51-85079 *F
Figure 22. 28-pin SOIC (0.713 × 0.300 × 0.0932 Inches) Package Outline, 51-85026
51-85026 *H
Document Number: 38-12013 Rev. AD
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Figure 23. 44-pin TQFP (10 × 10 × 1.4 mm) Package Outline, 51-85064
51-85064 *G
Figure 24. 48-pin SSOP (300 Mils) Package Outline, 51-85061
51-85061 *F
Document Number: 38-12013 Rev. AD
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Figure 25. 48-pin QFN (7 × 7 × 1.0 mm) 5.1 × 5.1 E-Pad (Sawn) Package Outline, 001-13191
001-13191 *H
Figure 26. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline, 51-85048
51-85048 *K
Important Note For information on the preferred dimensions for mounting the QFN packages, see the application note Design
Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices – AN72845 available at http://www.cypress.com.
Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device.
Document Number: 38-12013 Rev. AD
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Thermal Impedances
Capacitance on Crystal Pins
Table 41. Thermal Impedances per Package
Package
Typical
Table 42. Typical Package Capacitance on Crystal Pins
JA[30]
Package
Package Capacitance
28-pin PDIP
69 °C/W
28-pin PDIP
3.5 pF
28-pin SSOP
94 °C/W
28-pin SSOP
2.8 pF
28-pin SOIC
67 °C/W
28-pin SOIC
2.7 pF
44-pin TQFP
60 °C/W
44-pin TQFP
2.6 pF
48-pin SSOP
69 °C/W
48-pin SSOP
3.3 pF
48-pin QFN[31]
28 °C/W
48-pin QFN
1.8 pF
100-pin TQFP
50 °C/W
100-pin TQFP
3.1 pF
Solder Reflow Specifications
Table 43 shows the solder reflow temperature limits that must not be exceeded.
Table 43. Solder Reflow Specifications
Package
Maximum Peak Temperature
(TC)
Maximum Time above
TC – 5 °C
28-pin PDIP
260 °C
30 seconds
28-pin SSOP
260 °C
30 seconds
28-pin SOIC
260 °C
30 seconds
44-pin TQFP
260 °C
30 seconds
48-pin SSOP
260 °C
30 seconds
48-pin QFN
260 °C
30 seconds
100-pin TQFP
260 °C
30 seconds
Notes
30. TJ = TA + POWER × JA.
31. To achieve the thermal impedance specified for the QFN package, refer to the application note Design Guidelines for Cypress Quad Flat No Extended Lead
(QFN) Packaged Devices – AN72845 available at http://www.cypress.com.
Document Number: 38-12013 Rev. AD
Page 53 of 69
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Development Tool Selection
This section presents the development tools available for all
current PSoC device families including the CY8C29x66 family.
Software
PSoC Designer
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is available free of charge at http://www.cypress.com
and includes a free C compiler.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free of charge at http://www.cypress.com.
Development Kits
All development kits can be purchased from the Cypress Online
Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the content of specific memory locations. Advance
emulation features also supported through PSoC Designer. The
kit includes:
Evaluation Tools
All evaluation tools can be purchased from the Cypress online
store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg programming unit
■
MiniEval socket programming and evaluation board
■
28-pin CY8C27443-24PXI PDIP PSoC device sample
■
PSoC Designer software CD
■
Getting Started guide
■
USB 2.0 cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
■
Evaluation board with LCD module
■
MiniProg programming unit
■
PSoC Designer software CD
■
Getting Started guide
■
USB 2.0 cable
■
PSoC Designer software CD
■
ICE-Cube In-Circuit Emulator
■
ICE Flex-Pod for CY8C29x66 family
■
Cat-5 adapter
■
Mini-Eval programming board
■
110 ~ 240 V power supply, Euro-Plug adapter
The CY3214-PSoCEvalUSB evaluation kit features a
development board for the CY8C24794-24LFXI PSoC device.
Special features of the board include both USB and capacitive
sensing development and debugging support. This evaluation
board also includes an LCD module, potentiometer, LEDs, an
enunciator and plenty of bread boarding space to meet all of your
evaluation needs. The kit includes:
■
iMAGEcraft C compiler
■
PSoCEvalUSB board
■
ISSP cable
■
LCD module
■
USB 2.0 cable and Blue Cat-5 cable
■
MIniProg programming unit
■
Mini USB cable
■
PSoC Designer and example projects CD
■
Getting Started guide
■
Wire pack
Document Number: 38-12013 Rev. AD
CY3214-PSoCEvalUSB
Page 54 of 69
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Device Programmers
CY3207ISSP In-System Serial Programmer (ISSP)
All device programmers can be purchased from the Cypress
Online Store.
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
CY3216 Modular Programmer
Note CY3207ISSP needs special software and is not compatible
with PSoC Programmer. The kit includes:
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
Modular programmer base
■
Three programming module cards
■
MiniProg programming unit
■
PSoC Designer software CD
■
Getting Started guide
■
USB 2.0 cable
■
CY3207 programmer unit
■
PSoC ISSP software CD
■
110 ~ 240 V power supply, Euro-Plug adapter
■
USB 2.0 cable
Accessories (Emulation and Programming)
Table 44. Emulation and Programming Accessories
Part #
Pin
Package
Flex-Pod Kit[32]
Foot Kit[33]
CY8C29466-24PVXI
28-pin SSOP
CY3250-29XXX
CY3250-28SSOP-FK
CY8C29466-24SXI
28-pin SOIC
CY3250-29XXX
CY3250-28SOIC-FK
CY8C29566-24AXI
44-pin TQFP
CY3250-29XXX
CY3250-44TQFP-FK
CY8C29666-24PVXI
48-pin SSOP
CY3250-29XXX
CY3250-48SSOP-FK
CY8C29666-24LTXI
48-pin QFN
CY3250-29XXXQFN
CY8C29866-24AXI
100-pin TQFP CY3250-29XXX
Adapter[34]
Adapters can be found at
http://www.emulation.com.
CY3250-48QFN-FK
CY3250-100TQFP-FK
Notes
32. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
33. Foot kit includes surface mount feet that can be soldered to the target PCB.
34. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com
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CY8C29666/CY8C29866
Ordering Information
Flash
(KB)
RAM
(KB)
Switch Mode
Pump
Temperature
Range
Digital PSoC
Blocks
Analog PSoC
Blocks
Digital I/O
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
CY8C29466-24PVXIT
32
2
Yes
–40 °C to +85 °C
16
12
24
12
4
Yes
CY8C29466-24SXI
32
2
Yes
–40 °C to +85 °C
16
12
24
12
4
Yes
CY8C29466-24SXIT
32
2
Yes
–40 °C to +85 °C
16
12
24
12
4
Yes
CY8C29566-24AXI
32
2
Yes
–40 °C to +85 °C
16
12
40
12
4
Yes
CY8C29566-24AXIT
32
2
Yes
–40 °C to +85 °C
16
12
40
12
4
Yes
CY8C29666-24PVXI
32
2
Yes
–40 °C to +85 °C
16
12
44
12
4
Yes
CY8C29666-24PVXIT
32
2
Yes
–40 °C to +85 °C
16
12
44
12
4
Yes
CY8C29000-24AXI
32
2
Yes
–40 °C to +85 °C
16
12
64
12
4
Yes
CY8C29666-24LTXI
32
2
Yes
–40 °C to +85 °C
16
12
44
12
4
Yes
CY8C29666-24LTXIT
32
2
Yes
–40 °C to +85 °C
16
12
44
12
4
Yes
Package
Ordering
Code
The following table lists the CY8C29x66 PSoC device’s key package features and ordering codes.
28-pin (210-mil) SSOP
(Tape and Reel)
28-pin (300-mil) SOIC
28-pin (300-mil) SOIC
(Tape and Reel)
44-pin TQFP
44-pin TQFP
(Tape and Reel)
48-pin (300-mil) SSOP
48-pin (300-mil) SSOP
(Tape and Reel)
100-Pin OCD TQFP[35]
48-Pin (7 × 7 × 1.0 mm)
QFN (Sawn)
48-Pin (7 × 7 × 1.0 mm)
QFN (Sawn)
Note For Die sales information, contact a local Cypress sales office or field applications engineer (FAE).
Ordering Code Definitions
CY 8 C 29 xxx-SPxx
Package Type:Thermal Rating:
PX = PDIP Pb-freeC = Commercial
SX = SOIC Pb-freeI = Industrial
PVX = SSOP Pb-freeE = Extended
LFX/LKX/LTX/LQX/LCX = QFN Pb-free
AX = TQFP Pb-free
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Note
35. This part may be used for in-circuit debugging. It is NOT available for production.
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Acronyms
Table 45 lists the acronyms that are used in this document.
Table 45. Acronyms Used in this Datasheet
Acronym
AC
Description
Acronym
Description
alternating current
MIPS
ADC
analog-to-digital converter
OCD
on-chip debug
API
application programming interface
PCB
printed circuit board
complementary metal oxide semiconductor
PDIP
plastic dual-in-line package
CPU
central processing unit
PGA
programmable gain amplifier
CRC
cyclic redundancy check
PLL
phase-locked loop
continuous time
POR
power on reset
CMOS
CT
DAC
DC
digital-to-analog converter
direct current
PPOR
PRS
million instructions per second
precision power on reset
pseudo-random sequence
DTMF
dual-tone multi-frequency
PSoC®
ECO
external crystal oscillator
PWM
pulse width modulator
electrically erasable programmable read-only
memory
QFN
quad flat no leads
EEPROM
GPIO
ICE
Programmable System-on-Chip
general purpose I/O
RTC
real time clock
in-circuit emulator
SAR
successive approximation
IDE
integrated development environment
SC
switched capacitor
ILO
internal low speed oscillator
SMP
switch mode pump
IMO
internal main oscillator
SOIC
small-outline integrated circuit
I/O
input/output
SPI
serial peripheral interface
IrDA
infrared data association
SRAM
static random access memory
ISSP
in-system serial programming
SROM
supervisory read only memory
LCD
liquid crystal display
SSOP
shrink small-outline package
LED
light-emitting diode
TQFP
thin quad flat pack
LPC
low power comparator
UART
universal asynchronous reciever / transmitter
LVD
low voltage detect
USB
universal serial bus
MAC
multiply-accumulate
WDT
watchdog timer
MCU
microcontroller unit
XRES
external reset
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,
CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Design Aids – Reading and Writing PSoC® Flash - AN2015 (001-40459)
Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices – AN72845 available at
http://www.cypress.com.
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Document Conventions
Units of Measure
Table 46 lists the unit sof measures.
Table 46. Units of Measure
Symbol
dB
°C
fF
pF
kHz
MHz
rt-Hz
k
µA
mA
nA
pA
µs
Unit of Measure
decibels
degree Celsius
femto farad
picofarad
kilohertz
megahertz
root hertz
kilohm
ohm
microampere
milliampere
nanoampere
pikoampere
microsecond
Symbol
ms
ns
ps
µV
mV
mVpp
nV
V
µW
W
mm
ppm
%
Unit of Measure
millisecond
nanosecond
picosecond
microvolts
millivolts
millivolts peak-to-peak
nanovolts
volts
microwatts
watt
millimeter
parts per million
percent
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimals.
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that
create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
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Glossary (continued)
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less
sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift
check (CRC)
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)
converter performs the reverse operation.
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Glossary (continued)
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
External Reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
Flash
An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
OFF.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash
space that may be protected. A Flash block holds 64 bytes.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated
Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in
the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building
control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high
with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage
detect (LVD)
A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold.
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the Flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
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Glossary (continued)
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port
A group of pins, usually eight.
Power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of
hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
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Glossary (continued)
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
slave device
A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM
An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,
operating from Flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD
A name for a power net meaning “voltage drain.” The most positive power supply signal. Usually 5 V or 3.3 V.
VSS
A name for a power net meaning “voltage source.” The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
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Errata
This section describes the errata for the PSoC Programmable System-on-Chip, CY8C29xxx family of devices. Details include errata
trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales
Representative if you have questions.
Part Numbers Affected
Part Number
CY8C29xxx
Ordering Information
CY8C29466-24PVXI
CY8C29466-24PVXIT
CY8C29466-24SXI
CY8C29466-24SXIT
CY8C29566-24AXI
CY8C29566-24AXIT
CY8C29666-24PVXI
CY8C29666-24PVXIT
CY8C29666-24LFXI
CY8C29866-24AXI
CY8C29000-24AXI
Qualification Status
Product Status: In Production
Errata Summary
The following table defines the errata applicability to available CY8C29xxx family devices.
Items
Part Number Silicon Revision
Fix Status
[1]. Invalid Flash reads may occur if VDD is pulled to –0.5 V just CY8C29xxx
before power-on
A
No silicon fix is planned.
Workaround is required.
[2]. Internal main oscillator (IMO) tolerance deviation at
temperature extremes
A
No silicon fix planned.
Workaround is required.
CY8C29xxx
1. Invalid Flash reads may occur if VDD is pulled to –0.5 V just before power-on
■
Problem Definition
When VDD of the device is pulled below ground just before power-on; the first read from each 8 K Flash bank may be corrupted.
This issue does not affect Flash bank 0 because it is the selected bank upon reset.
■
Parameters Affected
When VDD is pulled below ground prior to power-on, an internal Flash reference may deviate from its nominal voltage. The
reference deviation tends to result in the first Flash read from that bank returning 0xFF. During the first read from each bank, the
reference is reset resulting in all future reads returning the correct value. A short delay of 5 µs before the first real read provides
time for the reference voltage to stabilize. When VDD of the device is pulled below ground just before power-on; the first read from
each 8K Flash bank may be corrupted apart from Flash bank 0. This can be solved by doing a dummy read from each Flash bank
prior to use of the Flash banks.
■
Workaround
To prevent an invalid Flash read, a dummy read from each Flash bank must occur prior to use of the Flash banks. A delay of 5 µs
must occur after the dummy read and before a real read. The dummy reads should occur as soon as possible and must be located
in Flash bank 0 prior to a read from any other Flash bank. An example for reading a byte of memory from each Flash bank is listed
below and should be placed in boot.tpl and boot.asm immediately after the ‘start:’ label.
// dummy read from each 8 K Flash bank
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// bank 1
mov A, 0x20
// MSB
mov X, 0x00
// LSB
romx
// bank 2
mov A, 0x40
// MSB
mov X, 0x00
// LSB
romx
// bank 3
mov A, 0x60
// MSB
mov X, 0x00
// LSB
romx
// wait at least 5 µs
mov X, 14
loop1:
dec X
jnz loop1
2. Internal main oscillator (IMO) tolerance deviation at temperature extremes
■
Problem Definition
Asynchronous digital communications interfaces may fail framing beyond 0 to 70 °C. This problem does not affect end-product
usage between 0 and 70 °C.
■
Parameters Affected
The IMO frequency tolerance. The worst case deviation when operated below 0 °C and above +70 °C and within the upper and
lower datasheet temperature range is ±5%.
■
Trigger Condition(S)
The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the data sheet limit of ±2.5% when operated
beyond the temperature range of 0 to +70 °C.
■
Scope of Impact
This problem may affect UART, IrDA, and FSK implementations.
■
Workaround
Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface.
■
Fix Status
Silicon fix is not planned. The workaround mentioned above should be used.
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Document History Page
Document Title: CY8C29466/CY8C29566/CY8C29666/CY8C29866, PSoC® Programmable System-on-Chip™
Document Number: 38-12013
Revision
ECN
Submission
Date
Description of Change
**
131151
11/13/2003
New document (Revision **).
*A
132848
01/21/2004
New information. First edition of preliminary datasheet.
*B
133205
01/27/2004
Changed part numbers, increased SRAM data storage to 2 K bytes.
*C
133656
02/09/2004
Changed part numbers and removed a 28-pin SOIC.
*D
227240
*E
240108
See ECN
Added a 28-lead (300 mil) SOIC part.
*F
247492
See ECN
New information added to the Electrical Specifications chapter.
*G
288849
See ECN
Add DS standards, update device table, fine-tune pinouts, add Reflow Peak Temp. table.
Finalize.
*H
722736
See ECN
Add QFN package clarifications. Add new QFN diagram. Add Low Power Comparator
(LPC) AC/DC electrical spec. tables. Add CY8C20x34 to PSoC Device Characteristics
table. Update emulation pod/feet kit part numbers. Add OCD non-production pinouts and
package diagrams. Add ISSP note to pinout tables. Update package diagram revisions.
Update typical and recommended Storage Temperature per industrial specs. Update CY
branding and QFN convention. Add new Dev. Tool section. Update copyright and trademarks.
*I
2503350
See ECN
Pinout for CY8C29000 OCD wrongly included details of CY8C24X94. The correct pinout
for CY8C29000 is included in this version. Added note on digital signaling in “DC Analog
Reference Specifications” section.
Added note to Ordering Information
Changes to Overview section, 48-pin MLF pinout, and significant changes to the
Electrical Specs.
06/01/2004
*J
2545030
07/29/08
*K
2708295
04/22/2009
Changed title from “CY8C29466, CY8C29566, CY8C29666, and CY8C29866 PSoC
Mixed Signal Array Final datasheet” to “CY8C29466, CY8C29566, CY8C29666, and
CY8C29866 PSoC® Programmable System-on-Chip™”
Updated to datasheet template
Added 48-Pin QFN (Sawn) package diagram and CY8C29666-24LTXI and
CY8C29666-24LTXIT part details in the Ordering Information table
Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as follows:
Modified FIMO6 (page 27), TWRITE specifications (page 34)
Added IOH (page 21), IOL (page 21), DCILO (page 28), F32K_U (page 27), TPOWERUP (page
28), TERASEALL (page 34), TPROGRAM_HOT (page 34), and TPROGRAM_COLD (page 34)
specifications
*L
2761941
09/10/2009
Added SRPOWER_UP parameter in AC specs table..
*M
2842762
01/08/2010
Corrected Notes for VDD parameter in Table 13, “DC Chip-Level Specifications,” on
page 22.
Added “Contents” on page 3.
Updated links in Sales, Solutions, and Legal Information.
*N
2902396
03/30/2010
Updated and content in Digital System
Updated Cypress website links.
Removed reference to PSoC Designer 4.4 in PSoC Designer Software Subsystems
Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings
Updated AC Chip-Level Specifications
Changed unit for SPIS function to ns in AC Digital Block Specifications
Updated notes in Packaging Information and package diagrams.
Updated Solder Reflow Specifications
Updated Emulation and Programming Accessories
Removed Third Party Tools and Build a PSoC Emulator into Your Board.
Updated Ordering Information and Ordering Code Definitions.
Document Number: 38-12013 Rev. AD
Page 65 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Document History Page (continued)
Document Title: CY8C29466/CY8C29566/CY8C29666/CY8C29866, PSoC® Programmable System-on-Chip™
Document Number: 38-12013
Revision
ECN
Submission
Date
*O
2940410
05/31/2010
Updated content to match current style guide and datasheet template.
No technical updates.
*P
3044869
10/01/2010
Added PSoC Device Characteristics table .
Added DC I2C Specifications table.
Added F32K_U max limit.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated Analog reference tables.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
No specific changes were made to AC Digital Block Specifications table and I2C Timing
Diagram. They were updated for clearer understanding.
Updated Figure 13 since the labelling for y-axis was incorrect.
Template and styles update.
Removed footnote reference for “Solder Reflow Peak Temperature” table.
*Q
3017427
11/08/10
Removed the pruned part “CY8C29666-24LFXI” from the Ordering Information and
Accessories (Emulation and Programming).
*R
3263978
05/23/11
Updated Logic Block Diagram.
Updated Solder Reflow Specifications.
*S
3301676
07/04/11
Fixed page numbering error on footer.
*T
3358177
09/26/11
Updated max value for ‘0b011’ under Table 22 on page 33.
Updated VREFHI values for ‘0b100’ under Table 21 on page 29.
Incorrect flash/SRAM size mentioned under section PSoC Core on page 4.
Changed paragraph “Memory uses 16 KB of flash for program storage, 256 bytes of
SRAM for data storage, and up to 2 KB of EEPROM emulated using the flash. Program
flash uses four protection levels on blocks of 64 bytes, allowing customized software
information protection (IP)” to “Memory uses 16 KB of flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the flash.
Program flash uses four protection levels on blocks of 64 bytes, allowing customized
software information protection (IP)”.
Removed package diagram spec 001-12919 as there is no MPN mapped to this
package.
The text “Pin must be left floating” is included under Description of NC pin in Table 6 on
page 14.
*U
3598291
04/24/2012
Changed the PWM description string from “8- to 32-bit” to “8- and 16-bit”.
Updated package diagrams 001-13191 and 51-85048.
*V
3991993
05/08/2013
Updated Packaging Information:
spec 51-85014 – Changed revision from *F to *G.
spec 51-85061 – Changed revision from *E to *F.
spec 001-13191 – Changed revision from *F to *G.
Updated Reference Documents (Removed 001-17397 spec, 001-14503 spec related
information).
Added Errata.
Document Number: 38-12013 Rev. AD
Description of Change
Page 66 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Document History Page (continued)
Document Title: CY8C29466/CY8C29566/CY8C29666/CY8C29866, PSoC® Programmable System-on-Chip™
Document Number: 38-12013
Revision
ECN
Submission
Date
*W
4081641
07/31/2013
Description of Change
Added Errata footnotes (Note 1, 2, 14, 21, 25).
Updated Features:
Replaced “+2.5%” with “+5%”.
Added Note 1 and referred the same note in +5% under “Precision, programmable
clocking”.
Updated PSoC Functional Overview:
Updated PSoC Core:
Replaced “2.5%” with “5%” in 4th paragraph.
Added Note 2 and referred the same note in 5%.
Updated Electrical Specifications:
Updated DC Electrical Characteristics:
Updated DC Chip-Level Specifications:
Added Note 14 and referred the same note in VDD parameter.
Updated AC Electrical Characteristics:
Updated AC Chip-Level Specifications:
Added Note 21 and referred the same note in FIMO24 parameter in Table 29.
Replaced all instances of “24.6” with “25.2” in Table 29.
Replaced all instances of “23.4” with “22.8” in Table 29.
Replaced all instances of “49.2” with “50.4” in Table 29.
Replaced “12.3” with “12.6” for maximum value of FCPU2 parameter in Table 29.
Replaced “46.8” with “45.6” for minimum value of Fout48M parameter in Table 29.
Added Note 25 and referred the same note in TPOWERUP parameter in Table 29.
Updated AC Digital Block Specifications:
Replaced all instances of “49.2” with “50.4” in Table 34.
Replaced all instances of “24.6” with “25.2” in Table 34.
Updated Packaging Information:
spec 51-85026 – Changed revision from *F to *G.
spec 51-85048 – Changed revision from *G to *H.
Updated Errata.
Updated in new template.
*X
4378144
05/13/2014
Updated Electrical Specifications:
Updated AC Electrical Characteristics:
Updated AC External Clock Specifications:
Updated Table 37:
Changed unit from “ms” to “µs” corresponding to “Power-up IMO to switch”.
Updated Packaging Information:
spec 51-85026 – Changed revision from *G to *H.
spec 51-85064 – Changed revision from *E to *F.
spec 51-85048 – Changed revision from *H to *I.
Completing Sunset Review.
Document Number: 38-12013 Rev. AD
Page 67 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Document History Page (continued)
Document Title: CY8C29466/CY8C29566/CY8C29666/CY8C29866, PSoC® Programmable System-on-Chip™
Document Number: 38-12013
Revision
ECN
Submission
Date
Description of Change
*Y
4461247
07/30/2014
Replaced references of “Application Notes for Surface Mount Assembly of Amkor’s
MicroLeadFrame (MLF) Packages” with “Design Guidelines for Cypress Quad Flat No
Extended Lead (QFN) Packaged Devices – AN72845” in all instances across the
document.
Added More Information.
Added PSoC Designer.
Removed “Getting Started”.
Updated Electrical Specifications:
Updated DC Electrical Characteristics:
Updated DC I2C Specifications:
Updated Table 28:
Replaced VOHI2C with VOLI2C.
*Z
4479512
09/03/2014
Updated Electrical Specifications:
Updated DC Electrical Characteristics:
Added DC Analog External Reference Specifications.
Updated AC Electrical Characteristics:
Updated AC Operational Amplifier Specifications:
Updated description.
Updated Figure 18.
Updated Errata:
Updated Errata Summary:
Updated details in “Fix Status” column in the table.
Updated details in “Fix Status” bulleted point below the table.
AA
4622517
01/13/2015
Updated Pinouts:
Updated 100-Pin Part Pinout:
Updated Table 6:
Added Note 10 and referred the same note in description of pin 15, pin 34, pin 65, pin
84 and pin 85.
Updated 100-Pin Part Pinout (On-Chip Debug):
Updated Table 7:
Added Note 12 and referred the same note in description of pin 15, pin 34, pin 65, pin
84 and pin 85.
Updated Packaging Information:
spec 51-85079 – Changed revision from *E to *F.
AB
AC
AD
4882080
5702069
6882394
08/12/2015
04/19/2017
5/15/2020
Document Number: 38-12013 Rev. AD
Replaced “Flash pages” with “Flash banks” in all instances across the document.
Updated Packaging Information:
spec 001-13191 – Changed revision from *G to *H.
Updated Cypress logo.
Updated Copyright.
Updated the following Packaging Information:
Figure 23 (spec 51-85064 *F to *G)
Figure 26 (spec 51-85048 *I to *J)
Removed the MPN CY8C29466-24PXI, as this Part number is in EOL-Obsolete status
in Oracle PLM.
Updated Packaging Information:
spec 51-85048– Changed revision from *J to *K.
Page 68 of 69
CY8C29466/CY8C29566
CY8C29666/CY8C29866
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
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Interface
cypress.com/arm
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cyprmmess.com/clocks
cypress.com/interface
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Memory
cypress.com/iot
cypress.com/memory
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cypress.com/mcu
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cypress.com/psoc
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
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Community | Code Examples | Projects | Video | Blogs |
Training | Components
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cypress.com/support
cypress.com/pmic
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cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2003-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or
firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves
all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If
the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
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solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)
to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility
of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device" means any
device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices.
"Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect
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as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims,
costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical
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Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-12013 Rev. AD
Revised May 29, 2020
Page 69 of 69
PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
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