Please note that Cypress is an Infineon Technologies Company.
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to offer the product to new and existing customers as part of the Infineon product
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The fact that Infineon offers the following product as part of the Infineon product
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when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
PSoC 6 MCU: CY8C62x5 Datasheet
PSoC 62 MCU
General Description
PSoC® 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT applications. Based on the
PSoC 6 MCU platform, this product line is a combination of a dual CPU microcontroller with low-power flash technology, digital
programmable logic, high-performance analog-to-digital conversion and standard communication and timing peripherals.
Features
32-bit Dual CPU Subsystem
Quad-SPI (QSPI)/Serial Memory Interface (SMIF)
®
■ 150-MHz Arm
(CM4) CPU with single-cycle
multiply, floating point, and memory protection unit (MPU)
■
■
100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply
and MPU
■
■
User-selectable core logic operation at either 1.1 V or 0.9 V
Cortex®-M4F
Active CPU current slope with 1.1-V core operation
❐ Cortex-M4: 40 µA/MHz
❐ Cortex-M0+: 20 µA/MHz
■ Active CPU current slope with 0.9-V core operation
❐ Cortex-M4: 22 µA/MHz
❐ Cortex-M0+: 15 µA/MHz
■ Three DMA controllers
■
■
■
Segment LCD Drive
■
■
512-KB application flash, 32-KB auxiliary flash (AUXflash), and
32-KB supervisory flash (SFlash); read-while-write (RWW)
support. Two 8-KB flash caches, one for each CPU.
■
256-KB SRAM with programmable power control and retention
granularity
■
One-time-programmable (OTP) 1-Kb eFuse array
Low-Power 1.7-V to 3.6-V Operation
■
Six power modes for fine-grained power management
■
Deep Sleep mode current of 7 µA with 64-KB SRAM retention
■
On-chip DC-DC buck converter, 2.7 V
Ports 0, 1
8 MHz
DRIVE_SEL 2
DRIVE_SEL 3
Port 2
50 MHz
DRIVE_SEL 1
DRIVE_SEL 2
Ports 3 to 10
16 MHz; 25 MHz for SPI
DRIVE_SEL 2
DRIVE_SEL 3
Ports 11 to 12
80 MHz for SMIF (QSPI).
DRIVE_SEL 1
DRIVE_SEL 2
Ports 9 and 10
Slow slew rate setting for TQFP
Packages for ADC performance
No restrictions
No restrictions
Document Number: 002-26168 Rev. *M
Page 17 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Special-Function Peripherals
IDAC
CapSense Subsystem
The CSD block has two programmable current sources, which
offer the following features:
CapSense is supported in PSoC 6 MCU through a CapSense
sigma-delta (CSD) hardware block. It is designed for
high-sensitivity self-capacitance and mutual-capacitance
measurements, and is specifically built for user interface
solutions.
In addition to CapSense, the CSD hardware block supports three
general-purpose functions. These are available when CapSense
is not being used. Alternatively, two or more functions can be
time-multiplexed in an application under firmware control. The
four functions supported by the CSD hardware block are:
■
7-bit resolution
■
Sink and source current modes
■
A current source programmable from 37.5 nA to 609 A
■
Two IDACs that can be used in parallel to form one 8-bit IDAC
Comparator
■
CapSense
■
10-bit ADC
The CapSense subsystem comparator operates in the system
Low Power and Ultra-Low Power modes. The inverting input is
connected to an internal programmable reference voltage and
the non-inverting input can be connected to any GPIO via the
AMUXBUS.
■
Programmable current sources (IDAC)
CapSense Hardware Subsystem
■
Comparator
Figure 7 shows the high-level hardware overview of the
CapSense subsystem, which includes a delta sigma converter,
internal clock dividers, a shield driver, and two programmable
current sources.
CapSense
Capacitive touch sensors are designed for user interfaces that
rely on human body capacitance to detect the presence of a
finger on or near a sensor. Cypress CapSense solutions bring
elegant, reliable, and simple capacitive touch sensing functions
to applications including IoT, industrial, automotive, and home
appliances.
The Cypress-proprietary CapSense technology offers the
following features:
■
Best-in-class signal-to-noise ratio (SNR) and robust sensing
under harsh and noisy conditions
■
Self-capacitance (CSD) and mutual-capacitance (CSX)
sensing methods
■
Support for various widgets, including buttons, matrix buttons,
sliders, touchpads, and proximity sensors
■
High-performance sensing across a variety of materials
■
Best-in-class liquid tolerance
■
SmartSense™ auto-tuning technology that helps avoid
complex manual tuning processes
■
Superior immunity against external noise
■
Spread-spectrum clocks for low radiated emissions
■
Gesture and built-in self-test libraries
■
Ultra-low power consumption
■
An integrated graphical CapSense tuner for real-time tuning,
testing, and debugging
ADC
The CapSense subsystem slope ADC offers the following
features:
■
Selectable 8- or 10-bit resolution
■
Selectable input range: GND to VREF and GND to VDDA on any
GPIO input
■
Measurement of VDDA against an internal reference without the
use of GPIO or external components
Document Number: 002-26168 Rev. *M
The inputs are managed through analog multiplexed buses
(AMUXBUS A/B). The input and output of all functions offered by
the CSD block can be provided on any GPIO or on a group of
GPIOs under software control, with the exception of the
comparator output and external capacitors that use dedicated
GPIOs.
Self-capacitance is supported by the CSD block using
AMUXBUS A, an external modulator capacitor, and a GPIO for
each sensor. There is a shield electrode (optional) for
self-capacitance sensing. This is supported using AMUXBUS B
and an optional external shield tank capacitor (to increase the
drive capability of the shield driver) should this be required.
Mutual-capacitance is supported by the CSD block using
AMUXBUS A, two external integrated capacitors, and a GPIO for
transmit and receive electrodes.
The ADC does not require an external component. Any GPIO
that can be connected to AMUXBUS A can be an input to the
ADC under software control. The ADC can accept VDDA as an
input without needing GPIOs (for applications such as battery
voltage measurement).
The two programmable current sources (IDACs) in
general-purpose mode can be connected to AMUXBUS A or B.
They can therefore connect to any GPIO pin. The comparator
resides in the delta-sigma converter. The comparator inverting
input can be connected to the reference. Both comparator inputs
can be connected to any GPIO using AMUXBUS B; see
Figure 6. The reference has a direct connection to a dedicated
GPIO; see Table 9.
The CSD block can operate in active and sleep CPU power
modes, and seamlessly transition between system LP and ULP
modes. It can be powered down in system Deep Sleep and
Hibernate modes. Upon wakeup from Hibernate mode, the CSD
block requires re-initialization. However, operation can be
resumed without re-initialization upon exit from Deep Sleep
mode, under firmware control.
Page 18 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Figure 7. CapSense Hardware Subsystem
GPIO Pin
CSD Sensor 1
CS1
I/O Configured for CSD Mode
GPIO Pin
CSD Sensor 2
CS2
AMUXBUS
A
B
GPIO
Cell
Clock Input
GPIO
Cell
CSD Hardware Block
CMOD Pin
CMOD
CSH_TANK
(optional)
Sense clock
Clock
Generator
GPIO Pin
Modulator
Clock
Shield Drive
Circuit
GPIO Pin
CSHIELD
GPIO
Cell
Compensation
IDAC
Shield Electrode
Modulator
IDAC
I/O Configured for CSX Mode
GPIO Pin
Tx
CSX Sensor 3
CS3
Rx
GPIO Pin
CINTA Pin
CINTA
CINTB
CINTB Pin
IDAC control
GPIO
Cell
GPIO
Cell
Sigma Delta
Converter
Raw
Count
V REF
GPIO
Cell
GPIO
Cell
I/O for General
Purpose Mode
ADC Input
IDAC Outputs
Comp Input
Document Number: 002-26168 Rev. *M
Page 19 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
CapSense and ADC middleware use the CSD interrupt to
implement non-blocking sensing and A-to-D conversion.
Therefore, interrupt service routines are a defined part of the
middleware, which must be initialized by the application.
Middleware and drivers can operate on either CPU. Cypress
recommends using the middleware only in one CPU. If both
CPUs must access the CSD driver, memory access should be
managed in the application.
Figure 18 shows the high-level software overview. Cypress
provides middleware libraries for CapSense, ADC, and IDAC on
GitHub to enable quick integration. The Board Support Package
for any kit with CapSense capabilities automatically includes the
CapSense library in any application that uses the BSP.
User applications interact only with middleware to implement
functions of the CSD block. The middleware interacts with
underlying drivers to access hardware as necessary. The CSD
driver facilitates time-multiplexing of the CSD hardware if more
than one piece of CSD-related middleware is present in a project.
It prevents access conflicts in this case.
Refer to AN85951: PSoC 4 and PSoC 6 MCU CapSense Design
Guide for more details on CSX sensing, CSD sensing, shield
electrode usage and its benefits, and capacitive system design
guidelines.
ModusToolbox Software provides a CapSense configurator to
enable fast library configuration. It also provides a tuner for
performance evaluation and real-time tuning of the system. The
tuner requires an EZI2C communication interface in the
application to enable real-time tuning capability. The tuner can
update configuration parameters directly in the device as well as
in the configurator.
Refer to the API reference guides for CapSense, ADC, and IDAC
available on GitHub.
Figure 8. CapSense Software/Firmware Subsystem
Application Program
Software
Middleware
Comp
IDAC
ADC
CapSense
Configuration
Tuner
SCB Driver
(EZI2C)
CSD Driver
GPIO / Clock
Drivers
SCB
CSD Block
GPIOs / Clock
Hardware and Drivers
Document Number: 002-26168 Rev. *M
Page 20 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Pinouts
Note: The CY8C62x5 datasheet web page contains a spreadsheet with a consolidated list of pinouts and pin alternate functions with
HSIOM mapping.
GPIO ports are powered by VDDx pins as follows:
■
P0: VBACKUP
■
P2, P3: VDDIO2
■
P5, P6, P7, P8: VDDIO1
■
P9, P10: VDDIOA, VDDA (VDDIOA, when present, and VDDA must be connected together on the PCB)
■
P11, P12: VDDIO0
■
P14: VDDUSB
Table 7. Packages and Pin Information
Pin
Packages
100-TQFP
68-QFN
49-WLCSP
VDDD
2
68
C11
VCCD
1, 100
67
A11
VDDA
73
48
B2
VDDIOA
53
36
–
VDDIO0
91, 92
64
A9
VDDIO1
51
35
G1
VDDIO2
31
22
J7
VBACKUP
6
1
–
VDDUSB
20
11
–
VSS
3, 4, 5, 13, 15, 18, 19,
33, 38, 49, 50, 54, 71,
72, 93, 94
GND PAD
B6, H6
VDD_NS
16
9
F10
VIND1
17
10
G11
XRES
14
8
E11
VREF
74
49
C3
P0.0
7
2
E9
P0.1
8
3
D10
P0.2
9
4
–
P0.3
10
5
–
P0.4
11
6
–
P0.5
12
7
–
P2.0
23
14
H10
P2.1
24
15
F8
P2.2
25
16
H8
P2.3
26
17
G9
P2.4
27
18
J11
P2.5
28
19
J9
P2.6
29
20
–
P2.7
30
21
–
P3.0
34
23
–
Document Number: 002-26168 Rev. *M
Page 21 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 7. Packages and Pin Information (continued)
Pin
Packages
100-TQFP
68-QFN
49-WLCSP
P3.1
35
24
–
P5.0
36
25
J5
P5.1
37
26
G7
P5.6
39
27
–
P5.7
40
28
–
P6.0
41
–
–
P6.1
42
–
–
P6.2
43
29
J3
P6.3
44
30
H4
P6.4
45
31
G5
P6.5
46
32
J1
P6.6
47
33
H2
P6.7
48
34
G3
P7.0
55
37
F6
P7.1
56
38
F4
P7.2
57
39
F2
P7.3
58
40
E3
P7.4
59
–
E1
P7.5
60
–
–
P7.6
61
–
–
P7.7
62
41
–
P8.0
63
42
–
P8.1
64
43
–
P8.2
65
–
–
P8.3
66
–
–
P9.0
67
44
D2
P9.1
68
45
E5
P9.2
69
46
E7
P9.3
70
47
C1
P10.0
75
50
D4
P10.1
76
51
A5
P10.2
77
52
B4
P10.3
78
53
A3
P10.4
79
54
C5
P10.5
80
55
D6
P10.6
81
–
–
P10.7
82
–
–
P11.0
83
56
–
P11.1
84
57
–
P11.2
85
58
C7
P11.3
86
59
A7
P11.4
87
60
D8
Document Number: 002-26168 Rev. *M
Page 22 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 7. Packages and Pin Information (continued)
Pin
Packages
100-TQFP
68-QFN
49-WLCSP
P11.5
88
61
B8
P11.6
89
62
C9
P11.7
90
63
B10
P12.0
95
–
–
P12.1
96
–
–
P12.6
98
65
–
P12.7
99
66
–
P14.0 / USBDP
22
13
–
P14.1 / USBDM
21
12
–
NC
97
–
–
Document Number: 002-26168 Rev. *M
P11.0
P10.7
P10.6
P10.5
P10.4
P10.3
P10.2
P10.1
VSS
VDDIO0
VDDIO0
P11.7
P11.6
P11.5
P11.4
P11.3
P11.2
P11.1
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
TQFP
P10.0
VREF
VDDA
VSS
VSS
P9.3
P9.2
P9.1
P9.0
P8.3
P8.2
P8.1
P8.0
P7.7
P7.6
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0
VSS
VDDIOA
VDDIO1
VDDIO1
VSS
VSS
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDUSB
P14.1 / USBDM
P14.0 / USBDP
P2.0
P2.1
P2.2
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P5.0
P5.1
VSS
P5.6
P5.7
P6.0
VSS
VSS
75
74
26
27
28
29
30
31
32
33
34
35
VBACKUP
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
VSS
XRES
VSS
VDD_NS
VIND1
P2.4
P2.5
P2.6
P2.7
VDDIO2
VDDIO2
VSS
P3.0
P3.1
VSS
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P2.3
VCCD
VDDD
VSS
100
99
VCCD
P12.7
P12.6
NC
P12.1
P12.0
VSS
Figure 9. Device Pinout for 100-TQFP Package
Page 23 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
55
54
53
52
P11.5
P11.4
P11.3
P11.2
P11.1
P11.0
P10.5
P10.4
P10.3
P10.2
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
QFN
28
29
30
31
32
33
34
P5.7
P6.2
P6.3
P6.4
P6.5
P6.6
P10.1
P10.0
VREF
VDDA
P9.3
P9.2
P9.1
P9.0
P8.1
P8.0
P7.7
P7.3
P7.2
P7.1
P7.0
VDDIOA
VDDIO1
P6.7
18
19
20
21
22
23
24
25
26
27
(TOP VIEW)
P2.5
P2.6
P2.7
VDDIO2
P3.0
P3.1
P5.0
P5.1
P5.6
P0.2
P0.3
P0.4
P0.5
XRES
VDD_NS
VIND1
VDDUSB
P14.1 / USBDM
P14.0 / USBDP
P2.0
P2.1
P2.2
P2.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
P2.4
VBACKUP
P0.0
P0.1
66
65
64
63
62
61
60
59
58
57
56
68
67
VDDD
VCCD
P12.7
P12.6
VDDIO0
P11.7
P11.6
Figure 10. Device Pinout for 68-QFN Package[1]
Note: If the USB pins are not used, connect VDDUSB to ground and leave the P14.0/USBDP and P14.1/USBDM pins unconnected.
Note
1. The center pad on the QFN package should be connected to PCB ground relative to device VDDx for best mechanical, thermal, and electrical performance. For more
information, see AN72845, Design Guidelines for QFN Devices.
Document Number: 002-26168 Rev. *M
Page 24 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Each port pin has multiple alternate functions. These are defined in Table 8. The columns ACT #x and DS #y denote active (System LP/ULP) and Deep Sleep mode signals
respectively.
The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there is more than one signal for
a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the
fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize use of on-chip resources.
Table 8. Multiple Alternate Functions
Port/Pin ACT #0
ACT #1
ACT #2
ACT #3
P0.0
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[0]:0 .line[0]:0
tx:0
tx_n:0
P0.1
DS #2
DS #3
ACT #4
ACT #5
ACT #6
ACT #7
ACT #8
ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15
scb[0].spi
_select1:
0
peri.tr_io
_input[0]
:0
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:1
tx_n:1
compl[0]: compl[0]:
0
0
scb[0].spi
_select2:
0
peri.tr_io
_input[1]
:0
P0.2
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[1]:0 .line[1]:0
tx:2
tx_n:2
scb[0].ua scb[0].i2 scb[0].spi
rt_rx:0
c_scl:0 _mosi:0
P0.3
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:3
tx_n:3
compl[1]: compl[1]:
0
0
scb[0].ua scb[0].i2 scb[0].spi
rt_tx:0
c_sda:0 _miso:0
P0.4
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[2]:0 .line[2]:0
tx:4
tx_n:4
scb[0].ua
rt_rts:0
scb[0].spi
_clk:0
peri.tr_io peri.tr_io
_input[2] _output[
:0
0]:2
P0.5
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:5
tx_n:5
compl[2]: compl[2]:
0
0
scb[0].ua
rt_cts:0
scb[0].spi
_select0:
0
peri.tr_io peri.tr_io
_input[3] _output[
:0
1]:2
P2.0
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[3]:0 .line[3]:0
tx:6
tx_n:6
scb[1].ua scb[1].i2 scb[1].spi
rt_rx:0
c_scl:0 _mosi:0
peri.tr_io
_input[4]
:0
sdhc[0].c
ard_dat_
3to0[0]
P2.1
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:7
tx_n:7
compl[3]: compl[3]:
0
0
scb[1].ua scb[1].i2 scb[1].spi
rt_tx:0
c_sda:0 _miso:0
peri.tr_io
_input[5]
:0
sdhc[0].c
ard_dat_
3to0[1]
P2.2
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[0]:1 .line[4]:0
tx:8
tx_n:8
scb[1].ua
rt_rts:0
scb[1].spi
_clk:0
sdhc[0].c
ard_dat_
3to0[2]
P2.3
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:9
tx_n:9
compl[0]: compl[4]:
1
0
scb[1].ua
rt_cts:0
scb[1].spi
_select0:
0
sdhc[0].c
ard_dat_
3to0[3]
P2.4
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[1]:1 .line[5]:0
tx:10
tx_n:10
scb[1].spi
_select1:
0
sdhc[0].c
ard_cmd
Document Number: 002-26168 Rev. *M
srss.ext_
clk:0
srss.ext_
clk:1
DS #5
DS #6
DS #7
cpuss.s
wj_trstn
Page 25 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 8. Multiple Alternate Functions (continued)
Port/Pin ACT #0
ACT #1
ACT #2
ACT #3
DS #2
DS #3
ACT #4
ACT #5
ACT #6
ACT #7
ACT #8
P2.5
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:11
tx_n:11
compl[1]: compl[5]:
1
0
scb[1].spi
_select2:
0
P2.6
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[2]:1 .line[6]:0
tx:12
tx_n:12
scb[1].spi
_select3:
0
P2.7
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:13
tx_n:13
compl[2]: compl[6]:
1
0
P3.0
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[3]:1 .line[7]:0
tx:14
tx_n:14
P3.1
ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15
DS #5
DS #6
DS #7
sdhc[0].c
lk_card
peri.tr_io
_input[8]
:0
sdhc[0].c
ard_detect_n
peri.tr_io
_input[9]
:0
sdhc[0].c
ard_mec
h_write_
prot
scb[2].ua scb[2].i2 scb[2].spi
rt_rx:1
c_scl:1 _mosi:1
peri.tr_io
_input[6]
:0
sdhc[0].i
o_volt_s
el
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:15
tx_n:15
compl[3]: compl[7]:
1
0
scb[2].ua scb[2].i2 scb[2].spi
rt_tx:1
c_sda:1 _miso:1
peri.tr_io
_input[7]
:0
sdhc[0].c
ard_if_pwr_en
P5.0
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[0]:2 .line[0]:1
tx:16
tx_n:16
scb[5].ua scb[5].i2 scb[5].spi
rt_rx:1
c_scl:1 _mosi:1
canfd[0]. peri.tr_io
ttcan_rx[ _input[1
0]
0]:0
P5.1
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:17
tx_n:17
compl[0]: compl[0]:
2
1
scb[5].ua scb[5].i2 scb[5].spi
rt_tx:1
c_sda:1 _miso:1
canfd[0]. peri.tr_io
ttcan_tx[ _input[11
0]
]:0
P5.6
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[1]:2 .line[1]:1
tx:18
tx_n:18
P5.7
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:19
tx_n:19
compl[1]: compl[1]:
2
1
P6.0
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[2]:2 .line[2]:1
tx:20
tx_n:20
scb[3].ua scb[3].i2 scb[3].spi
rt_rx:0
c_scl:0 _mosi:0
cpuss.fa
ult_out[0
]
P6.1
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:21
tx_n:21
compl[2]: compl[2]:
2
1
scb[3].ua scb[3].i2 scb[3].spi
rt_tx:0
c_sda:0 _miso:0
cpuss.fa
ult_out[1
]
P6.2
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[3]:2 .line[3]:1
tx:22
tx_n:22
scb[3].ua
rt_rts:0
scb[3].spi
_clk:0
P6.3
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:23
tx_n:23
compl[3]: compl[3]:
2
1
scb[3].ua
rt_cts:0
scb[3].spi
_select0:
0
P6.4
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_ scb[6].i2
.line[0]:3 .line[4]:1
tx:24
tx_n:24 c_scl:0
peri.tr_io peri.tr_io
_input[1 _output[
2]:0
0]:1
cpuss.s scb[6].sp srss.ddft
wj_swo_ i_mosi:0 _pin_in[0
tdo
]:0
P6.5
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_ scb[6].i2
.line_.line_tx:25
tx_n:25 c_sda:0
compl[0]: compl[4]:
3
1
peri.tr_io peri.tr_io
_input[1 _output[
3]:0
1]:1
cpuss.s scb[6].sp srss.ddft
wj_swdo i_miso:0 _pin_in[1
e_tdi
]:0
Document Number: 002-26168 Rev. *M
Page 26 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 8. Multiple Alternate Functions (continued)
Port/Pin ACT #0
ACT #1
ACT #2
ACT #3
DS #2
DS #3
ACT #4
ACT #5
ACT #6
ACT #7
ACT #8
ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15
DS #5
DS #6
P6.6
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[1]:3 .line[5]:1
tx:26
tx_n:26
cpuss.s scb[6].sp
wj_swdio i_clk:0
_tms
P6.7
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:27
tx_n:27
compl[1]: compl[5]:
3
1
cpuss.s scb[6].sp
wj_swclk i_select0
_tclk
:0
P7.0
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[2]:3 .line[6]:1
tx:28
tx_n:28
scb[4].ua scb[4].i2 scb[4].spi
rt_rx:1
c_scl:1 _mosi:1
peri.tr_io
_input[1
4]:0
P7.1
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:29
tx_n:29
compl[2]: compl[6]:
3
1
scb[4].ua scb[4].i2 scb[4].spi
rt_tx:1
c_sda:1 _miso:1
peri.tr_io
_input[1
5]:0
P7.2
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[3]:3 .line[7]:1
tx:30
tx_n:30
scb[4].ua
rt_rts:1
scb[4].spi
_clk:1
P7.3
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:31
tx_n:31
compl[3]: compl[7]:
3
1
scb[4].ua
rt_cts:1
scb[4].spi
_select0:
1
P7.4
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[0]:4 .line[0]:2
tx:32
tx_n:32
scb[4].spi
_select1:
1
cpuss.tra
ce_data[
3]:2
P7.5
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:33
tx_n:33
compl[0]: compl[0]:
4
2
scb[4].spi
_select2:
1
cpuss.tra
ce_data[
2]:2
P7.6
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[1]:4 .line[1]:2
tx:34
tx_n:34
scb[4].spi
_select3:
1
cpuss.tra
ce_data[
1]:2
P7.7
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:35
tx_n:35
compl[1]: compl[1]:
4
2
P8.0
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[2]:4 .line[2]:2
tx:36
tx_n:36
scb[4].ua scb[4].i2 scb[4].spi
rt_rx:0
c_scl:0 _mosi:0
peri.tr_io
_input[1
6]:0
P8.1
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:37
tx_n:37
compl[2]: compl[2]:
4
2
scb[4].ua scb[4].i2 scb[4].spi
rt_tx:0
c_sda:0 _miso:0
peri.tr_io
_input[1
7]:0
P8.2
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[3]:4 .line[3]:2
tx:38
tx_n:38
lpcomp.d
si_comp
0:0
scb[4].ua
rt_rts:0
scb[4].spi
_clk:0
P8.3
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:39
tx_n:39
compl[3]: compl[3]:
4
2
lpcomp.d
si_comp
1:0
scb[4].ua
rt_cts:0
scb[4].spi
_select0:
0
P9.0
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[0]:5 .line[4]:2
tx:40
tx_n:40
Document Number: 002-26168 Rev. *M
cpuss.cl
k_fm_pu
mp
scb[2].ua scb[2].i2 scb[2].spi
rt_rx:0
c_scl:0 _mosi:0
DS #7
cpuss.tra
ce_clock
cpuss.tra
ce_data[
0]:2
peri.tr_io
_input[1
8]:0
cpuss.tra
ce_data[
3]:0
Page 27 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 8. Multiple Alternate Functions (continued)
Port/Pin ACT #0
ACT #1
ACT #2
ACT #3
DS #2
DS #3
ACT #4
ACT #5
ACT #6
ACT #7
ACT #8
ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15
P9.1
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:41
tx_n:41
compl[0]: compl[4]:
5
2
scb[2].ua scb[2].i2 scb[2].spi
rt_tx:0
c_sda:0 _miso:0
P9.2
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[1]:5 .line[5]:2
tx:42
tx_n:42
scb[2].ua
rt_rts:0
scb[2].spi
_clk:0
cpuss.tra
ce_data[
1]:0
P9.3
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:43
tx_n:43
compl[1]: compl[5]:
5
2
scb[2].ua
rt_cts:0
scb[2].spi
_select0:
0
cpuss.tra
ce_data[
0]:0
P10.0
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[2]:5 .line[6]:2
tx:44
tx_n:44
scb[1].ua scb[1].i2 scb[1].spi
rt_rx:1
c_scl:1 _mosi:1
peri.tr_io
_input[2
0]:0
cpuss.tra
ce_data[
3]:1
P10.1
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:45
tx_n:45
compl[2]: compl[6]:
5
2
scb[1].ua scb[1].i2 scb[1].spi
rt_tx:1
c_sda:1 _miso:1
peri.tr_io
_input[2
1]:0
cpuss.tra
ce_data[
2]:1
P10.2
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[3]:5 .line[7]:2
tx:46
tx_n:46
scb[1].ua
rt_rts:1
scb[1].spi
_clk:1
cpuss.tra
ce_data[
1]:1
P10.3
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:47
tx_n:47
compl[3]: compl[7]:
5
2
scb[1].ua
rt_cts:1
scb[1].spi
_select0:
1
cpuss.tra
ce_data[
0]:1
P10.4
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[0]:6 .line[0]:3
tx:48
tx_n:48
scb[1].spi
_select1:
1
P10.5
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:49
tx_n:49
compl[0]: compl[0]:
6
3
scb[1].spi
_select2:
1
P10.6
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[1]:6 .line[1]:3
tx:50
tx_n:50
scb[1].spi
_select3:
1
P10.7
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:51
tx_n:51
compl[1]: compl[1]:
6
3
P11.0
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[2]:6 .line[2]:3
tx:52
tx_n:52
smif.spi_ scb[5].ua scb[5].i2 scb[5].spi
select2
rt_rx:0
c_scl:0 _mosi:0
peri.tr_io
_input[2
2]:0
P11.1
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:53
tx_n:53
compl[2]: compl[2]:
6
3
smif.spi_ scb[5].ua scb[5].i2 scb[5].spi
select1
rt_tx:0
c_sda:0 _miso:0
peri.tr_io
_input[2
3]:0
P11.2
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[3]:6 .line[3]:3
tx:54
tx_n:54
smif.spi_ scb[5].ua
select0
rt_rts:0
Document Number: 002-26168 Rev. *M
peri.tr_io
_input[1
9]:0
cpuss.tra
ce_data[
2]:0
DS #5
DS #6
DS #7
srss.ddft
_pin_in[0
]:1
srss.ddft
_pin_in[1
]:1
scb[5].spi
_clk:0
Page 28 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 8. Multiple Alternate Functions (continued)
Port/Pin ACT #0
ACT #1
ACT #2
ACT #3
DS #2
DS #3
ACT #4
ACT #5
ACT #6
ACT #7
ACT #8
ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15
P11.3
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:55
tx_n:55
compl[3]: compl[3]:
6
3
smif.spi_ scb[5].ua
data3
rt_cts:0
scb[5].spi
_select0:
0
peri.tr_io
_output[
0]:0
P11.4
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[0]:7 .line[4]:3
tx:56
tx_n:56
smif.spi_
data2
scb[5].spi
_select1:
0
peri.tr_io
_output[
1]:0
P11.5
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:57
tx_n:57
compl[0]: compl[4]:
7
3
smif.spi_
data1
scb[5].spi
_select2:
0
P11.6
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[1]:7 .line[5]:3
tx:58
tx_n:58
smif.spi_
data0
scb[5].spi
_select3:
0
P11.7
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:59
tx_n:59
compl[1]: compl[5]:
7
3
smif.spi_
clk
P12.0
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_ scb[6].i2
.line[2]:7 .line[6]:3
tx:60
tx_n:60 c_scl:1
peri.tr_io
_input[2
4]:0
P12.1
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_ scb[6].i2
.line_.line_tx:61
tx_n:61 c_sda:1
compl[2]: compl[6]:
7
3
peri.tr_io
_input[2
5]:0
P12.6
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line[3]:7 .line[7]:3
tx:62
tx_n:62
P12.7
tcpwm[0] tcpwm[1] csd.csd_ csd.csd_
.line_.line_tx:63
tx_n:63
compl[3]: compl[7]:
7
3
Document Number: 002-26168 Rev. *M
DS #5
DS #6
DS #7
Page 29 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Analog and Smart I/O alternate port pin functionality is provided in Table 9.
Table 9. Port Pin Analog, and Smart I/O Functions
Name
P0.0
Analog
wco_in
P0.1
wco_out
Digital HV
AMUXA
AMUXB
SMARTIO
amuxbus_a_csd0
amuxbus_b_csd0
amuxbus_a_csd0
amuxbus_b_csd0
amuxbus_a_csd0
amuxbus_b_csd0
amuxbus_a_csd0
amuxbus_b_csd0
amuxbus_a_csd0
amuxbus_b_csd0
amuxbus_a_csd0
amuxbus_b_csd0
amuxbus_a_csd0
amuxbus_b_csd0
amuxbus_a_csd0
amuxbus_b_csd0
P8.0
amuxbus_a_csd0
amuxbus_b_csd0
smartio[8].io[0]
P8.1
amuxbus_a_csd0
amuxbus_b_csd0
smartio[8].io[1]
P8.2
amuxbus_a_csd0
amuxbus_b_csd0
smartio[8].io[2]
P8.3
amuxbus_a_csd0
amuxbus_b_csd0
smartio[8].io[3]
P9.0
amuxbus_a_sar
amuxbus_b_sar
smartio[9].io[0]
P9.1
amuxbus_a_sar
amuxbus_b_sar
smartio[9].io[1]
amuxbus_a_sar
amuxbus_b_sar
smartio[9].io[2]
amuxbus_a_sar
amuxbus_b_sar
smartio[9].io[3]
P0.2
P0.3
P0.4
pmic_wakeup_in
hibernate_wakeup[1]
pmic_wakeup_out
P0.5
P5.6
lpcomp.inp_comp0
P5.7
lpcomp.inn_comp0
P6.2
lpcomp.inp_comp1
P6.3
lpcomp.inn_comp1
P6.6
swd_data
P6.7
swd_clk
P7.0
P7.1
P7.2
P7.3
csd.cmodpadd
csd.cmodpads
csd.csh_tankpadd
csd.csh_tankpads
csd.vref_ext
P7.4
hibernate_wakeup[0]
P7.5
P7.6
P7.7
csd.cshieldpads
P9.2
P9.3
aref_ext_vref
P10.0
sarmux_pads[0]
P10.1
sarmux_pads[1]
P10.2
sarmux_pads[2]
P10.3
sarmux_pads[3]
P10.4
sarmux_pads[4]
P10.5
sarmux_pads[5]
P10.6
sarmux_pads[6]
P10.7
sarmux_pads[7]
P12.6
eco_in
P12.7
eco_out
Document Number: 002-26168 Rev. *M
Page 30 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Power Supply Considerations
The following power system diagrams show typical connections for power pins for all supported packages, and with and without usage
of the buck regulator.
In these diagrams, the package pin is shown with the pin name, for example "VDDA, 53". For VDDx pins, the I/O port that is powered
by that pin is also shown, for example "VBACKUP, 6; I/O port P0".
Figure 11. 100-TQFP Power Connection Diagram
1.7 to 3.6 V
CY8C62x5, 100-TQFP package
1 KΩ at
100 MHz
10 µF
0.1 µF
1 µF
0.1 µF
1 µF
1 KΩ at
100 MHz
1 KΩ at
100 MHz
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
10 µF
0.1 µF
VDDD, 2
VDD_NS, 16
VBACKUP, 6; I/O port P0
0.1 µF
10 µF
VIND1, 17
2.2 µH
VDDIO0, 91, 92; I/O ports P11, P12
VCCD, 1, 100
VDDIO1, 51, 52; I/O ports P5, P6, P7, P8
4.7 µF
VDDIO2, 31, 32; I/O ports P2, P3
VDDUSB, 20; I/O port P14
VDDA, 73
VDDIOA, 53; I/O ports P9, P10
3, 4, 5, 13, 15, 18, 19, 33, 49, 50, 54, 71, 72, 93, 94
VSS
Document Number: 002-26168 Rev. *M
Page 31 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Figure 12. 100-TQFP (No Buck) Power Connection Diagram
1.7 to 3.6 V
CY8C62x5, 100-TQFP package
1 KΩ at
100 MHz
1 KΩ at
100 MHz
10 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
10 µF
0.1 µF
VDDD, 2
VDD_NS, 16
VBACKUP, 6; I/O port P0
VIND1, 17
VDDIO0, 91, 92; I/O ports P11, P12
VCCD, 1, 100
VDDIO1, 51, 52; I/O ports P5, P6, P7, P8
4.7 µF
VDDIO2, 31, 32; I/O ports P2, P3
VDDUSB, 20; I/O port P14
VDDA, 73
VDDIOA, 53; I/O ports P9, P10
3, 4, 5, 13, 15, 18, 19, 33, 49, 50, 54, 71, 72, 93, 94
VSS
Document Number: 002-26168 Rev. *M
Page 32 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
In the QFN package, all internal grounds are routed to the metal pad (epad) in the package. This pad must be grounded on the PCB.
Figure 13. 68-QFN Power Connection Diagram
1.7 to 3.6 V
CY8C62x5, 68-QFN package
1 KΩ at
100 MHz
1 KΩ at
100 MHz
10 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
10 µF
0.1 µF
1 KΩ at
100 MHz
VDDD, 68
VDD_NS, 9
VBACKUP, 1; I/O port P0
0.1 µF
10 µF
VIND1, 10
2.2 µH
VDDIO0, 64; I/O ports P11, P12
VCCD, 67
4.7 µF
VDDIO1, 35; I/O ports P5, P6, P7, P8
VDDIO2, 22; I/O ports P2, P3
VDDUSB, 11; I/O port P14
VDDA, 48
VDDIOA, 36; I/O ports P9, P10
GND PAD
Figure 14. 68-QFN (No Buck) Power Connection Diagram
1.7 to 3.6 V
CY8C62x5, 68-QFN package
1 KΩ at
100 MHz
1 KΩ at
100 MHz
10 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
10 µF
0.1 µF
VDDD, 68
VDD_NS, 9
VBACKUP, 1; I/O port P0
VIND1, 10
VDDIO0, 64; I/O ports P11, P12
VCCD, 67
VDDIO1, 35; I/O ports P5, P6, P7, P8
4.7 µF
VDDIO2, 22; I/O ports P2, P3
VDDUSB, 11; I/O port P14
VDDA, 48
VDDIOA, 36; I/O ports P9, P10
GND PAD
Document Number: 002-26168 Rev. *M
Page 33 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Figure 15. 49-WLCSP Power Connection Diagram
1.7 to 3.6 V
CY8C62x5, 49-WLCSP package
1 KΩ at
100 MHz
1 KΩ at
100 MHz
1 KΩ at
100 MHz
10 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
10 µF
0.1 µF
VDDD , C11; I/O port P0
VDD_NS, F10
VDDIO0, A9; I/O port P11
0.1 µF
10 µF
VIND1, G11
2.2 µH
VDDIO1, G1; I/O ports P5, P6, P7
V CCD, A11
4.7 µF
VDDIO2, J7; I/O port P2
VDDA, B2; I/O ports P9, P10
B6, H6
VSS
Figure 16. 49-WLCSP (No Buck) Power Connection Diagram
1.7 to 3.6 V
CY8C62x5, 49-WLCSP package
1 KΩ at
100 MHz
1 KΩ at
100 MHz
10 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
10 µF
0.1 µF
VDDD , C11; I/O port P0
VDD_NS, F10
VDDIO0, A9; I/O port P11
VIND1, G11
VDDIO1, G1; I/O ports P5, P6, P7
V CCD, A11
4.7 µF
VDDIO2, J7; I/O port P2
VDDA, B2; I/O ports P9, P10
B6, H6
VSS
Document Number: 002-26168 Rev. *M
Page 34 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
There are as many as eight VDDx supply pins, depending on the
package, and multiple VSS ground pins. The power pins are:
■
VDDD: the main digital supply. It powers the LDO and switching
regulators. It also powers I/O port 0 on packages where
VBACKUP is not available.
■
VCCD: the main LDO output. It requires a 4.7-µF capacitor for
regulation. The LDO can be turned off when VCCD is driven
from the switching regulator (see below). For more information,
see the power system block diagram in the device technical
reference manual (TRM).
■
VDDA: the supply for the analog peripherals. Voltage must be
applied to this pin for correct device initialization and boot up.
■
VDDIOA: the supply for I/O ports 9 and 10. If it is present in the
device package, it must be connected to VDDA.
■
VDDIO0: the supply for I/O ports 11 and 12.
■
VDDIO1: the supply for I/O ports 5, 6, 7, and 8. Some of the ports
are not available depending on package.
■
VDDIO2: the supply for I/O ports 2 and 3.
■
VBACKUP: the supply for the backup domain, which includes the
32-kHz WCO and the RTC. It can be a separate supply as low
as 1.4 V, for battery or supercapacitor backup, as Figure 17
shows, otherwise it is connected to VDDD. It powers I/O port 0[2].
Figure 17. Separate Battery Connection to VBACKUP
■
Voltage must be applied to the VDDD pin, and the VDDA pin as
noted above, for correct device initialization and operation. If an
I/O port is not being used, applying voltage to the corresponding
VDDx pin is optional.
■
VSS: ground pins for the above supplies. All ground pins should
be connected together to a common ground.
In addition to the LDO regulator, a switching regulator is
included. The regulator pins are:
■
VDD_NS: the regulator supply.
■
VIND1: the regulator output. It is typically used to drive VCCD
through an inductor.
The VDD power pins are not connected on chip. They can be
connected off chip, in one or more separate nets. If separate
power nets are used, they can be isolated from noise from the
other nets using optional ferrite beads, as indicated in the
diagrams.
No external load should be placed on VCCD, or VIND1, whether
or not these pins are used.
There are no power pin sequencing requirements; power
supplies may be brought up in any order. The power
management system holds the device in reset until all power pins
are at the voltage levels required for proper operation.
Note: If a battery is installed on the PCB first, VDDD must be
cycled for at least 50 µs. This prevents premature drain of the
battery during product manufacture and storage.
1.7 to 3.6 V
1.4 to 3.6 V
Note: If the USB pins are not used, connect VDDUSB to ground
and leave the P14.0/USBDP and P14.1/USBDM pins unconnected.
10 µF
0.1 µF
1 µF
0.1 µF
VDDD
VBACKUP
VDDUSB: the supply for the USB peripheral and the USBDP and
USBDM pins. It must be 2.85 V to 3.6 V for USB operation. If
USB is not used, it can be 1.7 V to 3.6 V, and the USB pins can
be used as limited-capability GPIOs on I/O port 14.
Table 10 shows a summary of the I/O port supplies:
Table 10. I/O Power Supplies
Port
Supply
Alternate Supply
0
VBACKUP
VDDD
2, 3
VDDIO2
–
5, 6, 7, 8
VDDIO1
–
9, 10
VDDIOA
VDDA
11, 12
VDDIO0
–
14
VDDUSB
–
Bypass capacitors must be connected to a common ground from
the VDDx and other pins, as indicated in the diagrams. Typical
practice for systems in this frequency range is to use a 10-µF or
1-µF capacitor in parallel with a smaller capacitor (0.1 µF, for
example). Note that these are simply rules of thumb and that, for
critical applications, the PCB layout, lead inductance, and
bypass capacitor parasitic should be simulated for optimal
bypassing.
All capacitors and inductors should be ±20% or better. The
recommended inductor value is 2.2 µH ±20% (for example, TDK
MLP2012H2R2MT0S1).
It is good practice to check the datasheets for your bypass
capacitors, specifically the working voltage and the DC bias
specifications. With some capacitors, the actual capacitance can
decrease considerably when the applied voltage is a significant
percentage of the rated working voltage.
For more information on pad layout, refer to PSoC 6 CAD
libraries.
Note
2. It is not available in the 49-WLCSP package. VDDD powers port 0.
Document Number: 002-26168 Rev. *M
Page 35 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Electrical Specifications
All specifications are valid for –40 °C ≤ TA ≤ 85 °C and for 1.71 V to 3.6 V except where noted.
Absolute Maximum Ratings
Table 11. Absolute Maximum Ratings[3]
Spec ID#
Parameter
Description
Min
Typ
Max
Units
SID1
VDD_ABS
Analog or digital supply relative to VSS
(VSSD = VSSA)
–0.5
–
4
V
SID2
VCCD_ABS
Direct digital core voltage input relative to
VSSD
–0.5
–
1.2
V
SID3
VGPIO_ABS
GPIO voltage; VDDD or VDDA
–0.5
–
VDD +
0.5
V
SID4
IGPIO_ABS
Current per GPIO
–25
–
25
mA
SID5
IGPIO_injection GPIO injection current per pin
–0.5
–
0.5
mA
SID3A
ESD_HBM
Electrostatic discharge Human Body Model
2200
–
–
V
SID4A
ESD_CDM
Electrostatic discharge Charged Device
Model
500
–
–
V
SID5A
LU
Pin current for latchup-free operation
–100
–
100
mA
Details / Conditions
Device-Level Specifications
Table 14 provides detailed specifications of CPU current. Table 12 summarizes these specifications, for rapid review of CPU currents
under common conditions. Note that the max frequency for CM4 is 150 MHz, and for CM0+ is 100 MHz. IMO and FLL are used to
generate the CPU clocks; FLL is not used when the CPU clock frequency is 8 MHz.
Table 12. CPU Current Specifications Summary
Condition
Range
Typ Range
Max Range
LP Mode, VDDD = 3.3 V, VCCD = 1.1 V, with buck regulator
CM4 active, CM0+ sleep
0.9–6.3 mA
1.5–7 mA
CM0+ active, CM4 sleep
0.8–3.8 mA
1.3–4.5 mA
0.7–1.5 mA
1.3–2.2 mA
0.7–1.3 mA
1.3–2 mA
0.6–0.7 mA
1.1–1.1 mA
CM4 sleep, CM0+ sleep
Across CPUs clock ranges: 8–150/100 MHz; Dhrystone
with flash cache enabled
CM0+ sleep, CM4 off
Minimum regulator current mode
Across CM4/CM0+ CPU active/sleep modes
ULP Mode, VDDD = 3.3 V, VCCD = 0.9 V, with buck regulator
CM4 active, CM0+ sleep
0.65–1.6 mA
0.8–2.2mA
CM0+ active, CM4 sleep
0.51–0.91 mA
0.72–1.25 mA
0.42–0.76 mA
0.65–1.1 mA
0.41–0.62 mA
0.6–0.9 mA
0.39–0.54 mA
0.6–0.76 mA
7–9 µA
-
300–800 nA
-
CM4 sleep, CM0+ sleep
Across CPUs clock ranges: 8 – 50/25 MHz; Dhrystone
with flash cache enabled
CM0+ sleep, CM4 off
Minimum regulator current mode
Across CM4/CM0+ CPU active/sleep modes
Deep Sleep
Across SRAM retention
Hibernate
Across VDDD
Note
3. Usage above the absolute maximum conditions listed in Table 11 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-26168 Rev. *M
Page 36 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Figure 18. Typical Device Currents vs. CPU Frequency; System Low Power (LP) Mode
7
CM4 Active, CM0+ Sleep 1/2 CM4
6
CM4 Active, CM0+ Sleep same as CM4
CM0+ Active, CM4 Sleep
IDDD, mA
5
4
3
2
1
0
0
25
50
75
100
125
150
CPU Clock, MHz
Power Supplies
Table 13. Power Supply DC Specifications
Min
Typ
Max
Units
SID6
Spec ID#
VDDD
Parameter
Internal regulator
Description
1.7
–
3.6
V
–
Details / Conditions
SID7
VDDA
Analog power supply voltage. Shorted to
VDDIOA on PCB.
1.7
–
3.6
V
Internally unregulated
supply
SID7A
VDDIO1
GPIO supply for Ports 5 to 8 when present
1.7
–
3.6
V
Must be ≥ VDDA if the
CapSense (CSD) block is
used in the application
SID7B
VDDIO0
GPIO supply for Ports 11 and 12
1.7
–
3.6
V
–
SID7E
VDDIO0
Supply for eFuse programming
2.38
2.5
2.62
V
–
SID7C
VDDIO2
GPIO supply for Ports 2 and 3 when present
1.7
–
3.6
V
–
SID7D
VDDIOA
GPIO supply for Ports 9 and 10 when present.
Must be connected to VDDA on PCB.
1.7
–
3.6
V
–
SID7F
VDDUSB
Supply for Port 14 (USB or GPIO) when
present
1.7
–
3.6
V
Min supply is 2.85 V for USB
SID6B
VBACKUP
Backup power and GPIO Port 0 supply when
present
1.7
–
3.6
V
Min. is 1.4 V when VDDD is
removed
SID8
VCCD1
Output voltage (for core logic bypass)
–
1.1
–
V
SID9
VCCD2
Output voltage (for core logic bypass)
SID10
CEFC
External regulator voltage (VCCD) bypass
SID11
CEXC
Power supply decoupling capacitor
Document Number: 002-26168 Rev. *M
System LP mode
ULP mode. Valid for –20 to
85 °C.
–
0.9
–
3.8
4.7
5.6
µF
X5R ceramic or better. Value
for 0.8 to 1.2 V
–
10
–
µF
X5R ceramic or better
Page 37 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
CPU Current and Transition Times
Table 14. CPU Current and Transition Times
Spec ID#
Parameter
Description
LP Range Power Specifications (for VCCD = 1.1 V with Buck and LDO)
Cortex-M4. Active Mode
Execute with Cache Disabled (Flash)
SIDF1
SIDF2
IDD1
IDD2
Execute from flash; CM4 Active 50 MHz,
CM0+ Sleep 25 MHz. With IMO and FLL.
While(1).
Execute from flash; CM4 Active 8 MHz,
CM0+ Sleep 8 MHz.With IMO. While(1).
Min
Typ
Max
Units
–
2.3
3.2
mA
–
3.1
3.6
mA
–
5.7
6.5
mA
–
0.9
1.5
mA
–
1.2
1.6
mA
–
2.8
3.5
mA
–
6.3
7
mA
–
9.7
11.2
mA
–
14.4
15.1
mA
–
4.8
5.8
mA
–
7.4
8.4
mA
–
11.3
12
mA
–
2.4
3.4
mA
–
3.7
4.1
mA
–
6.3
7.2
mA
–
0.90
1.5
mA
–
1.3
1.8
mA
–
3
3.8
mA
Details / Conditions
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
max at 85 °C.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
Execute with Cache Enabled
SIDC1
SIDC2
SIDC3
SIDC4
IDD3
IDD4
IDD5
IDD6
Execute from cache;CM4 Active 150 MHz,
CM0+ Sleep 75 MHz. IMO and PLL.
Dhrystone.
Execute from cache;CM4 Active 100 MHz,
CM0+ Sleep 100MHz. IMO and FLL.
Dhrystone.
Execute from cache;CM4 Active 50 MHz,
CM0+ Sleep 25MHz. IMO and FLL.
Dhrystone.
Execute from cache;CM4 Active 8 MHz,
CM0+ Sleep 8 MHz. IMO. Dhrystone.
Document Number: 002-26168 Rev. *M
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
max at 85 °C.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
VDDD=3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
Page 38 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID#
Parameter
Cortex-M0+. Active Mode
Execute with Cache Disabled (Flash)
SIDF3
SIDF4
IDD7
IDD8
Description
Execute from flash;CM4 OFF, CM0+ Active
50 MHz. With IMO and FLL. While (1).
Execute from flash;CM4 OFF, CM0+ Active
8 MHz. With IMO. While (1).
Min
Typ
Max
Units
–
2.4
3.3
mA
–
3.2
3.7
mA
–
5.6
6.3
mA
–
0.8
1.5
mA
–
1.1
1.6
mA
–
2.6
3.4
mA
–
3.8
4.5
mA
–
5.9
6.5
mA
–
9
9.7
mA
–
0.8
1.3
mA
–
1.2
1.7
mA
–
2.6
3.4
mA
–
1.5
2.2
mA
–
2.2
2.7
mA
–
4
4.6
mA
–
1.2
1.9
mA
–
1.7
2.2
mA
–
3.4
4.3
mA
–
0.7
1.3
mA
–
1
1.5
mA
–
2.4
3.3
mA
Details / Conditions
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
Execute with Cache Enabled
SIDC5
SIDC6
IDD9
IDD10
Execute from cache;CM4 OFF, CM0+ Active
100 MHz. With IMO and FLL. Dhrystone.
Execute from cache;CM4 OFF, CM0+ Active
8 MHz. With IMO. Dhrystone.
VDDD = 3.3V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
Cortex-M4. Sleep Mode
SIDS1
SIDS2
SIDS3
IDD11
IDD12
IDD13
CM4 Sleep 100 MHz, CM0+ Sleep 25 MHz.
With IMO and FLL.
CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz.
With IMO & FLL.
CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With
IMO.
Document Number: 002-26168 Rev. *M
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
max at 85 °C.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
Page 39 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID#
Parameter
Cortex-M0+. Sleep Mode
SIDS4
SIDS5
IDD14
IDD15
Description
CM4 Off, CM0+ Sleep 50 MHz. With IMO
and FLL.
CM4 Off, CM0+ Sleep 8 MHz. With IMO.
Min
Typ
Max
Units
–
1.3
2
mA
–
1.9
2.4
mA
–
3.8
4.6
mA
–
0.7
1.3
mA
–
1
1.5
mA
–
2.4
3.3
mA
–
0.9
1.5
mA
–
1.2
1.7
mA
–
2.8
3.5
mA
–
0.9
1.5
mA
–
1.3
1.8
mA
–
2.9
3.7
mA
–
0.8
1.4
mA
–
1.1
1.6
mA
–
2.7
3.6
mA
–
0.8
1.4
mA
–
1.2
1.7
mA
–
2.7
3.6
mA
–
0.7
1.1
mA
–
1
1.5
mA
–
2.4
3.3
mA
Details / Conditions
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
VDDD = 3.3V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
Cortex-M4. Minimum Regular Current Mode
SIDLPA1
SIDLPA2
IDD16
IDD17
Execute from flash; CM4 Active 8 MHz,
CM0+ Sleep 8 MHz. With IMO. While (1).
Execute from cache; CM4 Active 8 MHz,
CM0+ Sleep 8 MHz. With IMO. Dhrystone.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
max at 85 °C.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
Cortex-M0+. Minimum Regulator Current Mode
SIDLPA3
SIDLPA4
IDD18
IDD19
Execute from flash; CM4 OFF, CM0+ Active
8 MHz. With IMO. While (1).
Execute from cache; CM4 Off, CM0+ Active
8 MHz. With IMO. Dhrystone
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
Cortex-M4. Minimum Regulator Current Mode
SIDLPS1
IDD20
CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With
IMO.
Document Number: 002-26168 Rev. *M
VDDD=3.3 V, Buck ON, Max
at 60 °C.
VDDD=1.8 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
Max at 85 °C.
Page 40 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID#
Parameter
Description
Cortex-M0+. Minimum Regulator Current Mode
Min
Typ
Max
Units
Details / Conditions
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
–
0.9
1.5
mA
SIDLPS3
IDD22
CM4 Off, CM0+ Sleep 8 MHz. With IMO.
at 60 °C.
VDDD = 1.8 to 3.3 V, LDO,
–
2.4
3.3
mA
Max at 85 °C.
ULP RANGE POWER SPECIFICATIONS (for VCCD = 0.9 V using the Buck). ULP mode is valid from –20 to +85 °C.
Cortex-M4. Active Mode
Execute with Cache Disabled (Flash)
VDDD = 3.3 V, Buck ON, Max
–
1.7
2.2
mA
Execute from flash; CM4 Active 50 MHz,
at 60 °C.
CM0+ Sleep 25 MHz. With IMO and FLL.
SIDF5
IDD3
VDDD = 1.8 V, Buck ON, Max
While(1).
–
2.1
2.4
mA
at 60 °C.
VDDD = 3.3 V, Buck ON, Max
–
0.56
0.8
mA
at 60 °C.
Execute from flash; CM4 Active 8 MHz,
SIDF6
IDD4
CM0+ Sleep 8 MHz. With IMO. While (1).
VDDD = 1.8 V, Buck ON, Max
–
0.75
1
mA
at 60 °C.
Execute with Cache Enabled
VDDD = 3.3 V, Buck ON, Max
–
1.6
2.2
mA
Execute from cache; CM4 Active 50 MHz,
at 60 °C.
CM0+ Sleep 25 MHz. With IMO and FLL.
SIDC8
IDD10
VDDD = 1.8 V, Buck ON, Max
Dhrystone.
–
2.4
2.7
mA
at 60 °C.
VDDD = 3.3 V, Buck ON, Max
–
0.65
0.8
mA
at 60 °C.
Execute from cache; CM4 Active 8 MHz,
SIDC9
IDD11
CM0+ Sleep 8 MHz. With IMO. Dhrystone.
VDDD = 1.8 V, Buck ON, Max
–
0.8
1.1
mA
at 60 °C.
Cortex-M0+. Active Mode
Execute with Cache Disabled (Flash)
VDDD = 3.3 V, Buck ON, Max
–
1
1.4
mA
at 60 °C.
Execute from flash; CM4 OFF, CM0+ Active
SIDF7
IDD16
25 MHz. With IMO and FLL. Write(1).
VDDD = 1.8 V, Buck ON, Max
–
1.34
1.6
mA
at 60 °C.
VDDD = 3.3 V, Buck ON, Max
–
0.54
0.75
mA
at 60 °C.
Execute from flash; CM4 OFF, CM0+ Active
SIDF8
IDD17
8 MHz. With IMO. While(1).
VDDD = 1.8 V, Buck ON, Max
–
0.73
1
mA
at 60 °C.
Execute with Cache Enabled
VDDD = 3.3 V, Buck ON, Max
–
0.91
1.25
mA
at 60 °C.
Execute from cache; CM4 OFF, CM0+ Active
SIDC10
IDD18
25 MHz. With IMO and FLL. Dhrystone.
VDDD = 1.8 V, Buck ON, Max
–
1.34
1.6
mA
at 60 °C.
VDDD = 3.3 V, Buck ON, Max
–
0.51
0.72
mA
at 60 °C.
Execute from cache; CM4 OFF, CM0+ Active
SIDC11
IDD19
8 MHz. With IMO. Dhrystone.
VDDD = 1.8 V, Buck ON, Max
–
0.73
0.95
mA
at 60 °C.
Cortex-M4. Sleep Mode
VDDD = 3.3 V, Buck ON, Max
–
0.76
1.1
mA
at 60 °C.
CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz.
SIDS7
IDD21
With IMO and FLL.
VDDD = 1.8 V, Buck ON, Max
–
1.1
1.4
mA
at 60 °C.
–
Document Number: 002-26168 Rev. *M
0.6
1.1
mA
Page 41 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID#
SIDS8
Parameter
IDD22
Description
CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With
IMO.
Min
Typ
Max
Units
Details / Conditions
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
–
0.42
0.65
mA
–
0.59
0.8
mA
–
0.62
0.9
mA
–
0.88
1.1
mA
–
0.41
0.6
mA
–
0.58
0.8
mA
–
0.52
0.75
mA
–
0.76
1
mA
–
0.54
0.76
mA
–
0.78
1
mA
–
0.51
0.75
mA
–
0.75
1
mA
–
0.48
0.7
mA
–
0.7
0.95
mA
–
0.4
0.6
mA
–
0.57
0.8
mA
–
0.39
0.6
mA
–
0.56
0.8
mA
–
7
–
µA
Max value is at 85 °C
–
7
–
µA
Max value is at 60 °C.
–
9
–
µA
Max value is at 85 °C
–
9
–
µA
Max value is at 60 °C.
Cortex-M0+. Sleep Mode
SIDS9
SIDS10
IDD23
IDD24
CM4 Off, CM0+ Sleep 25 MHz. With IMO
and FLL.
CM4 Off, CM0+ Sleep 8 MHz. With IMO.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8°V, Buck ON,
Max at 60 °C.
Cortex-M4. Minimum Regulator Current Mode
SIDLPA5
SIDLPA6
IDD25
IDD26
Execute from flash. CM4 Active 8 MHz,
CM0+ Sleep 8 MHz. With IMO. While(1).
Execute from cache. CM4 Active 8 MHz,
CM0+ Sleep 8 MHz. With IMO. Dhrystone.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
Cortex-M0+. Minimum Regulator Current Mode
SIDLPA7
SIDLPA8
IDD27
IDD28
Execute from flash. CM4 OFF, CM0+ Active
8 Hz. With IMO. While (1).
Execute from cache. CM4 OFF, CM0+ Active
8 MHz. With IMO. Dhrystone.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
Cortex-M4. Minimum Regulator Current Mode
SIDLPS5
IDD29
CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With
IMO.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
Cortex-M0+. Minimum Regulator Current Mode
SIDLPS7
IDD31
CM4 Off, CM0+ Sleep 8 MHz. With IMO.
VDDD = 3.3 V, Buck ON, Max
at 60 °C.
VDDD = 1.8 V, Buck ON, Max
at 60 °C.
Deep Sleep Mode
SIDDS1
IDD33A
SIDDS1_B
IDD33A_B
SIDDS2
IDD33B
SIDDS2_B
IDD33B_B
With internal Buck enabled and 64-KB
SRAM retention
With internal Buck enabled and 64-KB
SRAM retention
With internal Buck enabled and 256-KB
SRAM retention
With internal Buck enabled and 256-KB
SRAM retention
Document Number: 002-26168 Rev. *M
Page 42 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID#
Parameter
Description
Hibernate Mode
VDDD = 1.8 V
SIDHIB1
IDD34
VDDD = 3.3 V
SIDHIB2
IDD34A
Power Mode Transition Times
Minimum regulator current to LP transition
SID12
TLPACT_ACT
time
SID13
TDS_LPACT
Deep Sleep to LP transition time
Hibernate to LP transition time
SID14
THIB_ACT
Min
Typ
Max
Units
Details / Conditions
–
–
300
800
–
–
nA
nA
No clocks running
No clocks running
–
–
35
µs
Including PLL lock time
–
–
–
2000
15
–
µs
µs
Guaranteed by design
Including PLL lock time
XRES
Table 15. XRES DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SID17
TXRES_IDD
IDD when XRES asserted
–
300
–
nA
VDDD = 1.8 V
SID17A
TXRES_IDD_1
IDD when XRES asserted
–
800
–
nA
VDDD = 3.3 V
SID77
VIH
Input voltage HIGH threshold
0.7 * VDD
–
–
V
CMOS input
SID78
VIL
Input voltage LOW threshold
–
–
0.3 * VDD
V
CMOS input
SID80
CIN
Input capacitance
–
3
–
pF
–
SID81
VHYSXRES
Input voltage hysteresis
–
100
–
mV
–
SID82
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
–
Table 16. XRES AC Specifications
Spec ID#
Parameter
Description
SID15
TXRES_ACT
POR or XRES release to Active
transition time
SID16
TXRES_PW
XRES pulse width
Min
Typ
Max
Units
–
2000
–
µs
Normal mode, 50-MHz
CM0+
Details / Conditions
5
–
–
µs
–
GPIO
Table 17. GPIO DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
0.7 * VDD
–
–
V
CMOS Input
SID57
VIH
Input voltage HIGH threshold
SID57A
IIHS
Input current when Pad > VDDIO for
OVT inputs
–
–
10
µA
Per I2C Spec
SID58
VIL
Input voltage LOW threshold
–
–
0.3 * VDD
V
CMOS Input
SID241
VIH
LVTTL input, VDD < 2.7 V
0.7 * VDD
–
–
V
–
SID242
VIL
LVTTL input, VDD < 2.7 V
–
–
0.3 * VDD
V
–
SID243
VIH
LVTTL input, VDD ≥ 2.7 V
2.0
–
–
V
–
SID244
VIL
LVTTL input, VDD ≥ 2.7 V
–
–
0.8
V
–
SID59
VOH
Output voltage HIGH level
VDD – 0.5
–
–
V
IOH = 8 mA
SID62A
VOL
Output voltage LOW level
–
–
0.4
V
IOL = 8 mA
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
–
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
–
Document Number: 002-26168 Rev. *M
Page 43 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 17. GPIO DC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SID65
IIL
Input leakage current (absolute value)
–
–
2
nA
25 °C, VDD = 3.0 V
SID66
CIN
Input capacitance
–
–
5
pF
–
SID67
VHYSTTL
Input hysteresis LVTTL VDD > 2.7 V
100
0
–
mV
–
SID68
VHYSCMOS
Input hysteresis CMOS
0.05 * VDD
–
–
mV
–
SID69
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
SID69A
ITOT_GPIO
Maximum total source or sink chip
current
–
–
200
mA
Description
Min
Typ
Max
Units
–
–
Table 18. GPIO AC Specifications
Spec ID#
Parameter
Details / Conditions
SID70
TRISEF
Rise time in Fast Strong Mode. 10% to
90% of VDD.
–
–
2.5
ns
Cload = 15 pF, 8-mA
drive strength
SID71
TFALLF
Fall time in Fast Strong Mode. 10% to
90% of VDD.
–
–
2.5
ns
Cload = 15 pF, 8-mA
drive strength
–
142
ns
TRISES_1
Rise time in Slow Strong Mode. 10% to
90% of VDD.
52
SID72
Cload = 15 pF, 8-mA
drive strength, VDD
2.7 V
–
102
ns
TRISES_2
Rise time in Slow Strong Mode. 10% to
90% of VDD.
48
SID72A
Cload = 15 pF, 8-mA
drive strength, 2.7 V <
VDD 3.6 V
SID73
TFALLS_1
Fall time in Slow Strong Mode. 10% to
90% of VDD.
44
–
211
ns
Cload = 15 pF, 8 mA drive
strength, VDD 2.7 V
–
93
ns
TFALLS_2
Fall time in Slow Strong Mode. 10% to
90% of VDD.
42
SID73A
Cload = 15 pF, 8-mA
drive strength, 2.7 V <
VDD 3.6 V
SID73G
TFALL_I2C
Fall time (30% to 70% of VDD) in Slow 20 * VDDIO /
5.5
Strong mode.
–
250
ns
Cload = 10 pF to 400 pF,
8-mA drive strength
SID74
FGPIOUT1
GPIO Fout. Fast Strong mode.
–
–
100
MHz 90/10%, 15-pF load,
–
–
1.5
MHz 90/10%, 15-pF load,
SID75
FGPIOUT2
GPIO Fout; Slow Strong mode.
SID76
FGPIOUT3
GPIO Fout; Fast Strong mode.
SID245
FGPIOUT4
GPIO Fout; Slow Strong mode.
FGPIOIN
GPIO input operating frequency;
1.71 V VDD 3.6 V
SID246
Document Number: 002-26168 Rev. *M
60/40 duty cycle
60/40 duty cycle
–
–
100
MHz 90/10%, 25-pF load,
60/40 duty cycle
–
–
1.3
MHz 90/10%, 25-pF load,
–
–
100
MHz
60/40 duty cycle
90/10% VIO
Page 44 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Analog Peripherals
Low-Power (LP) Comparator
Table 19. LP Comparator DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID84
VOFFSET1
Input offset voltage. Normal power
mode.
–10
–
10
mV
–
SID85A
VOFFSET2
Input offset voltage. Low-power mode.
–25
±12
25
mV
–
SID85B
VOFFSET3
Input offset voltage. Ultra low-power
mode.
–25
±12
25
mV
–
SID86
VHYST1
Hysteresis when enabled in Normal
mode
–
–
60
mV
–
SID86A
VHYST2
Hysteresis when enabled in Low-power
mode
–
–
80
mV
–
SID87
VICM1
Input common mode voltage in Normal
mode
0
–
VDDIO1 – 0.1
V
–
SID247
VICM2
Input common mode voltage in Low
power mode
0
–
VDDIO1 – 0.1
V
–
SID247A
VICM3
Input common mode voltage in Ultra
low power mode
0
–
VDDIO1 – 0.1
V
–
SID88
CMRR
Common mode rejection ratio in
Normal power mode
50
–
–
dB
–
SID89
ICMP1
Block current, Normal mode
–
–
150
µA
–
SID248
ICMP2
Block current, Low-power mode
–
–
10
µA
–
SID259
ICMP3
Block current in Ultra low-power mode
–
0.3
0.85
µA
–
SID90
ZCMP
DC input impedance of comparator
35
–
–
MΩ
–
Description
Min
Typ
Max
Units
Table 20. LP Comparator AC Specifications
Spec ID#
Parameter
Details/Conditions
LP Comparator AC Specifications
SID91
TRESP1
Response time, Normal mode, 100 mV
overdrive
–
–
100
ns
–
SID258
TRESP2
Response time, Low power mode, 100
mV overdrive
–
–
1000
ns
–
SID92
TRESP3
Response time, Ultra-low power mode,
100 mV overdrive
–
–
20
µs
–
SID92E
T_CMP_EN1
Time from Enabling to operation
–
–
10
µs
Normal and low-power
modes
SID92F
T_CMP_EN2
Time from Enabling to operation
–
–
50
µs
Ultra-low-power mode
Document Number: 002-26168 Rev. *M
Page 45 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Temperature Sensor
Table 21. Temperature Sensor Specifications
Spec ID
SID93
Parameter
Description
TSENSACC
Temperature sensor accuracy
Min
–5
Typ
±1
Max
5
Min
1.188
Typ
1.2
Max
1.212
Units
Details/Conditions
°C –40 to +85 °C
Internal Reference
Table 22. Internal Reference Specification
Spec ID
SID93R
Parameter
VREFBG
Description
–
Units
–
V
Details/Conditions
SAR ADC
Table 23. 12-bit SAR ADC DC Specifications
Spec ID
Parameter
SID94
A_RES
Min
Typ
Max
Units
SAR ADC Resolution
Description
–
–
12
bits
Details/Conditions
SID95
A_CHNLS_S
Number of channels - single-ended
–
–
16
8 full speed.
SID96
A-CHNKS_D
Number of channels - differential
–
–
8
Diff inputs use neighboring I/O
SID97
A-MONO
Monotonicity
–
–
-
SID98
A_GAINERR
Gain error
–
–
±0.2
%
SID99
A_OFFSET
Input offset voltage
–
–
Yes.
With external reference.
2
mV
Measured with 1-V reference
1.05
mA
At 1 Msps. External reference
mode
1.3
mA
At 1 Msps. Internal reference
mode
1.65
mA
At 2 Msps. External reference
mode
2.15
mA
At 2 Msps. Internal reference
mode
V
SID100
A_ISAR_1
Current consumption at 1 Msps
–
–
SID100A
A_ISAR_2
Current consumption at 1 Msps
–
–
SID1002
A_ISAR_3
Current consumption at 2 Msps
–
–
SID1003
A_ISAR_4
Current consumption at 2 Msps
–
–
SID101
A_VINS
Input voltage range - single-ended
VSS
–
VDDA
SID102
A_VIND
Input voltage range - differential
VSS
–
VDDA
V
SID103
A_INRES
Input resistance
–
1
–
kΩ
SID104
A_INCAP
Input capacitance
–
5
–
pF
Min
Typ
Max
Units
Table 24. 12-bit SAR ADC AC Specifications
Spec ID
Parameter
Description
Details/Conditions
SID106
A_PSRR
Power supply rejection ratio
70
–
–
dB
SID107
A_CMRR
Common mode rejection ratio
66
–
–
dB
SID1081
A_SAMP_1
Sample rate with external reference
With bypass cap
–
–
2
Msps VDDA 2.7 - 3.6
SID1082
A_SAMP_1
Sample rate with external reference
With bypass cap
–
–
1
Msps VDDA 1.7 - 3.6
SID108A1 A_SAMP_2
Sample rate with VDD reference;
No bypass cap
–
–
2
Msps VDDA 2.7 - 3.6
SID108A2 A_SAMP_2
Sample rate with VDD reference;
No bypass cap
–
–
1
Msps VDDA 1.7 - 3.6
SID108B
Sample rate with internal reference;
With bypass cap
–
–
1
Msps -
A_SAMP_3
Document Number: 002-26168 Rev. *M
Measured at 1 V
Page 46 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 24. 12-bit SAR ADC AC Specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
–
–
200
ksps
Details/Conditions
SID108C
A_SAMP_4
Sample rate with Internal Reference.
No bypass cap
SID109
A_SINAD
Signal-to-noise and distortion ratio
(SINAD).
64
–
–
dB
SID111A
A_INL
Integral non-linearity.
Up to 1 Msps
–2
–
2
LSB
All Reference Mode
SID111B
A_INL
Integral non-linearity.
2 Msps.
–2.5
–
2.5
LSB
External Reference or VDDA
Reference Mode, VREF ≥ 2 V.
VDDA = 2.7 V to 3.6 V
SID112A
A_DNL
Differential non-linearity.
Up to 1Msps
–1
–
1.5
LSB
All Reference Modes
SID112B
A_DNL
Differential non-linearity.
2Msps.
–1
–
1.6
LSB
External Reference or VDDA
Reference Mode, VREF ≥ 2V.
VDDA = 2.7 to 3.6 V
SID113
A_THD
Total harmonic distortion. 1 Msps.
–
–
–65
dB
Description
Min
Typ
Max
Units
VDD_RIPPLE
Max allowed ripple on power supply,
DC to 10 MHz
–
–
±50
mV
VDDA > 2 V (with ripple),
25 °C TA,
Sensitivity = 0.1 pF
SYS.PER#16
VDD_RIPPLE_1.8
Max allowed ripple on power supply,
DC to 10 MHz
–
–
±25
mV
VDDA > 1.75 V (with ripple),
25 ° C TA,
Parasitic Capacitance (CP) <
20 pF, Sensitivity ≥ 0.4 pF
SID.CSD.BLK
ICSD
Maximum block current
–
–
4500
µA
–
SID.CSD#15
VREF
Voltage reference for CSD and
Comparator
0.6
1.2
VDDA –
0.6
V
VDDA – VREF ≥ 0.6 V
SID.CSD#15A VREF_EXT
External Voltage reference for CSD
and Comparator
0.6
–
VDDA –
0.6
V
VDDA – VREF ≥ 0.6 V
SID.CSD#16
IDAC1IDD
IDAC1 (7-bits) block current
–
–
1900
µA
–
SID.CSD#17
IDAC2IDD
IDAC2 (7-bits) block current
–
–
1900
µA
–
SID308
VCSD
Voltage range of operation
1.7
–
3.6
V
1.71 to 3.6 V
SID308A
VCOMPIDAC
Voltage compliance range of IDAC
0.6
–
VDDA –
0.6
V
VDDA – VREF ≥ 0.6 V
SID309
IDAC1DNL
DNL
–1
–
1
LSB
–
SID310
IDAC1INL
INL
–3
–
3
LSB
If VDDA < 2 V then for LSB of
2.4 µA or less
SID311
IDAC2DNL
DNL
–1
–
1
LSB
–
SID312
IDAC2INL
INL
–3
–
3
LSB
If VDDA < 2 V then for LSB of
2.4 µA or less
–
Ratio
9.5-pF max. capacitance
Fin = 10 kHz
Fin = 10 kHz. VDDA = 2.7 to 3.6 V.
CSD
Table 25. CapSense Sigma-Delta (CSD) Specifications
Spec ID#
Parameter
Details / Conditions
CSD V2 Specifications
SYS.PER#3
SNRC of the following is Ratio of counts of finger to noise. Guaranteed by characterization.
SID313_1A
SNRC_1
SRSS reference. IMO + FLL clock
source. 0.1-pF sensitivity.
Document Number: 002-26168 Rev. *M
5
–
Page 47 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 25. CapSense Sigma-Delta (CSD) Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SID313_1B
SNRC_2
SRSS reference. IMO + FLL clock
source. 0.3-pF sensitivity.
5
–
–
Ratio
31-pF max. capacitance
SID313_1C
SNRC_3
SRSS reference. IMO + FLL clock
source. 0.6-pF sensitivity.
5
–
–
Ratio
61-pF max. capacitance
SID313_2A
SNRC_4
PASS reference. IMO + FLL clock
source. 0.1-pF sensitivity.
5
–
–
Ratio
12-pF max. capacitance
SID313_2B
SNRC_5
PASS reference. IMO + FLL clock
source. 0.3-pF sensitivity.
5
–
–
Ratio
47-pF max. capacitance
SID313_2C
SNRC_6
PASS reference. IMO + FLL clock
source. 0.6-pF sensitivity.
5
–
–
Ratio
86-pF max. capacitance
SID313_3A
SNRC_7
PASS reference. IMO + PLL clock
source. 0.1-pF sensitivity.
5
–
–
Ratio
27-pF max. capacitance
SID313_3B
SNRC_8
PASS reference. IMO + PLL clock
source. 0.3-pF sensitivity.
5
–
–
Ratio
86-pF max. capacitance
SID313_3C
SNRC_9
PASS reference. IMO + PLL clock
source. 0.6-pf sensitivity.
5
–
–
Ratio
168 pF Max. capacitance
SID314
IDAC1CRT1
Output current of IDAC1 (7 bits) in
low range
4.2
5.7
µA
LSB = 37.5-nA typ.
SID314A
IDAC1CRT2
Output current of IDAC1 (7 bits) in
medium range
33.7
45.6
µA
LSB = 300-nA typ.
SID314B
IDAC1CRT3
Output current of IDAC1 (7 bits) in
high range
270
365
µA
LSB = 2.4-µA typ.
SID314C
IDAC1CRT12
Output current of IDAC1 (7 bits) in
low range, 2X mode
8
11.4
µA
LSB = 37.5-nA typ. 2X output
stage
SID314D
IDAC1CRT22
Output current of IDAC1 (7 bits) in
medium range, 2X mode
67
91
µA
LSB = 300-nA typ. 2X output
stage
SID314E
IDAC1CRT32
Output current of IDAC1 (7 bits) in
high range, 2X mode. VDDA > 2 V
540
730
µA
LSB = 2.4-µA typ. 2X output
stage
SID315
IDAC2CRT1
Output current of IDAC2 (7 bits) in
low range
4.2
5.7
µA
LSB = 37.5-nA typ.
SID315A
IDAC2CRT2
Output current of IDAC2 (7 bits) in
medium range
33.7
45.6
µA
LSB = 300-nA typ.
SID315B
IDAC2CRT3
Output current of IDAC2 (7 bits) in
high range
270
365
µA
LSB = 2.4-µA typ.
SID315C
IDAC2CRT12
Output current of IDAC2 (7 bits) in
low range, 2X mode
8
11.4
µA
LSB = 37.5-nA typ. 2X output
stage
SID315D
IDAC2CRT22
Output current of IDAC2 (7 bits) in
medium range, 2X mode
67
91
µA
LSB = 300-nA typ. 2X output
stage
SID315E
IDAC2CRT32
Output current of IDAC2 (7 bits) in
high range, 2X mode. VDDA > 2V
540
730
µA
LSB = 2.4-µA typ. 2X output
stage
SID315F
IDAC3CRT13
Output current of IDAC in 8-bit mode
in low range
8
11.4
µA
LSB = 37.5-nA typ.
SID315G
IDAC3CRT23
Output current of IDAC in 8-bit mode
in medium range
67
91
µA
LSB = 300-nA typ.
SID315H
IDAC3CRT33
Output current of IDAC in 8-bit mode
in high range. VDDA > 2V
540
730
µA
LSB = 2.4-µA typ.
SID320
IDACOFFSET
All zeroes input
1
LSB
Document Number: 002-26168 Rev. *M
–
–
Polarity set by Source or
Sink
Page 48 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 25. CapSense Sigma-Delta (CSD) Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SID321
IDACGAIN
–
–
±15
%
LSB = 2.4-µA typ.
SID322
Mismatch between IDAC1 and
IDACMISMATCH1
IDAC2 in Low mode
–
–
9.2
LSB
LSB = 37.5-nA typ.
SID322A
IDACMISMATCH2
Mismatch between IDAC1 and
IDAC2 in Medium mode
–
–
6
LSB
LSB = 300-nA typ.
SID322B
IDACMISMATCH3
Mismatch between IDAC1 and
IDAC2 in High mode
–
–
5.8
LSB
LSB = 2.4-µA typ.
SID323
IDACSET8
Settling time to 0.5 LSB for 8-bit
IDAC
–
–
10
µs
Full-scale transition. No
external load.
SID324
IDACSET7
Settling time to 0.5 LSB for 7-bit
IDAC
–
–
10
µs
Full-scale transition. No
external load.
SID325
CMOD
External modulator capacitor.
–
2.2
–
nF
5-V rating, X7R or NP0 cap.
Full-scale error less offset
Table 26. CSD ADC Specifications
Spec ID#
Parameter
Description
Min
Typ Max Units
Details / Conditions
CSDv2 ADC Specifications
–
–
10
bits
Auto-zeroing is required every millisecond
Number of channels - single ended
–
–
–
16
–
Monotonicity
–
–
Yes
–
VREF mode
–
0.6
–
%
Reference Source: SRSS
(VREF = 1.20 V, VDDA < 2.2 V),
(VREF = 1.6 V, 2.2 V < VDDA <
2.7 V), (VREF = 2.13 V, VDDA >
2.7 V)
–
0.2
–
%
Reference Source: SRSS
(VREF=1.20 V, VDDA < 2.2V),
(VREF=1.6 V,
2.2 V < VDDA < 2.7 V),
(VREF = 2.13 V, VDDA > 2.7 V)
–
0.5
–
SIDA94
A_RES
Resolution
SID95
A_CHNLS_S
SIDA97
A-MONO
SIDA98
SIDA98A
SIDA99
A_GAINERR_VREF
A_GAINERR_VDDA
A_OFFSET_VREF
Gain error
Gain error
LSB After ADC calibration, Ref. Src =
SRSS, (VREF = 1.20 V, VDDA <
2.2 V),
(VREF = 1.6 V, 2.2 V < VDDA <
2.7 V),
(VREF = 2.13 V, VDDA > 2.7 V)
Input offset voltage
–
0.5
–
LSB After ADC calibration, Ref. Src =
SRSS, (VREF = 1.20 V, VDDA <
2.2 V),
(VREF = 1.6 V, 2.2 V < VDDA <
2.7 V),
(VREF = 2.13 V, VDDA > 2.7 V)
SIDA99A
A_OFFSET_VDDA
Input offset voltage
SIDA100
A_ISAR_VREF
Current consumption
–
0.3
–
mA
CSD ADC Block current
SIDA100A A_ISAR_VDDA
Current consumption
–
0.3
–
mA
CSD ADC Block current
Document Number: 002-26168 Rev. *M
Page 49 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 26. CSD ADC Specifications (continued)
Spec ID#
SIDA101
Parameter
A_VINS_VREF
Description
Min
Typ Max Units
VSSA
–
VREF
V
(VREF = 1.20 V, VDDA < 2.2 V),
(VREF = 1.6 V, 2.2 V < VDDA <
2.7 V),
(VREF = 2.13 V, VDDA > 2.7 V)
VSSA
–
VDDA
V
(VREF = 1.20 V, VDDA < 2.2 V),
(VRE F = 1.6 V, 2.2 V < VDDA <
2.7 V),
(VREF = 2.13 V, VDDA > 2.7 V)
Input voltage range - single ended
SIDA101A A_VINS_VDDA
Input voltage range - single ended
Details / Conditions
SIDA103
A_INRES
Input charging resistance
–
15
–
kΩ
–
SIDA104
A_INCAP
Input capacitance
–
41
–
pF
–
SIDA106
A_PSRR
Power supply rejection ratio (DC)
–
60
–
dB
–
–
10
–
µs
Measured with 50-Ω source
impedance. 10 µs is default
software driver acquisition time
setting. Settling to within 0.05%.
25
–
µs
SIDA107
A_TACQ
Sample acquisition time
A_CONV8
Conversion time for 8-bit resolution at
conversion rate = Fhclk / (2"(N + 2)).
Clock frequency = 50 MHz.
–
SIDA108
Conversion time for 10-bit resolution at
conversion rate = Fhclk / (2"(N + 2)).
Clock frequency = 50 MHz.
–
SIDA108A A_CONV10
SIDA109
Signal-to-noise and distortion ratio
(SINAD)
–
57
–
dB
Measured with 50-Ω source
impedance
SIDA109A A_SND_VDDA
Signal-to-noise and distortion ratio
(SINAD)
–
52
–
dB
Measured with 50-Ω source
impedance
SIDA111
A_INL_VREF
Integral non-linearity. 11.6 ksps
–
–
2
SIDA111A A_INL_VDDA
Integral non-linearity. 11.6 ksps
SIDA112
Differential non-linearity. 11.6 ksps
A_SND_VRE
A_DNL_VREF
SIDA112A A_DNL_VDDA
Differential non-linearity. 11.6 ksps
Document Number: 002-26168 Rev. *M
Does not include acquisition time.
60
–
µs
Does not include acquisition time.
LSB Measured with 50-Ω source
impedance
–
–
2
LSB Measured with 50-Ω source
impedance
–
–
1
LSB Measured with 50-Ω source
–
–
1
LSB Measured with 50-Ω source
impedance
impedance
Page 50 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Digital Peripherals
Timer/Counter/PWM
Table 27. Timer/Counter/PWM (TCPWM) Specifications
Spec ID#
Parameter
Description
Min
Typ
Max Units
Details/Conditions
SID.TCPWM.1
ITCPWM1
Block current consumption at 8 MHz
–
–
70
µA
All modes (TCPWM)
SID.TCPWM.2
ITCPWM2
Block current consumption at 24 MHz
–
–
180
µA
All modes (TCPWM)
SID.TCPWM.2A
ITCPWM3
Block current consumption at 50 MHz
–
–
270
µA
All modes (TCPWM)
SID.TCPWM.2B
ITCPWM4
Block current consumption at 100 MHz
–
–
540
µA
All modes (TCPWM)
SID.TCPWM.3
TCPWMFREQ
Operating frequency
–
–
100
SID.TCPWM.4
TPWMENEXT
Input trigger pulse width for all trigger
events
–
ns
1.5/Fc
–
–
ns
Resolution of counter
1/Fc
–
–
ns
Minimum time between
successive counts
PWM resolution
1/Fc
–
–
ns
Minimum pulse width of PWM
output
ns
Minimum pulse width between
Quadrature phase inputs.
Delays from pins should be
similar.
TPWMEXT
Output trigger pulse widths
SID.TCPWM.5A
TCRES
SID.TCPWM.5B
PWMRES
QRES
–
Trigger events can be Stop,
Start, Reload, Count, Capture,
or Kill depending on which
mode of operation is selected.
Fc is counter operating
frequency.
Minimum possible width of
Overflow, Underflow, and CC
(Counter equals Compare
value) trigger outputs
SID.TCPWM.5
SID.TCPWM.5C
2/Fc
MHz Maximum = 100 MHz
Quadrature inputs resolution
2/Fc
–
–
Min
Typ
Max
Units
Serial Communication Block (SCB)
Table 28. Serial Communication Block (SCB) Specifications
Spec ID#
Parameter
Description
Details / Conditions
Fixed I2C DC Specifications
SID149
II2C1
Block current consumption at 100 kHz
–
–
30
µA
–
SID150
II2C2
Block current consumption at 400 kHz
–
–
80
µA
–
SID151
II2C3
Block current consumption at 1 Mbps
–
–
180
µA
–
SID152
II2C4
I2C enabled in Deep Sleep mode
–
–
1.7
µA
At 60°C.
Bit Rate
–
–
1
Fixed
I2C
SID153
AC Specifications
FI2C1
Mbps –
Fixed UART DC Specifications
SID160
IUART1
Block current consumption at 100 kbps
–
–
30
µA
–
SID161
IUART2
Block current consumption at 1000 kbps
–
–
180
µA
–
–
–
3
–
–
8
–
–
220
Fixed UART AC Specifications
SID162A
FUART1
SID162B
FUART2
Bit Rate
Mbps ULP Mode
LP Mode
Fixed SPI DC Specifications
SID163
ISPI1
Block current consumption at 1 Mbps
Document Number: 002-26168 Rev. *M
µA
–
Page 51 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 28. Serial Communication Block (SCB) Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SID164
ISPI2
Block current consumption at 4 Mbps
–
–
340
µA
–
SID165
ISPI3
Block current consumption at 8 Mbps
–
–
360
µA
–
SID165A
ISP14
Block current consumption at 25 Mbps
–
–
800
µA
–
–
–
25
Fixed SPI AC Specifications for LP Mode (1.1 V) unless noted otherwise.
SID166
FSPI
SPI Operating frequency externally clocked
slave
SID166B
FSPI_EXT
SPI operating frequency master (Fscb is
SPI clock).
SID166A
FSPI_IC
SPI slave internally clocked
MHz 12-MHz max for ULP (0.9 V)
mode
–
–
Fscb/4 MHz Fscb max is 100 MHz in LP
(1.1 V) mode, 25 MHz in ULP
mode.
–
–
15
MHz 5 MHz max for ULP (0.9 V)
mode
Fixed SPI Master mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.
SID167
TDMO
MOSI valid after SClock driving edge
SID168
TDSI
MISO valid before SClock capturing edge
SID169
THMO
MOSI data hold time
–
–
12
ns
20 ns max for ULP (0.9 V)
mode
5
–
–
ns
Full clock, late MISO
sampling
0
–
–
ns
Referred to Slave capturing
edge
Fixed SPI Slave mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.
SID170
TDMI
MOSI valid before Sclock capturing edge
5
–
–
ns
–
SID171A
TDSO_EXT
MISO valid after Sclock driving edge in Ext.
Clk. mode
–
–
20
ns
35 ns max. for ULP (0.9 V)
mode
–
TDSO_
ns
TDSO
MISO valid after Sclock driving edge in
Internally Clk. mode
–
SID171
SID171B
TDSO
MISO Valid after Sclock driving edge in
Internally Clk. Mode with median filter
enabled.
SID172
THSO
Previous MISO data hold time
5
SID172A
TSSELSCK1
SSEL Valid to first SCK valid edge
SID172B
TSSELSCK2
SSEL Hold after Last SCK valid edge
Document Number: 002-26168 Rev. *M
EXT + 3
* Tscb
–
–
Tscb is Serial Comm. Block
clock period.
TDSO_
EXT +
4*
Tscb
ns
–
–
ns
–
65
–
–
ns
–
65
–
–
ns
–
Tscb is Serial Comm. Block
clock period.
Page 52 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
LCD Specifications
Table 29. LCD Direct Drive DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max Units
Details / Conditions
SID154
ILCDLOW1
Operating current with 100-kHz LCD
block clock in ULP mode in Deep Sleep
–
90
–
µA
32×4 small display. 30-Hz.
PWM mode. Slow slew rate.
460-k series resistors
SID154A
ILCDLOW2
Operating current with 32- kHz LCD block
clock in ULP mode in Deep Sleep
–
50
–
µA
32×4 small display. 30-Hz.
PWM mode. Slow slew rate.
460-k series resistors
SID155
CLCDCAP
LCD capacitance per segment/common
driver
–
500
5000
pF
–
SID156
LCDOFFSET
Long-term segment offset
–
20
–
mV –
SID157
ILCDOP1
PWM Mode current.
3.3 V bias. 8 MHz IMO. 25 °C.
–
0.6
–
mA
32 × 4 segments
50 Hz
SID158
ILCDOP2
PWM Mode current.
3.3 V bias. 8 MHz IMO. 25 °C.
–
0.5
–
mA
32 × 4 segments
50 Hz
Min
Typ
Max
Units
10
50
150
Hz
Table 30. LCD Direct Drive AC Specifications
Spec ID
SID159
Parameter
FLCD
Description
LCD frame rate
Document Number: 002-26168 Rev. *M
Details/Conditions
–
Page 53 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Memory
Table 31. Flash Specifications[6]
Spec ID
Parameter
Description
Min
Typ
Max
Units
Erase and Program current
–
–
6
mA
Details/Conditions
Flash DC Specifications
SID173A
IPE
Flash AC Specifications
SID174
TROWWRITE
Row write time (erase and program)
–
–
16
ms
Row = 512 bytes
SID175
TROWERASE
Row erase time
–
–
11
ms
–
SID176
TROWPROGRAM
Row program time after erase
–
–
5
ms
–
SID178
TBULKERASE
Bulk erase time (512 KB)
–
–
11
ms
–
SID179
TSECTORERASE
Sector erase time (256 KB)
–
–
11
ms
512 rows per sector
SID178S
TSSERIAE
Subsector erase time
–
–
11
ms
8 rows per subsector
SID179S
TSSWRITE
Subsector write time; 1 erase plus 8
program times
–
–
51
ms
–
SID180S
TSWRITE
Sector write time; 1 erase plus 512 program
times
–
–
2.6
seconds –
SID180
TDEVPROG
Total device write time
seconds –
SID181
FEND
Flash endurance
SID182
FRET1
SID182A
–
–
7.5
100K
–
–
cycles
–
Flash retention. Ta 25 °C, 100K P/E
cycles
10
–
–
years
–
FRET2
Flash retention. Ta 85 °C, 10K P/E cycles
10
–
–
years
–
SID182B
FRET3
Flash retention. Ta 55 °C, 20K P/E cycles
20
–
–
years
–
SID256
TWS100
Number of Wait states at 100 MHz
3
–
–
–
SID257
TWS50
Number of Wait states at 50 MHz
2
–
–
–
Note
4. It can take as much as 16 milliseconds to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
Document Number: 002-26168 Rev. *M
Page 54 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
System Resources
Table 32. System Resources
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Power-On-Reset with Brown-out DC Specifications
Precise POR (PPOR)
SID190
VFALLPPOR
BOD trip voltage in Active and Sleep
modes. VDDD.
1.54
–
–
V
BOD reset guaranteed for levels
below 1.54 V
SID192
VFALLDPSLP
BOD trip voltage in Deep Sleep. VDDD.
1.54
–
–
V
–
SID192A
VDDRAMP
Maximum power supply ramp rate (any
supply)
–
–
100
mV/µs Active mode
–
–
10
mV/µs BOD operation guaranteed
POR with Brown-out AC Specification
SID194A
VDDRAMP_DS
Maximum power supply ramp rate (any
supply) in Deep Sleep
Voltage Monitors DC Specifications
SID195
VHVDI1
–
1.38 1.43
1.47
V
–
SID196
VHVDI2
–
1.57 1.63
1.68
V
–
SID197
VHVDI3
–
1.76 1.83
1.89
V
–
SID198
VHVDI4
–
1.95 2.03
2.1
V
–
SID199
VHVDI5
–
2.05 2.13
2.2
V
–
SID200
VHVDI6
–
2.15 2.23
2.3
V
–
SID201
VHVDI7
–
2.24 2.33
2.41
V
–
SID202
VHVDI8
–
2.34 2.43
2.51
V
–
SID203
VHVDI9
–
2.44 2.53
2.61
V
–
SID204
VHVDI10
–
2.53 2.63
2.72
V
–
SID205
VHVDI11
–
2.63 2.73
2.82
V
–
SID206
VHVDI12
–
2.73 2.83
2.92
V
–
SID207
VHVDI13
–
2.82 2.93
3.03
V
–
SID208
VHVDI14
–
2.92 3.03
3.13
V
–
SID209
VHVDI15
–
3.02 3.13
3.23
V
–
SID211
LVI_IDD
Block current
–
5
15
µA
–
–
–
170
ns
–
Voltage Monitors AC Specification
SID212
TMONTRIP
Voltage monitor trip time
Document Number: 002-26168 Rev. *M
Page 55 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
SWD Interface
Table 33. SWD and Trace Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SWD and Trace Interface
SID214
F_SWDCLK2
1.7 V VDDD 3.6 V
–
–
25
MHz
LP Mode.
VCCD = 1.1 V.
SID214L
F_SWDCLK2L
1.7 V VDDD 3.6 V
–
–
12
MHz
ULP Mode.
VCCD = 0.9 V.
SID215
T_SWDI_SETUP T = 1/f SWDCLK
0.25 * T
–
–
ns
–
SID216
T_SWDI_HOLD
0.25 * T
–
–
ns
–
SID217
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5 * T
ns
–
SID217A
T_SWDO_HOLD T = 1/f SWDCLK
–
T = 1/f SWDCLK
1
–
–
ns
–
–
50
MHz
LP Mode. VDD = 1.1 V.
SID214T
F_TRCLK_LP1
With Trace Data setup/hold times of
2/1 ns respectively
SID215T
F_TRCLK_LP2
With Trace Data setup/hold times of
3/2 ns respectively
–
–
50
MHz
LP Mode. VDD = 1.1 V.
SID216T
F_TRCLK_ULP
With Trace Data setup/hold times of
3/2 ns respectively
–
–
20
MHz
ULP Mode. VDD = 0.9 V.
Min
Typ
Max
Units
Details/Conditions
–
9
15
µA
Internal Main Oscillator
Table 34. IMO DC Specifications
Spec ID
SID218
Parameter
IIMO1
Description
IMO operating current at 8 MHz
–
Table 35. IMO AC Specifications
Spec ID
Parameter
Description
SID223
FIMOTOL1
Frequency variation centered on
8 MHz
SID227
TJITR
Cycle-to-Cycle and Period jitter
Min
Typ
Max
Units
Details/Conditions
–
–
±2
%
–
–
250
–
ps
–
Min
Typ
Max
Units
–
0.3
0.7
µA
Min
Typ
Max
Units
Internal Low-Speed Oscillator
Table 36. ILO DC Specification
Spec ID
SID231
Parameter
IILO2
Description
ILO operating current at 32 kHz
Details/Conditions
–
Table 37. ILO AC Specifications
Spec ID
Parameter
Description
Details/Conditions
SID234
TSTARTILO1
ILO startup time
–
–
7
µs
Startup time to 95% of
final frequency
SID236
TLIODUTY
ILO Duty cycle
45
50
55
%
–
SID237
FILOTRIM1
32 kHz trimmed frequency
28.8
32
35.2
kHz
Document Number: 002-26168 Rev. *M
10% variation
Page 56 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Crystal Oscillator Specifications
Table 38. ECO Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Block operating current with Cload up to
18 pF
–
800
1600
µA
Crystal frequency range
16
–
35
MHz
Block operating current with 32-kHz crystal
–
0.38
1
µA
–
MHz ECO DC Specification
SID316
IDD_MHz
Max = 35 MHz,
Typ = 16 MHz
MHz ECO AC Specification
SID317
F_MHz
Some restrictions apply.
Refer to the device TRM.
kHz ECO DC Specification
SID318
IDD_kHz
SID321E
ESR32K
Equivalent series resistance
–
80
–
kΩ
–
SID322E
PD32K
Drive level
–
–
1
µW
–
32.768
–
kHz
–
kHz ECO AC Specification
SID319
F_kHz
32 kHz frequency
–
SID320
Ton_kHz
Startup time
–
–
500
ms
–
SID320E
FTOL32K
Frequency tolerance
–
50
250
ppm
–
External Clock Specifications
Table 39. External Clock Specifications
Min
Typ
Max
Units
SID305
Spec ID
EXTCLKFREQ
Parameter
External clock input frequency
Description
0
–
100
MHz
–
Details/Conditions
SID306
EXTCLKDUTY
Duty cycle; measured at VDD/2
45
–
55
%
–
Min
Typ
Max
Units
4
–
64
MHz
PLL Specifications
Table 40. PLL Specifications
Spec ID
Parameter
Description
SID304P PLL_IN
Input frequency to PLL block
SID305P PLL_LOCK
Time to achieve PLL lock
SID306P PLL_OUT
Output frequency from PLL block
SID307P PLL_IDD
PLL current
SID308P PLL_JTR
Details/Conditions
–
16
35
µs
–
10.625
–
150
MHz
–
–
0.55
1.1
mA
Typ. at 100 MHz out.
–
–
150
ps
100-MHz output
frequency
Description
Min
Typ
Max
Units
Clock switching from clk1 to clk2 in clock
periods; for example, from IMO (clk1) to FLL
(clk2).[5]
–
–
Period jitter
Table 41. Clock Source Switching Time
Spec ID
SID262
Parameter
TCLKSWITCH
Details/Conditions
4 clk1 +
periods –
3 clk2
Note
5. As an example, if the clk_path[1] source is changed from the IMO to the FLL (see Figure 3) then clk1 is the IMO and clk2 is the FLL.
Document Number: 002-26168 Rev. *M
Page 57 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
FLL Specifications
Table 42. Frequency Locked Loop (FLL) Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
0.001
–
100
MHz
Lower limit allows lock to
USB SOF signal (1 kHz).
Upper limit is for External
input.
Frequency Locked Loop (FLL) Specifications
SID450
FLL_RANGE
Input frequency range.
SID451
FLL_OUT_DIV2
Output frequency range.
VCCD = 1.1 V
24.00
–
100.00
MHz
Output range of FLL
divided-by-2 output
SID451A
FLL_OUT_DIV2
Output frequency range.
VCCD = 0.9 V
24.00
–
50.00
MHz
Output range of FLL
divided-by-2 output
SID452
FLL_DUTY_DIV2
Divided-by-2 output; High or Low
47.00
–
53.00
%
–
–
–
7.50
µs
SID454
FLL_WAKEUP
Time from stable input clock to 1%
of final value on Deep Sleep
wakeup
With IMO input, less than
10 °C change in
temperature while in Deep
Sleep, and Fout ≥ 50 MHz.
SID455
FLL_JITTER
Period jitter (1 sigma) at 100 MHz
–
–
35.00
ps
50 ps at 48 MHz, 35 ps at
100 MHz
SID456
FLL_CURRENT
CCO + Logic current
–
–
5.50
µA/MHz –
USB
Table 43. USB Specifications (USB requires LP Mode 1.1-V internal supply)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
USB Block Specifications
SID322U
VUSB_3.3
Device supply for USB operation
3.15
–
3.6
V
USB Configured
SID323U
VUSB_3
Device supply for USB operation
(functional operation only)
2.85
–
3.6
V
USB Configured
SID325U
Iusb_config
Block supply current in Active mode
–
8
–
mA
VDDD = 3.3 V
SID328
Iusb_suspend
Block supply current in suspend
mode
–
0.5
–
mA
VDDD = 3.3 V, Device
connected
SID329
Iusb_suspend
Block supply current in suspend
mode
–
0.3
–
mA
VDDD = 3.3 V, Device
disconnected
SID330U
USB_Drive_Res
USB driver impedance
28
–
44
Ω
Series resistors are on
chip
SID332U
USB_Pullup_Idle
Idle mode range
900
–
1575
Ω
Bus idle
SID333U
USB_Pullup
Active mode
1425
–
3090
Ω
Upstream device transmitting
Document Number: 002-26168 Rev. *M
Page 58 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 44. QSPI Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SMIF QSPI Specifications. All specs with 15-pF load. Measured from 50% to 50% waveform transitions.
SID390Q
Fsmifclock
SMIF QSPI output clock frequency
–
–
80
MHz
LP mode (1.1 V)
SID390QU
Fsmifclocku
SMIF QSPI output clock frequency
–
–
50
MHz
ULP mode (0.9 V).
Guaranteed by Char.
SID399Q
Clk_dutycycle
Clock duty cycle (high or low time)
45
–
55
%
SID397Q
Idd_qspi
Block current in LP mode (1.1 V)
–
–
1900
µA
LP mode (1.1 V)
SID398Q
Idd_qspi_u
Block current in ULP mode (0.9 V)
–
–
590
µA
ULP mode (0.9 V)
SID391Q
Tsetup
Input data set-up time with respect to
clock capturing falling edge
4.5
–
–
ns
–
SID392Q
Tdatahold
Input data hold time with respect to
clock capturing falling edge
1
–
–
ns
–
SID393Q
Tdataoutvalid
Output data valid time with respect to
clock falling edge
–
–
3.7
ns
7.5-ns max for ULP
mode (0.9 V)
SID394Q
Tholdtime
Output data hold time with respect to
clock rising edge
3
–
–
ns
–
SID395Q
Tseloutvalid
Output Select valid time with respect to
clock rising edge
–
–
7.5
ns
15-ns max for ULP
mode (0.9 V)
SID396Q
Tselouthold
Output Select hold time with respect to
Tsclk/2
clock rising edge
–
–
ns
Tsclk = Fsmifclk cycle
time
Smart I/O
Table 45. Smart I/O Specifications
Min
Typ
Max
Units
SID420
Spec ID#
SMIO_BYP
Parameter
Smart I/O bypass delay
Description
–
–
2
ns
–
Details/Conditions
SID421
SMIO_LUT
Smart I/O LUT prop delay
–
8
–
ns
–
Min
Typ
Max
Units
SD Host Controller and eMMC
Table 46. SD Host Controller and eMMC Specifications
Spec ID#
Parameter
Description
Details / Conditions
SD Host Controller and eMMC Specifications (SD Host clock (see the Clocking Diagram) must be divided by 2 or more
when used as source in DDR modes. Specs are Guaranteed by Design.)
4
–
4
mA
drive_sel = '01' for all
modes
0.7
–
3
ns
–
Interface clock period (LP mode)
–
–
25
MHz
(40-ns period)
Interface clock period (ULP mode)
–
–
8
MHz
(125-ns period)
SD_DCMD_CL I/O loading at DATA/CMD pins
–
30
–
pF
–
SD_CLK_CL
I/O loading at CLK pins
–
30
–
pF
–
SD_TS_OUT
Output: Setup time of CMD/DAT prior to
CLK
5.1
–
–
ns
–
SID_SD390
SD_DS
I/O drive select
SID_SD391
SD_TR
Input transition time
SID_SD392
SD_CLK
SID_SD393
SD_CLK
SID_SD394
SID_SD395
SID_SD396
SD:DS Timing
Document Number: 002-26168 Rev. *M
Page 59 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 46. SD Host Controller and eMMC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SID_SD397
SD_HLD_OUT
Output: Hold time of CMD/DAT after
CLK
5.1
–
–
ns
–
SID_SD398
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (LP mode)
24
–
–
ns
–
SID_SD399
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (ULP mode)
109
–
–
ns
–
SID_SD400
SD_HLD_IN
Input: Hold time of CMD/DAT after CLK
0
–
–
ns
–
SD:HS Timing
SID_SD401
SD_CLK
Interface clock period (LP mode)
–
–
45
MHz
(22.5-ns period)
SID_SD402
SD_CLK
Interface clock period (ULP mode)
–
–
16
MHz
(62.5-ns period)
SID_SD403
SD_DCMD_CL I/O loading at DATA/CMD pins
–
30
–
pF
–
SID_SD404
SD_CLK_CL
I/O loading at CLK pins
–
30
–
pF
–
SID_SD405
SD_TS_OUT
Output: Setup time of CMD/DAT prior to
CLK
6.1
–
–
ns
–
SID_SD406
SD_HLD_OUT
Output: Hold time of CMD/DAT after
CLK
2.1
–
–
ns
–
SID_SD407
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (LP mode)
8
–
–
ns
–
SID_SD408
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (ULP mode)
48.3
–
–
ns
–
SID_SD409
SD_HLD_IN
Input: Hold time of CMD/DAT after CLK
2.5
–
–
ns
–
SD:SDR-12 Timing
SID_SD410
SD_CLK
Interface clock period (LP mode)
–
–
25
MHz
(40-ns period)
SID_SD411
SD_CLK
Interface clock period (ULP mode)
–
–
8
MHz
(125-ns period)
SID_SD412
SD_CLK_DC
Duty cycle of output CLK
30
–
70
%
–
SID_SD413
SD_DCMD_CL I/O loading at DATA/CMD pins
–
30
–
pF
–
SID_SD414
SD_CLK_CL
I/O loading at CLK pins
–
30
–
pF
–
SID_SD415
SD_TS_OUT
Output: Setup time of CMD/DAT prior to
CLK
3.1
–
–
ns
–
SID_SD416
SD_HLD_OUT
Output: Hold time of CMD/DAT after
CLK
0.9
–
–
ns
–
SID_SD417
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (LP mode)
24
–
–
ns
–
SID_SD418
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (ULP mode)
109
–
–
ns
–
SID_SD419
SD_HLD_IN
Input: Hold time of CMD/DAT after CLK
1.5
–
–
ns
–
SD:SDR-25 Timing
SID_SD420
SD_CLK
Interface clock period (LP mode)
–
–
50
MHz
(20-ns period)
SID_SD421
SD_CLK
Interface clock period (ULP mode)
–
–
16
MHz
(62.5-ns period)
SID_SD422
SD_CLK_DC
Duty cycle of output CLK
30
–
70
%
–
SID_SD423
SD_DCMD_CL I/O loading at DATA/CMD pins
–
30
–
pF
–
SID_SD424
SD_CLK_CL
–
30
–
pF
–
I/O loading at CLK pins
Document Number: 002-26168 Rev. *M
Page 60 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 46. SD Host Controller and eMMC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
SID_SD425
Details / Conditions
SD_TS_OUT
Output: Setup time of CMD/DAT prior to
CLK
3.1
–
–
ns
–
SID_SD426
SD_HLD_OUT
Output: Hold time of CMD/DAT after
CLK
0.9
–
–
ns
–
SID_SD427
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (LP mode)
5.8
–
–
ns
–
SID_SD428
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (ULP mode)
48.3
–
–
ns
–
SID_SD429
SD_HLD_IN
Input: Hold time of CMD/DAT after CLK
1.5
–
–
ns
–
SD:SDR-50 Timing
SID_SD430
SD_CLK
Interface clock period (LP mode)
–
–
80
MHz
(12.5-ns period)
SID_SD431
SD_CLK
Interface clock period (ULP mode)
–
–
32
MHz
(31.25-ns period)
SID_SD432
SD_CLK_DC
Duty cycle of output CLK
30
–
70
%
–
SID_SD433
SD_DCMD_CL I/O loading at DATA/CMD pins
–
20
–
pF
–
SID_SD434
SD_CLK_CL
I/O loading at CLK pins
–
20
–
pF
–
SID_SD435
SD_TS_OUT
Output: Setup time of CMD/DAT prior to
CLK
3.1
–
–
ns
–
SID_SD436
SD_HLD_OUT
Output: Hold time of CMD/DAT after
CLK
0.9
–
–
ns
–
SID_SD437
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (LP mode)
5
–
–
ns
–
SID_SD438
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (ULP mode)
23.6
–
–
ns
–
SID_SD439
SD_HLD_IN
Input: Hold time of CMD/DAT after CLK
1.5
–
–
ns
–
SD:DDR-50 Timing
SID_SD440
SD_CLK
Interface clock period (LP mode)
–
–
40
MHz
(25-ns period).
SID_SD441
SD_CLK
Interface clock period (ULP mode)
–
–
16
MHz
(62.5-ns period)
SID_SD442
SD_CLK_DC
Duty cycle of output CLK
45
–
55
%
–
SID_SD443
SD_DCMD_CL I/O loading at DATA/CMD pins
–
30
–
pF
–
SID_SD444
SD_CLK_CL
I/O loading at CLK pins
–
30
–
pF
–
SID_SD445
SD_TS_OUT
Output: Setup time of CMD/DAT prior to
CLK
3.1
–
–
ns
SID_SD446
SD_HLD_OUT
Output: Hold time of CMD/DAT after
CLK
0.9
–
–
ns
SID_SD447
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (LP mode)
5.7
–
–
ns
SID_SD448
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (ULP mode)
24
–
–
ns
SID_SD449
SD_HLD_IN
Input: Hold time of CMD/DAT after CLK
1.5
–
–
ns
–
–
–
–
–
eMMC:BWC Timing
SID_SD450
SD_CLK
Interface clock period (LP mode)
–
–
26
MHz
(38.4-ns period)
SID_SD451
SD_CLK
Interface clock period (ULP mode)
–
–
8
MHz
(125-ns period)
SID_SD452
SD_DCMD_CL I/O loading at DATA/CMD pins
–
30
–
pF
Document Number: 002-26168 Rev. *M
–
Page 61 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 46. SD Host Controller and eMMC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
SID_SD453
SD_CLK_CL
I/O loading at CLK pins
SID_SD454
SD_TS_OUT
Output: Setup time of CMD/DAT prior to
CLK
SID_SD455
SD_HLD_OUT
Output: Hold time of CMD/DAT after
CLK
SID_SD456
SD_TS_IN
SID_SD457
SID_SD458
Details / Conditions
–
30
–
pF
3.1
–
–
ns
3.1
–
–
ns
Input: Setup time of CMD/DAT prior to
CLK (LP mode)
9.7
–
–
ns
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (ULP mode)
96.3
–
–
ns
SD_HLD_IN
Input: Hold time of CMD/DAT after CLK
8.3
–
–
ns
–
–
52
MHz
(19.2-ns period)
(62.5-ns period)
–
–
–
–
–
–
eMMC:SDR Timing
SID_SD459
SD_CLK
Interface clock period (LP mode)
Interface clock period (ULP mode)
SID_SD460
SD_CLK
–
–
16
MHz
SID_SD461
SD_DCMD_CL I/O loading at DATA/CMD pins
–
30
–
pF
–
SID_SD462
SD_CLK_CL
I/O loading at CLK pins
–
30
–
pF
–
SID_SD463
SD_TS_OUT
Output: Setup time of CMD/DAT prior to
CLK
3.1
–
–
ns
SID_SD464
SD_HLD_OUT
Output: Hold time of CMD/DAT after
CLK
3.1
–
–
ns
SID_SD465
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (LP mode)
5.3
–
–
ns
SID_SD466
SD_TS_IN
Input: Setup time of CMD/DAT prior to
CLK (ULP mode)
48.6
–
–
ns
SID_SD467
SD_HLD_IN
Input: Hold time of CMD/DAT after CLK
2.5
–
–
ns
–
–
–
–
–
SD Host Block Current Specs
SID400SD
IDD_SD_1
SD Host block current consumption at
100 MHz
–
4.65
5
mA
SDR-50
SID401SD
IDD_SD_2
SD Host block current consumption at
50 MHz
–
3.75
4.3
mA
SDR-25
JTAG Boundary Scan
Table 47. JTAG Boundary Scan
Spec ID#
Parameter
Min
Typ
JTAG Boundary Scan Parameters for 1.1 V (LP) Mode Operation:
SID468
TCKLOW
TCK LOW
52
–
SID469
TCKHIGH
TCK HIGH
10
SID470
TCK_TDO
TCK falling edge to output valid
Max Units Details / Conditions
JTAG Boundary Scan Parameters
–
ns
–
–
–
ns
–
–
40
ns
–
SID471
TSU_TCK
Input valid to TCK rising edge
12
–
–
ns
–
SID472
TCk_THD
Input hold time to TCK rising edge
10
–
–
ns
–
SID473
TCK_TDOV
TCK falling edge to output valid (High-Z
to Active).
40
–
–
ns
SID474
TCK_TDOZ
TCK falling edge to output valid (Active
to High-Z).
40
–
–
ns
Document Number: 002-26168 Rev. *M
–
–
Page 62 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Table 47. JTAG Boundary Scan (continued)
Spec ID#
Parameter
Min
Typ
Max Units Details / Conditions
JTAG Boundary Scan Parameters for 0.9 V (ULP) Mode Operation:
SID468A
TCKLOW
TCK low
102
–
–
ns
–
SID469A
TCKHIGH
TCK high
20
–
–
ns
–
SID470A
TCK_TDO
TCK falling edge to output valid
–
80
ns
–
SID471A
TSU_TCK
Input valid to TCK rising edge
22
–
–
ns
–
SID472A
TCk_THD
Input hold time to TCK rising edge
20
–
–
ns
–
SID473A
TCK_TDOV
TCK falling edge to output valid (high-Z
to active).
80
–
–
ns
SID474A
TCK_TDOZ
TCK falling edge to output valid (active
to high-Z).
80
–
–
ns
Document Number: 002-26168 Rev. *M
–
–
Page 63 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Ordering Information
Table 49 lists the CY8C62x5 part numbers and features. See also the product selector guide.
Performance Line
Arm CM4 and CM0+,
DC-DC converter, 12-bit SAR
ADC, 2 LPCOMPs,
7 SCBs, 12 TCPWMs, SD Host
Controller
Document Number: 002-26168 Rev. *M
Marketing
Part Number
Flash (KB)
SRAM (KB)
CapSense
CAN FD
Crypto
USB
GPIO
Package
Base Features
Family
Table 48. Ordering Information
CY8C6245AZI-S3D72
512
256
Y
1
Y
Y
64
100-TQFP
CY8C6245LQI-S3D72
512
256
Y
1
Y
Y
53
68-QFN
CY8C6245FNI-S3D71
512
256
Y
1
Y
–
37
49-WLCSP
CY8C6245AZI-S3D62
512
256
–
1
–
Y
64
100-TQFP
CY8C6245LQI-S3D62
512
256
–
1
–
Y
53
68-QFN
CY8C6245AZI-S3D42
512
256
Y
–
Y
Y
64
100-TQFP
CY8C6245LQI-S3D42
512
256
Y
–
Y
Y
53
68-QFN
CY8C6245FNI-S3D41
512
256
Y
–
Y
–
37
49-WLCSP
CY8C6245AZI-S3D12
512
256
Y
–
–
Y
64
100-TQFP
CY8C6245LQI-S3D12
512
256
Y
–
–
Y
53
68-QFN
CY8C6245FNI-S3D11
512
256
Y
–
–
–
37
49-WLCSP
CY8C6245AZI-S3D02
512
256
–
–
–
Y
64
100-TQFP
CY8C6245LQI-S3D02
512
256
–
–
–
Y
53
68-QFN
Page 64 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
PSoC 6 MPN Decoder
CY XX 6 A B C DD E - FF G H I JJ K L
Field
CY
XX
6
A
B
Description
Cypress
Firmware
Architecture
Line
Speed
Values
CY
8C
Standard
B0
“Secure Boot” v1
S0
“Standard Secure” AWS
6
PSoC 6
0
Value
1
Programmable
2
Performance
3
Connectivity
4
Secured
2
100 MHz
3
150 MHz
4
150/50 MHz
0-3
C
Memory Size
(Flash/SRAM)
Meaning
Field
Description
Cypress
Reserved
4
256K/128K
5
512K/256K
6
512K/128K
7
1024K/288K
8
1024K/512K
9
Reserved
A
2048K/1024K
Values
C
E
FF
Temperature Range
Feature Code
I
Industrial
Q
Extended Industrial
Cypress internal
S2-S6
BL
G
CPU Core
H
Attributes Code
I
GPIO count
JJ
K
Die Revision
(optional)
L
Tape/Reel Shipment
(optional)
Integrated Bluetooth LE
F
Single Core
D
Dual Core
0–9
Feature set
1
31-50
2
51-70
3
71-90
4
Engineering sample
(optional)
Meaning
Consumer
ES
91-110
Engineering samples or
not
Base
A1-A9
T
Die revision
Tape and Reel shipment
AZ, AX TQFP
DD
Package
LQ
QFN
BZ
BGA
FM
M-CSP
FN, FD,
WLCSP
FT
Document Number: 002-26168 Rev. *M
Page 65 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Packaging
This product line is offered in 100 TQFP, 68 QFN, and 49 WLCSP packages.
Table 49. Package Dimensions
Spec ID#
Package
PKG_1
100-TQFP
PKG_2
68 QFN
PKG_3
Description
Package Dwg #
100 TQFP package
51-85048
68 QFN package
001-96836
002-26627
49 WLCSP 49 WLCSP package
Table 50. Package Characteristics
Conditions
Min
Typ
Max
Units
TA
Parameter
Operating ambient temperature
Description
–
–40
25
85
°C
TJ
Operating junction temperature
–
–40
–
100
°C
TJA
Package JA (100 TQFP)
–
–
37.2
–
°C/watt
TJC
Package JC (100 TQFP)
–
–
20.7
–
°C/watt
TJA
Package JA (68 QFN)
–
–
15.4
–
°C/watt
TJC
Package JC (68 QFN)
–
–
2
–
°C/watt
TJA
Package JA (49 WLCSP)
–
–
21.5
–
°C/watt
TJC
Package JC (49 WLCSP)
–
–
0.21
–
°C/watt
Table 51. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
All packages
260 °C
30 seconds
Table 52. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
100 TQFP and 68 QFN
MSL 3
49 WLCSP
MSL 1
Document Number: 002-26168 Rev. *M
Page 66 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Figure 19. 100-TQFP 14.0 × 14.0 ×1.4 mm
51-85048 *K
Figure 20. 68-QFN Package Diagram
001-96836 *A
Document Number: 002-26168 Rev. *M
Page 67 of 74
PSoC 6 MCU: CY8C62x5 Datasheet
Figure 21. 49-Ball WLCSP Package Diagram
T
%T
6
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