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CY8C624ABZI-S2D44T

CY8C624ABZI-S2D44T

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    VFBGA124

  • 描述:

    PSOC6

  • 数据手册
  • 价格&库存
CY8C624ABZI-S2D44T 数据手册
Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet PSoC 62 MCU General Description PSoC® 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT applications. The CY8C62x8/A product line, based on the PSoC 6 MCU platform, is a combination of a dual CPU microcontroller with low-power flash technology, digital programmable logic, high-performance analog-to-digital conversion and standard communication and timing peripherals. Features 32-bit Dual CPU Subsystem Quad-SPI (QSPI)/Serial Memory Interface (SMIF) 150-MHz Arm6® Cortex®-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU) ■ Execute-In-Place (XIP) from external quad SPI flash 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU ■ On-the-fly encryption and decryption ■ ■ 4-KB cache for greater XIP performance with lower power ■ User-selectable core logic operation at either 1.1 V or 0.9 V ■ Supports single, dual, quad, dual-quad, and octal interfaces with throughput up to 640 Mbps ■ Active CPU current slope with 1.1-V core operation ❐ Cortex-M4: 40 µA/MHz ❐ Cortex-M0+: 28 µA/MHz ■ Active CPU current slope with 0.9-V core operation ❐ Cortex-M4: 27 µA/MHz ❐ Cortex-M0+: 20 µA/MHz ■ Three DMA controllers ■ Segment LCD Drive ■ Serial Communication ■ 13 run-time configurable serial communication blocks (SCBs) 2 ❐ Eight SCBs: configurable as SPI, I C, or UART 2 ❐ Four SCBs: configurable as I C or UART 2 ❐ One Deep Sleep SCB: configurable as SPI or I C USB Full-Speed device interface ■ Two independent SD Host Controller/eMMC/SD controllers ■ Memory Subsystem 2048-KB application flash, 32-KB auxiliary flash (AUXflash), and 32-KB supervisory flash (Sflash); read-while-write (RWW) support. Two 8-KB flash caches, one for each CPU. ■ 1024-KB SRAM with three independent blocks for power and data retention control ■ One-time-programmable (OTP) 1-Kb eFuse array ■ Low-Power 1.7-V to 3.6-V Operation ■ Six power modes for fine-grained power management ■ Deep Sleep mode current of 7 µA with 64-KB SRAM retention ■ On-chip DC-DC buck converter, 2.7 V Ports 0, 1 8 MHz DRIVE_SEL 2 DRIVE_SEL 3 Port 2 50 MHz DRIVE_SEL 1 DRIVE_SEL 2 Ports 3 to 10 16 MHz; 25 MHz for SPI DRIVE_SEL 2 DRIVE_SEL 3 Ports 11 to 13 80 MHz for SMIF (QSPI). DRIVE_SEL 1 DRIVE_SEL 2 Ports 9 and 10 Slow slew rate setting for TQFP Packages for ADC performance No restrictions No restrictions Special-Function Peripherals Audio Subsystem This subsystem consists of the following hardware blocks: ■ Two Inter-IC Sound (I2S) interfaces ■ Two PDM to PCM decoder channels Each of the I2S interfaces implements two independent hardware FIFO buffers – Tx and Rx, which can operate in master or slave mode. The following features are supported: ■ Multiple data formats – I2S, left-justified, Time Division Multiplexed (TDM) mode A, and TDM mode B ■ Programmable channel/word lengths – 8/16/18/20/24/32 bits ■ Internal/external clock operation up to 192 ksps ■ Interrupt mask events – trigger, not empty, full, overflow, underflow, watchdog ■ Configurable FIFO trigger level with DMA support The PDM-to-PCM decoder implements a single hardware Rx FIFO that decodes a stereo or mono 1-bit PDM input stream to PCM data output. The following features are supported: ■ Programmable data output word length – 16/18/20/24 bits ■ Programmable gain amplifier (PGA) for volume control – from –12 dB to +10.5 dB in 1.5 dB steps ■ Configurable PDM clock generation. Range from 384 kHz to 3.072 MHz ■ Droop correction and configurable decimation rate for sampling; up to 48 ksps ■ Programmable high-pass filter gain ■ Interrupt mask events – not empty, overflow, trigger, underflow ■ Configurable FIFO trigger level with DMA support The PDM-to-PCM decoder is commonly used to connect to digital PDM microphones. Up to two microphones can be connected to the same PDM Data line. The I2S interface is commonly used to connect with audio codecs, simple DACs, and digital microphones. Document Number: 002-23185 Rev. *R Page 18 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet CapSense Subsystem IDAC CapSense is supported in PSoC 6 MCU through a CapSense sigma-delta (CSD) hardware block. It is designed for high-sensitivity self-capacitance and mutual-capacitance measurements, and is specifically built for user interface solutions. The CSD block has two programmable current sources, which offer the following features: In addition to CapSense, the CSD hardware block supports three general-purpose functions. These are available when CapSense is not being used. Alternatively, two or more functions can be time-multiplexed in an application under firmware control. The four functions supported by the CSD hardware block are: ■ CapSense ■ 10-bit ADC ■ Programmable current sources (IDAC) ■ Comparator CapSense Capacitive touch sensors are designed for user interfaces that rely on human body capacitance to detect the presence of a finger on or near a sensor. Cypress CapSense solutions bring elegant, reliable, and simple capacitive touch sensing functions to applications including IoT, industrial, automotive, and home appliances. The Cypress-proprietary CapSense technology offers the following features: ■ Best-in-class signal-to-noise ratio (SNR) and robust sensing under harsh and noisy conditions ■ Self-capacitance (CSD) and mutual-capacitance (CSX) sensing methods ■ Support for various widgets, including buttons, matrix buttons, sliders, touchpads, and proximity sensors ■ High-performance sensing across a variety of materials ■ Best-in-class liquid tolerance ■ SmartSense™ auto-tuning technology that helps avoid complex manual tuning processes ■ Superior immunity against external noise ■ Spread-spectrum clocks for low radiated emissions ■ Gesture and built-in self-test libraries ■ Ultra-low power consumption ■ An integrated graphical CapSense tuner for real-time tuning, testing, and debugging ADC The CapSense subsystem slope ADC offers the following features: ■ Selectable 8- or 10-bit resolution ■ Selectable input range: GND to VREF and GND to VDDA on any GPIO input ■ Measurement of VDDA against an internal reference without the use of GPIO or external components Document Number: 002-23185 Rev. *R ■ 7-bit resolution ■ Sink and source current modes ■ A current source programmable from 37.5 nA to 609 A ■ Two IDACs that can be used in parallel to form one 8-bit IDAC Comparator The CapSense subsystem comparator operates in the system Low Power and Ultra-Low Power modes. The inverting input is connected to an internal programmable reference voltage and the non-inverting input can be connected to any GPIO via the AMUXBUS. CapSense Hardware Subsystem Figure 7 shows the high-level hardware overview of the CapSense subsystem, which includes a delta sigma converter, internal clock dividers, a shield driver, and two programmable current sources. The inputs are managed through analog multiplexed buses (AMUXBUS A/B). The input and output of all functions offered by the CSD block can be provided on any GPIO or on a group of GPIOs under software control, with the exception of the comparator output and external capacitors that use dedicated GPIOs. Self-capacitance is supported by the CSD block using AMUXBUS A, an external modulator capacitor, and a GPIO for each sensor. There is a shield electrode (optional) for self-capacitance sensing. This is supported using AMUXBUS B and an optional external shield tank capacitor (to increase the drive capability of the shield driver) should this be required. Mutual-capacitance is supported by the CSD block using AMUXBUS A, two external integrated capacitors, and a GPIO for transmit and receive electrodes. The ADC does not require an external component. Any GPIO that can be connected to AMUXBUS A can be an input to the ADC under software control. The ADC can accept VDDA as an input without needing GPIOs (for applications such as battery voltage measurement). The two programmable current sources (IDACs) in general-purpose mode can be connected to AMUXBUS A or B. They can therefore connect to any GPIO pin. The comparator resides in the delta-sigma converter. The comparator inverting input can be connected to the reference. Both comparator inputs can be connected to any GPIO using AMUXBUS B; see Figure 7. The reference has a direct connection to a dedicated GPIO; see Table 9. The CSD block can operate in active and sleep CPU power modes, and seamlessly transition between system LP and ULP modes. It can be powered down in system Deep Sleep and Hibernate modes. Upon wakeup from Hibernate mode, the CSD block requires re-initialization. However, operation can be resumed without re-initialization upon exit from Deep Sleep mode, under firmware control. Page 19 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 7. CapSense Hardware Subsystem AMUXBUS A GPIO Pin B GPIO Cell CSD Sensor1 Clock Input CS1 GPIO Pin GPIO Cell I / O Configur ed f or CSD M ode CSD Sensor 2 CS2 CSD Hardware Block C MOD Pin CMOD Sense clock Clock Generator CSH_TANK ( optional ) GPIO Pin Modulator Shield Drive Clock Circuit GPIO Pin GPIO Cell Compensation IDAC C SHIELD Shield Electrode Modulator IDAC GPIO Pin Tx IDAC control GPIO Cell CSX Sensor 3 I / O Configured for CSX M ode C S3 Raw Rx GPIO Pin GPIO Cell CINTA Pin C INTA C INTB Sigma Delta Converter Count VREF GPIO Cell C INTB Pin GPIO ADC Input Mode I / O for General Purpose Cell IDAC Outputs Comp Input Document Number: 002-23185 Rev. *R Page 20 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 8 shows the high-level software overview. Cypress provides middleware libraries for CapSense, ADC, and IDAC on GitHub to enable quick integration. The Board Support Package for any kit with CapSense capabilities automatically includes the CapSense library in any application that uses the BSP. User applications interact only with middleware to implement functions of the CSD block. The middleware interacts with underlying drivers to access hardware as necessary. The CSD driver facilitates time-multiplexing of the CSD hardware if more than one piece of CSD-related middleware is present in a project. It prevents access conflicts in this case. ModusToolbox Software provides a CapSense configurator to enable fast library configuration. It also provides a tuner for performance evaluation and real-time tuning of the system. The tuner requires an EZI2C communication interface in the application to enable real-time tuning capability. The tuner can update configuration parameters directly in the device as well as in the configurator. CapSense and ADC middleware use the CSD interrupt to implement non-blocking sensing and A-to-D conversion. Therefore, interrupt service routines are a defined part of the middleware, which must be initialized by the application. Middleware and drivers can operate on either CPU. Cypress recommends using the middleware only in one CPU. If both CPUs must access the CSD driver, memory access should be managed in the application. Refer to AN85951: PSoC 4 and PSoC 6 MCU CapSense Design Guide for more details on CSX sensing, CSD sensing, shield electrode usage and its benefits, and capacitive system design guidelines. Refer to the API reference guides for CapSense, ADC, and IDAC available on GitHub. Figure 8. CapSense Software/Firmware Subsystem Application Program Software Middleware Co m p IDAC ADC CapSense Configurator Tuner SCB Driver (EZI 2C) SCB CSD Driver GPIO / Clock Drivers CSD Block GPIOs / Clock Hardware and Drivers Document Number: 002-23185 Rev. *R Page 21 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Pinouts Note: The CY8C62x8/CY8C62xA datasheet web page contains a spreadsheet with the consolidated list of pinouts and pin alternate functions with HSIOM mapping. GPIO ports are powered by VDDx pins as follows: ■ P0: VBACKUP ■ P1: VDDD. Port 1 pins are overvoltage tolerant (OVT). ■ P2, P3, P4: VDDIO2 ■ P5, P6, P7, P8: VDDIO1 ■ P9, P10: VDDIOA, VDDA (VDDIOA, when present, and VDDA must be connected together on the PCB) ■ P11, P12, P13: VDDIO0 P14: VDDUSB Table 7. Packages and Pin Information Pin Packages 128-TQFP 124-BGA 100-WLCSP 68-QFN VDDD 6 A1 D14 68 VCCD 4, 5 A2 C15 67 VDDA 96 A12 J1 48 VDDIOA 69 A13 - 36 VDDIO0 114 C4 A11 64 VDDIO1 68 K12 K2 35 VDDIO2 39 L4 M10 22 VBACKUP 9 D1 C17 1 VDDUSB 27 M1 J17 11 VSS 7, 8, 25, 26, 36, 40, 67, 70, 95, 115 B12, C3, D4, D10, K4, K10 D2, E13, J13, L1 GND PAD VDD_NS 23 J1 J15 9 VIND1 24 J2 H16 10 XRES 16 F1 E17 8 VREF 97 B13 C3 49 P0.0 10 E3 F14 2 P0.1 11 E2 G13 3 P0.2 12 E1 D16 4 P0.3 13 F3 E15 5 P0.4 14 F2 G11 6 P0.5 15 G3 F16 7 P1.0 17 G2 H12 - P1.1 18 G1 G15 - P1.2 19 H3 - - Document Number: 002-23185 Rev. *R Page 22 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 7. Packages and Pin Information (continued) Pin Packages 128-TQFP 124-BGA 100-WLCSP 68-QFN P1.3 20 H2 - - P1.4 21 H1 H14 - P1.5 22 J3 G17 - P2.0 30 M2 L17 14 P2.1 31 N2 K12 15 P2.2 32 L3 L15 16 P2.3 33 M3 L13 17 P2.4 34 N3 L11 18 P2.5 35 N1 M16 19 P2.6 37 M4 M14 20 P2.7 38 N4 M12 21 P3.0 41 L5 - 23 P3.1 42 M5 - 24 P3.2 43 N5 - - P3.3 44 L6 - - P3.4 45 M6 - - P3.5 46 N6 - - P4.0 47 L7 - - P4.1 48 M7 - - P4.2 49 - - - P4.3 50 - - - P5.0 51 N7 M8 25 P5.1 52 L8 K10 26 P5.2 53 M8 J11 - P5.3 54 N8 H10 - P5.4 55 L9 L9 - P5.5 56 M9 M6 - P5.6 57 N9 G9 27 P5.7 58 N10 G7 28 P6.0 59 M10 M4 - P6.1 60 L10 L7 - P6.2 61 L11 L5 29 P6.3 62 M11 K8 30 P6.4 63 N11 J9 31 Document Number: 002-23185 Rev. *R Page 23 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 7. Packages and Pin Information (continued) Pin Packages 128-TQFP 124-BGA 100-WLCSP 68-QFN P6.5 64 M12 L3 32 P6.6 65 N12 M2 33 P6.7 66 M13 K4 34 P7.0 71 L13 K6 37 P7.1 72 L12 J7 38 P7.2 73 K13 J3 39 P7.3 74 N13 H8 40 P7.4 75 K11 - - P7.5 76 J13 - - P7.6 77 J12 - - P7.7 78 J11 G1 41 P8.0 79 H13 H2 42 P8.1 80 H12 J5 43 P8.2 81 H11 H6 - P8.3 82 G13 H4 - P8.4 83 G12 F2 - P8.5 84 G11 - - P8.6 85 F13 - - P8.7 86 F12 - - P9.0 87 E11 E1 44 P9.1 88 E12 G3 45 P9.2 89 E13 G5 46 P9.3 90 F11 F4 47 P9.4 91 D13 E3 - P9.5 92 D12 - - P9.6 93 D11 - - P9.7 94 C13 C1 - P10.0 98 C12 F6 50 P10.1 99 A11 E5 51 P10.2 100 B11 B2 52 P10.3 101 C11 D4 53 P10.4 102 A10 C5 54 P10.5 103 B10 B4 55 P10.6 104 C10 A3 - Document Number: 002-23185 Rev. *R Page 24 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 7. Packages and Pin Information (continued) Pin Packages 128-TQFP 124-BGA 100-WLCSP 68-QFN P10.7 105 A9 F8 - P11.0 106 B9 E9 P11.1 107 C9 D6 57 P11.2 108 A8 E7 58 P11.3 109 B8 A7 59 P11.4 110 C8 B6 60 P11.5 111 A7 A5 61 P11.6 112 B7 C7 62 P11.7 113 C7 B8 63 P12.0 116 A6 A9 - P12.1 117 B6 D8 - P12.2 118 C6 A13 - P12.3 119 A5 B10 - P12.4 120 B5 C9 - P12.5 121 C5 B12 - P12.6 122 A4 C11 65 P12.7 123 B4 D10 66 P13.0 124 B1 B14 - P13.1 125 A3 A15 - P13.2 126 B3 C13 - P13.3 127 B2 D12 - P13.4 128 C2 E11 - P13.5 1 C1 F10 - P13.6 2 D3 F12 - P13.7 3 D2 B16 - P14.0 / USBDP 29 L2 K14 13 P14.1 / USBDM 28 L1 K16 12 56 Note: Balls K2 and K3 are connected together internally in the 124-BGA package. Note: If the USB pins are not used, connect VDDUSB to ground and leave the P14.0/USBDP and P14.1/USBDM pins unconnected. Note 1. DNC means Do Not Connect. Do Not Connect anything to these pins. Document Number: 002-23185 Rev. *R Page 25 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 TQFP 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P10.4 P10.3 P10.2 P10.1 P10.0 VREF VDDA VSS P9.7 P9.6 P9.5 P9.4 P9.3 P9.2 P9.1 P9.0 P8.7 P8.6 P8.5 P8.4 P8.3 P8.2 P8.1 P8.0 P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 VSS VDDIOA VDDIO1 VSS P6.7 P6.6 VDDIO2 VSS P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P4.0 P4.1 P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 P13.5 P13.6 P13.7 VCCD VCCD VDDD VSS VSS VBACKUP P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 XRES P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 VDD_NS VIND1 VSS VSS VDDUSB P14.1 / USBDM P14.0 / USBDP P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 VSS P2.6 P2.7 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 P13.4 P13.3 P13.2 P13.1 P13.0 P12.7 P12.6 P12.5 P12.4 P12.3 P12.2 P12.1 P12.0 VSS VDDIO0 P11.7 P11.6 P11.5 P11.4 P11.3 P11.2 P11.1 P11.0 P10.7 P10.6 P10.5 Figure 9. Device Pinout for 128-TQFP Package Document Number: 002-23185 Rev. *R Page 26 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet 55 54 53 52 P11.5 P11.4 P11.3 P11.2 P11.1 P11.0 P10.5 P10.4 P10.3 P10.2 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 QFN 28 29 30 31 32 33 34 P5.7 P6.2 P6.3 P6.4 P6.5 P6.6 P10.1 P10.0 VREF VDDA P9.3 P9.2 P9.1 P9.0 P8.1 P8.0 P7.7 P7.3 P7.2 P7.1 P7.0 VDDIOA VDDIO1 P6.7 18 19 20 21 22 23 24 25 26 27 (TOP VIEW) P2.5 P2.6 P2.7 VDDIO2 P3.0 P3.1 P5.0 P5.1 P5.6 P0.2 P0.3 P0.4 P0.5 XRES VDD_NS VIND1 VDDUSB P14.1 / USBDM P14.0 / USBDP P2.0 P2.1 P2.2 P2.3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 P2.4 VBACKUP P0.0 P0.1 66 65 64 63 62 61 60 59 58 57 56 68 67 VDDD VCCD P12.7 P12.6 VDDIO0 P11.7 P11.6 Figure 10. Device Pinout for 68-QFN Package[2] Note 2. The center pad on the QFN package should be connected to PCB ground relative to device VDDx for best mechanical, thermal, and electrical performance. For more information, see AN72845, Design Guidelines for QFN Devices. Document Number: 002-23185 Rev. *R Page 27 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Each port pin has multiple alternate functions. These are defined in Table 8. The columns ACT #x and DS #y denote active (System LP/ULP) and Deep Sleep mode signals respectively. The notation for a signal is of the form IPName[x].signal_name[u]:y. IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there is more than one signal for a particular signal name, y = Designates copies of the signal name. For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize use of on-chip resources. For ease of use, the CY8C62x8 and CY8C62xA datasheet web page contains a spreadsheet with the consolidated list of pin functions. Table 8. Multiple Alternate Functions Port/ Pin ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3 P0.0 tcpwm[0]. line[0]:0 tcpwm[1] .line[0]:0 csd.csd _tx:0 csd.csd _tx_n:0 P0.1 tcpwm[0]. line_com pl[0]:0 tcpwm[1] .line_co mpl[0]:0 csd.csd _tx:1 csd.csd _tx_n:1 P0.2 tcpwm[0]. line[1]:0 tcpwm[1] .line[1]:0 csd.csd _tx:2 csd.csd _tx_n:2 scb[0] .uart_ rx:0 scb[0]. i2c_scl :0 scb[0]. spi_m osi:0 P0.3 tcpwm[0]. line_com pl[1]:0 tcpwm[1] .line_co mpl[1]:0 csd.csd _tx:3 csd.csd _tx_n:3 scb[0] .uart_ tx:0 scb[0]. i2c_sd a:0 scb[0]. spi_mi so:0 P0.4 tcpwm[0]. line[2]:0 tcpwm[1] .line[2]:0 csd.csd _tx:4 csd.csd _tx_n:4 scb[0] .uart_ rts:0 scb[0]. spi_cl k:0 peri.tr_io_ output[0]:2 P0.5 tcpwm[0]. line_com pl[2]:0 tcpwm[1] .line_co mpl[2]:0 csd.csd _tx:5 csd.csd _tx_n:5 scb[0] .uart_ cts:0 scb[0]. spi_se lect0:0 peri.tr_io_ output[1]:2 P1.0 tcpwm[0]. line[3]:0 tcpwm[1] .line[3]:0 csd.csd _tx:6 csd.csd _tx_n:6 scb[7] .uart_ rx:0 scb[7]. i2c_scl :0 scb[7]. spi_m osi:0 peri.tr _io_in put[2]: 0 P1.1 tcpwm[0]. line_com pl[3]:0 tcpwm[1] .line_co mpl[3]:0 csd.csd _tx:7 csd.csd _tx_n:7 scb[7] .uart_ tx:0 scb[7]. i2c_sd a:0 scb[7]. spi_mi so:0 peri.tr _io_in put[3]: 0 P1.2 tcpwm[0]. line[4]:4 tcpwm[1] .line[12]: 1 csd.csd _tx:8 csd.csd _tx_n:8 scb[7] .uart_ rts:0 Document Number: 002-23185 Rev. *R srss.e xt_clk: 0 srss.e xt_clk: 1 scb[0]. spi_se lect1:0 peri.tr _io_in put[0]: 0 scb[0]. spi_se lect2:0 peri.tr _io_in put[1]: 0 ACT #13 ACT #14 ACT #15 DS #5 DS #6 scb[7]. spi_cl k:0 Page 28 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 8. Multiple Alternate Functions (continued) Port/ Pin ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #1 ACT #2 ACT #3 DS #2 DS #3 P1.3 tcpwm[0]. line_com pl[4]:4 tcpwm[1] .line_co mpl[12]:1 csd.csd _tx:9 csd.csd _tx_n:9 P1.4 tcpwm[0]. line[5]:4 tcpwm[1] .line[13]: 1 csd.csd _tx:10 csd.csd _tx_n:1 0 scb[7]. spi_se lect1:0 P1.5 tcpwm[0]. line_com pl[5]:4 tcpwm[1] .line_co mpl[14]:1 csd.csd _tx:11 csd.csd _tx_n:1 1 scb[7]. spi_se lect2:0 P2.0 tcpwm[0]. line[6]:4 tcpwm[1] .line[15]: 1 csd.csd _tx:12 csd.csd _tx_n:1 2 scb[1] .uart_ rx:0 scb[1]. i2c_scl :0 scb[1]. spi_m osi:0 peri.tr _io_in put[4]: 0 sdhc[0]. card_da t_3to0[0 ] P2.1 tcpwm[0]. line_com pl[6]:4 tcpwm[1] .line_co mpl[15]:1 csd.csd _tx:13 csd.csd _tx_n:1 3 scb[1] .uart_ tx:0 scb[1]. i2c_sd a:0 scb[1]. spi_mi so:0 peri.tr _io_in put[5]: 0 sdhc[0]. card_da t_3to0[1 ] P2.2 tcpwm[0]. line[7]:4 tcpwm[1] .line[16]: 1 csd.csd _tx:14 csd.csd _tx_n:1 4 scb[1] .uart_ rts:0 scb[1]. spi_cl k:0 sdhc[0]. card_da t_3to0[2 ] P2.3 tcpwm[0]. line_com pl[7]:4 tcpwm[1] .line_co mpl[16]:1 csd.csd _tx:15 csd.csd _tx_n:1 5 scb[1] .uart_ cts:0 scb[1]. spi_se lect0:0 sdhc[0]. card_da t_3to0[3 ] P2.4 tcpwm[0]. line[0]:5 tcpwm[1] .line[17]: 1 csd.csd _tx:16 csd.csd _tx_n:1 6 scb[9] .uart_ rx:0 scb[9]. i2c_scl :0 scb[1]. spi_se lect1:0 sdhc[0]. card_c md P2.5 tcpwm[0]. line_com pl[0]:5 tcpwm[1] .line_co mpl[17]:1 csd.csd _tx:17 csd.csd _tx_n:1 7 scb[9] .uart_ tx:0 scb[9]. i2c_sd a:0 scb[1]. spi_se lect2:0 sdhc[0]. clk_card P2.6 tcpwm[0]. line[1]:5 tcpwm[1] .line[18]: 1 csd.csd _tx:18 csd.csd _tx_n:1 8 scb[9] .uart_ rts:0 scb[1]. spi_se lect3:0 sdhc[0]. card_de tect_n P2.7 tcpwm[0]. line_com pl[1]:5 tcpwm[1] .line_co mpl[18]:1 csd.csd _tx:19 csd.csd _tx_n:1 9 scb[9] .uart_ cts:0 P3.0 tcpwm[0]. line[2]:5 tcpwm[1] .line[19]: 1 csd.csd _tx:20 csd.csd _tx_n:2 0 scb[2] .uart_ rx:1 Document Number: 002-23185 Rev. *R scb[7] .uart_ cts:0 ACT #13 ACT #14 ACT #0 ACT #15 DS #5 DS #6 scb[7]. spi_se lect0:0 sdhc[0]. card_m ech_writ e_prot scb[2]. i2c_scl :1 scb[2]. spi_m osi:1 peri.tr _io_in put[6]: 0 sdhc[0].i o_volt_s el Page 29 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 8. Multiple Alternate Functions (continued) Port/ Pin ACT #6 ACT #7 ACT #8 csd.csd _tx_n:2 1 scb[2] .uart_ tx:1 scb[2]. i2c_sd a:1 scb[2]. spi_mi so:1 csd.csd _tx:22 csd.csd _tx_n:2 2 scb[2] .uart_ rts:1 scb[2]. spi_cl k:1 tcpwm[1] .line_co mpl[20]:1 csd.csd _tx:23 csd.csd _tx_n:2 3 scb[2] .uart_ cts:1 scb[2]. spi_se lect0:1 tcpwm[0]. line[4]:5 tcpwm[1] .line[21]: 1 csd.csd _tx:24 csd.csd _tx_n:2 4 scb[2]. spi_se lect1:1 P3.5 tcpwm[0]. line_com pl[4]:5 tcpwm[1] .line_co mpl[21]:1 csd.csd _tx:25 csd.csd _tx_n:2 5 scb[2]. spi_se lect2:1 P4.0 tcpwm[0]. line[5]:5 tcpwm[1] .line[22]: 1 csd.csd _tx:26 csd.csd _tx_n:2 6 scb[7] .uart_ rx:1 scb[7]. i2c_scl :1 scb[7]. spi_m osi:1 peri.tr _io_in put[8]: 0 P4.1 tcpwm[0]. line_com pl[5]:5 tcpwm[1] .line_co mpl[22]:1 csd.csd _tx:27 csd.csd _tx_n:2 7 scb[7] .uart_ tx:1 scb[7]. i2c_sd a:1 scb[7]. spi_mi so:1 peri.tr _io_in put[9]: 0 P4.2 tcpwm[0]. line[6]:5 tcpwm[1] .line[23]: 1 csd.csd _tx:28 csd.csd _tx_n:2 8 scb[7] .uart_ rts:1 scb[7]. spi_cl k:1 P4.3 tcpwm[0]. line_com pl[6]:5 tcpwm[1] .line_co mpl[23]:1 csd.csd _tx:29 csd.csd _tx_n:2 9 scb[7] .uart_ cts:1 scb[7]. spi_se lect0:1 P5.0 tcpwm[0]. line[4]:0 tcpwm[1] .line[4]:0 csd.csd _tx:30 csd.csd _tx_n:3 0 scb[5] .uart_ rx:0 scb[5]. i2c_scl :0 scb[5]. spi_m osi:0 tcpwm[0]. line_com pl[4]:0 tcpwm[1] .line_co mpl[4]:0 csd.csd _tx:31 csd.csd _tx_n:3 1 scb[5] .uart_ tx:0 scb[5]. i2c_sd a:0 scb[5]. spi_mi so:0 P5.2 tcpwm[0]. line[5]:0 tcpwm[1] .line[5]:0 csd.csd _tx:32 csd.csd _tx_n:3 2 scb[5] .uart_ rts:0 scb[5]. spi_cl k:0 audioss [0].tx_w s:0 P5.3 tcpwm[0]. line_com pl[5]:0 tcpwm[1] .line_co mpl[5]:0 csd.csd _tx:33 csd.csd _tx_n:3 3 scb[5] .uart_ cts:0 scb[5]. spi_se lect0:0 audioss [0].tx_s do:0 ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3 P3.1 tcpwm[0]. line_com pl[2]:5 tcpwm[1] .line_co mpl[19]:1 csd.csd _tx:21 P3.2 tcpwm[0]. line[3]:5 tcpwm[1] .line[20]: 1 P3.3 tcpwm[0]. line_com pl[3]:5 P3.4 P5.1 Document Number: 002-23185 Rev. *R ACT #4 ACT #5 ACT #9 ACT #10 ACT #12 peri.tr _io_in put[7]: 0 audioss [0].clk_i 2s_if:0 peri.tr _io_in put[10 ]:0 audioss [0].tx_s ck:0 peri.tr _io_in put[11 ]:0 ACT #13 ACT #14 ACT #15 DS #5 DS #6 sdhc[0]. card_if_ pwr_en Page 30 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 8. Multiple Alternate Functions (continued) Port/ Pin ACT #6 ACT #7 ACT #8 csd.csd _tx_n:3 4 scb[1 0].uar t_rx:0 scb[10 ].i2c_s cl:0 scb[5]. spi_se lect1:0 audioss [0].rx_s ck:0 csd.csd _tx:35 csd.csd _tx_n:3 5 scb[1 0].uar t_tx:0 scb[10 ].i2c_s da:0 scb[5]. spi_se lect2:0 audioss [0].rx_w s:0 tcpwm[1] .line[7]:0 csd.csd _tx:36 csd.csd _tx_n:3 6 scb[1 0].uar t_rts: 0 scb[5]. spi_se lect3:0 tcpwm[0]. line_com pl[7]:0 tcpwm[1] .line_co mpl[7]:0 csd.csd _tx:37 csd.csd _tx_n:3 7 scb[1 0].uar t_cts: 0 scb[3]. spi_se lect3:0 P6.0 tcpwm[0]. line[0]:1 tcpwm[1] .line[8]:0 csd.csd _tx:38 csd.csd _tx_n:3 8 scb[8]. i2c_scl :0 scb[3] .uart_ rx:0 scb[3]. i2c_scl :0 scb[3]. spi_m osi:0 cpuss.faul t_out[0] scb[8] .spi_ mosi: 0 P6.1 tcpwm[0]. line_com pl[0]:1 tcpwm[1] .line_co mpl[8]:0 csd.csd _tx:39 csd.csd _tx_n:3 9 scb[8]. i2c_sd a:0 scb[3] .uart_ tx:0 scb[3]. i2c_sd a:0 scb[3]. spi_mi so:0 cpuss.faul t_out[1] scb[8] .spi_ miso: 0 P6.2 tcpwm[0]. line[1]:1 tcpwm[1] .line[9]:0 csd.csd _tx:40 csd.csd _tx_n:4 0 scb[3] .uart_ rts:0 scb[3]. spi_cl k:0 scb[8] .spi_c lk:0 P6.3 tcpwm[0]. line_com pl[1]:1 tcpwm[1] .line_co mpl[9]:0 csd.csd _tx:41 csd.csd _tx_n:4 1 scb[3] .uart_ cts:0 scb[3]. spi_se lect0:0 scb[8] .spi_s elect0 :0 P6.4 tcpwm[0]. line[2]:1 tcpwm[1] .line[10]: 0 csd.csd _tx:42 csd.csd _tx_n:4 2 scb[8]. i2c_scl :1 scb[6] .uart_ rx:2 scb[6]. i2c_scl :2 scb[6]. spi_m osi:2 peri.tr _io_in put[12 ]:0 peri.tr_io_ output[0]:1 cpuss. swj_s wo_td o scb[8] .spi_ mosi: 1 P6.5 tcpwm[0]. line_com pl[2]:1 tcpwm[1] .line_co mpl[10]:0 csd.csd _tx:43 csd.csd _tx_n:4 3 scb[8]. i2c_sd a:1 scb[6] .uart_ tx:2 scb[6]. i2c_sd a:2 scb[6]. spi_mi so:2 peri.tr _io_in put[13 ]:0 peri.tr_io_ output[1]:1 cpuss. swj_s wdoe_ tdi scb[8] .spi_ miso: 1 P6.6 tcpwm[0]. line[3]:1 tcpwm[1] .line[11]: 0 csd.csd _tx:44 csd.csd _tx_n:4 4 scb[6] .uart_ rts:2 scb[6]. spi_cl k:2 cpuss. swj_s wdio_t ms scb[8] .spi_c lk:1 P6.7 tcpwm[0]. line_com pl[3]:1 tcpwm[1] .line_co mpl[11]:0 csd.csd _tx:45 csd.csd _tx_n:4 5 scb[6] .uart_ cts:2 scb[6]. spi_se lect0:2 cpuss. swj_s wclk_t clk scb[8] .spi_s elect0 :1 ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3 P5.4 tcpwm[0]. line[6]:0 tcpwm[1] .line[6]:0 csd.csd _tx:34 P5.5 tcpwm[0]. line_com pl[6]:0 tcpwm[1] .line_co mpl[6]:0 P5.6 tcpwm[0]. line[7]:0 P5.7 Document Number: 002-23185 Rev. *R ACT #4 ACT #5 ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15 DS #5 DS #6 audioss [0].rx_s di:0 Page 31 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 8. Multiple Alternate Functions (continued) Port/ Pin ACT #6 ACT #7 ACT #8 csd.csd _tx_n:4 6 scb[4] .uart_ rx:1 scb[4]. i2c_scl :1 scb[4]. spi_m osi:1 peri.tr _io_in put[14 ]:0 csd.csd _tx:47 csd.csd _tx_n:4 7 scb[4] .uart_ tx:1 scb[4]. i2c_sd a:1 scb[4]. spi_mi so:1 peri.tr _io_in put[15 ]:0 tcpwm[1] .line[13]: 0 csd.csd _tx:48 csd.csd _tx_n:4 8 scb[4] .uart_ rts:1 scb[4]. spi_cl k:1 tcpwm[0]. line_com pl[5]:1 tcpwm[1] .line_co mpl[13]:0 csd.csd _tx:49 csd.csd _tx_n:4 9 scb[4] .uart_ cts:1 scb[4]. spi_se lect0:1 P7.4 tcpwm[0]. line[6]:1 tcpwm[1] .line[14]: 0 csd.csd _tx:50 csd.csd _tx_n:5 0 scb[4]. spi_se lect1:1 cpuss.tr ace_da ta[3]:2 P7.5 tcpwm[0]. line_com pl[6]:1 tcpwm[1] .line_co mpl[14]:0 csd.csd _tx:51 csd.csd _tx_n:5 1 scb[4]. spi_se lect2:1 cpuss.tr ace_da ta[2]:2 P7.6 tcpwm[0]. line[7]:1 tcpwm[1] .line[15]: 0 csd.csd _tx:52 csd.csd _tx_n:5 2 scb[4]. spi_se lect3:1 cpuss.tr ace_da ta[1]:2 P7.7 tcpwm[0]. line_com pl[7]:1 tcpwm[1] .line_co mpl[15]:0 csd.csd _tx:53 csd.csd _tx_n:5 3 scb[3]. spi_se lect1:0 P8.0 tcpwm[0]. line[0]:2 tcpwm[1] .line[16]: 0 csd.csd _tx:54 csd.csd _tx_n:5 4 scb[4] .uart_ rx:0 scb[4]. i2c_scl :0 scb[4]. spi_m osi:0 peri.tr _io_in put[16 ]:0 P8.1 tcpwm[0]. line_com pl[0]:2 tcpwm[1] .line_co mpl[16]:0 csd.csd _tx:55 csd.csd _tx_n:5 5 scb[4] .uart_ tx:0 scb[4]. i2c_sd a:0 scb[4]. spi_mi so:0 peri.tr _io_in put[17 ]:0 P8.2 tcpwm[0]. line[1]:2 tcpwm[1] .line[17]: 0 csd.csd _tx:56 csd.csd _tx_n:5 6 lpcom p.dsi_ comp 0:0 scb[4] .uart_ rts:0 scb[4]. spi_cl k:0 P8.3 tcpwm[0]. line_com pl[1]:2 tcpwm[1] .line_co mpl[17]:0 csd.csd _tx:57 csd.csd _tx_n:5 7 lpcom p.dsi_ comp 1:0 scb[4] .uart_ cts:0 scb[4]. spi_se lect0:0 ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3 P7.0 tcpwm[0]. line[4]:1 tcpwm[1] .line[12]: 0 csd.csd _tx:46 P7.1 tcpwm[0]. line_com pl[4]:1 tcpwm[1] .line_co mpl[12]:0 P7.2 tcpwm[0]. line[5]:1 P7.3 Document Number: 002-23185 Rev. *R ACT #4 ACT #5 ACT #9 ACT #10 ACT #12 cpuss. clk_fm _pum p ACT #13 ACT #14 ACT #15 DS #5 DS #6 cpuss.tr ace_clo ck cpuss.tr ace_da ta[0]:2 Page 32 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 8. Multiple Alternate Functions (continued) Port/ Pin ACT #6 ACT #7 ACT #8 csd.csd _tx_n:5 8 scb[1 1].uar t_rx:0 scb[11 ].i2c_s cl:0 scb[4]. spi_se lect1:0 csd.csd _tx:59 csd.csd _tx_n:5 9 scb[1 1].uar t_tx:0 scb[11 ].i2c_s da:0 scb[4]. spi_se lect2:0 tcpwm[1] .line[19]: 0 csd.csd _tx:60 csd.csd _tx_n:6 0 scb[1 1].uar t_rts: 0 scb[4]. spi_se lect3:0 tcpwm[0]. line_com pl[3]:2 tcpwm[1] .line_co mpl[19]:0 csd.csd _tx:61 csd.csd _tx_n:6 1 scb[1 1].uar t_cts: 0 scb[3]. spi_se lect2:0 tcpwm[0]. line[4]:2 tcpwm[1] .line[20]: 0 csd.csd _tx:62 csd.csd _tx_n:6 2 scb[2] .uart_ rx:0 scb[2]. i2c_scl :0 scb[2]. spi_m osi:0 tcpwm[0]. line_com pl[4]:2 tcpwm[1] .line_co mpl[20]:0 csd.csd _tx:63 csd.csd _tx_n:6 3 scb[2] .uart_ tx:0 scb[2]. i2c_sd a:0 scb[2]. spi_mi so:0 P9.2 tcpwm[0]. line[5]:2 tcpwm[1] .line[21]: 0 csd.csd _tx:64 csd.csd _tx_n:6 4 scb[2] .uart_ rts:0 scb[2]. spi_cl k:0 audioss [0].tx_w s:1 cpuss.tr ace_da ta[1]:0 P9.3 tcpwm[0]. line_com pl[5]:2 tcpwm[1] .line_co mpl[21]:0 csd.csd _tx:65 csd.csd _tx_n:6 5 scb[2] .uart_ cts:0 scb[2]. spi_se lect0:0 audioss [0].tx_s do:1 cpuss.tr ace_da ta[0]:0 P9.4 tcpwm[0]. line[7]:5 tcpwm[1] .line[0]:2 csd.csd _tx:66 csd.csd _tx_n:6 6 scb[2]. spi_se lect1:0 audioss [0].rx_s ck:1 P9.5 tcpwm[0]. line_com pl[7]:5 tcpwm[1] .line_co mpl[0]:2 csd.csd _tx:67 csd.csd _tx_n:6 7 scb[2]. spi_se lect2:0 audioss [0].rx_w s:1 P9.6 tcpwm[0]. line[0]:6 tcpwm[1] .line[1]:2 csd.csd _tx:68 csd.csd _tx_n:6 8 scb[2]. spi_se lect3:0 audioss [0].rx_s di:1 P9.7 tcpwm[0]. line_com pl[0]:6 tcpwm[1] .line_co mpl[1]:2 csd.csd _tx:69 csd.csd _tx_n:6 9 P10.0 tcpwm[0]. line[6]:2 tcpwm[1] .line[22]: 0 csd.csd _tx:70 csd.csd _tx_n:7 0 ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3 P8.4 tcpwm[0]. line[2]:2 tcpwm[1] .line[18]: 0 csd.csd _tx:58 P8.5 tcpwm[0]. line_com pl[2]:2 tcpwm[1] .line_co mpl[18]:0 P8.6 tcpwm[0]. line[3]:2 P8.7 P9.0 P9.1 Document Number: 002-23185 Rev. *R ACT #4 ACT #5 scb[1] .uart_ rx:1 scb[1]. i2c_scl :1 scb[1]. spi_m osi:1 ACT #9 ACT #10 ACT #12 audioss [0].clk_i 2s_if:1 peri.tr _io_in put[18 ]:0 cpuss.tr ace_da ta[3]:0 audioss [0].tx_s ck:1 peri.tr _io_in put[19 ]:0 cpuss.tr ace_da ta[2]:0 peri.tr _io_in put[20 ]:0 ACT #13 ACT #14 ACT #15 DS #5 DS #6 cpuss.tr ace_da ta[3]:1 Page 33 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 8. Multiple Alternate Functions (continued) Port/ Pin ACT #6 ACT #7 ACT #8 csd.csd _tx_n:7 1 scb[1] .uart_ tx:1 scb[1]. i2c_sd a:1 scb[1]. spi_mi so:1 csd.csd _tx:72 csd.csd _tx_n:7 2 scb[1] .uart_ rts:1 scb[1]. spi_cl k:1 cpuss.tr ace_da ta[1]:1 tcpwm[1] .line_co mpl[23]:0 csd.csd _tx:73 csd.csd _tx_n:7 3 scb[1] .uart_ cts:1 scb[1]. spi_se lect0:1 cpuss.tr ace_da ta[0]:1 tcpwm[0]. line[0]:3 tcpwm[1] .line[0]:1 csd.csd _tx:74 csd.csd _tx_n:7 4 scb[1]. spi_se lect1:1 audios s[0].p dm_cl k:0 P10.5 tcpwm[0]. line_com pl[0]:3 tcpwm[1] .line_co mpl[0]:1 csd.csd _tx:75 csd.csd _tx_n:7 5 scb[1]. spi_se lect2:1 audios s[0].p dm_d ata:0 P10.6 tcpwm[0]. line[1]:6 tcpwm[1] .line[2]:2 csd.csd _tx:76 csd.csd _tx_n:7 6 scb[1]. spi_se lect3:1 P10.7 tcpwm[0]. line_com pl[1]:6 tcpwm[1] .line_co mpl[2]:2 csd.csd _tx:77 csd.csd _tx_n:7 7 P11.0 tcpwm[0]. line[1]:3 tcpwm[1] .line[1]:1 csd.csd _tx:78 csd.csd _tx_n:7 8 smif. spi_s elect 2 scb[5] .uart_ rx:1 scb[5]. i2c_scl :1 scb[5]. spi_m osi:1 audioss [1].clk_i 2s_if:1 peri.tr _io_in put[22 ]:0 P11.1 tcpwm[0]. line_com pl[1]:3 tcpwm[1] .line_co mpl[1]:1 csd.csd _tx:79 csd.csd _tx_n:7 9 smif. spi_s elect 1 scb[5] .uart_ tx:1 scb[5]. i2c_sd a:1 scb[5]. spi_mi so:1 audioss [1].tx_s ck:1 peri.tr _io_in put[23 ]:0 P11.2 tcpwm[0]. line[2]:3 tcpwm[1] .line[2]:1 csd.csd _tx:80 csd.csd _tx_n:8 0 smif. spi_s elect 0 scb[5] .uart_ rts:1 scb[5]. spi_cl k:1 audioss [1].tx_w s:1 P11.3 tcpwm[0]. line_com pl[2]:3 tcpwm[1] .line_co mpl[2]:1 csd.csd _tx:81 csd.csd _tx_n:8 1 smif. spi_ data 3 scb[5] .uart_ cts:1 scb[5]. spi_se lect0:1 audioss [1].tx_s do:1 peri.tr_io_ output[0]:0 P11.4 tcpwm[0]. line[3]:3 tcpwm[1] .line[3]:1 csd.csd _tx:82 csd.csd _tx_n:8 2 smif. spi_ data 2 scb[5]. spi_se lect1:1 audioss [1].rx_s ck:1 peri.tr_io_ output[1]:0 ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3 P10.1 tcpwm[0]. line_com pl[6]:2 tcpwm[1] .line_co mpl[22]:0 csd.csd _tx:71 P10.2 tcpwm[0]. line[7]:2 tcpwm[1] .line[23]: 0 P10.3 tcpwm[0]. line_com pl[7]:2 P10.4 Document Number: 002-23185 Rev. *R ACT #4 ACT #5 ACT #9 ACT #10 ACT #12 ACT #13 peri.tr _io_in put[21 ]:0 ACT #14 ACT #15 DS #5 DS #6 cpuss.tr ace_da ta[2]:1 Page 34 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 8. Multiple Alternate Functions (continued) Port/ Pin P11.5 ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3 tcpwm[0]. line_com pl[3]:3 tcpwm[1] .line_co mpl[3]:1 P11.6 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 csd.csd _tx:83 csd.csd _tx_n:8 3 smif. spi_ data 1 scb[5]. spi_se lect2:1 audioss [1].rx_w s:1 csd.csd _tx:84 csd.csd _tx_n:8 4 smif. spi_ data 0 scb[5]. spi_se lect3:1 audioss [1].rx_s di:1 P11.7 ACT #12 ACT #13 ACT #14 ACT #15 DS #5 DS #6 smif. spi_c lk P12.0 tcpwm[0]. line[4]:3 tcpwm[1] .line[4]:1 csd.csd _tx:85 csd.csd _tx_n:8 5 smif. spi_ data 4 scb[6] .uart_ rx:0 scb[6]. i2c_scl :0 scb[6]. spi_m osi:0 peri.tr _io_in put[24 ]:0 sdhc[1]. card_e mmc_re set_n P12.1 tcpwm[0]. line_com pl[4]:3 tcpwm[1] .line_co mpl[4]:1 csd.csd _tx:86 csd.csd _tx_n:8 6 smif. spi_ data 5 scb[6] .uart_ tx:0 scb[6]. i2c_sd a:0 scb[6]. spi_mi so:0 peri.tr _io_in put[25 ]:0 sdhc[1]. card_de tect_n P12.2 tcpwm[0]. line[5]:3 tcpwm[1] .line[5]:1 csd.csd _tx:87 csd.csd _tx_n:8 7 smif. spi_ data 6 scb[6] .uart_ rts:0 scb[6]. spi_cl k:0 sdhc[1]. card_m ech_writ e_prot P12.3 tcpwm[0]. line_com pl[5]:3 tcpwm[1] .line_co mpl[5]:1 csd.csd _tx:88 csd.csd _tx_n:8 8 smif. spi_ data 7 scb[6] .uart_ cts:0 scb[6]. spi_se lect0:0 sdhc[1].l ed_ctrl P12.4 tcpwm[0]. line[6]:3 tcpwm[1] .line[6]:1 csd.csd _tx:89 csd.csd _tx_n:8 9 smif. spi_s elect 3 P12.5 tcpwm[0]. line_com pl[6]:3 tcpwm[1] .line_co mpl[6]:1 csd.csd _tx:90 P12.6 tcpwm[0]. line[7]:3 tcpwm[1] .line[7]:1 P12.7 tcpwm[0]. line_com pl[7]:3 P13.0 tcpwm[0]. line[0]:4 scb[6]. spi_se lect1:0 audios s[0].p dm_cl k:1 sdhc[1]. card_c md csd.csd _tx_n:9 0 scb[6]. spi_se lect2:0 audios s[0].p dm_d ata:1 sdhc[1]. clk_card csd.csd _tx:91 csd.csd _tx_n:9 1 scb[6]. spi_se lect3:0 tcpwm[1] .line_co mpl[7]:1 csd.csd _tx:92 csd.csd _tx_n:9 2 tcpwm[1] .line[8]:1 csd.csd _tx:93 csd.csd _tx_n:9 3 Document Number: 002-23185 Rev. *R sdhc[1]. card_if_ pwr_en sdhc[1].i o_volt_s el scb[6] .uart_ rx:1 scb[6]. i2c_scl :1 scb[6]. spi_m osi:1 audioss [1].clk_i 2s_if:0 peri.tr _io_in put[26 ]:0 sdhc[1]. card_da t_3to0[0 ] Page 35 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 8. Multiple Alternate Functions (continued) Port/ Pin P13.1 P13.2 P13.3 P13.4 P13.5 P13.6 P13.7 ACT #6 ACT #7 ACT #8 csd.csd _tx_n:9 4 scb[6] .uart_ tx:1 scb[6]. i2c_sd a:1 scb[6]. spi_mi so:1 csd.csd _tx:95 csd.csd _tx_n:9 5 scb[6] .uart_ rts:1 scb[6]. spi_cl k:1 tcpwm[1] .line_co mpl[9]:1 csd.csd _tx:96 csd.csd _tx_n:9 6 scb[6] .uart_ cts:1 scb[6]. spi_se lect0:1 tcpwm[0]. line[2]:4 tcpwm[1] .line[10]: 1 csd.csd _tx:97 csd.csd _tx_n:9 7 scb[1 2].uar t_rx:0 scb[12 ].i2c_s cl:0 scb[6]. spi_se lect1:1 tcpwm[0]. line_com pl[2]:4 tcpwm[1] .line_co mpl[10]:1 csd.csd _tx:98 csd.csd _tx_n:9 8 scb[1 2].uar t_tx:0 scb[12 ].i2c_s da:0 scb[6]. spi_se lect2:1 tcpwm[0]. line[3]:4 tcpwm[1] .line[11]: 1 csd.csd _tx:99 csd.csd _tx_n:9 9 scb[1 2].uar t_rts: 0 tcpwm[0]. line_com pl[3]:4 tcpwm[1] .line_co mpl[11]:1 csd.csd _tx:100 csd.csd _tx_n:1 00 scb[1 2].uar t_cts: 0 ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3 tcpwm[0]. line_com pl[0]:4 tcpwm[1] .line_co mpl[8]:1 csd.csd _tx:94 tcpwm[0]. line[1]:4 tcpwm[1] .line[9]:1 tcpwm[0]. line_com pl[1]:4 Document Number: 002-23185 Rev. *R ACT #4 ACT #5 scb[6]. spi_se lect3:1 ACT #9 ACT #10 ACT #12 audioss [1].tx_s ck:0 peri.tr _io_in put[27 ]:0 ACT #13 ACT #14 ACT #15 DS #5 DS #6 sdhc[1]. card_da t_3to0[1 ] audioss [1].tx_w s:0 sdhc[1]. card_da t_3to0[2 ] audioss [1].tx_s do:0 sdhc[1]. card_da t_3to0[3 ] audioss [1].rx_s ck:0 sdhc[1]. card_da t_7to4[0 ] audioss [1].rx_w s:0 sdhc[1]. card_da t_7to4[1 ] audioss [1].rx_s di:0 sdhc[1]. card_da t_7to4[2 ] sdhc[1]. card_da t_7to4[3 ] Page 36 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Analog and Smart I/O alternate port pin functionality is provided in Table 9. Table 9. Port Pin Analog, Digital, and Smart I/O Functions Port/Pin Analog P0.0 wco_in P0.1 P5.6 P5.7 P6.2 P6.3 P6.6 P6.7 P7.2 P7.3 P7.7 P9.7 P10.0 P10.1 P10.2 P10.3 P10.4 P10.5 P10.6 P10.7 P12.6 P12.7 wco_out lpcomp.inp_comp0 lpcomp.inn_comp0 lpcomp.inp_comp1 lpcomp.inn_comp1 swd_data swd_clk csd.csh_tank csd.vref_ext csd.shield aref_ext_vref sarmux_pads[0] sarmux_pads[1] sarmux_pads[2] sarmux_pads[3] sarmux_pads[4] sarmux_pads[5] sarmux_pads[6] sarmux_pads[7] eco_in eco_out Document Number: 002-23185 Rev. *R Table 9. Port Pin Analog, Digital, and Smart I/O Functions Port/Pin Digital P0.4 P1.4 P0.5 Port/Pin pmic_wakeup_in hibernate_wakeup[1] hibernate_wakeup[0] pmic_wakeup_out SMARTIO P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 P9.0 P9.1 P9.2 P9.3 P9.4 P9.5 P9.6 P9.7 smartio[8].io[0] smartio[8].io[1] smartio[8].io[2] smartio[8].io[3] smartio[8].io[4] smartio[8].io[5] smartio[8].io[6] smartio[8].io[7] smartio[9].io[0] smartio[9].io[1] smartio[9].io[2] smartio[9].io[3] smartio[9].io[4] smartio[9].io[5] smartio[9].io[6] smartio[9].io[7] Page 37 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Power Supply Considerations The following power system diagrams show typical connections for power pins for all supported packages and with and without usage of the buck regulator. In these diagrams, the package pin is shown with the pin name, for example "VDDA, A12". For VDDx pins, the I/O port that is powered by that pin is also shown, for example "VDDD, A1; I/O port P1". Figure 11. 128-TQFP Power Connection Diagram 1.7 to 3.6 V CY8C62x8/A, 128-TQFP package 1 KΩ at 100 MHz 1 KΩ at 100 MHz 1 KΩ at 100 MHz 10 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 10 µF 0.1 µF VDDD , 6; I/O port P1 VDD_NS, 23 VBACKUP, 9; I/O port P0 0.1 µF 10 µF V IND1, 24 2.2 µH VDDIO0, 114; I/O ports P11, P12, P13 V CCD, 4, 5 VDDIO1, 68; I/O ports P5, P6, P7, P8 4.7 µF VDDIO2, 39; I/O ports P2, P3, P4 VDDUSB , 27; I/O port P14 VDDA, 96 VDDIOA, 69; I/O ports P9, P10 7, 8, 25, 26, 36, 40, 67, 70, 95, 115 V SS Document Number: 002-23185 Rev. *R Page 38 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 12. 128-TQFP (No Buck) Power Connection Diagram 1.7 to 3.6 V CY8C62x8/A, 128-TQFP package 1 KΩ at 100 MHz 1 KΩ at 100 MHz 10 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 10 µF 0.1 µF VDDD , 6; I/O port P1 VDD_NS, 23 VBACKUP, 9; I/O port P0 VIND1, 24 VDDIO0, 114; I/O ports P11, P12, P13 VCCD, 4, 5 VDDIO1, 68; I/O ports P5, P6, P7, P8 4.7 µF VDDIO2, 39; I/O ports P2, P3, P4 VDDUSB , 27; I/O port P14 VDDA , 96 VDDIOA, 69; I/O ports P9, P10 7, 8, 25, 26, 36, 40, 67, 70, 95, 115 VSS Document Number: 002-23185 Rev. *R Page 39 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 13. 124-BGA Power Connection Diagram 1.7 to 3.6 V CY8C62x8/A, 124-BGA package 1 KΩ at 100 MHz 10 µF 0.1 µF 1 µF 0.1 µF 1 µF 1 KΩ at 100 MHz 1 KΩ at 100 MHz 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 10 µF 0.1 µF VDDD , A1; I/O port P1 VDD_NS, J1 VBACKUP, D1; I/O port P0 0.1 µF 10 µF V IND1, J2 2.2 µH VDDIO0, C4; I/O ports P11, P12, P13 V CCD, A2 VDDIO1, K12; I/O ports P5, P6, P7, P8 4.7 µF VDDIO2, L4; I/O ports P2, P3, P4 VDDUSB , M1; I/O port P14 VDDA, A12 VDDIOA, A13; I/O ports P9, P10 B12, C3, D4, D10, K4, K10 VSS Document Number: 002-23185 Rev. *R Page 40 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 14. 124-BGA (No Buck) Power Connection Diagram 1.7 to 3.6 V CY8C62x8/A, 124-BGA package 1 KΩ at 100 MHz 1 KΩ at 100 MHz 10 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 10 µF 0.1 µF VDDD , A1; I/O port P1 VDD_NS , J1 VBACKUP, D1; I/O port P0 VIND1 , J2 VDDIO0, C4; I/O ports P11, P12, P13 VCCD , A2 VDDIO1, K12; I/O ports P5, P6, P7, P8 4.7 µF VDDIO2, L4; I/O ports P2, P3, P4 VDDUSB , M1; I/O port P14 VDDA , A12 VDDIOA, A13; I/O ports P9, P10 B12, C3, D4, D10, K4, K10 VSS Document Number: 002-23185 Rev. *R Page 41 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 15. 100-WLCSP Power Connection Diagram 1.7 to 3.6 V CY8C62x8/A, 100-WLCSP package 1 KΩ at 100 MHz 10 µF 0.1 µF 1 µF 0.1 µF 1 µF 1 KΩ at 100 MHz 1 KΩ at 100 MHz 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 10 µF 0.1 µF VDDD , D14; I/O port P1 VDD_NS, J15 VBACKUP, C17; I/O port P0 0.1 µF 10 µF VIND1, H16 2.2 µH VDDIO0, A11; I/O ports P11, P12, P13 VCCD , C15 VDDIO1, K2; I/O ports P5, P6, P7, P8 4.7 µF VDDIO2, M10; I/O port P2 VDDUSB , J17; I/O port P14 VDDA, J1; I/O ports P9, P10 D2, E13, J13, L1 VSS Document Number: 002-23185 Rev. *R Page 42 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 16. 100-WLCSP (No Buck) Power Connection Diagram 1.7 to 3.6 V CY8C62x8/A, 100-WLCSP package 1 KΩ at 100 MHz 1 KΩ at 100 MHz 10 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 10 µF 0.1 µF VDDD, D14; I/O port P1 VDD_NS, J15 VBACKUP, C17; I/O port P0 VIND1 , H16 VDDIO0, A11; I/O ports P11, P12, P13 VCCD, C15 VDDIO1, K2; I/O ports P5, P6, P7, P8 4.7 µF VDDIO2 , M10; I/O port P2 VDDUSB , J17; I/O port P14 V DDA, J1; I/O ports P9, P10 D2, E13, J13, L1 V SS In the QFN package, all internal grounds are routed to the metal pad (epad) in the package. This pad must be grounded on the PCB. Document Number: 002-23185 Rev. *R Page 43 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 17. 68-QFN Power Connection Diagram 1.7 to 3.6 V CY8C62x8/A, 68-QFN package 1 KΩ at 100 MHz 1 KΩ at 100 MHz 10 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 10 µF 0.1 µF 1 KΩ at 100 MHz VDDD, 68 VDD_NS, 9 VBACKUP, 1; I/O port P0 0.1 µF 10 µF VIND1, 10 2.2 µH VDDIO0, 64; I/O ports P11, P12 VCCD, 67 4.7 µF VDDIO1, 35; I/O ports P5, P6, P7, P8 VDDIO2, 22; I/O ports P2, P3 VDDUSB, 11; I/O port P14 VDDA, 36 VDDIOA, 48; I/O ports P9, P10 GND PAD Figure 18. 68-QFN (No Buck) Power Connection Diagram 1.7 to 3.6 V CY8C62x8/A, 68-QFN package 1 KΩ at 100 MHz 1 KΩ at 100 MHz 10 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 10 µF 0.1 µF VDDD, 68 VDD_NS, 9 VBACKUP, 1; I/O port P0 VIND1, 10 VDDIO0, 64; I/O ports P11, P12 VCCD, 67 VDDIO1, 35; I/O ports P5, P6, P7, P8 4.7 µF VDDIO2, 22; I/O ports P2, P3 VDDUSB, 11; I/O port P14 VDDA, 36 VDDIOA, 48; I/O ports P9, P10 GND PAD Document Number: 002-23185 Rev. *R Page 44 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet There are as many as eight VDDx supply pins, depending on the package, and multiple VSS ground pins. The power pins are: ■ VDDD: the main digital supply. It powers the low dropout (LDO) regulators and I/O port 1 ■ VCCD: the main LDO output. It requires a 4.7-µF capacitor for regulation. The LDO can be turned off when VCCD is driven from the switching regulator (see below). For more information, see the power system block diagram in the device technical reference manual (TRM). ■ VDDA: the supply for the analog peripherals. Voltage must be applied to this pin for correct device initialization and boot up. ■ VDDIOA: the supply for I/O ports 9 and 10. If it is present in the device package, it must be connected to VDDA. ■ VDDIO0: the supply for I/O ports 11, 12, and 13. ■ VDDIO1: the supply for I/O ports 5, 6, 7, and 8. ■ VDDIO2: the supply for I/O ports 2, 3, and 4. Some of the ports are not available depending on package. ■ VBACKUP: the supply for the backup domain, which includes the 32-kHz WCO and the RTC. It can be a separate supply as low as 1.4 V, for battery or supercapacitor backup, as Figure 19 shows, otherwise it is connected to VDDD. It powers I/O port 0. Figure 19. Separate Battery Connection to VBACKUP 1.7 to 3.6 V 1.4 to 3.6 V ■ 10 µF 0.1 µF 1 µF 0.1 µF VDDD VBACKUP VDDUSB: the supply for the USB peripheral and the USBDP and USBDM pins. It must be 2.85 V to 3.6 V for USB operation. If USB is not used, it can be 1.7 V to 3.6 V, and the USB pins can be used as limited-capability GPIOs on I/O port 14. Table 10 shows a summary of the I/O port supplies: Table 10. I/O Port Supplies Port Supply Alternate Supply 0 VBACKUP VDDD 1 VDDD - 2, 3, 4 VDDIO2 - 5, 6, 7, 8 VDDIO1 - 9, 10 VDDIOA VDDA 11, 12, 13 VDDIO0 - 14 VDDUSB - Document Number: 002-23185 Rev. *R Note: If the USB pins are not used, connect VDDUSB to ground and leave the P14.0/USBDP and P14.1/USBDM pins unconnected. Voltage must be applied to the VDDD pin, and the VDDA pin as noted above, for correct device initialization and operation. If an I/O port is not being used, applying voltage to the corresponding VDDx pin is optional. ■ VSS: ground pins for the above supplies. All ground pins should be connected together to a common ground. In addition to the LDO regulator, a switching regulator is included. The regulator pins are: ■ VDD_NS: the regulator supply. ■ VIND1: the regulator output. It is typically used to drive VCCD through an inductor. The VDD power pins are not connected on chip. They can be connected off chip, in one or more separate nets. If separate power nets are used, they can be isolated from noise from the other nets using optional ferrite beads, as indicated in the diagrams. No external load should be placed on VCCD, or VIND1, whether or not these pins are used. There are no power pin sequencing requirements; power supplies may be brought up in any order. The power management system holds the device in reset until all power pins are at the voltage levels required for proper operation. Note: If a battery is installed on the PCB first, VDDD must be cycled for at least 50 µs. This prevents premature drain of the battery during product manufacture and storage. Bypass capacitors must be connected to a common ground from the VDDx and other pins, as indicated in the diagrams. Typical practice for systems in this frequency range is to use a 10-µF or 1-µF capacitor in parallel with a smaller capacitor (0.1 µF, for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and bypass capacitor parasitic should be simulated for optimal bypassing. All capacitors and inductors should be ±20% or better. The recommended inductor value is 2.2 µH ±20% (for example, TDK MLP2012H2R2MT0S1). It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifications. With some capacitors, the actual capacitance can decrease considerably when the applied voltage is a significant percentage of the rated working voltage. For more information on pad layout, refer to PSoC 6 CAD libraries. Page 45 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Electrical Specifications All specifications are valid for –40 °C ≤ TA ≤ 85 °C and for 1.71 V to 3.6 V except where noted. Absolute Maximum Ratings Table 11. Absolute Maximum Ratings[3] Spec ID# Parameter Description Min Typ Max Units SID1 VDD_ABS Analog or digital supply relative to VSS (VSSD = VSSA) –0.5 – 4 V SID2 VCCD_ABS Direct digital core voltage input relative to VSSD –0.5 – 1.2 V SID3 VGPIO_ABS GPIO voltage; VDDD or VDDA –0.5 – VDD + 0.5 V SID4 IGPIO_ABS Current per GPIO –25 – 25 mA SID5 IGPIO_injection GPIO injection current per pin –0.5 – 0.5 mA SID3A ESD_HBM Electrostatic discharge Human Body Model 2200 – – V SID4A ESD_CDM Electrostatic discharge Charged Device Model 500 – – V SID5A LU Pin current for latchup-free operation –100 – 100 mA Details / Conditions Device-Level Specifications Table 14 provides detailed specifications of CPU current. Table 12 summarizes these specifications, for rapid review of CPU currents under common conditions. Note that the max frequency for CM4 is 150 MHz, and for CM0+ is 100 MHz. IMO and FLL are used to generate the CPU clocks; FLL is not used when the CPU clock frequency is 8 MHz. Table 12. CPU Current Specifications Summary Condition Range Typ Range Max Range LP Mode, VDDD = 3.3 V, VCCD = 1.1 V, with buck regulator CM4 active, CM0+ sleep CM0+ active, CM4 sleep CM4 sleep, CM0+ sleep Across CPUs clock ranges: 8 – 150/100 MHz; Dhrystone with flash cache enabled CM0+ sleep, CM4 off Minimum regulator current mode Across CM4/CM0+ CPU active/sleep modes 0.9–7.35 mA 2–9.5 mA 0.8–4.4 mA 2–5.8 mA 0.7–1.55 mA 1.3–2.2 mA 0.7–1.3 mA 1.3–2 mA 0.64–0.85 mA 1.2–1.5 mA 0.65–1.85 mA 1.2–2.5 mA ULP Mode, VDDD = 3.3 V, VCCD = 0.9 V, with buck regulator CM4 active, CM0+ sleep CM0+ active, CM4 sleep CM4 sleep, CM0+ sleep Across CPUs clock ranges: 8–50/25 MHz; Dhrystone with flash cache enabled CM0+ sleep, CM4 off Minimum regulator current mode Across CM4/CM0+ CPU active/sleep modes Deep Sleep Across SRAM retention Hibernate Across VDDD 0.55–1 mA 0.95–1.5 mA 0.45–0.85 mA 0.9–1.2 mA 0.41–0.62 mA 0.72–1.2 mA 0.4–0.55 mA 1–1 mA 7–9 µA - 300–2100 nA - Note 3. Usage above the absolute maximum conditions listed in Table 11 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Document Number: 002-23185 Rev. *R Page 46 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 20. Typical Device Currents vs. CPU Frequency; System Low Power (LP) Mode 8 CM4 Active, CM0+ Sleep 1/2 CM4 CM4 Active, CM0+ Sleep same as CM4 CM0+ Active, CM4 Sleep 7 IDDD, mA 6 5 4 3 2 1 0 0 25 50 75 CPU Clock, MHz 100 125 150 Power Supplies Table 13. Power Supply DC Specifications Spec ID# Parameter Description Min Typ Max Units Details / Conditions SID6 VDDD Internal regulator and Port 1 GPIO supply 1.7 – 3.6 V – SID7 VDDA Analog power supply voltage. Shorted to VDDIOA on PCB. 1.7 – 3.6 V Internally unregulated supply SID7A VDDIO1 GPIO supply for ports 5 to 8 when present 1.7 – 3.6 V Must be ≥ VDDA if the CapSense (CSD) block is used in the application SID7B VDDIO0 GPIO supply for ports 11 to 13 when present 1.7 – 3.6 V – SID7E VDDIO0 Supply for eFuse Programming 2.38 2.5 2.62 V – SID7C VDDIO2 GPIO supply for ports 2 to 4 when present 1.7 – 3.6 V – SID7D VDDIOA GPIO supply for ports 9 and 10 when present. Must be connected to VDDA on PCB. 1.7 – 3.6 V – SID7F VDDUSB Supply for port 14 (USB or GPIO) when present 1.7 – 3.6 V Min supply is 2.85 V for USB SID6B VBACKUP Backup power and GPIO Port 0 supply when present 1.7 – 3.6 V Min is 1.4 V when VDDD is removed SID8 VCCD1 Output voltage (for core logic bypass) – 1.1 – V System LP mode SID9 VCCD2 Output voltage (for core logic bypass) – 0.9 – SID10 CEFC External regulator voltage (VCCD) bypass 3.8 4.7 5.6 µF X5R ceramic or better. Value for 0.8 to 1.2 V. SID11 CEXC Power supply decoupling capacitor – 10 – µF X5R ceramic or better Document Number: 002-23185 Rev. *R ULP mode. Valid for –20 to 85 °C. Page 47 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet CPU Current and Transition Times Table 14. CPU Current and Transition Times Spec ID# Parameter Description Min Typ Max Units Details / Conditions LP RANGE POWER SPECIFICATIONS (for VCCD = 1.1 V with Buck and LDO) Cortex-M4. Active Mode Execute with Cache Disabled (Flash) SIDF1 SIDF2 IDD1 IDD2 Execute from Flash; CM4 Active 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. While(1). Execute from Flash; CM4 Active 8 MHz, CM0+ Sleep 8 MHz.With IMO. While(1). – – VDDD = 3.3 V, Buck ON, Max at 60 °C 2.85 4.5 4.1 5.1 6.8 10 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 0.9 2.1 VDDD = 3.3 V, Buck ON, Max at 60 °C 1.2 2.2 2.4 5.5 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 7.35 9.5 VDDD = 3.3 V, Buck ON, Max at 60 °C 12 14.5 18 21 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 5.4 6.8 VDDD = 3.3 V, Buck ON, Max at 60 °C 8.95 10 13.8 17 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 2.65 3.8 VDDD = 3.3 V, Buck ON, Max at 60 °C 4.25 5.3 6.8 10 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 0.9 2 VDDD = 3.3 V, Buck ON, Max at 60 °C 1.27 2.1 2.3 5.5 mA mA VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 V, Buck ON, Max at 60 °C Execute with Cache Enabled SIDC1 SIDC2 SIDC3 SIDC4 IDD3 IDD4 IDD5 IDD6 Execute from Cache;CM4 Active150 MHz, CM0+ Sleep 75 MHz. IMO & PLL. Dhrystone. Execute from Cache;CM4 Active100 MHz, CM0+ Sleep 100 MHz. IMO & FLL. Dhrystone. Execute from Cache;CM4 Active 50 MHz, CM0+ Sleep 25 MHz. IMO & FLL. Dhrystone. Execute from Cache;CM4 Active 8 MHz, CM0+ Sleep 8 MHz. IMO. Dhrystone. Document Number: 002-23185 Rev. *R – – – – mA mA mA mA VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 to 3.3 V, LDO, max at 60 °C Page 48 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 14. CPU Current and Transition Times (continued) Spec ID# Parameter Description Min Typ Max Units Details / Conditions 2.6 4 3.9 5 6.5 10 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 0.8 1.5 VDDD = 3.3 V, Buck ON, Max at 60 °C 1.1 2 2.2 5.5 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 4.40 5.8 VDDD = 3.3 V, Buck ON, Max at 60 °C 7.35 8.5 11.5 14.5 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 0.8 2 VDDD = 3.3 V, Buck ON, Max at 60 °C 1.2 2 2.2 5.5 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 1.55 2.2 VDDD = 3.3 V, Buck ON, Max at 60 °C 2.4 3.5 4.2 7.2 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 1.2 2 VDDD = 3.3 V, Buck ON, Max at 60 °C 1.75 2.7 3.2 6.3 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 0.7 1.3 VDDD = 3.3 V, Buck ON, Max at 60 °C 0.96 1.8 1.7 5 Cortex M0+. Active Mode Execute with Cache Disabled (Flash) SIDF3 SIDF4 IDD7 IDD8 Execute from Flash;CM4 Off, CM0+ Active 50 MHz. With IMO & FLL. While (1). Execute from Flash;CM4 Off, CM0+ Active 8 MHz. With IMO. While (1). – – VDDD = 3.3 V, Buck ON, Max at 60 °C mA mA VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 V, Buck ON, Max at 60 °C Execute with Cache Enabled SIDC5 SIDC6 IDD9 IDD10 Execute from Cache;CM4 Off, CM0+ Active 100 MHz. With IMO & FLL. Dhrystone. Execute from Cache;CM4 Off, CM0+ Active 8 MHz. With IMO. Dhrystone. – – mA mA VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 V, Buck ON, Max at 60 °C Cortex M4. Sleep Mode SIDS1 SIDS2 SIDS3 IDD11 IDD12 IDD13 CM4 Sleep 100 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With IMO. Document Number: 002-23185 Rev. *R – – – mA mA mA VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 to 3.3 V, LDO, max at 60 °C Page 49 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 14. CPU Current and Transition Times (continued) Spec ID# Parameter Description Min Typ Max Units Details / Conditions 1.3 2 2.05 3 3.6 6.8 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 0.7 1.3 VDDD = 3.3 V, Buck ON, Max at 60 °C 0.95 1.5 1.7 5 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 0.85 1.8 VDDD = 3.3 V, Buck ON, Max at 60 °C 1.18 2 2.2 5.5 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 0.9 1.5 VDDD = 3.3 V, Buck ON, Max at 60 °C 1.27 2 2.2 5.5 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 0.8 1.5 VDDD = 3.3 V, Buck ON, Max at 60 °C 1.14 2 2.1 5.5 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 0.8 1.5 VDDD = 3.3 V, Buck ON, Max at 60 °C 1.15 2 2.1 5.5 VDDD = 1.8 to 3.3 V, LDO, max at 60 °C 0.65 1.2 VDDD = 3.3 V, Buck ON, Max at 60 °C 0.95 1.7 1.6 5 Cortex M0+. Sleep Mode SIDS4 SIDS5 IDD14 IDD15 CM4 Off, CM0+ Sleep 50 MHz. With IMO & FLL. CM4 Off, CM0+ Sleep 8 MHz. With IMO. – – VDDD = 3.3 V, Buck ON, Max at 60 °C mA mA VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 V, Buck ON, Max at 60 °C Cortex M4. Minimum Regulator Current Mode SIDLPA1 SIDLPA2 IDD16 IDD17 Execute from Flash; CM4 Active 8 MHz, CM0+ Sleep 8 MHz. With IMO. While (1). Execute from Cache; CM4 Active 8 MHz, CM0+ Sleep 8 MHz. With IMO. Dhrystone. – – mA mA VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 V, Buck ON, Max at 60 °C Cortex M0+. Minimum Regulator Current Mode SIDLPA3 SIDLPA4 IDD18 IDD19 Execute from Flash; CM4 Off, CM0+ Active 8 MHz. With IMO. While (1). Execute from Cache; CM4 Off, CM0+ Active 8 MHz. With IMO. Dhrystone. – – mA mA VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 V, Buck ON, Max at 60 °C Cortex M4. Minimum Regulator Current Mode SIDLPS1 IDD20 CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With IMO. Document Number: 002-23185 Rev. *R – mA VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 to 3.3 V, LDO, max at 60 °C Page 50 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 14. CPU Current and Transition Times (continued) Spec ID# Parameter Description Min Typ Max 0.64 1.2 0.93 1.7 1.6 5 Units Details / Conditions Cortex M0+. Minimum Regulator Current Mode SIDLPS3 IDD22 CM4 Off, CM0+ Sleep 8 MHz. With IMO. – VDDD = 3.3 V, Buck ON, Max at 60 °C mA VDDD = 1.8 V, Buck ON, Max at 60 °C VDDD = 1.8 to 3.3 V, LDO, max at 60 °C ULP Range Power Specifications (for VCCD = 0.9 V using the Buck). ULP mode is valid from –20 to +85 °C. Cortex M4. Active Mode Execute with Cache Disabled (Flash) SIDF5 SIDF6 IDD3 IDD4 Execute from Flash; CM4 Active 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. While(1). Execute from Flash; CM4 Active 8 MHz, CM0+ Sleep 8 MHz. With IMO. While (1). VDDD = 3.3 V, Buck ON, Max at 60 °C 2.15 2.9 2.85 3.4 VDDD = 1.8 V, Buck ON, Max at 60 °C 0.65 1.2 VDDD = 3.3 V, Buck ON, Max at 60 °C 0.8 1.4 VDDD = 1.8 V, Buck ON, Max at 60 °C 1.85 2.5 VDDD = 3.3 V, Buck ON, Max at 60 °C 2.9 3.5 VDDD = 1.8 V, Buck ON, Max at 60 °C 0.65 1.2 VDDD = 3.3 V, Buck ON, Max at 60 °C 0.8 1.3 VDDD = 1.8 V, Buck ON, Max at 60 °C 1.1 1.5 VDDD = 3.3 V, Buck ON, Max at 60 °C 1.55 2.2 VDDD = 1.8 V, Buck ON, Max at 60 °C 0.55 1.2 VDDD = 3.3 V, Buck ON, Max at 60 °C 0.73 1.4 VDDD = 1.8 V, Buck ON, Max at 60 °C 1 1.5 VDDD = 3.3 V, Buck ON, – mA – mA Execute with Cache Enabled SIDC8 SIDC9 IDD10 IDD11 Execute from Cache; CM4 Active 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. Dhrystone. Execute from Cache; CM4 Active 8 MHz, CM0+ Sleep 8 MHz. With IMO. Dhrystone. – mA – mA Cortex M0+. Active Mode Execute with Cache Disabled (Flash) SIDF7 SIDF8 IDD16 IDD17 Execute from Flash; CM4 Off, CM0+ Active 25 MHz. With IMO & FLL. Write(1). Execute from Flash; CM4 Off, CM0+ Active 8 MHz. With IMO. While(1). – mA – mA Execute with Cache Enabled SIDC10 IDD18 Execute from Cache; CM4 Off, CM0+ Active 25 MHz. With IMO & FLL. Dhrystone. Document Number: 002-23185 Rev. *R – mA 1.5 2 Max at 60 °C VDDD = 1.8 V, Buck ON, Max at 60 °C Page 51 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 14. CPU Current and Transition Times (continued) Spec ID# SIDC11 Parameter IDD19 Description Execute from Cache; CM4 Off, CM0+ Active 8 MHz. With IMO. Dhrystone. Min Typ Max 0.55 0.95 – Units Details / Conditions VDDD = 3.3 V, Buck ON, mA Max at 60 °C 0.73 1.3 VDDD = 1.8 V, Buck ON, 0.85 1.2 VDDD = 3.3 V, Buck ON, Max at 60 °C Cortex M4. Sleep Mode SIDS7 SIDS8 IDD21 IDD22 CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With IMO. – mA Max at 60 °C 1.2 1.8 VDDD = 1.8 V, Buck ON, 0.45 0.9 VDDD = 3.3 V, Buck ON, – Max at 60 °C mA Max at 60 °C 0.59 1 VDDD = 1.8 V, Buck ON, 0.62 1.2 VDDD = 3.3 V, Buck ON, Max at 60 °C Cortex M0+. Sleep Mode SIDS9 SIDS10 IDD23 IDD24 CM4 Off, CM0+ Sleep 25 MHz. With IMO & FLL. CM4 Off, CM0+ Sleep 8 MHz. With IMO. – mA Max at 60 °C 0.88 1.5 VDDD = 1.8 V, Buck ON, 0.41 0.72 VDDD = 3.3 V, Buck ON, – Max at 60 °C mA Max at 60 °C 0.58 1.3 VDDD = 1.8 V, Buck ON, 0.65 1.2 VDDD = 3.3 V, Buck ON, Max at 60 °C Cortex M4. Minimum Regulator Current Mode ° SIDLPA5 SIDLPA6 IDD25 IDD26 Execute from Flash. CM4 Active 8 MHz, CM0+ Sleep 8 MHz. With IMO. While(1). Execute from Cache. CM4 Active 8 MHz, CM0+ Sleep 8 MHz. With IMO. Dhrystone. – mA 0.8 0.6 Max at 60 °C 1.4 VDDD = 1.8 V, Buck ON, 1 VDDD = 3.3 V, Buck ON, – Max at 60 °C mA Max at 60 °C VDDD = 1.8 V, Buck ON, 0.78 1.4 0.55 1 0.75 1.4 VDDD = 1.8 V, Buck ON, Max at 60 °C 0.5 1 VDDD = 3.3 V, Buck ON, Max at 60 °C 0.7 1.4 Max at 60 °C Cortex M0+. Minimum Regulator Current Mode SIDLPA7 SIDLPA8 IDD27 IDD28 Execute from Flash. CM4 Off, CM0+ Active 8 MHz. With IMO. While (1). Execute from Cache. CM4 Off, CM0+ Active 8 MHz. With IMO. Dhrystone. Document Number: 002-23185 Rev. *R – mA – mA VDDD = 3.3 V, Buck ON, Max at 60 °C VDDD = 1.8 V, Buck ON, Max at 60 °C Page 52 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 14. CPU Current and Transition Times (continued) Spec ID# Parameter Description Min Typ Max Units Details / Conditions 0.45 1 0.57 1.1 VDDD = 1.8 V, Buck ON, Max at 60 °C 0.4 1 VDDD = 3.3 V, Buck ON, Max at 60 °C 0.56 1.1 Cortex M4. Minimum Regulator Current Mode SIDLPS5 IDD29 CM4 Sleep 8 MHz, CM0 Sleep 8 MHz. With IMO. – mA VDDD = 3.3 V, Buck ON, Max at 60 °C Cortex M0+. Minimum Regulator Current Mode SIDLPS7 IDD31 CM4 Off, CM0+ Sleep 8 MHz. With IMO. – mA VDDD = 1.8 V, Buck ON, Max at 60 °C Deep Sleep Mode SIDDS1 IDD33A With internal Buck enabled and 64-KB SRAM retention. – 7 – µA Max value is at 85 °C SIDDS1_B IDD33A_B With internal Buck enabled and 64-KB SRAM retention. – 7 – µA Max value is at 60 °C SIDDS2 IDD33B With internal Buck enabled and 256-KB SRAM retention. – 9 – µA Max value is at 85 °C SIDDS2_B IDD33B_B With internal Buck enabled and 256-KB SRAM retention. – 9 – µA Max value is at 60 °C Hibernate Mode SIDHIB1 IDD34 VDDD = 1.8 V – 300 – nA No clocks running SIDHIB2 IDD34A VDDD = 3.3 V – 2100 – nA No clocks running – – 35 µs Including PLL lock time Power Mode Transition Times SID12 TLPACT_ACT Minimum Regulator Current to LP transition time. SID13 TDS_LPACT Deep Sleep to LP transition time – – 21 µs Guaranteed by design SID14 THIB_ACT Hibernate to LP transition time – 1000 – µs Including PLL lock time Min Typ Max Units – 300 500 nA VDDD = 1.8 V XRES Table 15. XRES DC Specifications Spec ID# Parameter Description Details / Conditions SID17 TXRES_IDD IDD when XRES asserted SID17A TXRES_IDD_1 IDD when XRES asserted – 2100 10500 nA VDDD = 3.3 V SID77 VIH Input voltage HIGH threshold 0.7 * VDD – – V CMOS input SID78 VIL Input voltage LOW threshold – – 0.3 * VDD V CMOS input SID80 CIN Input capacitance – 3 – pF – SID81 VHYSXRES Input voltage hysteresis – 100 – mV – IDIODE Current through protection diode to VDD/VSS – – 100 µA SID82 Document Number: 002-23185 Rev. *R – Page 53 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 16. XRES AC Specifications Spec ID# Parameter Description Min Typ Max Units Details / Conditions SID15 TXRES_ACT POR or XRES release to Active transition time – 1000 – µs Normal mode, 50-MHz CM0+. SID16 TXRES_PW XRES pulse width 5 – – µs – Min Typ Max Units 0.7 * VDD – – V CMOS Input GPIO Table 17. GPIO DC Specifications Spec ID# Parameter Description Details / Conditions SID57 VIH Input voltage HIGH threshold SID57A IIHS Input current when Pad > VDDIO for OVT inputs – – 10 µA Per I2C Spec SID58 VIL Input voltage LOW threshold – – 0.3 * VDD V CMOS Input SID241 VIH LVTTL input, VDD < 2.7 V 0.7 * VDD – – V – SID242 VIL LVTTL input, VDD < 2.7 V – – 0.3 * VDD V – SID243 VIH LVTTL input, VDD ≥ 2.7 V 2.0 – – V – SID244 VIL LVTTL input, VDD ≥ 2.7 V – – 0.8 V – SID59 VOH Output voltage HIGH level VDD – 0.5 – – V IOH = 8 mA SID62A VOL Output voltage LOW level – – 0.4 V IOL = 8 mA SID63 RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ – SID64 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ – SID65 IIL Input leakage current (absolute value) – – 2 nA SID66 CIN Input capacitance – – 5 pF SID67 VHYSTTL Input hysteresis LVTTL VDD > 2.7 V 100 0 – mV SID68 VHYSCMOS Input hysteresis CMOS 0.05 * VDD – – mV SID69 IDIODE Current through protection diode to VDD/VSS – – 100 µA SID69A ITOT_GPIO Maximum total source or sink chip current – – 200 mA Min Typ Max Units Details / Conditions 25 °C, VDD = 3.0 V – – – – – Table 18. GPIO AC Specifications Spec ID# Parameter Description SID70 TRISEF Rise time in Fast Strong Mode. 10% to 90% of VDD. – – 2.5 ns Cload = 15 pF, 8-mA drive strength SID71 TFALLF Fall time in Fast Strong Mode. 10% to 90% of VDD. – – 2.5 ns Cload = 15 pF, 8-mA drive strength SID72 TRISES_1 Rise time in Slow Strong Mode. 10% to 90% of VDD. 52 – 142 ns Cload = 15 pF, 8-mA drive strength, VDD  2.7 V – 102 ns TRISES_2 Rise time in Slow Strong Mode. 10% to 90% of VDD. 48 SID72A Cload = 15 pF, 8-mA drive strength, 2.7 V < VDD  3.6 V Document Number: 002-23185 Rev. *R Page 54 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 18. GPIO AC Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details / Conditions 44 – 211 ns Cload = 15 pF, 8-mA drive strength, VDD 2.7 V 42 – 93 ns Cload = 15 pF, 8-mA drive strength, 2.7 V < VDD  3.6 V – 250 ns Cload = 10 pF to 400 pF, 8-mA drive strength – – 100 MHz 90/10%, 15-pF load, 60/40 duty cycle – – 1.5 MHz 90/10%, 15-pF load, 60/40 duty cycle – – 100 MHz 90/10%, 25-pF load, 60/40 duty cycle – – 1.3 MHz 90/10%, 25-pF load, 60/40 duty cycle – – 100 MHz SID73 TFALLS_1 Fall time in Slow Strong Mode. 10% to 90% of VDD. SID73A TFALLS_2 Fall time in Slow Strong Mode. 10% to 90% of VDD. SID73G TFALL_I2C Fall time (30% to 70% of VDD) in 20 * VDDIO / 5.5 Slow Strong mode. SID74 FGPIOUT1 GPIO Fout. Fast Strong mode. SID75 FGPIOUT2 GPIO Fout; Slow Strong mode. SID76 FGPIOUT3 GPIO Fout; Fast Strong mode. SID245 FGPIOUT4 GPIO Fout; Slow Strong mode. SID246 FGPIOIN GPIO input operating frequency; 1.71 V  VDD 3.6 V 90/10% VIO Analog Peripherals Low-Power (LP) Comparator Table 19. LP Comparator DC Specifications Spec ID# Parameter Description Min Typ Max Units Details/Conditions –10 – 10 mV – SID84 VOFFSET1 Input offset voltage. Normal power mode. SID85A VOFFSET2 Input offset voltage. Low-power mode. –25 ±12 25 mV – SID85B VOFFSET3 Input offset voltage. Ultra low-power mode. –25 ±12 25 mV – SID86 VHYST1 Hysteresis when enabled in Normal mode – – 60 mV – SID86A VHYST2 Hysteresis when enabled in Low-power mode – – 80 mV – SID87 VICM1 Input common mode voltage in Normal mode 0 – VDDIO1 – 0.1 V – SID247 VICM2 Input common mode voltage in Low power mode 0 – VDDIO1 – 0.1 V – SID247A VICM3 Input common mode voltage in Ultra low power mode 0 – VDDIO1 – 0.1 V – SID88 CMRR Common mode rejection ratio in Normal power mode 50 – – dB – SID89 ICMP1 Block current, Normal mode – – 150 µA – SID248 ICMP2 Block current, Low-power mode – – 10 µA – SID259 ICMP3 Block current in Ultra low-power mode – 0.3 0.85 µA – SID90 ZCMP DC input impedance of comparator 35 – – MΩ – Document Number: 002-23185 Rev. *R Page 55 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 20. LP Comparator AC Specifications Spec ID# Parameter Description Min Typ Max Units Details/Conditions SID91 TRESP1 Response time, Normal mode, 100 mV overdrive – – 100 ns – SID258 TRESP2 Response time, Low power mode, 100 mV overdrive – – 1000 ns – SID92 TRESP3 Response time, Ultra-low power mode, 100 mV overdrive – – 20 µs – SID92E T_CMP_EN1 Time from Enabling to operation – – 10 µs Normal and low-power modes SID92F T_CMP_EN2 Time from Enabling to operation – – 50 µs Ultra-low-power mode Temperature Sensor Table 21. Temperature Sensor Specifications Spec ID SID93 Parameter TSENSACC Description Temperature sensor accuracy Min –5 Typ ±1 Max 5 Min 1.188 Typ 1.2 Max 1.212 Units Details/Conditions °C –40 to +85 °C Internal Reference Table 22. Internal Reference Specification Spec ID SID93R Parameter VREFBG Description – Units V Details/Conditions – SAR ADC Table 23. 12-bit SAR ADC DC Specifications Spec ID Parameter SID94 A_RES Min Typ Max Units SAR ADC resolution Description – – 12 bits Details/Conditions SID95 A_CHNLS_S Number of channels - single-ended – – 16 – 8 full speed. SID96 A-CHNKS_D Number of channels - differential – – 8 – Diff inputs use neighboring I/Os SID97 A-MONO Monotonicity – – - – Yes. SID98 A_GAINERR Gain error – – ±0.2 % With external reference. SID99 A_OFFSET Input offset voltage – – 2 mV Measured with 1-V reference 1.05 mA At 1 Msps. External reference mode 1.3 mA At 1 Msps. Internal reference mode 1.65 mA At 2 Msps. External reference mode At 2 Msps. Internal reference mode SID100 A_ISAR_1 Current consumption at 1 Msps – – SID100A A_ISAR_2 Current consumption at 1 Msps – – SID1002 A_ISAR_3 Current consumption at 2 Msps – – SID1003 A_ISAR_4 Current consumption at 2 Msps – – 2.15 mA SID101 A_VINS Input voltage range - single-ended VSS – VDDA V SID102 A_VIND Input voltage range - differential VSS – VDDA V SID103 A_INRES Input resistance – 1 – KΩ SID104 A_INCAP Input capacitance – 5 – pF Document Number: 002-23185 Rev. *R Page 56 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 24. 12-bit SAR ADC AC Specifications Min Typ Max Units SID106 Spec ID A_PSRR Parameter Power supply rejection ratio Description 70 – – dB Details/Conditions SID107 A_CMRR Common mode rejection ratio 66 – – dB SID1081 A_SAMP_1 Sample rate with external reference With bypass cap – – 2 Msps VDDA 2.7–3.6 SID1082 A_SAMP_1 Sample rate with external reference With bypass cap – – 1 Msps VDDA 1.7–3.6 SID108A1 A_SAMP_2 Sample rate with VDD reference; No Bypass Cap – – 2 Msps VDDA 2.7–3.6 SID108A2 A_SAMP_2 Sample rate with VDD Reference; No Bypass Cap – – 1 Msps VDDA 1.7–3.6 SID108B A_SAMP_3 Sample rate with internal reference; With Bypass Cap. – – 1 Msps SID108C A_SAMP_4 Sample rate with internal reference. No Bypass Cap – – 200 ksps SID109 A_SINAD Signal-to-noise and distortion ratio (SINAD). 64 – – dB SID111A A_INL Integral non-linearity. Up to 1 Msps –2 – 2 LSB All reference modes SID111B A_INL Integral non-linearity. 2 Msps. –2.5 – 2.5 LSB External reference or VDDA Reference Mode, VREF ≥ 2 V. VDDA = 2.7 V to 3.6 V SID112A A_DNL Differential non-linearity. Up to 1 Msps –1 – 1.5 LSB All reference modes SID112B A_DNL Differential non-linearity. 2 Msps. –1 – 1.6 LSB External reference or VDDA Reference Mode, VREF ≥ 2 V. VDDA = 2.7 to 3.6V SID113 A_THD Total harmonic distortion. 1 Msps. – – -65 dB Description Min Typ Max Units Details / Conditions Max allowed ripple on power supply, DC to 10 MHz – – ±50 mV VDDA > 2 V (with ripple), 25 °C TA, sensitivity = 0.1 pF ±25 mV VDDA > 1.75 V (with ripple), 25 °C TA, Parasitic capacitance (CP) < 20 pF, Sensitivity ≥ 0.4 pF – Measured at 1 V Fin = 10 kHz FIN = 10 kHz. VDDA = 2.7–3.6 V CSD Table 25. CapSense Sigma-Delta (CSD) Specifications Spec ID# Parameter CSD V2 Specifications SYS.PER#3 VDD_RIPPLE SYS.PER#16 Max allowed ripple on power supply, VDD_RIPPLE_1.8 DC to 10 MHz – – SID.CSD.BLK ICSD Maximum block current – – 4500 µA VREF Voltage reference for CSD and Comparator 0.6 1.2 VDDA – 0.6 V VDDA – VREF ≥ 0.6 V SID.CSD#15A VREF_EXT External Voltage reference for CSD and Comparator 0.6 – VDDA – 0.6 V VDDA – VREF ≥ 0.6 V SID.CSD#16 IDAC1IDD IDAC1 (7-bits) block current – – 1900 µA – SID.CSD#17 IDAC2IDD IDAC2 (7-bits) block current – – 1900 µA – SID308 VCSD Voltage range of operation 1.7 – 3.6 V SID.CSD#15 Document Number: 002-23185 Rev. *R 1.71–3.6 V Page 57 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 25. CapSense Sigma-Delta (CSD) Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details / Conditions SID308A VCOMPIDAC Voltage compliance range of IDAC 0.6 – VDDA – 0.6 V SID309 IDAC1DNL DNL –1 – 1 LSB – SID310 IDAC1INL INL –3 – 3 LSB If VDDA < 2 V then for LSB of 2.4 µA or less SID311 IDAC2DNL DNL –1 – 1 LSB – SID312 IDAC2INL INL –3 – 3 LSB If VDDA < 2 V then for LSB of 2.4 µA or less VDDA – VREF ≥ 0.6 V SNRC of the following is Ratio of counts of finger to noise. Measured typical devices at room temperature using Dual IDAC + PRS Clock Mode. Best performance is when using the PASS reference and the PLL. SID313_1A SNRC_1 SRSS Reference. IMO + FLL Clock Source. 0.1-pF sensitivity. 5 – – Ratio 9.5-pF max. capacitance SID313_1B SNRC_2 SRSS Reference. IMO + FLL Clock Source. 0.3-pF sensitivity. 5 – – Ratio 31-pF max. capacitance SID313_1C SNRC_3 SRSS Reference. IMO + FLL Clock Source. 0.6-pF sensitivity. 5 – – Ratio 61-pF max. capacitance SID313_2A SNRC_4 PASS Reference. IMO + FLL Clock Source. 0.1-pF sensitivity. 5 – – Ratio 12-pF max. capacitance SID313_2B SNRC_5 PASS Reference. IMO + FLL Clock Source. 0.3-pF sensitivity. 5 – – Ratio 47-pF max. capacitance SID313_2C SNRC_6 PASS Reference. IMO + FLL Clock Source. 0.6-pF sensitivity. 5 – – Ratio 86-pF max. capacitance SID313_3A SNRC_7 PASS Reference. IMO + PLL Clock Source. 0.1-pF sensitivity. 5 – – Ratio 25-pF max. capacitance SID313_3B SNRC_8 PASS Reference. IMO + PLL Clock Source. 0.3-pF sensitivity. 5 – – Ratio 86-pF max. capacitance SID313_3C SNRC_9 PASS Reference. IMO + PLL Clock Source. 0.6-pF sensitivity. 5 – – Ratio 168-pF Max. capacitance SID314 IDAC1CRT1 Output current of IDAC1 (7 bits) in low range 4.2 – 5.7 µA LSB = 37.5-nA typ. SID314A IDAC1CRT2 Output current of IDAC1 (7 bits) in medium range 33.7 – 45.6 µA LSB = 300-nA typ. SID314B IDAC1CRT3 Output current of IDAC1 (7 bits) in high range 270 – 365 µA LSB = 2.4-µA typ. SID314C IDAC1CRT12 Output current of IDAC1 (7 bits) in low range, 2X mode 8 – 11.4 µA LSB = 37.5-nA typ. 2X output stage SID314D IDAC1CRT22 Output current of IDAC1 (7 bits) in medium range, 2X mode 67 – 91 µA LSB = 300-nA typ. 2X output stage SID314E IDAC1CRT32 Output current of IDAC1 (7 bits) in high range, 2X mode. VDDA > 2 V 540 – 730 µA LSB = 2.4-µA typ. 2X output stage SID315 IDAC2CRT1 Output current of IDAC2 (7 bits) in low range 4.2 – 5.7 µA LSB = 37.5-nA typ. SID315A IDAC2CRT2 Output current of IDAC2 (7 bits) in medium range 33.7 – 45.6 µA LSB = 300-nA typ. SID315B IDAC2CRT3 Output current of IDAC2 (7 bits) in high range 270 – 365 µA LSB = 2.4-µA typ. Document Number: 002-23185 Rev. *R Page 58 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 25. CapSense Sigma-Delta (CSD) Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details / Conditions SID315C IDAC2CRT12 Output current of IDAC2 (7 bits) in low range, 2X mode 8 – 11.4 µA LSB = 37.5-nA typ. 2X output stage SID315D IDAC2CRT22 Output current of IDAC2 (7 bits) in medium range, 2X mode 67 – 91 µA LSB = 300-nA typ. 2X output stage SID315E IDAC2CRT32 Output current of IDAC2 (7 bits) in high range, 2X mode. VDDA > 2V 540 – 730 µA LSB = 2.4-µA typ. 2X output stage SID315F IDAC3CRT13 Output current of IDAC in 8-bit mode in low range 8 – 11.4 µA LSB = 37.5-nA typ. SID315G IDAC3CRT23 Output current of IDAC in 8-bit mode in medium range 67 – 91 µA LSB = 300-nA typ. SID315H IDAC3CRT33 Output current of IDAC in 8-bit mode in high range. VDDA > 2V 540 – 730 µA LSB = 2.4-µA typ. SID320 IDACOFFSET All zeroes input – – 1 LSB SID321 IDACGAIN Full-scale error less offset – – ±15 % LSB = 2.4-µA typ. SID322 IDACMIS- Mismatch between IDAC1 and IDAC2 in Low mode – – 9.2 LSB LSB = 37.5-nA typ. SID322A IDACMIS- Mismatch between IDAC1 and IDAC2 in Medium mode – – 6 LSB LSB = 300-nA typ. SID322B IDACMIS- Mismatch between IDAC1 and IDAC2 in High mode – – 5.8 LSB LSB = 2.4-µA typ. SID323 IDACSET8 Settling time to 0.5 LSB for 8-bit IDAC – – 10 µs Full-scale transition. No external load. SID324 IDACSET7 Settling time to 0.5 LSB for 7-bit IDAC – – 10 µs Full-scale transition. No external load. SID325 CMOD External modulator capacitor. – 2.2 – nF 5-V rating, X7R or NP0 cap. MATCH1 MATCH2 MATCH3 Polarity set by source or sink Table 26. CSD ADC Specifications Spec ID# Parameter Description Min Typ Max Units Details / Conditions CSDv2 ADC Specifications SIDA94 A_RES Resolution – – 10 bits Auto-zeroing is required every millisecond SID95 A_CHNLS_S Number of channels - single ended – – – 16 – SIDA97 A-MONO Monotonicity – – Yes – VREF mode % Reference source: SRSS (VREF = 1.20 V, VDDA < 2.2 V), (VREF = 1.6 V, 2.2 V < VDDA < 2.7 V), (VREF = 2.13 V, VDDA > 2.7 V) % Reference source: SRSS (VREF=1.20 V, VDDA < 2.2V), (VREF=1.6 V, 2.2 V < VDDA < 2.7 V), (VREF = 2.13 V, VDDA > 2.7 V) SIDA98 SIDA98A A_GAINERR_VREF A_GAINERR_VDDA Gain error Gain error Document Number: 002-23185 Rev. *R – – 0.6 0.2 – – Page 59 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 26. CSD ADC Specifications (continued) Spec ID# SIDA99 Parameter A_OFFSET_VREF Description Input offset voltage Min – Typ Max Units 0.5 Details / Conditions – After ADC calibration, Ref. Src = SRSS, (VREF = 1.20 V, VDDA < 2.2 V), LSB (VREF = 1.6 V, 2.2 V < VDDA < 2.7 V), (VREF = 2.13 V, VDDA > 2.7 V) SIDA99A A_OFFSET_VDDA Input offset voltage – 0.5 – After ADC calibration, Ref. Src = SRSS, (VREF = 1.20 V, VDDA < 2.2 V), LSB (VREF = 1.6 V, 2.2 V < VDDA < 2.7 V), (VREF = 2.13 V, VDDA > 2.7 V) SIDA100 A_ISAR_VREF Current consumption – 0.3 – mA CSD ADC Block current SIDA100A A_ISAR_VDDA Current consumption – 0.3 – mA CSD ADC Block current SIDA101 A_VINS_VREF Input voltage range - single ended SIDA101A A_VINS_VDDA Input voltage range - single ended VSSA – VREF V (VREF = 1.20 V, VDDA < 2.2 V), (VREF = 1.6 V, 2.2 V < VDDA < 2.7 V), (VREF = 2.13 V, VDDA > 2.7 V) (VREF = 1.20 V, VDDA < 2.2 V), (VRE F = 1.6 V, 2.2 V < VDDA < 2.7 V), (VREF = 2.13 V, VDDA > 2.7 V) VSSA – VDDA V SIDA103 A_INRES Input charging resistance – 15 – kΩ – SIDA104 A_INCAP Input capacitance – 41 – pF – SIDA106 A_PSRR Power supply rejection ratio (DC) – 60 – dB – SIDA107 A_TACQ Sample acquisition time – 10 – µs Measured with 50-Ω source impedance. 10 µs is default software driver acquisition time setting. Settling to within 0.05%. SIDA108 A_CONV8 Conversion time for 8-bit resolution at conversion rate = Fhclk / (2"(N + 2)). Clock frequency = 50 MHz. – 25 – µs Does not include acquisition time. SIDA108A A_CONV10 Conversion time for 10-bit resolution at conversion rate = Fhclk / (2"(N + 2)). Clock frequency = 50 MHz. – 60 – µs Does not include acquisition time. SIDA109 Signal-to-noise and Distortion ratio (SINAD) – 57 – dB Measured with 50-Ω source impedance SIDA109A A_SND_VDDA Signal-to-noise and Distortion ratio (SINAD) – 52 – dB Measured with 50-Ω source impedance SIDA111 A_INL_VREF Integral non-linearity. 11.6 ksps – – 2 LSB Measured with 50-Ω source impedance SIDA111A A_INL_VDDA Integral non-linearity. 11.6 ksps – – 2 LSB Measured with 50-Ω source impedance SIDA112 A_DNL_VREF Differential non-linearity. 11.6 ksps – – 1 LSB Measured with 50-Ω source impedance SIDA112A A_DNL_VDDA Differential non-linearity. 11.6 ksps – – 1 LSB Measured with 50-Ω source impedance A_SND_VRE Document Number: 002-23185 Rev. *R Page 60 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Digital Peripherals Timer/Counter/PWM Table 27. Timer/Counter/PWM (TCPWM) Specifications Spec ID# Parameter Description Min Typ Max Units Details/Conditions SID.TCPWM.1 ITCPWM1 Block current consumption at 8 MHz – – 70 µA All modes (TCPWM) SID.TCPWM.2 ITCPWM2 Block current consumption at 24 MHz – – 180 µA All modes (TCPWM) SID.TCPWM.2A ITCPWM3 Block current consumption at 50 MHz – – 270 µA All modes (TCPWM) SID.TCPWM.2B ITCPWM4 Block current consumption at 100 MHz – – 540 µA All modes (TCPWM) SID.TCPWM.3 TCPWMFREQ Operating frequency – – 100 SID.TCPWM.4 Input trigger pulse width for all trigger events TPWMENEXT – ns 1.5/Fc – – ns Resolution of counter 1/Fc – – ns Minimum time between successive counts. Fc is counter operating frequency. PWM resolution 1/Fc – – ns Minimum pulse width of PWM output. Fc is counter operating frequency. – ns Minimum pulse width between Quadrature phase inputs. Delays from pins should be similar. Fc is counter operating frequency. Details / Conditions TPWMEXT Output trigger pulse widths SID.TCPWM.5A TCRES SID.TCPWM.5B PWMRES QRES – Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected. Fc is counter operating frequency. Minimum possible width of Overflow, Underflow, and CC (Counter equals Compare value) trigger outputs. Fc is counter operating frequency. SID.TCPWM.5 SID.TCPWM.5C 2/Fc MHz Maximum = 100 MHz Quadrature inputs resolution 2/Fc – Serial Communication Block (SCB) Table 28. Serial Communication Block (SCB) Specifications Spec ID# Parameter Description Min Typ Max Units 30 µA – 2 Fixed I C DC Specifications SID149 II2C1 Block current consumption at 100 kHz – – SID150 II2C2 Block current consumption at 400 kHz – – 80 µA – SID151 II2C3 Block current consumption at 1 Mbps – – 180 µA – I C enabled in Deep Sleep mode – – 1.7 µA At 60 °C. Bit rate – – 1 SID152 II2C4 2 2 Fixed I C AC Specifications SID153 FI2C1 Mbps – Fixed UART DC Specifications SID160 IUART1 Block current consumption at 100 kbps – – 30 µA – SID161 IUART2 Block current consumption at 1000 kbps – – 180 µA – – – 3 – – 8 Fixed UART AC Specifications SID162A FUART1 SID162B FUART2 Bit Rate Document Number: 002-23185 Rev. *R Mbps ULP Mode LP Mode Page 61 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 28. Serial Communication Block (SCB) Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details / Conditions Fixed SPI DC Specifications SID163 ISPI1 Block current consumption at 1 Mbps – – 220 µA – SID164 ISPI2 Block current consumption at 4 Mbps – – 340 µA – SID165 ISPI3 Block current consumption at 8 Mbps – – 360 µA – SID165A ISP14 Block current consumption at 25 Mbps – – 800 µA – MHz Fixed SPI AC Specifications for LP Mode (1.1 V) unless noted otherwise. SID166 FSPI SPI Operating frequency externally clocked slave – – 25 SID166B FSPI_EXT SPI operating frequency master (Fscb is SPI clock). – – Fscb/4 FSPI_IC SPI slave internally clocked – SID166A – 12-MHz max for ULP (0.9 V) mode Fscb max is 100 MHz in LP MHz (1.1 V) mode, 25 MHz in ULP mode. 15 MHz 5 MHz max for ULP (0.9 V) mode Fixed SPI Master mode AC Specifications for LP Mode (1.1 V) unless noted otherwise. SID167 TDMO MOSI valid after SClock driving edge – – 12 ns 20-ns max for ULP (0.9 V) mode SID168 TDSI MISO valid before SClock capturing edge 5 – – ns Full clock, late MISO sampling SID169 THMO MOSI data hold time 0 – – ns Referred to Slave capturing edge Fixed SPI Slave mode AC Specifications for LP Mode (1.1 V) unless noted otherwise. SID170 TDMI MOSI valid before Sclock capturing edge 5 – – ns – SID171A TDSO_EXT MISO valid after Sclock driving edge in Ext. Clk. mode – – 20 ns 35-ns max. for ULP (0.9 V) mode SID171 TDSO MISO valid after Sclock driving edge in Internally Clk. mode – – EXT + 3 * ns TSCB is SCB clock period. SID171B TDSO MISO Valid after Sclock driving edge in Internally Clk. Mode with median filter enabled. – – TDSO_E +4* TSCB ns TSCB is SCB clock period. SID172 THSO Previous MISO data hold time 5 – – ns – SID172A TSSELSCK1 SSEL Valid to first SCK valid edge 65 – – ns – SID172B TSSELSCK2 SSEL Hold after Last SCK valid edge 65 – – ns – Document Number: 002-23185 Rev. *R TDSO_ TSCB XT Page 62 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet LCD Specifications Table 29. LCD Direct Drive DC Specifications Spec ID# Parameter Description Min Typ Max Units Details / Conditions SID155 CLCDCAP LCD capacitance per segment/common driver – 500 5000 SID156 LCDOFFSET Long-term segment offset – 20 – mV – SID157 ILCDOP1 PWM Mode current. 3.3 V bias. 8 MHz IMO. 25 °C. – 0.6 – mA 32 × 4 segments 50 Hz SID158 ILCDOP2 PWM Mode current. 3.3 V bias. 8 MHz IMO. 25 °C. – 0.5 – mA 32 × 4 segments 50 Hz Min Typ Max Units 10 50 150 Hz pF – Table 30. LCD Direct Drive AC Specifications Spec ID SID159 Parameter FLCD Description LCD frame rate Document Number: 002-23185 Rev. *R Details/Conditions – Page 63 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Memory Table 31. Flash Specifications[4] Spec ID Parameter Description Min Typ Max Units Details/Conditions Erase and program current – – 6 mA – TROWWRITE Row write time (erase and program) – – 16 ms Row = 512 bytes Flash DC Specifications SID173A IPE Flash AC Specifications SID174 SID175 TROWERASE Row erase time – – 11 ms – SID176 TROWPROGRAM Row program time after erase – – 5 ms – SID178 TBULKERASE Bulk erase time (2048 KB) – – 11 ms – SID179 TSECTORERASE Sector erase time (256 KB) – – 11 ms 512 rows per sector SID178S TSSERIAE Subsector erase time – – 11 ms 8 rows per subsector SID179S TSSWRITE Subsector write time; 1 erase plus 8 program times – – 51 ms – SID180S TSWRITE Sector write time; 1 erase plus 512 program times – – 2.6 seconds – SID180 TDEVPROG Total device write time – – 30 seconds – SID181 FEND Flash endurance 100K – – cycles – SID182 FRET1 Flash retention. TA  25 °C, 100K P/E cycles 10 – – years – SID182A FRET2 Flash retention. TA  85 °C, 10K P/E cycles 10 – – years – SID182B FRET3 Flash retention. TA 55 °C, 20K P/E cycles 20 – – years – SID256 TWS100 Number of Wait states at 100 MHz 3 – – LP mode. VCCD = 1.1 V SID257 TWS50 Number of Wait states at 50 MHz 2 – – ULP mode. VCCD = 0.9 V Note 4. It can take as much as 16 milliseconds to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 002-23185 Rev. *R Page 64 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet System Resources Table 32. System Resources Spec ID Parameter Description Min Typ Max Units Details/Conditions Power-On-Reset with Brown-out DC Specifications Precise POR (PPOR) SID190 VFALLPPOR BOD trip voltage in Active and Sleep modes. VDDD. 1.54 – – V BOD reset guaranteed for levels below 1.54 V SID192 VFALLDPSLP BOD trip voltage in Deep Sleep. VDDD. 1.54 – – V – VDDRAMP Maximum power supply ramp rate (any supply) – – 100 mV/µs Active mode – – 10 mV/µs BOD operation guaranteed SID192A POR with Brown-out AC Specification SID194A VDDRAMP_DS Maximum power supply ramp rate (any supply) in Deep Sleep Voltage Monitors DC Specifications SID195 VHVDI1 – 1.38 1.43 1.47 V – SID196 VHVDI2 – 1.57 1.63 1.68 V – SID197 VHVDI3 – 1.76 1.83 1.89 V – SID198 VHVDI4 – 1.95 2.03 2.1 V – SID199 VHVDI5 – 2.05 2.13 2.2 V – SID200 VHVDI6 – 2.15 2.23 2.3 V – SID201 VHVDI7 – 2.24 2.33 2.41 V – SID202 VHVDI8 – 2.34 2.43 2.51 V – SID203 VHVDI9 – 2.44 2.53 2.61 V – SID204 VHVDI10 – 2.53 2.63 2.72 V – SID205 VHVDI11 – 2.63 2.73 2.82 V – SID206 VHVDI12 – 2.73 2.83 2.92 V – SID207 VHVDI13 – 2.82 2.93 3.03 V – SID208 VHVDI14 – 2.92 3.03 3.13 V – SID209 VHVDI15 – 3.02 3.13 3.23 V – SID211 LVI_IDD Block current – 5 15 µA – – – 170 ns – Voltage Monitors AC Specification SID212 TMONTRIP Voltage monitor trip time Document Number: 002-23185 Rev. *R Page 65 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet SWD Interface Table 33. SWD and Trace Specifications Spec ID# Parameter Description Min Typ Max Units Details / Conditions SWD and Trace Interface SID214 F_SWDCLK2 1.7 V  VDDD  3.6 V – – 25 MHz LP Mode. VCCD = 1.1 V. SID214L F_SWDCLK2L 1.7 V VDDD  3.6 V – – 12 MHz ULP Mode. VCCD = 0.9 V. SID215 T_SWDI_SETUP T = 1/f SWDCLK 0.25 * T – – ns – SID216 T_SWDI_HOLD 0.25 * T – – ns – SID217 T_SWDO_VALID T = 1/f SWDCLK – – 0.5 * T ns – SID217A T_SWDO_HOLD T = 1/f SWDCLK – T = 1/f SWDCLK 1 – – ns – – 50 MHz LP Mode. VDD = 1.1 V. SID214T F_TRCLK_LP1 With Trace Data setup/hold times of 2/1 ns respectively SID215T F_TRCLK_LP2 With Trace Data setup/hold times of 3/2 ns respectively – – 50 MHz LP Mode. VDD = 1.1 V. SID216T F_TRCLK_ULP With Trace Data setup/hold times of 3/2 ns respectively – – 20 MHz ULP Mode. VDD = 0.9 V. Min Typ Max Units Details/Conditions – 9 15 µA Internal Main Oscillator Table 34. IMO DC Specifications Spec ID SID218 Parameter IIMO1 Description IMO operating current at 8 MHz – Table 35. IMO AC Specifications Spec ID Parameter Description SID223 FIMOTOL1 Frequency variation centered on 8 MHz SID227 TJITR Cycle-to-cycle and period jitter Min Typ Max Units Details/Conditions – – ±2 % – – 250 – ps – Min Typ Max Units – 0.3 0.7 µA Min Typ Max Units Internal Low-Speed Oscillator Table 36. ILO DC Specification Spec ID SID231 Parameter IILO2 Description ILO operating current at 32 kHz Details/Conditions – Table 37. ILO AC Specifications Spec ID Parameter Description Details/Conditions SID234 TSTARTILO1 ILO startup time – – 7 µs Startup time to 95% of final frequency SID236 TLIODUTY ILO duty cycle 45 50 55 % – SID237 FILOTRIM1 ILO frequency 28.8 32 36.1 kHz Document Number: 002-23185 Rev. *R Factory trimmed Page 66 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Crystal Oscillator Specifications Table 38. ECO Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions Block operating current with Cload up to 18 pF – 800 1600 µA Crystal frequency range 16 – 35 MHz Block operating current with 32-kHz crystal – 0.38 1 µA – MHz ECO DC Specifications SID316 IDD_MHz Max = 35 MHz, Typ = 16 MHz MHz ECO AC Specifications SID317 F_MHz Some restrictions apply. Refer to the device TRM. kHz ECO DC Specifications SID318 IDD_kHz SID321E ESR32K Equivalent series resistance – 80 – kΩ – SID322E PD32K Drive level – – 1 µW – 32.768 – kHz – kHz ECO AC Specifications SID319 F_kHz 32 kHz frequency – SID320 Ton_kHz Startup time – – 500 ms – SID320E FTOL32K Frequency tolerance – 50 250 ppm – External Clock Specifications Table 39. External Clock Specifications Min Typ Max Units SID305 Spec ID EXTCLKFREQ Parameter External clock input frequency Description 0 – 100 MHz – Details/Conditions SID306 EXTCLKDUTY Duty cycle; measured at VDD/2 45 – 55 % – Min Typ Max Units 4 – 64 MHz PLL Specifications Table 40. PLL Specifications Spec ID Parameter Description SID304P PLL_IN Input frequency to PLL block SID305P PLL_LOCK Time to achieve PLL lock SID306P PLL_OUT Output frequency from PLL block SID307P PLL_IDD SID308P PLL_JTR Details/Conditions – 16 35 µs – 10.625 – 150 MHz – PLL current – 0.55 1.1 mA Typ. at 100 MHz out. Period jitter – – 150 ps 100 MHz output frequency Description Min Typ Max Units Clock switching from clk1 to clk2 in clock periods; for example, from IMO (clk1) to FLL (clk2).[5] – – Table 41. Clock Source Switching Time Spec ID SID262 Parameter TCLKSWITCH Details/Conditions 4 clk1 + periods – 3 clk2 Note 5. As an example, if the clk_path[1] source is changed from the IMO to the FLL (see Figure 3) then clk1 is the IMO and clk2 is the FLL. Document Number: 002-23185 Rev. *R Page 67 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet FLL Specifications Table 42. Frequency Locked Loop (FLL) Specifications Spec ID Parameter Description Min Typ Max Units Details / Conditions SID450 FLL_RANGE Input frequency range. 0.001 – 100 MHz Lower limit allows lock to USB SOF signal (1 kHz). Upper limit is for External input. SID451 FLL_OUT_DIV2 Output frequency range. VCCD = 1.1 V 24.00 – 100.00 MHz Output range of FLL divided-by-2 output SID451A FLL_OUT_DIV2 Output frequency range. VCCD = 0.9 V 24.00 – 50.00 MHz Output range of FLL divided-by-2 output SID452 FLL_DUTY_DIV2 Divided-by-2 output; High or Low 47.00 – 53.00 % – SID454 FLL_WAKEUP Time from stable input clock to 1% of final value on Deep Sleep wakeup – – 7.50 µs With IMO input, less than 10 °C change in temperature while in Deep Sleep, and Fout ≥ 50 MHz. SID455 FLL_JITTER Period jitter (1 sigma) at 100 MHz – – 35.00 ps 50 ps at 48 MHz, 35 ps at 100 MHz SID456 FLL_CURRENT CCO + Logic current – – 5.50 µA/MHz – USB Table 43. USB Specifications (USB requires LP Mode 1.1-V internal supply) Spec ID Parameter Description Min Typ Max Units Details/Conditions USB Block Specifications SID322U Vusb_3.3 Device supply for USB operation 3.15 – 3.6 V USB Configured SID323U Vusb_3 Device supply for USB operation (functional operation only) 2.85 – 3.6 V USB Configured SID325U Iusb_config Block supply current in Active mode – 8 – mA VDDD = 3.3 V SID328 Iusb_suspend Block supply current in suspend mode – 0.5 – mA VDDD = 3.3 V, Device connected SID329 Iusb_suspend Block supply current in suspend mode – 0.3 – mA VDDD = 3.3 V, Device disconnected SID330U USB_Drive_Res USB driver impedance 28 – 44 Ω Series resistors are on chip SID331U USB_Pulldown USB pull-down resistors in Host mode 14.25 – 24.8 kΩ – SID332U USB_Pullup_Idle Idle mode range 900 – 1575 Ω Bus idle SID333U USB_Pullup Active mode 1425 – 3090 Ω Upstream device transmitting Document Number: 002-23185 Rev. *R Page 68 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet QSPI Table 44. QSPI Specifications Spec ID# Parameter Description Min Typ Max Units Details / Conditions SMIF QSPI Specifications. All specs with 15-pF load. Measured from 50% to 50% waveform transitions. SID390Q Fsmifclock SMIF QSPI output clock frequency – – 80 MHz LP mode (1.1 V) SID390QU Fsmifclocku SMIF QSPI output clock frequency – – 50 MHz ULP mode (0.9 V). Guaranteed by Char. SID397Q Idd_qspi Block current in LP mode (1.1 V) – – 1900 µA LP mode (1.1 V) SID398Q Idd_qspi_u Block current in ULP mode (0.9 V) – – 590 µA ULP mode (0.9 V) SID391Q Tsetup Input data set-up time with respect to clock capturing falling edge 4.5 – – ns Guaranteed by characterization SID392Q Tdatahold Input data hold time with respect to clock capturing falling edge 1 – – ns – SID393Q Tdataoutvalid Output data valid time with respect to clock falling edge – – 3.7 ns 7.5-ns max for ULP mode (0.9 V) SID394Q Tholdtime Output data hold time with respect to clock rising edge 3 – – ns – SID395Q Tseloutvalid Output Select valid time with respect to clock rising edge – – 7.5 ns 15-ns max for ULP mode (0.9 V) SID396Q Tselouthold Output Select hold time with respect to clock rising edge Tsclk/2 – – ns Tsclk = Fsmifclk cycle time Audio Subsystem Table 45. Audio Subsystem Specifications Spec ID# Parameter Description Min Typ Max Units Details / Conditions PDM Specifications SID400P PDM_IDD1 PDM Active current, stereo operation, 1-MHz clock – 175 – µA 16-bit audio at 16 ksps SID401 PDM_IDD2 PDM Active current, stereo operation, 3-MHz clock – 600 – µA 24-bit audio at 48 ksps SID402[6] PDM_JITTER RMS jitter in PDM clock –200 – 200 ps – SID403[6] PDM_CLK PDM clock speed 0.384 – 3.072 MHz – SID403A[6] PDM_BLK_CLK PDM block input clock 1.024 – 49.152 MHz – SID403B[6] PDM_SETUP Data input set-up time to PDM_CLK edge 10 – – ns – SID403C[6] PDM_HOLD Data input hold time to PDM_CLK edge 10 – – ns – SID404[6] PDM_OUT Audio sample rate 8 – 48 ksps – SID405[6] PDM_WL Word length 16 – 24 bits – SID406[6] PDM_SNR Signal-to-Noise Ratio (A-weighted) – 100 – dB PDM input, 20 Hz to 20 kHz BW SID407[6] PDM_DR Dynamic range (A-weighted) – 100 – dB 20 Hz to 20 kHz BW, -60 dB FS SID408[6] PDM_FR Frequency response –0.2 – 0.2 dB DC to 0.45f, DC Blocking filter off. SID409[6] PDM_SB Stop band – 0.566 – f – Note 6. Guaranteed by design, not production tested. Document Number: 002-23185 Rev. *R Page 69 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 45. Audio Subsystem Specifications (continued) Spec ID# Parameter Description SID410[6] PDM_SBA Stop band attenuation SID411[6] PDM_GAIN Adjustable gain SID412[6] PDM_ST Startup time Min Typ Max Units – 60 – dB – Details / Conditions –12 – 10.5 dB PDM to PCM, 1.5 dB/step – 48 – Word Select (WS) cycles I2S Specifications. The same for LP and ULP modes unless stated otherwise. SID415 I2S_IDD Block current – 400 – µA SID413 I2S_WORD Length of I2S Word 8 – 32 bits SID414 I2S_WS Word clock frequency in LP mode – – 192 kHz 12.288-MHz bit clock with 32-bit word SID414M I2S_WS_U Word clock frequency in ULP mode – – 48 kHz 3.072-MHz bit clock with 32-bit word SID414A I2S_WS_TDM Word clock frequency in TDM mode for LP – – 48 kHz Eight 32-bit channels SID414X I2S_WS_TDM_U Word clock frequency in TDM mode for ULP – – 12 kHz Eight 32-bit channels I2S Slave Mode SID430 TS_WS WS setup time to the following rising edge of SCK for LP mode 5 – – ns – SID430U TS_WS_U WS setup time to the following rising edge of SCK for ULP mode 11 – – ns – SID430A TH_WS WS hold time to the following edge TMCLK_SOC[7] of SCK +5 – – ns – SID432 TD_SDO Delay time of TX_SDO transition -(TMCLK_SOC from edge of TX_SCK for LP mode +25) – TMCLK_S OC+25 ns Associated clock edge depends on selected polarity SID432U TD_SDO_U Delay time of TX_SDO transition from edge of TX_SCK for ULP mode -(TMCLK_SOC +70) – TMCLK_S OC+70 ns Associated clock edge depends on selected polarity SID433 TS_SDI RX_SDI setup time to the following edge of RX_SCK in LP mode 5 – – ns – SID433U TS_SDI_U RX_SDI setup time to the following edge of RX_SCK in ULP mode 11 – – ns – SID434 TH_SDI RX_SDI hold time to the rising edge of RX_SCK TMCLK_SOC+ 5 – – ns – SID435 TSCKCY TX/RX_SCK bit clock duty cycle 45 – 55 % – I2S Master Mode SID437 TD_WS WS transition delay from falling edge of SCK in LP mode –10 – 20 ns – SID437U TD_WS_U WS transition delay from falling edge of SCK in ULP mode –10 – 40 ns – SID438 TD_SDO SDO transition delay from falling edge of SCK in LP mode –10 – 20 ns – SID438U TD_SDO SDO transition delay from falling edge of SCK in ULP mode –10 – 40 ns – Note 7. TMCLK_SOC is the internal I2S master clock period. Document Number: 002-23185 Rev. *R Page 70 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 45. Audio Subsystem Specifications (continued) Spec ID# Parameter Description Min Typ Units Details / Conditions ns Associated clock edge depends on selected polarity – ns T is TX/RX_SCK Bit Clock period. Associated clock edge depends on selected polarity. – 55 % – 1.024 – 98.304 MHz FMCLK_SOC = 8*Bit-clock 1.024 – 24.576 MHz FMCLK_SOC_U = 8 * Bit-clock MCLK_SOC duty cycle 45 – 55 % – MCLK_SOC input jitter –100 – 100 ps – TS_SDI SDI setup time to the associated edge of SCK 5 SID440 TH_SDI SDI hold time to the associated edge of SCK TMCLK_SOC+ 5 – SID443 TSCKCY SCK bit clock duty cycle 45 SID445 FMCLK_SOC MCLK_SOC frequency in LP mode SID445U FMCLK_SOC_U MCLK_SOC frequency in ULP mode SID446 TMCLKCY SID447 TJITTER SID439 Max – – Smart I/O Table 46. Smart I/O Specifications Spec ID# Parameter Description SID420 SMIO_BYP Smart I/O bypass delay SID421 SMIO_LUT Smart I/O LUT prop delay Min – – Typ – 8 Max 2 – Units ns ns Details/Conditions – – SD Host Controller and eMMC Table 47. SD Host Controller and eMMC Specifications Spec ID# Parameter Description Min Typ Max Units Details / Conditions SD Host Controller and eMMC Specifications (SD Host clock (see the Clocking Diagram) must be divided by 2 or more when used as source in DDR modes. Specifications are Guaranteed by Design. SID_SD390 SD_DS I/O drive select drive_sel = '01' for all modes 4 – 4 mA SID_SD391 SD_TR Input transition time 0.7 – 3 ns – SD:DS Timing SID_SD392 SD_CLK Interface clock period (LP mode) – – 25 MHz (40-ns period) SID_SD393 SD_CLK Interface clock period (ULP mode) – – 8 MHz (125-ns period) SID_SD394 SD_DCMD_CL I/O loading at DATA/CMD pins – 30 – pF – SID_SD395 SD_CLK_CL I/O loading at CLK pins – 30 – pF – SID_SD396 SD_TS_OUT Output: Setup time of CMD/DAT prior to CLK 5.1 – – ns – SID_SD397 SD_HLD_OUT Output: Hold time of CMD/DAT after CLK 5.1 – – ns – SID_SD398 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (LP mode) 24 – – ns – SID_SD399 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (ULP mode) 109 – – ns – SID_SD400 SD_HLD_IN Input: Hold time of CMD/DAT after CLK 2.1 – – ns – SID_SD401 SD_CLK Interface clock period (LP mode) – – 45 MHz (20-ns period) SID_SD402 SD_CLK Interface clock period (ULP mode) – – 16 MHz (62.5-ns period) SD:HS Timing Document Number: 002-23185 Rev. *R Page 71 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 47. SD Host Controller and eMMC Specifications (continued) Min Typ Max Units SID_SD403 Spec ID# SD_DCMD_CL I/O loading at DATA/CMD pins Parameter Description – 30 – pF – Details / Conditions SID_SD404 SD_CLK_CL I/O loading at CLK pins – 30 – pF – SID_SD405 SD_TS_OUT Output: Setup time of CMD/DAT prior to CLK 6.1 – – ns – SID_SD406 SD_HLD_OUT Output: Hold time of CMD/DAT after CLK 2.1 – – ns – SID_SD407 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (LP mode) 8 – – ns – SID_SD408 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (ULP mode) 48 – – ns – SID_SD409 SD_HLD_IN Input: Hold time of CMD/DAT after CLK 2.5 – – ns – SD:SDR-12 Timing SID_SD410 SD_CLK Interface clock period (LP mode) – – 25 MHz (40-ns period) SID_SD411 SD_CLK Interface clock period (ULP mode) – – 8 MHz (125-ns period) SID_SD412 SD_CLK_DC Duty cycle of output CLK 30 – 70 % – SID_SD413 SD_DCMD_CL I/O loading at DATA/CMD pins – 30 – pF – SID_SD414 SD_CLK_CL I/O loading at CLK pins – 30 – pF – SID_SD415 SD_TS_OUT Output: Setup time of CMD/DAT prior to CLK 3.1 – – ns – SID_SD416 SD_HLD_OUT Output: Hold time of CMD/DAT after CLK 0.9 – – ns – SID_SD417 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (LP mode) 24 – – ns – SID_SD418 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (ULP mode) 109 – – ns – SID_SD419 SD_HLD_IN Input: Hold time of CMD/DAT after CLK 1.85 – – ns – – – 50 MHz (20-ns period) (62.5-ns period) SD:SDR-25 Timing SID_SD420 SD_CLK Interface clock period (LP mode) SID_SD421 SD_CLK Interface clock period (ULP mode) – – 16 MHz SID_SD422 SD_CLK_DC Duty cycle of output CLK 30 – 70 % – SID_SD423 SD_DCMD_CL I/O loading at DATA/CMD pins – 30 – pF – SID_SD424 SD_CLK_CL I/O loading at CLK pins – 30 – pF – SID_SD425 SD_TS_OUT Output: Setup time of CMD/DAT prior to CLK 3.1 – – ns – SID_SD426 SD_HLD_OUT Output: Hold time of CMD/DAT after CLK 0.9 – – ns – SID_SD427 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (LP mode) 5.8 – – ns – SID_SD428 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (ULP mode) 48 – – ns – SID_SD429 SD_HLD_IN Input: Hold time of CMD/DAT after CLK 1.8 – – ns – – – 80 MHz SD:SDR-50 Timing SID_SD430 SD_CLK Interface clock period (LP mode) Document Number: 002-23185 Rev. *R (12.5-ns period) Page 72 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 47. SD Host Controller and eMMC Specifications (continued) Min Typ Max Units SID_SD431 Spec ID# SD_CLK Parameter Interface clock period (ULP mode) Description – – 32 MHz Details / Conditions SID_SD432 SD_CLK_DC Duty cycle of output CLK 30 – 70 % – SID_SD433 SD_DCMD_CL I/O loading at DATA/CMD pins – 20 – pF – SID_SD434 SD_CLK_CL I/O loading at CLK pins – 20 – pF – SID_SD435 SD_TS_OUT Output: Setup time of CMD/DAT prior to CLK 3.1 – – ns – SID_SD436 SD_HLD_OUT Output: Hold time of CMD/DAT after CLK 0.9 – – ns – SID_SD437 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (LP mode) 5 – – ns – SID_SD438 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (ULP mode) 23 – – ns – SID_SD439 SD_HLD_IN Input: Hold time of CMD/DAT after CLK 1.8 – – ns – – – 40 MHz (25-ns period). (62.5-ns period) (31.25-ns period) SD:DDR-50 Timing SID_SD440 SD_CLK Interface clock period (LP mode) SID_SD441 SD_CLK Interface clock period (ULP mode) – – 16 MHz SID_SD442 SD_CLK_DC Duty cycle of output CLK 45 – 55 % – SID_SD443 SD_DCMD_CL I/O loading at DATA/CMD pins – 30 – pF – SID_SD444 SD_CLK_CL I/O loading at CLK pins – 30 – pF – SID_SD445 SD_TS_OUT Output: Setup time of CMD/DAT prior to CLK 3.1 – – ns – SID_SD446 SD_HLD_OUT Output: Hold time of CMD/DAT after CLK 0.9 – – ns – SID_SD447 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (LP mode) 5.75 – – ns – SID_SD448 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (ULP mode) 24 – – ns – SID_SD449 SD_HLD_IN Input: Hold time of CMD/DAT after CLK 1.8 – – ns – – 26 MHz (38.4-ns period) (125-ns period) eMMC:BWC Timing SID_SD450 SD_CLK Interface clock period (LP mode) – SID_SD451 SD_CLK Interface clock period (ULP mode) – – 8 MHz SID_SD452 SD_DCMD_CL I/O loading at DATA/CMD pins – 30 – pF – SID_SD453 SD_CLK_CL I/O loading at CLK pins – 30 – pF – SID_SD454 SD_TS_OUT Output: Setup time of CMD/DAT prior to CLK 3.1 – – ns – SID_SD455 SD_HLD_OUT Output: Hold time of CMD/DAT after CLK 3.1 – – ns – SID_SD456 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (LP mode) 9.7 – – ns – SID_SD457 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (ULP mode) 96 – – ns – SID_SD458 SD_HLD_IN Input: Hold time of CMD/DAT after CLK 8.3 – – ns – Document Number: 002-23185 Rev. *R Page 73 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Table 47. SD Host Controller and eMMC Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details / Conditions eMMC:SDR Timing SID_SD459 SD_CLK Interface clock period (LP mode) – – 52 MHz (19.2-ns period) SID_SD460 SD_CLK Interface clock period (ULP mode) – – 16 MHz (62.5-ns period) SID_SD461 SD_DCMD_CL I/O loading at DATA/CMD pins – 30 – pF – SID_SD462 SD_CLK_CL I/O loading at CLK pins – 30 – pF – SID_SD463 SD_TS_OUT Output: Setup time of CMD/DAT prior to CLK 3.1 – – ns – SID_SD464 SD_HLD_OUT Output: Hold time of CMD/DAT after CLK 3.1 – – ns – SID_SD465 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (LP mode) 5.3 – – ns – SID_SD466 SD_TS_IN Input: Setup time of CMD/DAT prior to CLK (ULP mode) 48 – – ns – SID_SD467 SD_HLD_IN Input: Hold time of CMD/DAT after CLK 2.5 – – ns – SID_SD400SD IDD_SD_1 SD Host block current consumption at 100 MHz – 4.65 5 mA – SID_SD401SD IDD_SD_2 SD Host block current consumption at 50 MHz – 3.75 4.3 mA – SD Host Block Current Specs JTAG Boundary Scan Table 48. JTAG Boundary Scan Spec ID# Parameter Description Min Typ Max Units JTAG Boundary Scan Parameters JTAG Boundary Scan Parameters for 1.1 V (LP) Mode Operation: SID468 TCKLOW TCK LOW 52 – – ns – SID469 TCKHIGH TCK HIGH 10 – – ns – SID470 TCK_TDO TCK falling edge to output valid – 40 ns – SID471 TSU_TCK Input valid to TCK rising edge 12 – – ns – SID472 TCk_THD Input hold time to TCK rising edge 10 – – ns – SID473 TCK_TDOV TCK falling edge to output valid (High-Z to Active). 40 – – ns – SID474 TCK_TDOZ TCK falling edge to output valid (Active to High-Z). 40 – – ns – TCK low 102 – – ns – 20 – – ns – – 80 ns – JTAG Boundary Scan Parameters for 0.9 V (ULP) Mode Operation: SID468A TCKLOW SID469A TCKHIGH TCK high SID470A TCK_TDO TCK falling edge to output valid SID471A TSU_TCK Input valid to TCK rising edge 22 – – ns – SID472A TCk_THD Input hold time to TCK rising edge 20 – – ns – SID473A TCK_TDOV TCK falling edge to output valid (high-Z to active). 80 – – ns – SID474A TCK_TDOZ TCK falling edge to output valid (active to high-Z). 80 – – ns – Document Number: 002-23185 Rev. *R Page 74 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Ordering Information Table 49 lists the CY8C62X8 and CY8C62XA part numbers and features. See also the product selector guide. 62 Arm CM4/CM0+, DC-DC converter, QSPI SMIF, 12-bit SAR ADC, 2 LPCOMPs, 13 SCBs, 32 TCPWMs, 2 I2S, 2 PDM, 2 SD Host Controllers, USB-FS MPN CM4 CPU Speed (LP/ULP) CM0+ CPU Speed (LP/ULP) Power Modes Flash (KB) SRAM (KB) CapSense Crypto GPIO Pin Package Base Features Family Table 49. Ordering Information CY8C624ABZI-S2D04 150/50 100/25 FLEX 2048 1024 – – 100 124 BGA CY8C624ABZI-S2D14 150/50 100/25 FLEX 2048 1024 Y – 100 124 BGA CY8C624AAZI-S2D14 150/50 100/25 FLEX 2048 1024 Y – 102 128 TQFP CY8C624ABZI-S2D44 150/50 100/25 FLEX 2048 1024 Y Y 100 124 BGA CY8C624AAZI-S2D44 150/50 100/25 FLEX 2048 1024 Y Y 102 128 TQFP CY8C624AFNI-S2D43 150/50 100/25 FLEX 2048 1024 Y Y 82 100 WLCSP CY8C624ALQI-S2D42 150/50 100/25 FLEX 2048 1024 Y Y 53 68 QFN CY8C624ALQI-S2D02 150/50 100/25 FLEX 2048 1024 – – 53 68 QFN CY8C6248AZI-S2D14 150/50 100/25 FLEX 1024 512 Y – 102 128 TQFP CY8C6248BZI-S2D44 150/50 100/25 FLEX 1024 512 Y Y 100 124 BGA CY8C6248AZI-S2D44 150/50 100/25 FLEX 1024 512 Y Y 102 128 TQFP CY8C6248FNI-S2D43 150/50 100/25 FLEX 1024 512 Y Y 82 100 WLCSP CY8C6248LQI-S2D42 150/50 100/25 FLEX 1024 512 Y Y 53 68 QFN CY8C6248LQI-S2D02 150/50 100/25 FLEX 1024 512 – – 53 68 QFN Document Number: 002-23185 Rev. *R Page 75 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet PSoC 6 MPN Decoder CY XX 6 A B C DD E - FF G H I JJ K L Field Description Values CY Cypress CY Cypress 8C Standard B0 “Secure Boot” v1 S0 “Standard Secure” - AWS XX 6 A B Firmware Architecture Line Speed 6 PSoC 6 0 Value 1 Programmable 2 Performance 3 Connectivity 4 Secured 2 100 MHz 3 150 MHz 4 150/50 MHz 0-3 C Memory Size (Flash/SRAM) Meaning Reserved 4 256K/128K 5 512K/256K 6 512K/128K 7 1024K/288K 8 1024K/512K 9 Reserved A 2048K/1024K Field Description E Temperature Range FF Feature Code Values C Consumer I Industrial Q Extended Industrial S2-S6 BL G CPU Core H Attributes Code I GPIO count JJ Engineering sample (optional) K Die Revision (optional) L Tape/Reel Shipment (optional) Meaning Cypress internal Integrated Bluetooth LE F Single Core D Dual Core 0–9 Feature set 1 31-50 2 51-70 3 71-90 4 91-110 ES Engineering samples or not Base A1-A9 T Die revision Tape and Reel shipment AZ, AX TQFP DD Package LQ QFN BZ BGA FM M-CSP FN, FD, WLCSP FT Document Number: 002-23185 Rev. *R Page 76 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Packaging This product line is offered in 124-BGA, 128-TQFP, 68-QFN, and 100-WLCSP packages. Table 50. Package Dimensions Spec ID# Package Description Package Dwg # PKG_1 124-BGA 124 BGA, 9 mm × 9 mm × 1 mm height with 0.65-mm pitch 001-97718 PKG_2 128-TQFP 128 TQFP, 14 mm × 20 mm × 1.4 mm height with 0.5-mm pitch 51-85101 PKG_3 PKG_4 100-WLCSP 100 WLCSP, 4.1 mm × 3.9 mm × 0.5 mm height with 0.5-mm pitch 68-QFN 002-23991 68 QFN, 8 × 8 ×1.0 mm, 6.2 × 6.2 mm EPAD (Sawn Type) 001-96836 Table 51. Package Characteristics Conditions Min Typ Max Units TA Parameter Operating ambient temperature Description – –40 25 85 °C TJ Operating junction temperature – –40 – 100 °C TJA Package JA (124-BGA) – – 31.9 – °C/watt TJC Package JC (124-BGA) – – 11 – °C/watt TJA Package JA (128-TQFP) – – 33.24 – °C/watt TJC Package JC (128-TQFP) – – 6 – °C/watt TJA Package JA (100-WLCSP) – – 19.1 – °C/watt TJC Package JC (100-WLCSP) – – 0.12 – °C/watt TJA Package JA (68-QFN) – – 15.4 – °C/watt TJC Package JC (68-QFN) – – 2 – °C/watt Table 52. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature All packages 260 °C 30 seconds Table 53. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 124-BGA MSL 3 128-TQFP MSL 3 68-QFN MSL 3 100-WLCSP MSL 1 Document Number: 002-23185 Rev. *R Page 77 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 21. 124-BGA 9.0 × 9.0 ×1.0 mm 001-97718 *B Document Number: 002-23185 Rev. *R Page 78 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 22. 128-TQFP 14.0 × 20.0 ×1.4 mm 51-85101 *F Document Number: 002-23185 Rev. *R Page 79 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 23. 100-WLCSP 4.1068 × 3.9025 × 0.467mm 002-23991 *A Document Number: 002-23185 Rev. *R Page 80 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 24. 68-QFN Package Diagram 001-96836 *A Document Number: 002-23185 Rev. *R Page 81 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Acronyms Acronym Description 3DES triple DES (data encryption standard) ADC analog-to-digital converter ADMA3 advanced DMA version 3, a Secure Digital data transfer mode AES advanced encryption standard AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm data transfer bus AMUX analog multiplexer Acronym ESD Description electrostatic discharge ETM embedded trace macrocell FIFO first-in, first-out FLL frequency locked loop FPU floating-point unit FS full-speed GND Ground GPIO general-purpose input/output, applies to a PSoC pin AMUXBUS analog multiplexer bus HMAC Hash-based message authentication code API application programming interface HSIOM high-speed I/O matrix Arm® advanced RISC machine, a CPU architecture I/O input/output, see also GPIO, DIO, SIO, USBIO BGA ball grid array I2C, or IIC Inter-Integrated Circuit, a communications protocol inter-IC sound integrated circuit BOD brown-out detect I2S BREG backup registers IC BWC backward compatibility (eMMC data transfer mode) IDAC current DAC, see also DAC, VDAC CAD computer aided design IDE integrated development environment CCO current controlled oscillator ILO internal low-speed oscillator, see also IMO ChaCha a stream cipher IMO internal main oscillator, see also ILO CM0+ Cortex-M0+, an Arm CPU INL integral nonlinearity, see also DNL CM4 Cortex-M4, an Arm CPU IOSS input output subsystem CMAC cypher-based message authentication code IoT internet of things CMOS complementary metal-oxide-semiconductor, a process technology for IC fabrication IPC inter-processor communication IRQ interrupt request CMRR common-mode rejection ratio ISR interrupt service routine CPU central processing unit ITM instrumentation trace macrocell CRC cyclic redundancy check, an error-checking protocol JTAG Joint Test Action Group CSD CapSense Sigma-Delta LCD liquid crystal display LIN Local Interconnect Network, a communications protocol CSV clock supervisor CSX Cypress mutual capacitance sensing method. See also CSD LP low power CTI cross trigger interface LS low-speed DAC digital-to-analog converter, see also IDAC, VDAC LUT lookup table DAP debug access port LVD low-voltage detect, see also LVI DDR double data rate LVI low-voltage interrupt DES data encryption standard LVTTL low-voltage transistor-transistor logic DFT design for test MAC multiply-accumulate DMA direct memory access, see also TD MCU microcontroller unit DNL differential nonlinearity, see also INL MCWDT multi-counter watchdog timer DSI digital system interconnect MISO master-in slave-out DU data unit MMIO memory-mapped input output ECC error correcting code MOSI master-out slave-in ECC elliptic curve cryptography MPU memory protection unit ECO external crystal oscillator MSL moisture sensitivity level EEPROM electrically erasable programmable read-only memory Msps million samples per second EMI electromagnetic interference MTB micro trace buffer eMMC embedded MultiMediaCard MUL multiplier Document Number: 002-23185 Rev. *R Page 82 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Acronym Description NC no connect NMI nonmaskable interrupt NVIC nested vectored interrupt controller NVL nonvolatile latch, see also WOL OTP one-time programmable OVP over voltage protection OVT overvoltage tolerant PASS programmable analog subsystem PCB printed circuit board PCM pulse code modulation PDM pulse density modulation PHY physical layer PICU port interrupt control unit PLL phase-locked loop PMIC power management integrated circuit POR power-on reset PPU peripheral protection unit PRNG pseudo random number generator PSoC® Acronym SONOS SPI Description silicon-oxide-nitride-oxide-silicon, a flash memory technology Serial Peripheral Interface, a communications protocol SRAM static random access memory SROM supervisory read-only memory SRSS system resources subsystem SWD serial wire debug, a test protocol SWJ serial wire JTAG SWO single wire output SWV single-wire viewer TCPWM timer, counter, pulse-width modulator TDM time division multiplexed THD total harmonic distortion TQFP thin quad flat package TRM technical reference manual TRNG true random number generator TX transmit Programmable System-on-Chip™ UART PSRR power supply rejection ratio Universal Asynchronous Transmitter Receiver, a communications protocol PWM pulse-width modulator UDB universal digital block QD quadrature decoder QSPI quad serial peripheral interface RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square ROM read-only memory RSA Rivest–Shamir–Adleman, a public-key cryptography algorithm RTC real-time clock RWW read-while-write RX receive S/H sample and hold SAR successive approximation register SARMUX SAR ADC multiplexer bus SC/CT switched capacitor/continuous time SCB serial communication block SCL I2C serial clock SD Secure Digital SDA I2C serial data SDR single data rate Sflash supervisory flash SHA secure hash algorithm SINAD signal to noise and distortion ratio SMPU shared memory protection unit SNR signal-to-noise ratio SOF start of frame Document Number: 002-23185 Rev. *R ULP ultra-low power USB Universal Serial Bus WCO watch crystal oscillator WDT watchdog timer WIC wakeup interrupt controller WLCSP wafer level chip scale package XIP execute-in-place XRES external reset input pin Page 83 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Document Conventions Units of Measure Table 54. Units of Measure (continued) Table 54. Units of Measure Symbol Symbol Unit of Measure Unit of Measure µH microhenry microsecond °C degrees Celsius µs dB decibel µV microvolt fF femto farad µW microwatt Hz hertz mA milliampere KB 1024 bytes ms millisecond kbps kilobits per second mV millivolt khr kilohour nA nanoampere kHz kilohertz ns nanosecond k kilo ohm nV nanovolt ksps kilosamples per second W ohm LSB least significant bit pF picofarad Mbps megabits per second ppm parts per million MHz megahertz ps picosecond M mega-ohm s second Msps megasamples per second sps samples per second µA microampere sqrtHz square root of hertz microfarad V volt µF Document Number: 002-23185 Rev. *R Page 84 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Revision History Description Title: PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Document Number: 002-23185 Submission Revision ECN Description of Change Date ** 6085299 03/01/2018 New datasheet for PSoC 6A-2M. Updated the number of SCBs and removed CAN feature and specifications. *A 6100523 03/16/2018 Updated Multiple Alternate Functions. Updated Features. Updated Block Diagram. Updated IMO Clock Source, Watchdog Timer (WDT), Clock Dividers, Serial Communication Blocks (SCB). Updated GPIO. Updated Quad-SPI/Serial Memory Interface (SMIF). Added a note in Pinouts. Removed pins P14.1 and P14.0. *B 6169663 05/16/2018 Updated typ value for SID15. Updated Notes 2 and 3. Updated description for SID246. Updated Conditions for SID.CSD#15, SID.CSD#15A, and SID308A. Updated min and max values for SID314A, SID315A, and SID172B. Added SID308P Updated specs SID454, SID455, and SID408. Added Table 41. Updated Block Diagram. Updated CPU and Memory Subsystem. *C 6184665 05/24/2018 Updated SDHC Controllers. Updated SID262 description. Updated SDHC and eMMC Specifications. Added Security information (Protection Contexts and Protection Units). Changed Power Mode nomenclature to reflect Minimum Regulator Current mode instead *D 6235143 07/10/2018 of LPA/LPS. Revised SDHC and eMMC specs based on STA. Added note on drive setting valid for all AC specs. Added JTAG Boundary scan specs. Added 128 TQFP and 100 WLCSP pin and package information. Removed SID65A. Updated SID75, SID76, and SID245 max values. *E 6340009 10/09/2018 Updated SID421 typ value. Added CY8C624ABZI-D44ES(T) in Ordering Information. Added part numbering nomenclature table. Added Errata Document Number: 002-23185 Rev. *R Page 85 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Description Title: PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Document Number: 002-23185 Updated the title and replaced PSoC 6A-2M with PSoC CY8C62x8 and CY8C62xA PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet. Updated Features and Blocks and Functionality. Updated Development Ecosystem. Replaced “component” with “driver”. Updated System Resources and Fixed-Function Digital. *F 6420256 01/21/2019 Updated Pinouts Updated Power Supply Considerations. Updated Power Connections diagram. Updated CPU Current and Transition Times table. Removed spec SID13A Updated Ordering Information. Replaced “dual core” with “dual CPU.” *G 6564322 05/03/2019 Updated Block Diagram. Updated CY8C62x8, CY8C62xA Pinouts and Multiple Alternate Functions. Updated the title. *H 6660660 09/16/2019 Updated Ordering Information. Updated Features. *I 6756960 12/20/2019 Updated Blocks and Functionality and Functional Description. Updated Pinouts and Power Supply Considerations. Updated Features and Functional Description Updated Pinouts Updated Electrical Specifications based on Characterization: Added 2Ms/sec specs to SAR *J 6839822 03/27/2020 specs, updated SMIF, ECO, and SDHC specs Updated Ordering Information. Updated Errata. Updated SAR ADC 1 Msps references to 2 Msps. Removed reference to e.MMC DDR mode. Edited SAR specs to split VDDA dependent specs into separate specs instead of having *K 6854009 04/17/2020 qualifying comments. Also moved Supply Range specs from Description column to Details/Conditions column. Added SAR ADC 2 Msps supply current specs. Updated SAR ADC input impedance RC values to support 9RC 2 Msps sampling. Updated Development Ecosystem, GPIO, and LCD sections. *L 6891487 06/11/2020 Added External Crystal Oscillators. Updated Errata. Document Number: 002-23185 Rev. *R Page 86 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Description Title: PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Document Number: 002-23185 Updated Flexible Clocking Options and Block Diagram. Updated list of application notes and links in PSoC 6 MCU Resources. Updated ModusToolbox Software. Updated Clocking Diagram. Updated Power Supply Considerations. Updated CPUs and added InterProcessor Communication (IPC). Updated Analog Subsystem diagram. *M 6973720 10/09/2020 Updated the XRES bullet in Reset, SID15 Description and Conditions, and System Resources (Power-On-Reset specifications). Updated SD Host Controllers and SD Host Controller and eMMC Specifications. Updated SID7A conditions, SID7C description, and SID8 conditions. Added footnote to TMCLK_SOC specs. Integrated ECO erratum into External Crystal Oscillators. Added ECO Usage Guidelines table. Updated Security terminology to Infineon standards. Changed BLE references to Bluetooth LE. *N 7147463 06/03/2021 Added Table 12 and Figure 20 in Electrical Specifications. Added 68-QFN pin and package details. Updated Ordering Information. Corrected typo in Table 7. *O 7383583 10/19/2021 Updated SIDC1 description. Updated details/conditions for SID7A. *P 7469751 11/24/2021 Updated SID325U, SID328, and SID329 description. *Q 7750278 04/12/2022 Updated eFuse information in the Memory section. Added device identification and revision information in Features. Added spec SID415 and SID304P. *R 7787179 10/26/2022 Added footnote "Guaranteed by design, not production tested" for specs SID402 - SID412. Updated Clock System and PLL Specifications. Updated Protection Units. Document Number: 002-23185 Rev. *R Page 87 of 88 PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Community | Code Examples | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2018-2022. This document is the property of Cypress Semiconductor Corporation, an Infineon Technologies company, and its affiliates ("Cypress"). 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Cypress, the Cypress logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, Traveo, WICED, and ModusToolbox are trademarks or registered trademarks of Cypress or a subsidiary of Cypress in the United States or in other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-23185 Rev. *R Revised October 26, 2022 Page 88 of 88
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