CY8C42xx-BL
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
General description
PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system
controllers with an Arm® Cortex®-M0 CPU. It combines programmable and reconfigurable analog and digital
blocks with flexible automatic routing. The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE product
family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth® Low Energy,
also known as Bluetooth® smart, radio and subsystem (BLESS). The other features include digital programmable
logic, high-performance analog-to-digital conversion (ADC), opamps with Comparator mode, and standard
communication and timing peripherals. The programmable analog and digital subsystems allow flexibility and
in-field tuning of the design.
Features
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0 CPU with single-cycle multiply and DMA
- Up to 256 KB of flash with read accelerator
- Up to 32 KB of SRAM
• Bluetooth® LE radio and subsystem
- Bluetooth® LE 4.2 support
- 2.4-GHz RF transceiver with 50-Ω antenna drive
- Digital PHY
- Link-layer engine supporting master and slave modes
- RF output power: –18 dBm to +3 dBm
- RX sensitivity: –89 dBm
- RX current: 18.7 mA
- TX current: 15.6 mA at 0 dBm
- Received Signal Strength Indication (RSSI): 1-dB resolution
• Programmable analog
- Four opamps with reconfigurable high-drive external and high-bandwidth internal drive, Comparator modes,
and ADC input buffering capability. Can operate in Deep Sleep mode.
- 12-bit, 1-Msps SAR ADC with differential and single-ended modes; Channel Sequencer with signal averaging
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep mode
• Programmable digital
- Four programmable logic blocks called universal digital blocks, (UDBs), each with eight macrocells and data
path
- Infineon-provided peripheral component library, user-defined state machines, and Verilog input
• Power management
- Active mode: 1.7 mA at 3-MHz flash program execution
- Deep Sleep mode: 1.5 µA with watch crystal oscillator (WCO) on
- Hibernate mode: 150 nA with RAM retention
- Stop mode: 60 nA
• Capacitive sensing
- Capacitive sigma-delta (CSD) provides best-in-class SNR (>5:1) and liquid tolerance
- Infineon-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning algorithm (SmartSense)
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Features
• Segment LCD drive
- LCD drive supported on all pins (common or segment)
- Operates in Deep Sleep mode with four bits per pin memory
• Serial communication
- Two independent run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI,
or UART functionality
• Timing and pulse-width modulation
- Four 16-bit timer/counter pulse-width modulator (TCPWM) blocks
- Center-aligned, Edge, and Pseudo-random modes
- Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications
• Up to 36 programmable GPIOs
- 7 mm × 7 mm 56-pin QFN package
- 76-ball CSP package
- 68-ball CSP package
- Any GPIO pin can be CAPSENSE™, LCD, analog, or digital
- Two overvoltage-tolerant (OVT) pins; drive modes, strengths, and slew rates are programmable
• PSoC™ Creator design environment
- Integrated Design Environment (IDE) provides schematic design entry and build (with analog and digital
automatic routing)
- API components for all fixed-function and programmable peripherals
• Industry-standard tool compatibility
- After schematic entry, development can be done with Arm®-based industry-standard development tools
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
More information
More information
There is a wealth of data at www.infineon.com to help you to select the right PSoC™ device for your design, and
to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources,
see the introduction page for Bluetooth® Low Energy products. Following is an abbreviated list for PSoC™ 4
CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE:
• Overview: PSoC™ portfolio
• Product selectors: PSoC™ 1, PSoC™ 3, PSoC™ 4, PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE,
PSoC™ 5LP. In addition, PSoC™ Creator includes a device selection tool.
• Application notes: There are a large number of PSoC™ application notes covering a broad range of topics, from
basic to advanced level. Recommended application notes for getting started with PSoC™ 4 CY8C4xxx-BL MCU
with AIROC™ Bluetooth® LE are:
- AN91267: Getting started with PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE
- AN97060: PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE and PRoC-BLE - Over-The-Air (OTA) Device
Firmware Upgrade (DFU) guide
- AN91184: PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE - Designing Bluetooth® LE applications
- AN91162: Creating a Bluetooth® LE Custom Profile
- AN91445: Antenna design and RF layout guidelines
- AN96841: Getting started With EZ-BLE module
- AN85951: PSoC™ 4 CAPSENSE™ design guide
- AN95089: PSoC™ 4/PRoC-Bluetooth® LE crystal oscillator selection and tuning techniques
- AN92584: Designing for low power and estimating battery life for Bluetooth® LE applications
• Technical reference manual (TRM) is in two documents:
- Architecture TRM details each PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE functional block.
- Registers TRM describes each of the PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE registers.
• Development kits:
- CY8CKIT-042-BLE-A Pioneer Kit, is a flexible, Arduino-compatible, Bluetooth® LE development kit for
PSoC™ 4 with AIROC™ Bluetooth® LE.
- CY8CKIT-142, PSoC™ 4 with AIROC™ Bluetooth® LE Module, features a PSoC™ 4 CY8C4xxx-BL MCU with AIROC™
Bluetooth® LE device, two crystals for the antenna matching network, a PCB antenna, and other passives,
while providing access to all GPIOs of the device.
- CY8CKIT-143, PSoC™ 4 with AIROC™ Bluetooth® LE 256 KB module, features a PSoC™ 4 CY8C4xxx-BL MCU with
AIROC™ Bluetooth® LE 256 KB device, two crystals for the antenna matching network, a PCB antenna, and
other passives, while providing access to all GPIOs of the device.
- The MiniProg3 device provides an interface for flash programming and debug.
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
PSoC™ Creator
PSoC™ Creator
PSoC™ Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware
and firmware design of PSoC™ 3, PSoC™ 4, and PSoC™ 5LP based systems. Create designs using classic, familiar
schematic capture supported by over 100 pre-verified, production-ready PSoC™ Components; see the list of
component datasheets. With PSoC™ Creator, you can
1. Drag and drop component icons to build your hardware system design in the main design workspace
2. Codesign your application firmware with the PSoC™ hardware, using the PSoC™ Creator IDE C compiler
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets
1
4
2
5
3
Figure 1
Datasheet
Multiple-sensor example project in PSoC™ Creator contents
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
More information ..............................................................................................................................3
PSoC™ Creator ..................................................................................................................................4
Table of contents ...............................................................................................................................5
Block diagram...................................................................................................................................7
1 Functional definition.......................................................................................................................8
1.1 CPU and memory subsystem .................................................................................................................................8
1.1.1 CPU .......................................................................................................................................................................8
1.1.2 Flash .....................................................................................................................................................................8
1.1.3 SRAM.....................................................................................................................................................................8
1.1.4 SROM ....................................................................................................................................................................8
1.1.5 DMA.......................................................................................................................................................................8
1.2 System Resources ...................................................................................................................................................8
1.2.1 Power System ......................................................................................................................................................8
1.2.2 Clock system ........................................................................................................................................................9
1.2.3 IMO clock source ..................................................................................................................................................9
1.2.4 ILO clock source ...................................................................................................................................................9
1.2.5 External crystal oscillator (ECO)..........................................................................................................................9
1.2.6 Watch crystal oscillator (WCO) ............................................................................................................................9
1.2.7 Watchdog timer....................................................................................................................................................9
1.2.8 Reset ...................................................................................................................................................................10
1.2.9 Voltage Reference ..............................................................................................................................................10
1.3 Bluetooth® LE radio and subsystem ....................................................................................................................11
1.4 Analog blocks ........................................................................................................................................................12
1.4.1 12-bit SAR ADC ...................................................................................................................................................12
1.4.2 Opamps (CTBm block).......................................................................................................................................12
1.4.3 Temperature sensor ..........................................................................................................................................13
1.4.4 Low-power comparators ...................................................................................................................................13
1.5 Programmable digital...........................................................................................................................................13
1.5.1 Universal digital blocks (UDBs) and port interfaces ........................................................................................13
1.6 Fixed-function digital............................................................................................................................................14
1.6.1 Timer/counter/PWM block ................................................................................................................................14
1.6.2 Serial Communication Blocks (SCB) .................................................................................................................14
1.7 GPIO.......................................................................................................................................................................15
1.8 Special-function peripherals................................................................................................................................16
1.8.1 LCD segment drive .............................................................................................................................................16
1.8.2 CAPSENSE™ ........................................................................................................................................................16
2 Pinouts ........................................................................................................................................17
3 Power ..........................................................................................................................................27
4 Development support ...................................................................................................................28
4.1 Documentation .....................................................................................................................................................28
4.2 Online ....................................................................................................................................................................28
4.3 Tools ......................................................................................................................................................................28
5 Electrical specifications.................................................................................................................29
5.1 Absolute maximum ratings .................................................................................................................................29
5.2 Device-level specifications ...................................................................................................................................30
5.2.1 GPIO....................................................................................................................................................................33
5.2.2 XRES ...................................................................................................................................................................35
5.3 Analog peripherals................................................................................................................................................36
5.3.1 Opamp................................................................................................................................................................36
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Table of contents
5.3.2 Temperature sensor ..........................................................................................................................................38
5.3.3 SAR ADC ..............................................................................................................................................................39
5.3.4 CSD .....................................................................................................................................................................40
5.4 Digital peripherals.................................................................................................................................................41
5.4.1 Timer ..................................................................................................................................................................41
5.4.2 Counter ..............................................................................................................................................................42
5.4.3 Pulse width modulation (PWM) ........................................................................................................................43
5.4.4 I2C .......................................................................................................................................................................43
5.4.5 LCD direct drive..................................................................................................................................................44
5.4.6 SPI specifications ...............................................................................................................................................45
5.5 Memory..................................................................................................................................................................46
5.6 System resources..................................................................................................................................................47
5.6.1 Power-on reset (POR) ........................................................................................................................................47
5.6.2 Voltage monitors ...............................................................................................................................................48
5.6.3 SWD interface ....................................................................................................................................................48
5.6.4 Internal main oscillator .....................................................................................................................................49
5.6.5 Internal low-speed oscillator ............................................................................................................................49
6 Ordering information ....................................................................................................................55
6.1 Ordering code definitions.....................................................................................................................................56
7 Packaging ....................................................................................................................................57
7.1 WLCSP compatibility ............................................................................................................................................59
8 Acronyms .....................................................................................................................................63
9 Document conventions..................................................................................................................67
9.1 Units of measure ...................................................................................................................................................67
Revision history ..............................................................................................................................68
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Block diagram
Block diagram
CPU Subsystem
4200
SWD/ TC
SPCIF
Cortex®
M0
32-bit
48 MHz
FAST MUL
NVIC , IRQMUX
AHB- Lite
Flash
Up to 256 KB
SRAM
Up to 32 KB
ROM
8 KB
DataWire /
DMA
Read Accelerator
SRAM Controller
ROM Controller
Initiator /MMIO
System Resources
SARMUX
CTBm
x2
2 x OpAmp
UDB
x4
Port Interface & Digital System Interconnect ( DSI)
Bluetooth® LE Baseband
Peripheral
1 KB SRAM
GFSK Modem
2. 4 GHz
GFSK
Radio
LDO
x1
...
Bluetooth® Low
Energy Subsystem
32kHz X O
UDB
2x LP Comparator
SAR ADC
( 12-bit)
Programmable
Digital
LCD
Programmable
Analog
24M Hz X O
Test
Digital DFT
Analog DFT
Peripheral Interconnect (MMIO )
PCLK
2x S C B-I2 C/S PI/UA R T
Reset
Reset Control
XRES
Peripherals
CAPSENSE™
Clock
Clock Control
WDT
IMO
ILO
System Interconnect (Multi Layer AHB )
IO S S G PIO (7x ports)
Power
Sleep Control
WIC
POR
LVD
REF
BOD
PWRSYS
NVLatches
4x T C P W M
PSoC™
I/O : Antenna/Power /Crystal
High Speed I / O Matrix
Power Modes
Active/ Sleep
DeepSleep
Hibernate
36 x GPIOs , 2 x GPIO _ OVT
I/O Subsystem
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
The Arm® SWD interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the
standard programming connections are required to fully support debugging.
The PSoC™ Creator IDE provides fully integrated programming and debugging support for the PSoC™ 4
CY8C42xx-BL MCU with AIROC™ Bluetooth® LE devices. The SWD interface is fully compatible with
industry-standard third-party tools. With the ability to disable debug features, very robust flash protection, and
allowing customer-proprietary functionality to be implemented in on-chip programmable blocks, the PSoC™ 4
CY8C42xx-BL MCU with AIROC™ Bluetooth® LE family provides a level of security not possible with multi-chip
application solutions or with microcontrollers.
Debug circuits are enabled by default and can only be disabled in firmware. If not enabled, the only way to
re-enable them is to erase the entire device, clear flash protection, and reprogram the device with the new
firmware that enables debugging.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned
about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and
interrupting flash programming sequences. Because all programming, debug, and test interfaces are disabled
when maximum device security is enabled, PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE with device
security enabled may not be returned for failure analysis. This is a trade-off the PSoC™ 4 CY8C42xx-BL MCU with
AIROC™ Bluetooth® LE allows the customer to make.
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
1
Functional definition
1.1
CPU and memory subsystem
1.1.1
CPU
The Cortex®-M0 CPU in PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with extensive clock gating. It mostly uses 16-bit
instructions and executes a subset of the Thumb-2 instruction set. This enables fully compatible binary upward
migration of the code to higher-performance processors such as Cortex®-M3 and M4. The implementation
includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt
controller (NVIC) block with 32 interrupt inputs and a wakeup interrupt controller (WIC). The WIC can wake the
processor up from the Deep Sleep mode, allowing power to the main processor to be switched off when the chip
is in the Deep Sleep mode. The Cortex®-M0 CPU provides a nonmaskable interrupt (NMI) input, which is made
available to the user when it is not in use for system functions requested by the user.
The CPU also includes an SWD interface, which is a 2-wire form of JTAG; the debug configuration used for PSoC™
4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE has four break-point (address) comparators and two watchpoint
(data) comparators.
1.1.2
Flash
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE device has a flash module with 256 KB of flash
memory, tightly coupled to the CPU to improve average access times from the flash block. The flash block is
designed to deliver 2 wait-state (WS) access time at 48 MHz and with 1-WS access time at 24 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash module can be
used to emulate EEPROM operation if required. Maximum erase and program time is 20 ms per row (256 bytes).
This also applies to the emulated EEPROM.
1.1.3
SRAM
SRAM memory is retained during Hibernate.
1.1.4
SROM
The 8-KB supervisory ROM contains a library of executable functions for flash programming. These functions are
accessed through supervisory calls (SVC) and enable in-system programming of the flash memory.
1.1.5
DMA
A DMA engine, with eight channels, is provided that can do 32-bit transfers and has chainable ping-pong
descriptors.
1.2
System Resources
1.2.1
Power System
The power system is described in detail in the section “Power” on page 27. It provides an assurance that the
voltage levels are as required for the respective modes, and can either delay the mode entry (on power-on reset
(POR), for example) until voltage levels are as required or generate resets (brownout detect (BOD)) or interrupts
when the power supply reaches a particular programmable level between 1.8 and 4.5 V (low voltage detect
(LVD)). PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE operates with a single external supply (1.71 to 5.5 V
without radio, and 1.9 V to 5.5 V with radio). The device has five different power modes; transitions between these
modes are managed by the power system. PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE provides Sleep,
Deep Sleep, Hibernate, and Stop low-power modes. Refer to the Technical Reference Manual for more details.
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
1.2.2
Clock system
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE clock system is responsible for providing clocks to all
subsystems that require clocks and for switching between different clock sources without glitching. In addition,
the clock system ensures that no metastable conditions occur.
The clock system for PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE consists of the internal main
oscillator (IMO), the internal low-speed oscillator (ILO), the 24-MHz external crystal oscillator (ECO) and the
32-kHz watch crystal oscillator (WCO). In addition, an external clock may be supplied from a pin.
1.2.3
IMO clock source
The IMO is the primary source of internal clocking in PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE. It is
trimmed during testing to achieve the specified accuracy. Trim values are stored in nonvolatile latches (NVL).
Additional trim settings from flash can be used to compensate for changes. The IMO default frequency is 24 MHz
and it can be adjusted between 3 to 48 MHz in steps of 1 MHz. The IMO tolerance with Infineon-provided
calibration settings is ±2%.
1.2.4
ILO clock source
The ILO is a very low-power oscillator, which is primarily used to generate clocks for the peripheral operation in
the Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. A software
component is provided, which does the calibration.
1.2.5
External crystal oscillator (ECO)
The ECO is used as the active clock for the Bluetooth® LE subsystem to meet the ±50-ppm clock accuracy of the
Bluetooth® 4.2 Specification. PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE includes a tunable load
capacitor to tune the crystal clock frequency by measuring the actual clock frequency. The high-accuracy ECO
clock can also be used as a system clock.
1.2.6
Watch crystal oscillator (WCO)
The WCO is used as the sleep clock for the Bluetooth® LE subsystem to meet the ±500-ppm clock accuracy for the
Bluetooth® 4.2 Specification. The sleep clock provides an accurate sleep timing and enables wakeup at the
specified advertisement and connection intervals. The WCO output can be used to realize the real-time clock
(RTC) function in firmware.
1.2.7
Watchdog timer
A watchdog timer is implemented in the clock block running from the ILO or from the WCO; this allows the
watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the timeout occurs.
The watchdog reset is recorded in the Reset Cause register. With the WCO and firmware, an accurate real-time
clock (within the bounds of the 32-kHz crystal accuracy) can be realized.
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
HFCLK
ECO
Pre scal er
Divider
/2 n (n=0..3)
Divider 0
(/16)
SYSCLK
PER0_CLK
IMO
EXTCLK
Divider 9
(/16)
Fractional
Divider 0
(/16.5)
WCO
Fractional
Divider 1
(/16.5)
LFCLK
ILO
Figure 2
PER15_CLK
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE MCU clocking architecture
The HFCLK signal can be divided down (see Figure 2) to generate synchronous clocks for the UDBs, and the
analog and digital peripherals. There are a total of 12 clock dividers for PSoC™ 4 CY8C42xx-BL MCU with AIROC™
Bluetooth® LE: ten with 16-bit divide capability and two with 16.5-bit divide capability. This allows the generation
of 16 divided clock signals, which can be used by peripheral blocks. The analog clock leads the digital clocks to
allow analog events to occur before the digital clock-related noise is generated. The 16-bit and 16.5-bit dividers
allow a lot of flexibility in generating fine-grained frequency values and are fully supported in PSoC™ Creator.
1.2.8
Reset
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE device can be reset from a variety of sources including a
software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through resets and allows the software to determine the cause of the reset.
An XRES pin is reserved for an external reset to avoid complications with the configuration and multiple pin
functions during power-on or reconfiguration. The XRES pin has an internal pull-up resistor that is always
enabled.
1.2.9
Voltage Reference
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE reference system generates all internally required
references. A one-percent voltage reference spec is provided for the 12-bit ADC. To allow better signal-to-noise
ratios (SNR) and better absolute accuracy, it is possible to bypass the internal reference using a REF pin or use an
external reference for the SAR. See Table 21 for details.
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
1.3
Bluetooth® LE radio and subsystem
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE incorporates a Bluetooth® Smart subsystem that contains
the Physical Layer (PHY) and Link Layer (LL) engines with an embedded AES-128 security engine. The physical
layer consists of the digital PHY and the RF transceiver that transmits and receives GFSK packets at 1 Mbps over
a 2.4-GHz ISM band, which is compliant with Bluetooth® Smart Bluetooth® Specification 4.2. The baseband
controller is a composite hardware and firmware implementation that supports both master and slave modes.
Key protocol elements, such as HCI and link control, are implemented in firmware. Time-critical functional
blocks, such as encryption, CRC, data whitening, and access code correlation, are implemented in hardware (in
the LL engine).
The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50-Ω
antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from the
antenna to a digital bit stream after performing GFSK demodulation. In the transmit direction, this block
performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting
it to air through the antenna.
The Bluetooth® smart radio and subsystem (BLESS) requires a 1.9-V minimum supply (the range varies from 1.9 V
to 5.5 V).
Key features of BLESS are as follows:
• Master and slave single-mode protocol stack with logical link control and adaptation protocol (L2CAP), attribute
(ATT), and security manager (SM) protocols
• API access to generic attribute profile (GATT), generic access profile (GAP), and L2CAP
• L2CAP connection-oriented channel
• GAP features
- Broadcaster, Observer, Peripheral, and Central roles
- Security mode 1: Level 1, 2, 3, and 4
- Security mode 2: Level 1 and 2
- User-defined advertising data
- Multiple bond support
• GATT features
- GATT client and server
- Supports GATT sub-procedures
- 32-bit universally unique identifier (UUID)
• Security Manager (SM)
- Pairing methods: Just works, Passkey Entry, Out of Band, and Numeric Comparison
- Authenticated man-in-the-middle (MITM) protection and data signing
- LE secure connections (Bluetooth® 4.2 feature)
• Link layer (LL)
- Master and Slave roles
- 128-bit AES engine
- Encryption
- Low-duty cycle advertising
- LE ping
- LE data packet length extension (Bluetooth® 4.2 feature)
- Link layer privacy (with extended scanning filter policy, Bluetooth® 4.2 feature)
• Supports all SIG-adopted Bluetooth® LE profiles
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
1.4
Analog blocks
1.4.1
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks
at that frequency to do a 12-bit conversion.
The block functionality is augmented for the user by adding a reference buffer to it (trimmable to ±1%) and by
providing the choice of three internal voltage references, VDD, VDD/2, and VREF (nominally 1.024 V), as well as an
external reference through a REF pin. The sample-and-hold (S/H) aperture is programmable; it allows the gain
bandwidth requirements of the amplifier driving the SAR inputs, which determine its settling time, to be relaxed
if required. System performance will be 65 dB for true 12-bit precision provided appropriate references are used
and system noise levels permit it. To improve the performance in noisy conditions, it is possible to provide an
external bypass (through a fixed pin location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through the
selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, the
aggregate sampling bandwidth is equal to 1 Msps whether it is for a single channel or distributed over several
channels). The sequencer switching is effected through a state machine or through firmware-driven switching. A
feature provided by the sequencer is the buffering of each channel to reduce CPU interrupt-service requirements.
To accommodate signals with varying source impedances and frequencies, it is possible to have different sample
times programmable for each channel. Also, the signal range specification through a pair of range registers (low
and high range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds
the programmed range; this allows fast detection of out-of-range values without having to wait for a sequencer
scan to be completed and the CPU to read the values and check for out-of-range values in software.
The SAR is able to digitize the output of the on-chip temperature sensor for calibration and other
temperature-dependent functions. The SAR is not available in Deep Sleep and Hibernate modes as it requires a
high-speed clock (up to 18 MHz). The SAR operating range is 1.71 to 5.5 V.
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
vminus vplus
Data and
Status Flags
POS
SARADC
NEG
Reference
Selection
P7
SARMUX
Port 3 (8 inputs)
P0
Sequencing
and Control
VDD/2
VDDD
External
Reference
and Bypass
(optional)
VREF
Inputs from other Ports
Figure 3
SAR ADC system diagram
1.4.2
Opamps (CTBm block)
PSoC™ CY8C42x8_BLE has four opamps with Comparator modes, which allow most common analog functions to
be performed on-chip, eliminating external components. PGAs, voltage buffers, filters, transimpedance
amplifiers, and other functions can be realized with external passives saving power, cost, and space. The on-chip
opamps are designed with enough bandwidth to drive the sample-and-hold circuit of the ADC without requiring
external buffering.
Datasheet
12
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
1.4.3
Temperature sensor
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE has an on-chip temperature sensor. This consists of a
diode, which is biased by a current source that can be disabled to save power. The temperature sensor is
connected to the ADC, which digitizes the reading and produces a temperature value by using a Infineon-supplied
software that includes calibration and linearization.
1.4.4
Low-power comparators
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE has a pair of low-power comparators, which can also
operate in Deep Sleep and Hibernate modes. This allows the analog system blocks to be disabled while retaining
the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally
synchronized to avoid metastability unless operating in an asynchronous power mode (Hibernate) where the
system wake-up circuit is activated by a comparator-switch event.
1.5
Programmable digital
1.5.1
Universal digital blocks (UDBs) and port interfaces
The PSoC™ 4XX8 BLE 4.2 has four UDBs; the UDB array also provides a switched Digital System Interconnect (DSI)
fabric that allows signals from peripherals and ports to be routed to and through the UDBs for communication
and control.
System
Interconnect
CPU
Sub -system
Clocks
8 to 32
4 to 8
BUS IF
Other Digital
Signals in Chip
Routing
Channels
IRQ IF
DSI
CLK IF
Port
IF IF
Port
Port
IF
DSI
UDB
UDB
UDB
UDB
DSI
DSI
High -Spee d I/O Matrix
UDBIF
Programmable Digital Subsystem
Figure 4
UDB array
UDBs can be clocked from a clock-divider block, from a port interface (required for peripherals such as SPI), and
from the DSI network directly or after synchronization.
A port interface is defined, which acts as a register that can be clocked with the same source as the PLDs inside
the UDB array. This allows a faster operation because the inputs and outputs can be registered at the port
interface close to the I/O pins and at the edge of the array. The port interface registers can be clocked by one of
the I/Os from the same port. This allows interfaces such as SPI to operate at higher clock speeds by eliminating
the delay for the port input to be routed over DSI and used to register other inputs (see Figure 5).
Datasheet
13
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
High Speed I/O Matrix
To Clock
Tree
8
Input Registers
7
Digital
GlobalClocks
3 DSI Signals ,
1 I/O Signal
9
4
Clock Selector
Block from
UDB
6
...
0
7
...
2
0
3
2
1
0
[1]
4
8
[1]
[0]
To DSI
Figure 5
6
Enables
[1]
8
Reset Selector
Block from
UDB
4
Output Registers
[0]
2
8
8
From DSI
[1]
From DSI
Port interface
UDBs can generate interrupts (one UDB at a time) to the interrupt controller. UDBs retain the ability to connect
to any pin on the chip through the DSI.
1.6
Fixed-function digital
1.6.1
Timer/counter/PWM block
The timer/counter/PWM block consists of four 16-bit counters with user-programmable period length. There is a
capture register to record the count value at the time of an event (which may be an I/O event), a period register
which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare
registers to generate compare value signals which are used as PWM duty cycle outputs. The block also provides
true and complementary outputs with programmable offset between them to allow the use as deadband
programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state;
for example, this is used in motor-drive systems when an overcurrent state is indicated and the PWMs driving the
FETs need to be shut off immediately with no time for software intervention.
1.6.2
Serial Communication Blocks (SCB)
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE has two SCBs, each of which can implement an I2C, UART,
or SPI interface.
I2C mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of multimaster
arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible
buffering options to reduce the interrupt overhead and latency for the CPU. It also supports EzI2C that creates a
mailbox address range in the memory of PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE and effectively
reduces the I2C communication to reading from and writing to an array in the memory. In addition, the block
supports an 8-deep FIFO for receive and transmit, which, by increasing the time given for the CPU to read the
data, greatly reduces the need for clock stretching caused by the CPU not having read the data on time. The FIFO
mode is available in all channels and is very useful in the absence of DMA.
The I2C peripheral is compatible with I2C Standard-mode, Fast-mode, and Fast-Mode Plus devices as defined in
the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in
open-drain modes.
SCB1 is fully compliant with Standard mode (100 kHz), Fast mode (400 kHz), and Fast-Mode Plus (1 MHz) I2C
signaling specifications when routed to GPIO pins P5[0] and P5[1], except for hot-swap capability during I2C
active communication. The remaining GPIOs do not meet the hot-swap specification (VDD off; draw < 10-µA
current) for Fast mode and Fast-Mode Plus, IOL Spec (20 mA) for Fast-Mode Plus, hysteresis spec (0.05 VDD) for
Fast mode and Fast-Mode Plus, and minimum fall time spec for Fast mode and Fast-Mode Plus.
Datasheet
14
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
• GPIO cells, including P5.0 and P5.1, cannot be hot-swapped or powered up independent of the rest of the I2C
system.
• The GPIO pins P5.0 and P5.1 are over-voltage tolerant but cannot be hot-swapped or powered up independent
of the rest of the I2C system
• Fast-Mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8 mA
IOL with a VOL maximum of 0.6 V.
• Fast-mode and Fast-Mode Plus specify minimum Fall times, which are not met with the GPIO cell; the
Slow-Strong mode can help meet this spec depending on the bus load.
UART mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface
(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic
UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals
connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame
error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. Note that
hardware handshaking is not supported. This is not commonly used and can be implemented with a UDB-based
UART in the system, if required.
SPI mode: The SPI mode supports full Motorola SPI, TI Secure Simple Pairing (SSP) (essentially adds a start pulse
that is used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use
the FIFO for transmit and receive.
1.7
GPIO
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE has 36 GPIOs. The GPIO block implements the following:
• Eight drive strength modes:
- Analog input mode (input and output buffers disabled)
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL)
• Pins 0 and 1 of Port 5 are overvoltage-tolerant pins
• Individual control of input and output buffer enabling/disabling in addition to drive-strength modes
• Hold mode for latching previous state (used for retaining the I/O state in Deep Sleep and Hibernate modes)
• Selectable slew rates for dV/dt-related noise control to improve EMI
The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the
blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A
multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex between various signals that
may connect to an I/O pin. Pin locations for fixed-function peripherals are also fixed to reduce internal
multiplexing complexity (these signals do not go through the DSI network). DSI signals are not affected by this
and any pin may be routed to any UDB through the DSI network.
Data output and pin-state registers store, respectively, the values to be driven on the pins and the states of the
pins themselves.
Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt
service routine (ISR) vector associated with it (5 for PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE).
Datasheet
15
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2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
1.8
Special-function peripherals
1.8.1
LCD segment drive
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE has an LCD controller, which can drive up to four
commons and up to 32 segments. It uses full digital methods to drive the LCD segments requiring no generation
of internal LCD voltages. The two methods used are referred to as digital correlation and PWM.
The digital correlation method modulates the frequency and levels of the common and segment signals to
generate the highest RMS voltage across a segment to light it up or to keep the RMS signal zero. This method is
good for STN displays but may result in reduced contrast with TN (cheaper) displays.
The PWM method drives the panel with PWM signals to effectively use the capacitance of the panel to provide the
integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher
power consumption but can result in better results when driving TN displays. LCD operation is supported during
Deep Sleep mode, refreshing a small display buffer (four bits; one 32-bit register per port).
1.8.2
CAPSENSE™
CAPSENSE™ is supported on all pins in PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE through a
CAPSENSE™ Sigma-Delta (CSD) block that can be connected to any pin through an analog mux bus that any GPIO
pin can be connected to via an Analog switch. CAPSENSE™ function can thus be provided on any pin or group of
pins in a system under software control. A Component is provided for the CAPSENSE™ block to make it easy for
the user.
The shield voltage can be driven on another mux bus to provide liquid-tolerance capability. Liquid tolerance is
provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from
attenuating the sensed input.
The CAPSENSE™ block has two IDACs which can be used for general purposes if CAPSENSE™ is not being used
(both IDACs are available in that case) or if CAPSENSE™ is used without liquid tolerance (one IDAC is available).
Datasheet
16
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
2
Pinouts
Table 1, Table 2, and Table 3 show pin list for 56-pin QFN, 68-ball WLCSP, and 76-ball WLCSP packages of PSoC™
4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE respectively. Port 3 consists of the high-speed analog inputs for
the SAR mux. All pins support CSD CAPSENSE™ and analog mux bus connections.
Table 1
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(56-pin QFN package)
Pin
Name
Type
1
VDDD
POWER
1.71-V to 5.5-V digital supply
2
XTAL32O/P6.0
CLOCK
32.768-kHz crystal
3
XTAL32I/P6.1
CLOCK
32.768-kHz crystal or external clock input
4
XRES
RESET
Reset, active LOW
5
P4.0
GPIO
Port 4 Pin 0, lcd, csd
6
P4.1
GPIO
Port 4 Pin 1, lcd, csd
7
P5.0
GPIO
Port 5 Pin 0, lcd, csd
8
P5.1
GPIO
Port 5 Pin 1, lcd, csd
9
VSSD
GROUND
10
VDDR
POWER
1.9-V to 5.5-V radio supply
11
GANT1
GROUND
Antenna shielding ground
12
ANT
ANTENNA
Antenna pin
13
GANT2
GROUND
Antenna shielding ground
14
VDDR
POWER
1.9-V to 5.5-V radio supply
15
VDDR
POWER
1.9-V to 5.5-V radio supply
16
XTAL24I
CLOCK
24-MHz crystal or external clock input
17
XTAL24O
CLOCK
24-MHz crystal
18
VDDR
POWER
1.9-V to 5.5-V radio supply
19
P0.0
GPIO
Port 0 Pin 0, lcd, csd
20
P0.1
GPIO
Port 0 Pin 1, lcd, csd
21
P0.2
GPIO
Port 0 Pin 2, lcd, csd
22
P0.3
GPIO
Port 0 Pin 3, lcd, csd
23
VDDD
POWER
24
P0.4
GPIO
Port 0 Pin 4, lcd, csd
25
P0.5
GPIO
Port 0 Pin 5, lcd, csd
26
P0.6
GPIO
Port 0 Pin 6, lcd, csd
27
P0.7
GPIO
Port 0 Pin 7, lcd, csd
28
P1.0
GPIO
Port 1 Pin 0, lcd, csd
29
P1.1
GPIO
Port 1 Pin 1, lcd, csd
30
P1.2
GPIO
Port 1 Pin 2, lcd, csd
31
P1.3
GPIO
Port 1 Pin 3, lcd, csd
32
P1.4
GPIO
Port 1 Pin 4, lcd, csd
33
P1.5
GPIO
Port 1 Pin 5, lcd, csd
34
P1.6
GPIO
Port 1 Pin 6, lcd, csd
35
P1.7
GPIO
Port 1 Pin 7, lcd, csd
Datasheet
Description
17
Digital ground
1.71-V to 5.5-V digital supply
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
Table 1
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(56-pin QFN package) (continued)
Pin
Name
Type
36
VDDA
POWER
37
P2.0
GPIO
Port 2 Pin 0, lcd, csd
38
P2.1
GPIO
Port 2 Pin 1, lcd, csd
39
P2.2
GPIO
Port 2 Pin 2, lcd, csd
40
P2.3
GPIO
Port 2 Pin 3, lcd, csd
41
P2.4
GPIO
Port 2 Pin 4, lcd, csd
42
P2.5
GPIO
Port 2 Pin 5, lcd, csd
43
P2.6
GPIO
Port 2 Pin 6, lcd, csd
44
P2.7
GPIO
Port 2 Pin 7, lcd, csd
45
VREF
REF
External reference input or bypass capacitor
46
VDDA
POWER
47
P3.0
GPIO
Port 3 Pin 0, lcd, csd
48
P3.1
GPIO
Port 3 Pin 1, lcd, csd
49
P3.2
GPIO
Port 3 Pin 2, lcd, csd
50
P3.3
GPIO
Port 3 Pin 3, lcd, csd
51
P3.4
GPIO
Port 3 Pin 4, lcd, csd
52
P3.5
GPIO
Port 3 Pin 5, lcd, csd
53
P3.6
GPIO
Port 3 Pin 6, lcd, csd
54
P3.7
GPIO
Port 3 Pin 7, lcd, csd
55
VSSA
GROUND
56
VCCD
POWER
57
EPAD
GROUND
Table 2
Description
1.71-V to 5.5-V analog supply
1.71-V to 5.5-V analog supply
Analog ground
Regulated 1.8-V supply, connect to 1.3-µF
capacitor.
Ground paddle for the QFN package
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(68-ball WLCSP package)
Pin
Name
Type
A1
VREF
REF
A2
VSSA
GROUND
A3
P3.3
GPIO
Port 3 Pin 3, lcd, csd
A4
P3.7
GPIO
Port 3 Pin 7, lcd, csd
A5
VSSD
GROUND
Digital ground
A6
VSSA
GROUND
Analog ground
A7
VCCD
POWER
Regulated 1.8-V supply, connect to 1-μF capacitor
A8
VDDD
POWER
1.71-V to 5.5-V radio supply
B1
P2.3
GPI
B2
VSSA
GROUND
B3
P2.7
GPIO
Port 2 Pin 7, lcd, csd
B4
P3.4
GPIO
Port 3 Pin 4, lcd, csd
Datasheet
Pin description
External reference input or bypass capacitor
Analog ground
Port 2 Pin 3, lcd, csd
18
Analog ground
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
Table 2
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(68-ball WLCSP package) (continued)
Pin
Name
Type
B5
P3.5
GPIO
Port 3 Pin 5, lcd, csd
B6
P3.6
GPIO
Port 3 Pin 6, lcd, csd
B7
XTAL32I/P6.1
CLOCK
32.768-kHz crystal or external clock input
B8
XTAL32O/P6.0
CLOCK
32.768-kHz crystal
C1
VSSA
GROUND
C2
P2.2
GPIO
Port 2 Pin 2, lcd, csd
C3
P2.6
GPIO
Port 2 Pin 6, lcd, csd
C4
P3.0
GPIO
Port 3 Pin 0, lcd, csd
C5
P3.1
GPIO
Port 3 Pin 1, lcd, csd
C6
P3.2
GPIO
Port 3 Pin 2, lcd, csd
C7
XRES
RESET
Reset, active LOW
C8
P4.0
GPIO
Port 4 Pin 0, lcd, csd
D1
P1.7
GPIO
Port 1 Pin 7, lcd, csd
D2
VDDA
POWER
D3
P2.0
GPIO
Port 2 Pin 0, lcd, csd
D4
P2.1
GPIO
Port 2 Pin 1, lcd, csd
D5
P2.5
GPIO
Port 2 Pin 5, lcd, csd
D6
VSSD
GROUND
D7
P4.1
GPIO
Port 4 Pin 1, lcd, csd
D8
P5.0
GPIO
Port 5 Pin 0, lcd, csd
E1
P1.2
GPIO
Port 1 Pin 2, lcd, csd
E2
P1.3
GPIO
Port 1 Pin 3, lcd, csd
E3
P1.4
GPIO
Port 1 Pin 4, lcd, csd
E4
P1.5
GPIO
Port 1 Pin 5, lcd, csd
E5
P1.6
GPIO
Port 1 Pin 6, lcd, csd
E6
P2.4
GPIO
Port 2 Pin 4, lcd, csd
E7
P5.1
GPIO
Port 5 Pin 1, lcd, csd
E8
VSSD
GROUND
Digital ground
F1
VSSD
GROUND
Digital ground
F2
P0.7
GPIO
Port 0 Pin 7, lcd, csd
F3
P0.3
GPIO
Port 0 Pin 3, lcd, csd
F4
P1.0
GPIO
Port 1 Pin 0, lcd, csd
F5
P1.1
GPIO
Port 1 Pin 1, lcd, csd
F6
VSSR
GROUND
Radio ground
F7
VSSR
GROUND
Radio ground
F8
VDDR
POWER
G1
P0.6
GPIO
G2
VDDD
POWER
G3
P0.2
GPIO
Datasheet
Pin description
Analog ground
1.71-V to 5.5-V analog supply
Digital ground
1.9-V to 5.5-V radio supply
Port 0 Pin 6, lcd, csd
1.71-V to 5.5-V digital supply
Port 0 Pin 2, lcd, csd
19
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
Table 2
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(68-ball WLCSP package) (continued)
Pin
Name
Type
G4
VSSD
GROUND
Digital ground
G5
VSSR
GROUND
Radio ground
G6
VSSR
GROUND
Radio ground
G7
GANT
GROUND
Antenna shielding ground
G8
VSSR
GROUND
Radio ground
H1
P0.5
GPIO
Port 0 Pin 5, lcd, csd
H2
P0.1
GPIO
Port 0 Pin 1, lcd, csd
H3
XTAL24O
CLOCK
24-MHz crystal
H4
XTAL24I
CLOCK
24-MHz crystal or external clock input
H5
VSSR
GROUND
Radio ground
H6
VSSR
GROUND
Radio ground
H7
ANT
ANTENNA
Antenna pin
J1
P0.4
GPIO
Port 0 Pin 4, lcd, csd
J2
P0.0
GPIO
Port 0 Pin 0, lcd, csd
J3
VDDR
POWER
1.9-V to 5.5-V radio supply
J6
VDDR
POWER
1.9-V to 5.5-V radio supply
J7
No Connect
-
Table 3
Pin description
-
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(76-ball WLCSP package)
Pin
Name
Type
A1
NC
NC
Do not connect
A2
VREF
REF
External reference input or bypass capacitor
A3
VSSA
GROUND
A4
P3.3
GPIO
Port 3 Pin 3, analog/digital/lcd/csd
A5
P3.7
GPIO
Port 3 Pin 7, analog/digital/lcd/csd
A6
VSSD
GROUND
Digital ground
A7
VSSA
GROUND
Analog ground
A8
VCCD
POWER
Regulated 1.8-V supply, connect to 1-μF capacitor
A9
VDDD
POWER
1.71-V to 5.5-V digital supply
B1
NB
NO BALL
No Ball
B2
P2.3
GPIO
B3
VSSA
GROUND
B4
P2.7
GPIO
Port 2 Pin 7, analog/digital/lcd/csd
B5
P3.4
GPIO
Port 3 Pin 4, analog/digital/lcd/csd
B6
P3.5
GPIO
Port 3 Pin 5, analog/digital/lcd/csd
B7
P3.6
GPIO
Port 3 Pin 6, analog/digital/lcd/csd
B8
XTAL32I/P6.1
CLOCK
32.768-kHz crystal or external clock input
B9
XTAL32O/P6.0
CLOCK
32.768-kHz crystal
Datasheet
Description
Analog ground
Port 2 Pin 3, analog/digital/lcd/csd
Analog ground
20
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
Table 3
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(76-ball WLCSP package) (continued)
Pin
Name
Type
C1
NC
NC
Do not connect
C2
VSSA
GROUND
Analog ground
C3
P2.2
GPIO
Port 2 Pin 2, analog/digital/lcd/csd
C4
P2.6
GPIO
Port 2 Pin 6, analog/digital/lcd/csd
C5
P3.0
GPIO
Port 3 Pin 0, analog/digital/lcd/csd
C6
P3.1
GPIO
Port 3 Pin 1, analog/digital/lcd/csd
C7
P3.2
GPIO
Port 3 Pin 2, analog/digital/lcd/csd
C8
XRES
RESET
Reset, active LOW
C9
P4.0
GPIO
Port 4 Pin 0, analog/digital/lcd/csd
D1
NC
NC
D2
P1.7
GPIO
D3
VDDA
POWER
D4
P2.0
GPIO
Port 2 Pin 0, analog/digital/lcd/csd
D5
P2.1
GPIO
Port 2 Pin 1, analog/digital/lcd/csd
D6
P2.5
GPIO
Port 2 Pin 5, analog/digital/lcd/csd
D7
VSSD
GROUND
D8
P4.1
GPIO
Port 4 Pin 1, analog/digital/lcd/csd
D9
P5.0
GPIO
Port 5 Pin 0, analog/digital/lcd/csd
E1
NC
NC
E2
P1.2
GPIO
Port 1 Pin 2, analog/digital/lcd/csd
E3
P1.3
GPIO
Port 1 Pin 3, analog/digital/lcd/csd
E4
P1.4
GPIO
Port 1 Pin 4, analog/digital/lcd/csd
E5
P1.5
GPIO
Port 1 Pin 5, analog/digital/lcd/csd
E6
P1.6
GPIO
Port 1 Pin 6, analog/digital/lcd/csd
E7
P2.4
GPIO
Port 2 Pin 4, analog/digital/lcd/csd
E8
P5.1
GPIO
Port 5 Pin 1, analog/digital/lcd/csd
E9
VSSD
GROUND
Digital ground
F1
NC
NC
Do not connect
F2
VSSD
GROUND
Digital ground
F3
P0.7
GPIO
Port 0 Pin 7, analog/digital/lcd/csd
F4
P0.3
GPIO
Port 0 Pin 3, analog/digital/lcd/csd
F5
P1.0
GPIO
Port 1 Pin 0, analog/digital/lcd/csd
F6
P1.1
GPIO
Port 1 Pin 1, analog/digital/lcd/csd
F7
VSSR
GROUND
Radio ground
F8
VSSR
GROUND
Radio ground
F9
VDDR
POWER
G1
NC
NC
G2
P0.6
GPIO
G3
VDDD
POWER
Datasheet
Description
Do not connect
Port 1 Pin 7, analog/digital/lcd/csd
1.71-V to 5.5-V analog supply
Digital ground
Do not connect
1.9-V to 5.5-V radio supply
Do not connect
Port 0 Pin 6, analog/digital/lcd/csd
1.71-V to 5.5-V digital supply
21
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
Table 3
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(76-ball WLCSP package) (continued)
Pin
Name
Type
G4
P0.2
GPIO
G5
VSSD
GROUND
Digital ground
G6
VSSR
GROUND
Radio ground
G7
VSSR
GROUND
Radio ground
G8
GANT
GROUND
Antenna shielding ground
G9
VSSR
GROUND
Radio ground
H1
NC
NC
H2
P0.5
GPIO
Port 0 Pin 5, analog/digital/lcd/csd
H3
P0.1
GPIO
Port 0 Pin 1, analog/digital/lcd/csd
H4
XTAL24O
CLOCK
24-MHz crystal
H5
XTAL24I
CLOCK
24-MHz crystal or external clock input
H6
VSSR
GROUND
Radio ground
H7
VSSR
GROUND
Radio ground
H8
ANT
ANTENNA
Antenna pin
J1
NC
NC
J2
P0.4
GPIO
Port 0 Pin 4, analog/digital/lcd/csd
J3
P0.0
GPIO
Port 0 Pin 0, analog/digital/lcd/csd
J4
VDDR
POWER
1.9-V to 5.5-V radio supply
J7
VDDR
POWER
1.9-V to 5.5-V radio supply
J8
NO CONNECT
–
Datasheet
Description
Port 0 Pin 2, analog/digital/lcd/csd
Do not connect
Do not connect
–
22
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
High-speed I/O matrix (HSIOM) is a group of high-speed switches that routes GPIOs to the resources inside the
device. These resources include CAPSENSE™, TCPWMs, I2C, SPI, UART, and LCD. HSIOM_PORT_SELx are
32-bit-wide registers that control the routing of GPIOs. Each register controls one port; four dedicated bits are
assigned to each GPIO in the port. This provides up to 16 different options for GPIO routing as shown in Table 4.
Table 4
HSIOM port settings
Value
Description
0
Firmware-controlled GPIO
1
Output is firmware-controlled, but Output Enable (OE) is controlled from DSI.
2
Both output and OE are controlled from DSI.
3
Output is controlled from DSI, but OE is firmware-controlled.
4
Pin is a CSD sense pin
5
Pin is a CSD shield pin
6
Pin is connected to AMUXA
7
Pin is connected to AMUXB
8
Pin-specific Active function #0
9
Pin-specific Active function #1
10
Pin-specific Active function #2
11
Reserved
12
Pin is an LCD common pin
13
Pin is an LCD segment pin
14
Pin-specific Deep-Sleep function #0
15
Pin-specific Deep-Sleep function #1
Datasheet
23
002-23053 Rev. *B
2023-03-29
Name
Analog
Digital
GPIO
Active #0
Active #1
Active #2
Deep Sleep #0
Deep Sleep #1
24
002-23053 Rev. *B
2023-03-29
P0.0
COMP0_INP
GPIO
TCPWM0_P[3]
SCB1_UART_RX[1]
–
SCB1_I2C_SDA[1]
SCB1_SPI_MOSI[1]
P0.1
COMP0_INN
GPIO
TCPWM0_N[3]
SCB1_UART_TX[1]
–
SCB1_I2C_SCL[1]
SCB1_SPI_MISO[1]
P0.2
–
GPIO
TCPWM1_P[3]
SCB1_UART_RTS[1]
–
COMP0_OUT[0]
SCB1_SPI_SS0[1]
P0.3
–
GPIO
TCPWM1_N[3]
SCB1_UART_CTS[1]
–
COMP1_OUT[0]
SCB1_SPI_SCLK[1]
P0.4
COMP1_INP
GPIO
TCPWM1_P[0]
SCB0_UART_RX[1]
EXT_CLK[0]/
ECO_OUT[0]
SCB0_I2C_SDA[1]
SCB0_SPI_MOSI[1]
P0.5
COMP1_INN
GPIO
TCPWM1_N[0]
SCB0_UART_TX[1]
–
SCB0_I2C_SCL[1]
SCB0_SPI_MISO[1]
P0.6
–
GPIO
TCPWM2_P[0]
SCB0_UART_RTS[1]
–
SWDIO[0]
SCB0_SPI_SS0[1]
P0.7
–
GPIO
TCPWM2_N[0]
SCB0_UART_CTS[1]
–
SWDCLK[0]
SCB0_SPI_SCLK[1]
P1.0
CTBm1_OA0_INP
GPIO
TCPWM0_P[1]
–
–
COMP0_OUT[1]
WCO_OUT[2]
P1.1
CTBm1_OA0_INN
GPIO
TCPWM0_N[1]
–
–
COMP1_OUT[1]
SCB1_SPI_SS1
P1.2
CTBm1_OA0_OUT
GPIO
TCPWM1_P[1]
–
–
–
SCB1_SPI_SS2
P1.3
CTBm1_OA1_OUT
GPIO
TCPWM1_N[1]
–
–
–
SCB1_SPI_SS3
P1.4
CTBm1_OA1_INN
GPIO
TCPWM2_P[1]
SCB0_UART_RX[0]
–
SCB0_I2C_SDA[0]
SCB0_SPI_MOSI[1]
P1.5
CTBm1_OA1_INP
GPIO
TCPWM2_N[1]
SCB0_UART_TX[0]
–
SCB0_I2C_SCL[0]
SCB0_SPI_MISO[1]
P1.6
CTBm1_OA0_INP
GPIO
TCPWM3_P[1]
SCB0_UART_RTS[0]
–
–
SCB0_SPI_SS0[1]
P1.7
CTBm1_OA1_INP
GPIO
TCPWM3_N[1]
SCB0_UART_CTS[0]
–
–
SCB0_SPI_SCLK[1]
P2.0
CTBm0_OA0_INP
GPIO
–
–
–
–
SCB0_SPI_SS1
P2.1
CTBm0_OA0_INN
GPIO
–
–
–
–
SCB0_SPI_SS2
P2.2
CTBm0_OA0_OUT
GPIO
–
–
–
WAKEUP
SCB0_SPI_SS3
P2.3
CTBm0_OA1_OUT
GPIO
–
–
–
–
WCO_OUT[1]
P2.4
CTBm0_OA1_INN
GPIO
–
–
–
–
–
P2.5
CTBm0_OA1_INP
GPIO
–
–
–
–
–
P2.6
CTBm0_OA0_INP
GPIO
–
–
–
–
–
P2.7
CTBm0_OA1_INP
GPIO
–
–
EXT_CLK[1]/ECO_OUT[1] –
–
P3.0
SARMUX_0
GPIO
TCPWM0_P[2]
SCB0_UART_RX[2]
–
SCB0_I2C_SDA[2]
–
P3.1
SARMUX_1
GPIO
TCPWM0_N[2]
SCB0_UART_TX[2]
–
SCB0_I2C_SCL[2]
–
P3.2
SARMUX_2
GPIO
TCPWM1_P[2]
SCB0_UART_RTS[2]
–
–
–
P3.3
SARMUX_3
GPIO
TCPWM1_N[2]
SCB0_UART_CTS[2]
–
–
–
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Port pin connections
Based on Arm® Cortex®-M0
Table 5
Pinouts
Datasheet
The selection of peripheral function for different GPIO pins is given in Table 5.
Analog
Digital
GPIO
Active #0
Active #1
Active #2
Deep Sleep #0
Deep Sleep #1
P3.4
SARMUX_4
GPIO
TCPWM2_P[2]
SCB1_UART_RX[2]
–
SCB1_I2C_SDA[2]
–
P3.5
SARMUX_5
GPIO
TCPWM2_N[2]
SCB1_UART_TX[2]
–
SCB1_I2C_SCL[2]
–
P3.6
SARMUX_6
GPIO
TCPWM3_P[2]
SCB1_UART_RTS[2]
–
–
–
P3.7
SARMUX_7
GPIO
TCPWM3_N[2]
SCB1_UART_CTS[2]
–
–
WCO_OUT[0]
P4.0
CMOD
GPIO
TCPWM0_P[0]
SCB1_UART_RTS[0]
–
–
SCB1_SPI_MOSI[0]
P4.1
CTANK
GPIO
TCPWM0_N[0]
SCB1_UART_CTS[0]
–
–
SCB1_SPI_MISO[0]
P5.0
–
GPIO
TCPWM3_P[0]
SCB1_UART_RX[0]
EXTPA_EN
SCB1_I2C_SDA[0]
P5.1
–
GPIO
TCPWM3_N[0]
SCB1_UART_TX[0]
EXT_CLK[2]/ECO_OUT[2] SCB1_I2C_SCL[0]
SCB1_SPI_SCLK[0]
P6.0_XTAL32
O
–
GPIO
–
–
–
–
–
P6.1_XTAL32I
–
GPIO
–
–
–
–
–
SCB1_SPI_SS0[0]
25
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Name
Based on Arm® Cortex®-M0
Port pin connections (continued)
Pinouts
Datasheet
Table 5
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
The possible pin connections are shown for all analog and digital peripherals (except the radio, LCD, and CSD
blocks, which were shown in Table 1). A typical system application connection diagram is shown in Figure 6.
VDDA
C1
1.3 uF
1.0
C4
24pF
pF
18
U1
2
EPAD
VCCD
VSSA
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
VDDA
VREF
P2.7
P2.6
Y2
1
VDDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
ANTENNA
VDDR
1
2
C6
L1
PSoC™ 4XXX-BLE
PSoC 4XXX_BLE
56-QFN
VDDR
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
VDDA
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDA
15
16
17
18
19
20
21
22
23
24
25
26
27
28
C5
VDDD
XTAL32O/P6.0
XTAL32I/P6.1
XRES
P4.0
P4.1
P5.0
P5.1
VSS
VDDR
GANT1
ANT
GANT2
VDDR
VDDR
XTAL24I
XTAL24O
VDDR
P0.0
P0.1
P0.2
P0.3
VDDD
P0.4
P0.5
P0.6
P0.7
P1.0
32.768KHz
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
C3
47
36pF
pF
C2
1.0 uF
1
VDDD
2
3
Y1
24MHz
4
SWDIO
SWDCLK
VDDR
Figure 6
Datasheet
System application connection diagram
26
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Power
3
Power
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE device can be supplied from batteries with a voltage
range of 1.9 V to 5.5 V by directly connecting to the digital supply (VDDD), analog supply (VDDA), and radio supply
(VDDR) pins. Internal LDOs in the device regulate the supply voltage to the required levels for different blocks.
The device has one regulator for the digital circuitry and separate regulators for radio circuitry for noise isolation.
Analog circuits run directly from the analog supply (VDDA) input. The device uses separate regulators for Deep
Sleep and Hibernate (lowered power supply and retention) modes to minimize the power consumption. The
radio stops working below 1.9 V, but the device continues to function down to 1.71 V without RF.
Bypass capacitors must be used from VDDx (x = A, D, or R) to ground. The typical practice for systems in this
frequency range is to use a capacitor in the 1-µF range in parallel with a smaller capacitor (for example, 0.1 µF).
Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and
the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing.
Table 6
Power supply
Power supply
Bypass capacitors
VDDD
The internal bandgap may be bypassed with a 1-µF to 10-µF.
VDDA
0.1-µF ceramic at each pin plus bulk capacitor 1-µF to 10-µF.
VDDR
0.1-µF ceramic at each pin plus bulk capacitor 1-µF to 10-µF.
VCCD
1.3-µF ceramic capacitor at the VCCD pin.
VREF (optional)
The internal bandgap may be bypassed with a 1-µF to 10-µF capacitor.
Datasheet
27
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Development support
4
Development support
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE family has a rich set of documentation, development
tools, and online resources to assist you during your development process. See PSoC™ 4 MCU with AIROC™
Bluetooth® LE to find out more.
4.1
Documentation
A suite of documentation supports the PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE family to ensure
that you can find answers to your questions quickly. This section contains a list of some of the key documents.
Software user guide: A step-by-step guide for using PSoC™ Creator. The software user guide shows you how the
PSoC™ Creator build process works in detail, how to use source control with PSoC™ Creator, and much more.
Component datasheets: The flexibility of PSoC™ allows the creation of new peripherals (Components) long after
the device has gone into production. Component datasheets provide all of the information needed to select and
use a particular Component, including a functional description, API documentation, example code, and AC/DC
specifications.
Application notes: PSoC™ application notes discuss a particular application of PSoC™ in depth; examples
include creating standard and custom Bluetooth® LE profiles. Application notes often include example projects
in addition to the application note document.
Technical reference manual (TRM): The TRM contains all the technical detail you need to use a PSoC™ device,
including a complete description of all PSoC™ registers. The TRM is available in the Documentation section at
PSoC™ 4 MCU.
4.2
Online
In addition to print documentation, the PSoC™ forums connect you with fellow PSoC™ users and experts in
PSoC™ from around the world, 24 hours a day, 7 days a week.
4.3
Tools
With industry standard cores, programming, and debugging interfaces, the PSoC™ 4 CY8C42xx-BL MCU with
AIROC™ Bluetooth® LE family is part of a development tool ecosystem. See the PSoC™ Creator for the latest
information on the revolutionary, easy to use PSoC™ Creator IDE, supported third party compilers, programmers,
debuggers, and development kits.
Datasheet
28
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5
Electrical specifications
5.1
Absolute maximum ratings
Table 7
Absolute maximum ratings[1]
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID1
VDDD_ABS
Analog, digital, or radio supply
relative to VSS (VSSD = VSSA)
–0.5
–
6
V
Absolute max
SID2
VCCD_ABS
Direct digital core voltage
input relative to VSSD
–0.5
–
1.95
V
Absolute max
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD
+0.5
V
Absolute max
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
mA
Absolute max
SID5
IGPIO_injection
GPIO injection current, Max for
VIH > VDDD, and Min for VIL < VSS
–0.5
–
0.5
mA
Absolute max,
current injected
per pin
BID57
ESD_HBM
Electrostatic discharge human
body model
2200
–
–
V
–
BID58
ESD_CDM
Electrostatic discharge
charged device model
500
–
–
V
–
BID61
LU
Pin current for latch-up
–200
–
200
mA
–
Note
1. Usage above the absolute maximum conditions listed in Table 7 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability.
The maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Datasheet
29
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.2
Device-level specifications
All specifications are valid for –40°C TA 85°C and TJ 100°C, except where noted. Specifications are valid for
1.71 V to 5.5 V, except where noted.
Table 8
DC specifications
Spec ID#
Parameter
SID6
Details/
conditions
Description
Min
Typ
Max
Unit
VDD
Power supply input voltage (VDDA
= VDDD = VDD)
1.8
–
5.5
V
With regulator
enabled
SID7
VDD
Power supply input voltage
unregulated (VDDA = VDDD = VDD)
1.71
1.8
1.89
V
Internally
unregulated
Supply
SID8
VDDR
Radio supply voltage (Radio ON)
1.9
–
5.5
V
–
SID8A
VDDR
Radio supply voltage (Radio OFF)
1.71
–
5.5
V
–
SID9
VCCD
Digital regulator output voltage
(for core logic)
–
1.8
–
V
–
SID10
CVCCD
Digital regulator output bypass
capacitor
1
1.3
1.6
µF
X5R ceramic or
better
Active mode, VDD = 1.71 V to 5.5 V
SID13
IDD3
Execute from flash; CPU at 3 MHz
–
2.1
–
mA
T = 25°C,
VDD = 3.3 V
SID14
IDD4
Execute from flash; CPU at 3 MHz
–
–
–
mA
T = –40°C to 85°C
SID15
IDD5
Execute from flash; CPU at 6 MHz
–
2.5
–
mA
T = 25°C,
VDD = 3.3 V
SID16
IDD6
Execute from flash; CPU at 6 MHz
–
–
–
mA
T = –40°C to 85°C
SID17
IDD7
Execute from flash; CPU at 12 MHz
–
4
–
mA
T = 25°C,
VDD = 3.3 V
SID18
IDD8
Execute from flash; CPU at 12 MHz
–
–
–
mA
T = –40°C to 85°C
SID19
IDD9
Execute from flash; CPU at 24 MHz
–
7.1
–
mA
T = 25°C,
VDD = 3.3 V
SID20
IDD10
Execute from flash; CPU at 24 MHz
–
–
–
mA
T = –40°C to 85°C
SID21
IDD11
Execute from flash; CPU at 48 MHz
–
13.4
–
mA
T = 25°C,
VDD = 3.3 V
SID22
IDD12
Execute from flash; CPU at 48 MHz
–
–
–
mA
T = –40°C to 85°C
–
–
–
mA
T = 25°C,
VDD = 3.3 V,
SYSCLK = 3 MHz
–
–
–
mA
T = 25°C,
VDD = 3.3 V,
SYSCLK = 3 MHz
Sleep mode, VDD = 1.8 to 5.5 V
SID23
IDD13
IMO on
Sleep mode, VDD and VDDR = 1.9 to 5.5 V
SID24
IDD14
ECO on
Deep Sleep mode, VDD = 1.8 to 3.6 V
SID25
IDD15
WDT with WCO on
–
1.5
–
µA
T = 25°C,
VDD = 3.3 V
SID26
IDD16
WDT with WCO on
–
–
–
µA
T = –40°C to 85°C
Datasheet
30
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 8
Spec ID#
DC specifications (continued)
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
Deep Sleep mode, VDD = 3.6 to 5.5 V
SID27
IDD17
WDT with WCO on
–
–
–
µA
T = 25°C,
VDD = 5 V
SID28
IDD18
WDT with WCO on
–
–
–
µA
T = –40°C to 85°C
Deep Sleep mode, VDD = 1.71 to 1.89 V (Regulator bypassed)
SID29
IDD19
WDT with WCO on
–
–
–
µA
T = 25°C
SID30
IDD20
WDT with WCO on
–
–
–
µA
T = –40°C to 85°C
Deep Sleep mode, VDD = 1.8 to 3.6 V
SID31
IDD21
Opamp on
–
–
–
µA
T = 25°C,
VDD = 3.3 V
SID32
IDD22
Opamp on
–
–
–
µA
T = –40°C to 85°C
Deep Sleep mode, VDD = 3.6 to 5.5 V
SID33
IDD23
Opamp on
–
–
–
µA
T = 25°C,
VDD = 5 V
SID34
IDD24
Opamp on
–
–
–
µA
T = –40°C to 85°C
Deep Sleep mode, VDD = 1.71 to 1.89 V (Regulator bypassed)
SID35
IDD25
Opamp on
–
–
–
µA
T = 25°C
SID36
IDD26
Opamp on
–
–
–
µA
T = –40°C to 85°C
Hibernate mode, VDD = 1.8 to 3.6 V
SID37
IDD27
GPIO and reset active
–
150
–
nA
T = 25°C,
VDD = 3.3V
SID38
IDD28
GPIO and reset active
–
–
–
nA
T = –40°C to 85°C
Hibernate mode, VDD = 3.6 to 5.5 V
SID39
IDD29
GPIO and reset active
–
–
–
nA
T = 25°C,
VDD = 5 V
SID40
IDD30
GPIO and reset active
–
–
–
nA
T = –40°C to 85°C
Hibernate mode, VDD = 1.71 to 1.89 V (Regulator bypassed)
SID41
IDD31
GPIO and reset active
–
–
–
nA
T = 25°C
SID42
IDD32
GPIO and reset active
–
–
–
nA
T = –40°C to 85°C
Stop mode, VDD = 1.8 to 3.6 V
SID43
IDD33
Stop mode current (VDD)
–
20
–
nA
T = 25°C,
VDD = 3.3 V
SID44
IDD34
Stop mode current (VDDR)
–
40
–-
nA
T = 25°C,
VDDR = 3.3 V
SID45
IDD35
Stop mode current (VDD)
–
–
–
nA
T = –40°C to 85°C
nA
T = –40°C to
85°C,
VDDR = 1.9 V to
3.6 V
SID46
Datasheet
IDD36
Stop mode current (VDDR)
–
31
–
–
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 8
Spec ID#
DC specifications (continued)
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
Stop mode, VDD = 3.6 to 5.5 V
SID47
IDD37
Stop mode current (VDD)
–
–
–
nA
T = 25°C,
VDD = 5 V
SID48
IDD38
Stop mode current (VDDR)
–
–
–
nA
T = 25°C,
VDDR = 5 V
SID49
IDD39
Stop mode current (VDD)
–
–
–
nA
T = –40°C to 85°C
SID50
IDD40
Stop mode current (VDDR)
–
–
–
nA
T = –40°C to 85°C
Stop mode, VDD = 1.71 to 1.89 V (Regulator bypassed)
SID51
IDD41
Stop mode current (VDD)
–
–
–
nA
T = 25°C
SID52
IDD42
Stop mode current (VDD)
–
–
–
nA
T = –40°C to 85°C
Table 9
Spec ID#
AC specifications
Parameter
Description
Min
Typ
Max
Unit
DC
–
48
MHz
Details/
conditions
1.71 V VDD 5.5 V
SID53
FCPU
CPU frequency
SID54
TSLEEP
Wakeup from Sleep mode
–
0
–
µs
Guaranteed by
characterization
SID55
TDEEPSLEEP
Wakeup from Deep Sleep
mode
–
–
25
µs
24-MHz IMO.
Guaranteed by
characterization.
SID56
THIBERNATE
Wakeup from Hibernate
mode
–
–
0.7
ms
Guaranteed by
characterization
SID57
TSTOP
Wakeup from Stop mode
–
–
2.2
ms
Guaranteed by
characterization
Datasheet
32
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.2.1
GPIO
Table 10
GPIO DC specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID58
VIH
Input voltage HIGH threshold
0.7 × VDD
–
–
V
CMOS input
SID59
VIL
Input voltage LOW threshold
–
–
0.3
× VDD
V
CMOS input
SID60
VIH
LVTTL input, VDD < 2.7 V
0.7 × VDD
–
-
V
–
SID61
VIL
LVTTL input, VDD < 2.7 V
–
–
0.3× VDD
V
–
SID62
VIH
LVTTL input, VDD >= 2.7 V
2.0
–
-
V
–
SID63
VIL
LVTTL input, VDD >= 2.7 V
–
–
0.8
V
–
SID64
VOH
Output voltage HIGH level
VDD –0.6
–
–
V
Ioh = 4-mA at
3.3-V VDD
SID65
VOH
Output voltage HIGH level
VDD –0.5
–
–
V
Ioh = 1-mA at
1.8-V VDD
SID66
VOL
Output voltage LOW level
–
–
0.6
V
Iol = 8-mA at
3.3-V VDD
SID67
VOL
Output voltage LOW level
–
–
0.6
V
Iol = 4-mA at
1.8-V VDD
SID68
VOL
Output voltage LOW level
–
–
0.4
V
Iol = 3-mA at
3.3-V VDD
SID69
Rpullup
Pull-up resistor
3.5
5.6
8.5
kΩ
–
SID70
Rpulldown
Pull-down resistor
3.5
5.6
8.5
kΩ
–
SID71
IIL
Input leakage current (absolute
value)
–
–
2
nA
SID72
IIL_CTBM
Input leakage on CTBm input
pins
–
–
4
nA
–
SID73
CIN
Input capacitance
–
–
7
pF
–
SID74
Vhysttl
Input hysteresis LVTTL
25
40
SID75
Vhyscmos
Input hysteresis CMOS
0.05 × VDD
–
–
mV
–
SID76
Idiode
Current through protection
diode to VDD/VSS
–
–
100
µA
–
SID77
ITOT_GPIO
Maximum total source or sink
chip current
–
–
200
mA
–
mV
25°C,
VDD = 3.3 V
VDD > 2.7 V
Note
2. VIH must not exceed VDDD + 0.2 V.
Datasheet
33
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 11
Spec ID#
GPIO AC specifications
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID78
TRISEF
Rise time in Fast-Strong
mode
2
–
12
ns
3.3-V VDDD,
CLOAD = 25-pF
SID79
TFALLF
Fall time in Fast-Strong
mode
2
–
12
ns
3.3-V VDDD,
CLOAD = 25-pF
SID80
TRISES
Rise time in Slow-Strong
mode
10
–
60
–
3.3-V VDDD,
CLOAD = 25-pF
SID81
TFALLS
Fall time in Slow-Strong
mode
10
–
60
–
3.3-V VDDD,
CLOAD = 25-pF
SID82
FGPIOUT1
GPIO Fout; 3.3 V VDD
5.5 V. Fast-Strong mode
–
–
33
MHz
90/10%, 25-pF load,
60/40 duty cycle
SID83
FGPIOUT2
GPIO Fout; 1.7 VVDD 3.3 V.
Fast-Strong mode
–
–
16.7
MHz
90/10%, 25-pF load,
60/40 duty cycle
SID84
FGPIOUT3
GPIO Fout; 3.3 V VDD
5.5 V. Slow-Strong mode
–
–
7
MHz
90/10%, 25-pF load,
60/40 duty cycle
SID85
FGPIOUT4
GPIO Fout; 1.7 V VDD
3.3 V. Slow-Strong mode
–
–
3.5
MHz
90/10%, 25-pF load,
60/40 duty cycle
SID86
FGPIOIN
GPIO input operating
frequency;
1.71 V VDD 5.5 V
–
–
48
MHz 90/10% VIO
Table 12
Spec ID#
OVT GPIO DC specifications (P5_0 and P5_1 Only)
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID71A
IIL
Input leakage current (absolute
value), VIH > VDD
–
–
10
µA
25°C,
VDD = 0 V, VIH= 3.0 V
SID66A
VOL
Output voltage LOW level
–
–
0.4
V
IOL = 20-mA, VDD >
2.9-V
Table 13
Spec ID#
OVT GPIO AC specifications (P5_0 and P5_1 only)
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID78A
TRISE_OVFS
Output rise time in Fast-Strong
mode
1.5
–
12
ns
25-pF load, 10%–
90%, VDD=3.3-V
SID79A
TFALL_OVFS
Output fall time in Fast-Strong
mode
1.5
–
12
ns
25-pF load, 10%–
90%, VDD=3.3-V
SID80A
TRISSS
Output rise time in Slow-Strong
mode
10
–
60
ns
25-pF load, 10%–
90%, VDD=3.3-V
SID81A
TFALLSS
Output fall time in Slow-Strong
mode
10
–
60
ns
25-pF load, 10%–
90%, VDD=3.3-V
Datasheet
34
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 13
Spec ID#
OVT GPIO AC specifications (P5_0 and P5_1 only) (continued)
Parameter
Description
Min
Typ
Max
Details/
conditions
Unit
SID82A
FGPIOUT1
GPIO FOUT; 3.3 V ≤ VDD ≤ 5.5 V
Fast-Strong mode
–
–
24
90/10%, 25-pF
MHz load, 60/40 duty
cycle
SID83A
FGPIOUT2
GPIO FOUT; 1.71 V ≤ VDD ≤ 3.3 V
Fast-Strong mode
–
–
16
90/10%, 25-pF
MHz load, 60/40 duty
cycle
5.2.2
XRES
Table 14
XRES DC specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID87
VIH
Input voltage HIGH threshold
0.7 ×
VDDD
–
–
V
CMOS input
SID88
VIL
Input voltage LOW threshold
–
–
0.3 × VDDD
V
CMOS input
SID89
Rpullup
Pull-up resistor
3.5
5.6
8.5
kΩ
–
SID90
CIN
Input capacitance
–
3
–
pF
–
SID91
VHYSXRES
Input voltage hysteresis
–
100
–
mV
–
SID92
IDIODE
Current through protection
diode to VDDD/VSS
–
–
100
µA
–
Table 15
Spec ID#
SID93
Datasheet
XRES AC specifications
Parameter
Description
TRESETWIDTH Reset pulse width
35
Min
Typ
Max
Unit
Details/conditions
1
–
–
µs
–
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.3
Analog peripherals
5.3.1
Opamp
Table 16
Opamp specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
IDD (Opamp block current. VDD = 1.8 V. No load)
SID94
IDD_HI
Power = high
–
1000
1850
µA
–
SID95
IDD_MED
Power = medium
–
500
950
µA
–
SID96
IDD_LOW
Power = low
–
250
350
µA
–
GBW (Load = 20 pF, 0.1 mA. VDDA = 2.7 V)
SID97
GBW_HI
Power = high
6
–
–
MHz
–
SID98
GBW_MED
Power = medium
4
–
–
MHz
–
SID99
GBW_LO
Power = low
–
1
–
MHz
–
10
–
–
mA
–
IOUT_MAX (VDDA 2.7 V, 500 mV from rail)
SID100
IOUT_MAX_HI
SID101
IOUT_MAX_MID Power = medium
10
–
–
mA
–
SID102
IOUT_MAX_LO
–
5
–
mA
–
4
–
–
mA
–
Power = high
Power = low
IOUT (VDDA = 1.71 V, 500 mV from rail)
SID103
IOUT_MAX_HI
SID104
IOUT_MAX_MID Power = medium
4
–
–
mA
–
SID105
IOUT_MAX_LO
Power = low
–
2
–
mA
–
SID106
VIN
Charge pump on, VDDA 2.7 V
–0.05
–
VDDA – 0.2
V
–
SID107
VCM
Charge pump on, VDDA 2.7 V
–0.05
–
VDDA – 0.2
V
–
Power = high
VOUT (VDDA 2.7 V)
SID108
VOUT_1
Power = high, ILOAD=10 mA
0.5
–
VDDA – 0.5
V
–
SID109
VOUT_2
Power = high, ILOAD=1 mA
0.2
–
VDDA – 0.2
V
–
SID110
VOUT_3
Power = medium, ILOAD=1 mA
0.2
–
VDDA – 0.2
V
–
SID111
VOUT_4
Power = low, ILOAD=0.1 mA
0.2
–
VDDA – 0.2
V
–
SID112
VOS_TR
Offset voltage, trimmed
1
±0.5
1
mV
High mode
SID113
VOS_TR
Offset voltage, trimmed
–
±1
–
mV
Medium
mode
SID114
VOS_TR
Offset voltage, trimmed
–
±2
–
mV
Low mode
SID115
VOS_DR_TR
Offset voltage drift, trimmed
–10
±3
10
µV/C
High mode
SID116
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
µV/C
Medium
mode
SID117
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
µV/C
Low mode
SID118
CMRR
DC
70
80
–
dB
VDDD = 3.6-V
SID119
PSRR
At 1 kHz, 100-mV ripple
70
85
–
dB
VDDD = 3.6-V
Datasheet
36
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 16
Spec ID#
Opamp specifications (continued)
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
Noise
SID120
VN1
Input referred, 1 Hz–1 GHz,
power = high
–
94
–
µVrms
–
SID121
VN2
Input referred, 1-kHz, power =
high
–
72
–
nV/rtHz
–
SID122
VN3
Input referred, 10-kHz, power =
high
–
28
–
nV/rtHz
–
SID123
VN4
Input referred, 100-kHz, power =
high
–
15
–
nV/rtHz
–
SID124
CLOAD
Stable up to maximum load.
Performance specs at 50 pF
–
–
125
pF
–
SID125
Slew_rate
Cload = 50 pF, Power = High,
VDDA 2.7 V
6
–
–
V/µsec
–
SID126
T_op_wake
From disable to enable, no
external RC dominating
–
300
–
µsec
–
Comp_mode (Comparator mode; 50-mV drive, TRISE = TFALL (approx.)
SID127
TPD1
Response time; power = high
–
150
–
nsec
–
SID128
TPD2
Response time; power = medium
–
400
–
nsec
–
SID129
TPD3
Response time; power = low
–
2000
–
nsec
–
SID130
Vhyst_op
Hysteresis
–
10
–
mV
–
Deep Sleep (Deep Sleep mode operation is only guaranteed for VDDA > 2.5 V)
SID131
GBW_DS
Gain bandwidth product
–
50
–
kHz
–
SID132
IDD_DS
Current
–
15
–
µA
–
SID133
Vos_DS
Offset voltage
–
5
–
mV
–
SID134
Vos_dr_DS
Offset voltage drift
–
20
–
µV/°C
–
SID135
Vout_DS
Output voltage
0.2
–
VDD–0.2
V
–
SID136
Vcm_DS
Common mode voltage
0.2
–
VDD–1.8
V
–
Min
Typ
Max
Unit
Details/
conditions
Table 17
Comparator DC specifications[3]
Spec ID# Parameter
Description
SID140
VOFFSET1
Input offset voltage, Factory trim
–
–
±10
mV
–
SID141
VOFFSET2
Input offset voltage, Custom trim
–
–
±6
mV
–
SID141A VOFFSET3
Input offset voltage,
ultra-low-power mode
–
±12
–
mV
SID142
Hysteresis when enabled. Common
Mode voltage range from 0 to VDD –1
–
10
35
mV
VHYST
VDDD ≥ 2.6 V for
Temp < 0°C,
VDDD ≥ 1.8 V for
Temp > 0°C
–
Note
3. ULP LCOMP operating conditions:
- VDDD 2.6 V-5.5 V for datasheet temp range < 0°C
- VDDD 1.8 V-5.5 V for datasheet temp range ≥ 0°C
Datasheet
37
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 17
Comparator DC specifications[3] (continued)
Spec ID# Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID143
VICM1
Input common mode voltage in
normal mode
0
–
VDDD –
0.1
V
SID144
VICM2
Input common mode voltage in low
power mode
0
–
VDDD
V
SID145
VICM3
Input common mode voltage in ultra
low power mode
0
–
VDDD –
1.15
V
SID146
CMRR
Common mode rejection ratio
50
–
–
dB
VDDD ≥ 2.7 V
SID147
CMRR
Common mode rejection ratio
42
–
–
dB
VDDD ≤ 2.7 V
SID148
ICMP1
Block current, normal mode
–
–
400
µA
–
SID149
ICMP2
Block current, low power mode
–
–
100
µA
–
SID150
ICMP3
Block current in ultra low-power
mode
–
6
–
µA
SID151
ZCMP
DC input impedance of comparator
35
–
–
MΩ
Min
Typ
Max
Unit
Modes 1 and 2
–
VDDD ≥ 2.6 V for
Temp < 0°C,
VDDD ≥ 1.8 V for
Temp > 0°C
VDDD ≥ 2.6 V for
Temp < 0°C,
VDDD ≥ 1.8 V for
Temp > 0°C
–
Note
3. ULP LCOMP operating conditions:
- VDDD 2.6 V-5.5 V for datasheet temp range < 0°C
- VDDD 1.8 V-5.5 V for datasheet temp range ≥ 0°C
Table 18
Spec ID#
Comparator AC specifications[3]
Parameter
Description
Details/
conditions
SID152
TRESP1
Response time, normal mode,
50-mV overdrive
–
38
–
ns
50-mV
overdrive
SID153
TRESP2
Response time, low power mode,
50-mV overdrive
–
70
–
ns
50-mV
overdrive
SID154
TRESP3
Response time, ultra-low-power
mode, 50-mV overdrive
5.3.2
Temperature sensor
Table 19
Temperature sensor specifications
Spec ID#
SID155
Datasheet
Parameter
TSENSACC
Description
Temperature sensor accuracy
38
–
2.3
–
µs
200-mV
overdrive. VDDD
≥ 2.6 V for
Temp < 0°C,
VDDD ≥ 1.8 V for
Temp > 0°C
Min
Typ
Max
Unit
Details/
conditions
–5
±1
5
°C
–40 to +85°C
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.3.3
SAR ADC
Table 20
SAR ADC DC specifications
Spec ID# Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
–
SID156
A_RES
Resolution
–
–
12
bits
SID157
A_CHNIS_S
Number of channels single-ended
–
–
16
–
8 full-speed
SID158
A-CHNKS_D Number of channels - differential
–
–
8
–
Diff inputs use
neighboring I/O
SID159
A-MONO
–
–
–
–
Yes
SID160
A_GAINERR Gain error
–
–
±0.1
%
With external
reference.
SID161
A_OFFSET
Input offset voltage
–
–
2
mV
Measured with 1-V
VREF
SID162
A_ISAR
Current consumption
–
–
1
mA
–
SID163
A_VINS
Input voltage range single-ended
VSS
–
VDDA
V
–
SID164
A_VIND
Input voltage range - differential
VSS
–
VDDA
V
–
SID165
A_INRES
Input resistance
–
–
2.2
kΩ
–
SID166
A_INCAP
Input capacitance
–
–
10
pF
–
SID312
VREFSAR
Trimmed internal reference to
SAR
–1
–
1
%
Percentage of Vbg
(1.024-V)
Min
Typ
Max
Unit
Details/
conditions
Table 21
Monotonicity
SAR ADC AC specifications
Spec ID# Parameter
Description
SID167
A_psrr
Power supply rejection ratio
70
–
–
dB
Measured at 1-V
reference
SID168
A_cmrr
Common mode rejection ratio
66
–
–
dB
–
SID169
A_samp
Sample rate
–
–
1
Msps
SID313
Fsarintref
SAR operating speed without
external ref. bypass
–
–
100
SID170
A_snr
Signal-to-noise ratio (SNR)
65
–
–
dB
SID171
A_bw
Input bandwidth without aliasing
–
–
A_samp/
2
kHz
–
SID172
A_inl
Integral non linearity. VDD = 1.71 to
5.5 V, 1 Msps
–1.7
–
2
LSB
Vref = 1 V to VDD
SID173
A_INL
Integral non linearity. VDDD = 1.71
to 3.6 V, 1 Msps
–1.5
–
1.7
LSB
Vref = 1.71 V to
VDD
SID174
A_INL
Integral non linearity. VDD = 1.71 to
5.5 V, 500 Ksps
–1.5
–
1.7
LSB
Vref = 1 V to VDD
SID175
A_dnl
Differential non linearity. VDD =
1.71 to 5.5 V, 1 Msps
–1
–
2.2
LSB
Vref = 1 V to VDD
SID176
A_DNL
Differential non linearity. VDD =
1.71 to 3.6 V, 1 Msps
–1
–
2
LSB
Vref = 1.71 V to
VDD
Datasheet
39
Ksps 12-bit resolution
Fin = 10 kHz
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 21
SAR ADC AC specifications (continued)
Spec ID# Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID177
A_DNL
Differential non linearity. VDD =
1.71 to 5.5 V, 500 Ksps
–1
–
2.2
LSB
Vref = 1 V to VDD
SID178
A_thd
Total harmonic distortion
–
–
–65
dB
Fin = 10 kHz
5.3.4
CSD
Table 22
CSD block specifications
Spec ID# Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
1.71
–
5.5
V
–
SID179
VCSD
Voltage range of operation
SID180
IDAC1
DNL for 8-bit resolution
–1
–
1
LSB
–
SID181
IDAC1
INL for 8-bit resolution
–3
–
3
LSB
–
SID182
IDAC2
DNL for 7-bit resolution
–1
–
1
LSB
–
SID183
IDAC2
INL for 7-bit resolution
–3
–
3
LSB
–
SID184
SNR
Ratio of counts of finger to
noise
5
–
–
Ratio Capacitance range
of 9 to 35 pF, 0.1 pF
sensitivity. Radio is
not operating
during the scan
SID185
IDAC1_CRT1
Output current of IDAC1 (8 bits)
in High range
–
612
–
µA
SID186
IDAC1_CRT2
Output current of IDAC1 (8 bits)
in Low range
–
306
–
µA
SID187
IDAC2_CRT1
Output current of IDAC2 (7 bits)
in High range
–
305
–
µA
SID188
IDAC2_CRT2
Output current of IDAC2 (7 bits)
in Low range
–
153
–
µA
Datasheet
40
–
–
–
–
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.4
5.4.1
Digital peripherals
Timer
Table 23
Timer DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID189
ITIM1
Block current consumption at
3 MHz
–
–
50
µA
16-bit timer
SID190
ITIM2
Block current consumption at
12 MHz
–
–
175
µA
16-bit timer
SID191
ITIM3
Block current consumption at
48 MHz
–
–
712
µA
16-bit timer
Min
Typ
Max
Unit
Details/
conditions
Table 24
Spec ID
Timer AC specifications
Parameter
Description
SID192
TTIMFREQ
Operating frequency
FCLK
–
48
MHz
–
SID193
TCAPWINT
Capture pulse width (internal)
2×
TCLK
–
–
ns
–
SID194
TCAPWEXT
Capture pulse width (external)
2×
TCLK
–
–
ns
–
SID195
TTIMRES
Timer resolution
TCLK
–
–
ns
–
SID196
TTENWIDINT
Enable pulse width (internal)
2×
TCLK
–
–
ns
–
SID197
TTENWIDEXT
Enable pulse width (external)
2×
TCLK
–
–
ns
–
SID198
TTIMRESWINT
Reset pulse width (internal)
2×
TCLK
–
–
ns
–
SID199
TTIMRESEXT
Reset pulse width (external)
2×
TCLK
–
–
ns
–
Datasheet
41
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.4.2
Counter
Table 25
Counter DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/conditions
SID200
ICTR1
Block current consumption at
3 MHz
–
–
50
µA
16-bit counter
SID201
ICTR2
Block current consumption at
12 MHz
–
–
175
µA
16-bit counter
SID202
ICTR3
Block current consumption at
48 MHz
–
–
712
µA
16-bit counter
Min
Typ
Max
Unit
Details/conditions
FCLK
–
48
MHz
–
Table 26
Counter AC specifications
Spec ID Parameter
Description
SID203
TCTRFREQ
Operating frequency
SID204
TCTRPWINT
Capture pulse width (internal)
2 × TCLK
–
–
ns
–
SID205
TCTRPWEXT
Capture pulse width (external)
2 × TCLK
–
–
ns
–
SID206
TCTRES
Counter Resolution
TCLK
–
–
ns
–
SID207
TCENWIDINT Enable pulse width (internal)
2 × TCLK
–
–
ns
–
SID208
TCENWIDEXT Enable pulse width (external)
2 × TCLK
–
–
ns
–
SID209
TCTRRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
–
SID210
TCTRRESWEXT
Reset pulse width (external)
2 × TCLK
–
–
ns
–
Datasheet
42
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.4.3
Pulse width modulation (PWM)
Table 27
PWM DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID211
IPWM1
Block current consumption at
3 MHz
–
–
50
µA
16-bit PWM
SID212
IPWM2
Block current consumption at
12 MHz
–
–
175
µA
16-bit PWM
SID213
IPWM3
Block current consumption at
48 MHz
–
–
741
µA
16-bit PWM
Min
Typ
Max
Unit
Details/
conditions
Table 28
Spec ID
PWM AC specifications
Parameter
Description
SID214
TPWMFREQ
Operating frequency
FCLK
–
48
MHz
–
SID215
TPWMPWINT
Pulse width (internal)
2 × TCLK
–
–
ns
–
SID216
TPWMEXT
Pulse width (external)
2 × TCLK
–
–
ns
–
SID217
TPWMKILLINT
Kill pulse width (internal)
2 × TCLK
–
–
ns
–
SID218
TPWMKILLEXT
Kill pulse width (external)
2 × TCLK
–
–
ns
–
SID219
TPWMEINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
–
SID220
TPWMENEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
–
SID221
TPWMRESWINT Reset pulse width (internal)
2 × TCLK
–
–
ns
–
SID222
TPWMRESWEXT Reset pulse width (external)
2 × TCLK
–
–
ns
–
Min
Typ
Max
Unit
Details/
conditions
5.4.4
I2C
Table 29
Fixed I2C DC specifications
Spec ID
Parameter
Description
SID223
II2C1
Block current consumption at
100 kHz
–
–
50
µA
–
SID224
II2C2
Block current consumption at
400 kHz
–
–
155
µA
–
SID225
II2C3
Block current consumption at
1 Mbps
–
–
390
µA
–
SID226
II2C4
I2C enabled in Deep Sleep mode
–
–
1.4
µA
–
Min
Typ
Max
Unit
Details/
conditions
–
–
1
Mbps
–
Table 30
Spec ID
SID227
Datasheet
Fixed I2C AC specifications
Parameter
FI2C1
Description
Bit rate
43
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.4.5
LCD direct drive
Table 31
LCD direct drive DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID228
ILCDLOW
Operating current in low-power
mode
–
17.5
–
µA
16 × 4 small
segment display at
50 Hz
SID229
CLCDCAP
LCD capacitance per
segment/common driver
–
500
5000
pF
–
SID230
LCDOFFSET
Long-term segment offset
–
20
–
mV
–
SID231
ILCDOP1
LCD system operating current
VBIAS = 5 V.
–
2
–
mA
32 × 4 segments.
50 Hz at 25°C
SID232
ILCDOP2
LCD system operating current.
VBIAS = 3.3 V
–
2
–
mA
32 × 4 segments
50 Hz at 25°C
Min
Typ
Max
Unit
Details/
conditions
10
50
150
Hz
–
Min
Typ
Max
Unit
Details/
conditions
Table 32
Spec ID
SID233
Table 33
Spec ID
LCD direct drive AC specifications
Parameter
FLCD
Description
LCD frame rate
Fixed UART DC specifications
Parameter
Description
SID234
IUART1
Block current consumption at
100 kbps
–
–
55
µA
–
SID235
IUART2
Block current consumption at
1000 kbps
–
–
360
µA
–
Min
Typ
Max
Unit
Details/
conditions
–
–
1
Mbps
–
Table 34
Spec ID
SID236
Datasheet
Fixed UART AC specifications
Parameter
FUART
Description
Bit rate
44
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.4.6
SPI specifications
Table 35
Fixed SPI DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID237
ISPI1
Block current consumption at
1 Mbps
–
–
360
µA
–
SID238
ISPI2
Block current consumption at
4 Mbps
–
–
560
µA
–
SID239
ISPI3
Block current consumption at
8 Mbps
–
–
600
µA
–
Description
Min
Typ
Max
Unit
Details/
conditions
SPI operating frequency (master; 6X
oversampling)
–
–
8
MHz
–
Description
Min
Typ
Max
Unit
Details/
conditions
–
Table 36
Spec ID
SID240
Table 37
Spec ID
Fixed SPI AC specifications
Parameter
FSPI
Fixed SPI Master mode AC specifications
Parameter
SID241
TDMO
MOSI valid after Sclock driving edge
–
–
18
ns
SID242
TDSI
MISO valid before Sclock capturing
edge. Full clock, late MISO sampling
used
20
–
–
ns
Full clock, late
MISO sampling
SID243
THMO
Previous MOSI data hold time
0
–
–
ns
Referred to Slave
capturing edge
Description
Min
Typ
Max
Unit
Details/
conditions
Table 38
Spec ID
Fixed SPI Slave mode AC specifications
Parameter
SID244
TDMI
MOSI valid before Sclock capturing
edge
40
–
–
ns
–
SID245
TDSO
MISO valid after Sclock driving edge
–
–
42 + 3 ×
TCPU
ns
–
SID246
TDSO_ext
MISO valid after Sclock driving edge
in external clock mode
–
–
53
ns
SID247
THSO
Previous MISO data hold time
0
–
–
ns
–
SID248
TSSELSCK
SSEL valid to first SCK valid edge
100
–
–
ns
–
Datasheet
45
VDD < 3.0 V
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.5
Memory
Table 39
Flash DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
1.71
–
5.5
V
–
SID249
VPE
Erase and program voltage
SID309
TWS48
Number of Wait states at
32–48 MHz
2
–
–
CPU execution
from flash
SID310
TWS32
Number of Wait states at
16–32 MHz
1
–
–
CPU execution
from flash
SID311
TWS16
Number of Wait states for
0–16 MHz
0
–
–
CPU execution
from flash
Min
Typ
Max
Table 40
Spec ID
Flash AC specifications
Parameter
Description
Unit
Details/
conditions
SID250
TROWWRITE[4]
Row (block) write time
(erase and program)
–
–
20
ms
Row (block) = 128
bytes for 128 KB
flash devices
Row (block) = 256
bytes for 256 KB
flash devices
SID251
TROWERASE[4]
Row erase time
–
–
13
ms
–
SID252
TROWPROGRAM[4]
Row program time after
erase
–
–
7
ms
–
SID253
TBULKERASE[4]
Bulk erase time (256 KB)
–
–
35
ms
–
TDEVPROG[4]
Total device program time
–
–
50
–
–
25
SID255
FEND
Flash endurance
100 K
–
–
cycles
–
SID256
FRET
Flash retention. TA 55°C,
100 K P/E cycles
20
–
–
years
–
SID257
FRET2
Flash retention. TA 85°C,
10 K P/E cycles
10
–
–
years
–
SID254
SID254A
seconds
256 KB
128 KB
Note
4. It can take as much as 20 milliseconds to write to flash. During this time, the device should not be reset, or
flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the
XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and
watchdogs. Make certain that these are not inadvertently activated.
Datasheet
46
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.6
System resources
5.6.1
Power-on reset (POR)
Table 41
POR DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/conditions
SID258
VRISEIPOR
Rising trip voltage
0.80
–
1.45
V
–
SID259
VFALLIPOR
Falling trip voltage
0.75
–
1.40
V
–
SID260
VIPORHYST
Hysteresis
15
–
200
mV
–
Min
Typ
Max
Unit
Details/conditions
–
–
1
µs
–
Min
Typ
Max
Unit
Details/conditions
Table 42
Spec ID
SID264
Table 43
Spec ID#
POR AC specifications
Parameter
TPPOR_TR
Description
PPOR response time in
Active and Sleep modes
Brown-out detect
Parameter
Description
SID261
VFALLPPOR
BOD trip voltage in Active
and Sleep modes
1.64
–
–
V
–
SID262
VFALLDPSLP
BOD trip voltage in Deep
Sleep mode
1.4
–
–
V
–
Min
Typ
Max
Unit
Details/conditions
1.1
–
–
V
–
Table 44
Spec ID#
SID263
Datasheet
Hibernate reset
Parameter
VHBRTRIP
Description
BOD trip voltage in
Hibernate mode
47
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.6.2
Voltage monitors
Table 45
Voltage monitor DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID265
VLVI1
LVI_A/D_SEL[3:0] = 0000b
1.71
1.75
1.79
V
–
SID266
VLVI2
LVI_A/D_SEL[3:0] = 0001b
1.76
1.80
1.85
V
–
SID267
VLVI3
LVI_A/D_SEL[3:0] = 0010b
1.85
1.90
1.95
V
–
SID268
VLVI4
LVI_A/D_SEL[3:0] = 0011b
1.95
2.00
2.05
V
–
SID269
VLVI5
LVI_A/D_SEL[3:0] = 0100b
2.05
2.10
2.15
V
–
SID270
VLVI6
LVI_A/D_SEL[3:0] = 0101b
2.15
2.20
2.26
V
–
SID271
VLVI7
LVI_A/D_SEL[3:0] = 0110b
2.24
2.30
2.36
V
–
SID272
VLVI8
LVI_A/D_SEL[3:0] = 0111b
2.34
2.40
2.46
V
–
SID273
VLVI9
LVI_A/D_SEL[3:0] = 1000b
2.44
2.50
2.56
V
–
SID274
VLVI10
LVI_A/D_SEL[3:0] = 1001b
2.54
2.60
2.67
V
–
SID2705 VLVI11
LVI_A/D_SEL[3:0] = 1010b
2.63
2.70
2.77
V
–
SID276
VLVI12
LVI_A/D_SEL[3:0] = 1011b
2.73
2.80
2.87
V
–
SID277
VLVI13
LVI_A/D_SEL[3:0] = 1100b
2.83
2.90
2.97
V
–
SID278
VLVI14
LVI_A/D_SEL[3:0] = 1101b
2.93
3.00
3.08
V
–
SID279
VLVI15
LVI_A/D_SEL[3:0] = 1110b
3.12
3.20
3.28
V
–
SID280
VLVI16
LVI_A/D_SEL[3:0] = 1111b
4.39
4.50
4.61
V
–
SID281
LVI_IDD
Block current
–
–
100
µA
–
Min
Typ
Max
Unit
Details/
conditions
–
–
1
µs
–
Min
Typ
Max
Unit
Details/
conditions
Table 46
Spec ID
SID282
Voltage monitor AC specifications
Parameter
TMONTRIP
Description
Voltage monitor trip time
5.6.3
SWD interface
Table 47
SWD interface specifications
Spec ID
Parameter
Description
SID283
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
14
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID284
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID285
T_SWDI_SETUP T = 1/f SWDCLK
0.25 × T
–
–
ns
–
SID286
T_SWDI_HOLD
0.25 × T
–
–
ns
–
SID287
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5 × T
ns
–
SID288
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
ns
–
Datasheet
T = 1/f SWDCLK
48
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.6.4
Internal main oscillator
Table 48
IMO DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID289
IIMO1
IMO operating current at
48 MHz
–
–
1000
µA
–
SID290
IIMO2
IMO operating current at
24 MHz
–
–
325
µA
–
SID291
IIMO3
IMO operating current at
12 MHz
–
–
225
µA
–
SID292
IIMO4
IMO operating current at
6 MHz
–
–
180
µA
–
SID293
IIMO5
IMO operating current at
3 MHz
–
–
150
µA
–
Description
Min
Typ
Max
Unit
Details/
conditions
Table 49
Spec ID
IMO AC specifications
Parameter
SID296
FIMOTOL3
Frequency variation from 3 to
48 MHz
–
–
±2
%
With API-called
calibration
SID297
FIMOTOL3
IMO startup time
–
–
12
µs
–
5.6.5
Internal low-speed oscillator
Table 50
ILO DC specifications
Spec ID
SID298
Table 51
Spec ID
Parameter
IILO2
Description
ILO operating current at
32 kHz
Min
Typ
Max
Unit
–
0.3
1.05
µA
Details/
conditions
–
ILO AC specifications
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID299
TSTARTILO1
ILO startup time
–
–
2
ms
–
SID300
FILOTRIM1
32-kHz trimmed frequency
15
32
50
kHz
–
Min
Typ
Max
Unit
Table 52
Spec ID
External clock specifications
Parameter
Description
Details/
conditions
SID301
ExtClkFreq
External clock input
frequency
0
–
48
MHz
CMOS input level
only
SID302
ExtClkDuty
Duty cycle; Measured at VDD/2
45
–
55
%
CMOS input level
only
Datasheet
49
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 53
Spec ID
UDB AC specifications
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
Data path performance
SID303
FMAX-TIMER
Max frequency of 16-bit timer in
a UDB pair
–
–
48
MHz
–
SID304
FMAX-ADDER
Max frequency of 16-bit adder in
a UDB pair
–
–
48
MHz
–
SID305
FMAX_CRC
Max frequency of 16-bit
CRC/PRS in a UDB pair
–
–
48
MHz
–
Max frequency of 2-pass PLD
function in a UDB pair
–
–
48
MHz
–
PLD performance in UDB
SID306
FMAX_PLD
Clock to output performance
SID307
TCLK_OUT_UDB1
Prop. delay for clock in to data
out at 25°C, Typical
–
15
–
ns
–
SID308
TCLK_OUT_UDB2
Prop. delay for clock in to data
out, Worst case
–
25
–
ns
–
Datasheet
50
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 54
Spec ID#
Bluetooth® LE subsystem
Parameter
Min
Typ
Max
Unit
Details/
conditions
RX sensitivity with idle transmitter
–
–89
–
dBm
–
RX sensitivity with idle transmitter excluding Balun loss
–
–91
–
dBm
Guaranteed by
design simulation
Description
RF receiver specification
SID340
RXS, IDLE
SID340A
SID341
RXS, DIRTY
RX sensitivity with dirty transmitter
–
–87
–70
dBm
RF-PHY
Specification
(RCV-LE/CA/01/C)
SID342
RXS,
HIGHGAIN
RX sensitivity in high-gain mode
with idle transmitter
–
–91
–
dBm
–
SID343
PRXMAX
Maximum input power
–10
–1
–
dBm
RF-PHY
Specification
(RCV-LE/CA/06/C)
SID344
CI1
Co-channel interference,
Wanted signal at –67 dBm and
Interferer at FRX
–
9
21
dB
RF-PHY
Specification
(RCV-LE/CA/03/C)
SID345
CI2
Adjacent channel interference
Wanted signal at –67 dBm and
Interferer at FRX ±1 MHz
–
3
15
dB
RF-PHY
Specification
(RCV-LE/CA/03/C)
SID346
CI3
Adjacent channel interference
Wanted signal at –67 dBm and
Interferer at FRX ±2 MHz
–
–29
–
dB
RF-PHY
Specification
(RCV-LE/CA/03/C)
SID347
CI4
Adjacent channel interference
Wanted signal at –67 dBm and
Interferer at ≥FRX ±3 MHz
–
–39
–
dB
RF-PHY
Specification
(RCV-LE/CA/03/C)
CI5
Adjacent channel interference
Wanted Signal at –67 dBm and
Interferer at Image frequency
(FIMAGE)
–
–20
–
dB
RF-PHY
Specification
(RCV-LE/CA/03/C)
SID349
CI6
Adjacent channel interference
Wanted signal at –67 dBm and
Interferer at Image frequency
(FIMAGE ± 1 MHz)
–
–30
–
dB
RF-PHY
Specification
(RCV-LE/CA/03/C)
SID350
OBB1
Out-of-band blocking,
Wanted signal at –67 dBm and
Interferer at F = 30–2000 MHz
–30
–27
–
dBm
RF-PHY
Specification
(RCV-LE/CA/04/C)
SID351
OBB2
Out-of-band blocking,
Wanted signal at –67 dBm and
Interferer at F = 2003–2399 MHz
–35
–27
–
dBm
RF-PHY
Specification
(RCV-LE/CA/04/C)
SID352
OBB3
Out-of-band blocking,
Wanted signal at –67 dBm and
Interferer at F = 2484–2997 MHz
–35
–27
–
dBm
RF-PHY
Specification
(RCV-LE/CA/04/C)
SID353
OBB4
Out-of-band blocking,
Wanted signal a –67 dBm and
Interferer at F = 3000–12750 MHz
–30
–27
–
dBm
RF-PHY
Specification
(RCV-LE/CA/04/C)
SID348
Datasheet
51
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 54
Spec ID#
SID354
SID355
SID356
Bluetooth® LE subsystem (continued)
Parameter
IMD
RXSE1
RXSE2
Description
Intermodulation performance
Wanted signal at –64 dBm and
1-Mbps Bluetooth® LE, third,
fourth, and fifth offset channel
Receiver spurious emission
30 MHz to 1.0 GHz
Receiver spurious emission
1.0 GHz to 12.75 GHz
Min
Typ
Max
Unit
Details/
conditions
–50
–
–
dBm
RF-PHY
Specification
(RCV-LE/CA/05/C)
dBm
100-kHz
measurement
bandwidth
ETSI EN300 328
V1.8.1
1-MHz
measurement
bandwidth
ETSI EN300 328
V1.8.1
–
–
–57
–
–
–47
dBm
RF transmitter specifications
SID357
TXP, ACC
RF power accuracy
–
±1
–
dB
–
SID358
TXP, RANGE
RF power control range
–
20
–
dB
–
SID359
TXP, 0dBm
Output power, 0-dB Gain setting
(PA7)
–
0
–
dBm
–
SID360
TXP, MAX
Output power, maximum power
setting (PA10)
–
3
–
dBm
–
SID361
TXP, MIN
Output power, minimum power
setting (PA1)
–
–18
–
dBm
–
SID362
F2AVG
Average frequency deviation for
10101010 pattern
185
–
–
kHz
RF-PHY
Specification
(TRM-LE/CA/05/C)
SID363
F1AVG
Average frequency deviation for
11110000 pattern
225
250
275
kHz
RF-PHY
Specification
(TRM-LE/CA/05/C)
SID364
EO
Eye opening = ∆F2AVG/∆F1AVG
0.8
–
–
SID365
FTX, ACC
Frequency accuracy
–150
–
150
kHz
RF-PHY
Specification
(TRM-LE/CA/06/C)
SID366
FTX, MAXDR
Maximum frequency drift
–50
–
50
kHz
RF-PHY
Specification
(TRM-LE/CA/06/C)
SID367
FTX, INITDR
Initial frequency drift
–20
–
20
kHz
RF-PHY
Specification
(TRM-LE/CA/06/C)
SID368
FTX, DR
Maximum drift rate
–20
–
20
kHz/
50 µs
RF-PHY
Specification
(TRM-LE/CA/06/C)
SID369
IBSE1
In-band spurious emission at
2-MHz offset
–
–
–20
dBm
RF-PHY
Specification
(TRM-LE/CA/03/C)
Datasheet
52
RF-PHY
Specification
(TRM-LE/CA/05/C)
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 54
Spec ID#
Bluetooth® LE subsystem (continued)
Parameter
Description
Min
Typ
Max
Unit
Details/
conditions
SID370
IBSE2
In-band spurious emission at
≥3-MHz offset
–
–
-30
dBm
RF-PHY
Specification
(TRM-LE/CA/03/C)
SID371
TXSE1
Transmitter spurious emissions
(average), 1.0 GHz
–
–
-41.5
dBm
FCC-15.247
RF current specifications
SID373
IRX
Receive current in normal mode
–
18.7
–
mA
–
SID373A
IRX_RF
Radio receive current in normal
mode
–
16.4
–
mA
Measured at VDDR
SID374
IRX, HIGHGAIN
Receive current in high-gain
mode
–
21.5
–
mA
–
SID375
ITX, 3dBm
TX current at 3-dBm setting
(PA10)
–
20
–
mA
–
SID376
ITX, 0dBm
TX current at 0-dBm setting
(PA7)
–
16.5
–
mA
–
SID376A
ITX_RF, 0dBm
Radio TX current at 0 dBm
setting (PA7)
–
15.6
–
mA
Measured at VDDR
SID376B
ITX_RF, 0dBm
Radio TX current at 0 dBm
excluding Balun loss
–
14.2
–
mA
Guaranteed by
design simulation
SID377
ITX,-3dBm
TX current at –3-dBm setting
(PA4)
–
15.5
–
mA
–
SID378
ITX,-6dBm
TX current at –6-dBm setting
(PA3)
–
14.5
–
mA
–
SID379
ITX,-12dBm
TX current at –12-dBm setting
(PA2)
–
13.2
–
mA
–
SID380
ITX,-18dBm
TX current at –18-dBm setting
(PA1)
–
12.5
–
mA
–
SID380A
Iavg_1sec,
0dBm
Average current at 1-second
Bluetooth® LE connection
interval
SID380B
Iavg_4sec,
0dBm
Average current at 4-second
Bluetooth® LE connection
interval
–
17.1
–
µA
TXP: 0 dBm;
±20-ppm master
and slave clock
accuracy.
TXP: 0 dBm;
±20-ppm master
and slave clock
accuracy.
–
6.1
–
µA
2400
–
2482
MHz
–
General RF specifications
SID381
FREQ
RF operating frequency
SID382
CHBW
Channel spacing
–
2
–
MHz
–
SID383
DR
On-air data rate
–
1000
–
kbps
–
SID384
IDLE2TX
Bluetooth® LE.IDLE to
Bluetooth® LE. TX transition
time
–
120
140
µs
–
Datasheet
53
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 54
Bluetooth® LE subsystem (continued)
Spec ID#
SID385
Min
Typ
Max
Unit
Details/
conditions
Bluetooth® LE.IDLE to
Bluetooth® LE. RX transition
time
–
75
120
µs
–
Parameter
IDLE2RX
Description
RSSI specifications
SID386
RSSI, ACC
RSSI accuracy
–
±5
–
dB
–
SID387
RSSI, RES
RSSI resolution
–
1
–
dB
–
SID388
RSSI, PER
RSSI sample period
–
6
–
µs
–
Min
Typ
Max
Unit
Details/
conditions
–
24
–
MHz
–
–50
–
50
ppm
–
Table 55
Spec ID#
ECO specifications
Parameter
Description
SID389
FECO
Crystal frequency
SID390
FTOL
Frequency tolerance
SID391
ESR
Equivalent series resistance
–
–
60
Ω
–
SID392
PD
Drive level
–
–
100
µW
–
SID393
TSTART1
Startup time (Fast Charge on)
–
–
850
µs
–
SID394
TSTART2
Startup time (Fast Charge off)
–
–
3
ms
–
SID395
CL
Load capacitance
–
8
–
pF
–
SID396
C0
Shunt capacitance
–
1.1
–
pF
–
SID397
IECO
Operating current
–
1400
–
µA
–
Min
Typ
Max
Unit
Details/
conditions
Table 56
Spec ID#
WCO specifications
Parameter
Description
SID398
FWCO
Crystal frequency
–
32.768
–
kHz
–
SID399
FTOL
Frequency tolerance
–
50
–
ppm
–
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
–
SID401
PD
Drive level
–
–
1
µW
–
SID402
TSTART
Startup time
–
–
500
ms
–
SID403
CL
Crystal load capacitance
6
–
12.5
pF
–
SID404
C0
Crystal shunt capacitance
–
1.35
–
pF
–
SID405
IWCO1
Operating current
(High-Power mode)
–
–
8
µA
–
SID406
IWCO2
Operating current (Low-Power
mode)
–
–
2.6
µA
–
Datasheet
54
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Ordering information
6
Ordering information
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE part numbers and features are listed in Table 57.
Max CPU speed (MHz)
Bluetooth® LE subsystem
Flash (KB)
SRAM (KB)
UDB
Opamp
CAPSENSE™
TMG (Gestures)
Direct LCD drive
12-bit SAR ADC
DMA
LP comparators
TCPWM blocks
SCB Blocks
GPIO
Package
Temperature range
CY8C4247LQI-BL473
48
4.1 128
16
4
4
–
–
–
1 Msps
–
2
4
2
36
QFN
85°C
CY8C4247FNI-BL473
48
4.1 128
16
4
4
–
–
–
1 Msps
–
2
4
2
36
68-CSP
85°C
CY8C4247LQI-BL453
48
4.1 128
16
4
4
1
–
–
1 Msps
–
2
4
2
36
QFN
85°C
CY8C4247LQI-BL463
48
4.1 128
16
4
4
–
–
1
1 Msps
–
2
4
2
36
QFN
85°C
CY8C4247LQI-BL483
48
4.1 128
16
4
4
1
–
1
1 Msps
–
2
4
2
36
QFN
85°C
CY8C4247LQI-BL493
48
4.1 128
16
4
4
1
1
1
1 Msps
–
2
4
2
36
QFN
85°C
CY8C4247FNI-BL483
48
4.1 128
16
4
4
1
–
1
1 Msps
–
2
4
2
36
68-CSP
85°C
CY8C4247FNI-BL493
48
4.1 128
16
4
4
1
1
1
1 Msps
–
2
4
2
36
68-CSP
85°C
Product family
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE
CY8C42xx-BL MCU with AIROC™ Bluetooth® LE part numbers
MPN
Table 57
CY8C4247FNQ-BL483
48
4.1 128
16
4
4
1
–
1
1 Msps
–
2
4
2
36
68-CSP
105°C
CY8C4247LQQ-BL483
48
4.1 128
16
4
4
1
–
1
1 Msps
–
2
4
2
36
QFN
105°C
CY8C4247FLI-BL493
48
4.1 128
16
4
4
1
1
1
1 Msps
–
2
4
2
36
Thin 68-CSP
85°C
CY8C4248LQI-BL453
48
4.1 256
32
4
4
1
–
–
1 Msps
1
2
4
2
36
QFN
85°C
CY8C4248LQI-BL483
48
4.1 256
32
4
4
1
–
1
1 Msps
1
2
4
2
36
QFN
85°C
CY8C4248FNI-BL483
48
4.1 256
32
4
4
1
–
1
1 Msps
1
2
4
2
36
76-CSP
85°C
CY8C4248LQI-BL543
48
4.2 256
32
–
2
–
–
–
1 Msps
1
–
4
2
36
QFN
85°C
CY8C4248LQI-BL573
48
4.2 256
32
4
4
–
–
–
1 Msps
1
2
4
2
36
QFN
85°C
CY8C4248FNI-BL573
48
4.2 256
32
4
4
–
–
–
1 Msps
1
2
4
2
36
76-CSP
85°C
CY8C4248LQI-BL553
48
4.2 256
32
4
4
1
–
–
1 Msps
1
2
4
2
36
QFN
85°C
CY8C4248FNI-BL553
48
4.2 256
32
4
4
1
–
–
1 Msps
1
2
4
2
36
76-CSP
85°C
CY8C4248LQI-BL563
48
4.2 256
32
4
4
–
–
1
1 Msps
1
2
4
2
36
QFN
85°C
CY8C4248LQI-BL583
48
4.2 256
32
4
4
1
–
1
1 Msps
1
2
4
2
36
QFN
85°C
CY8C4248FNI-BL583
48
4.2 256
32
4
4
1
–
1
1 Msps
1
2
4
2
36
76-CSP
85°C
CY8C4248LQQ-BL583
48
4.2 256
32
4
4
1
–
1
1 Msps
1
2
4
2
36
QFN
105°C
CY8C4248LQI-BL593
48
4.2 256
32
4
4
1
1
1
1 Msps
1
2
4
2
36
QFN
85°C
PSoC™ 4 devices follow the part numbering convention described in the following table. All fields are
single-character alphanumeric (0, 1, 2, …, 9, A,B, …, Z) unless stated otherwise.
Datasheet
55
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Ordering information
6.1
Ordering code definitions
Example
CY 8 C 4 A B C D E F -
BLXYZ
Cypress prefix
CY8 C
4 : PSoC™ 4
Architecture
2 : 4200 family
Family within architecture
4 : 48MHz
Speed grade
8 : 256KB
Flash capacity
LQ : QFN
Package code
Temperature range
I : Industrial
BLXYZ : Attributes
Attributes code
The field values are listed in the following table:
Field
CY8C
Description
Values
Meaning
Cypress prefix
4
Architecture
4
PSoC™ 4
A
Family within
architecture
2
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE
family
B
CPU speed
4
48 MHz
C
Flash capacity
DE
F
BLXYZ
Datasheet
Package code
Temperature range
Attributes code
8, 7
256, 128 KB respectively
FN
WLCSP
LQ
QFN
FL
Thin CSP
I
Industrial
BL400-BL499 Bluetooth® 4.1 compliant
BL500-BL599 Bluetooth® 4.2 compliant
56
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Packaging
7
Packaging
Table 58
Package characteristics
Parameter
Description
Conditions
Min
Typ
Max
Unit
TA
Operating ambient
temperature
–
–40
25.00
105
°C
TJ
Operating junction
temperature
–
–40
–
125
°C
TJA
Package JA (56-pin QFN)
–
–
16.9
–
°C/watt
TJC
Package JC (56-pin QFN)
–
–
9.7
–
°C/watt
TJA
Package JA (76-ball WLCSP)
–
–
20.1
–
°C/watt
TJC
Package JC (76-ball WLCSP)
–
–
0.19
–
°C/watt
TJA
Package JA (76-ball thin
WLCSP)
–
–
20.9
–
°C/watt
TJC
Package JC (76-ball thin
WLCSP)
–
–
0.17
–
°C/watt
TJA
Package JA (68-ball WLCSP)
–
–
16.6
–
°C/watt
TJC
Package JC (68-ball WLCSP)
–
–
0.19
–
°C/watt
TJA
Package JA (68-ball thin
WLCSP)
–
–
16.6
–
°C/watt
TJC
Package JC (68-ball thin
WLCSP)
–
–
0.19
–
°C/watt
Table 59
Solder reflow peak temperature
Table 60
Table 61
Datasheet
Package
Maximum peak
temperature
Maximum time at peak
temperature
All packages
260°C
30 seconds
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2
Package
MSL
56-pin QFN
MSL 3
All WLCSP packages
MSL 1
Package details
Spec ID
Package
Description
001-58740 Rev. *C
56-pin QFN
7.0 mm × 7.0 mm × 0.6 mm
001-96603 Rev. *B
76-ball WLCSP
4.04 mm × 3.87 mm × 0.55 mm
002-10658 Rev. **
76-ball thin WLCSP
4.04 mm × 3.87 mm × 0.4 mm
001-92343 Rev. *A
68-ball WLCSP
3.52 mm × 3.91 mm × 0.55 mm
001-99408 Rev. **
68-ball thin WLCSP
52 mm × 3.91 mm × 0.4 mm
57
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Packaging
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTES:
1.
HATCH AREA IS SOLDERABLE EXPOSED PAD
2. BASED ON REF JEDEC # MO-248
3. ALL DIMENSIONS ARE IN MILLIMETERS
Figure 7
001-58740 *C
56-pin QFN 7 × 7 × 0.6 mm
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and
electrical performance.
Datasheet
58
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Packaging
7.1
WLCSP compatibility
The PSoC™ 4XXX-BLE family has products with 128 KB (16KB SRAM) and 256 KB (32KB SRAM) Flash. Package
pin-outs and sizes are identical for the 56-pin QFN package but are different in one dimension for the 68-ball
WLCSP.
The 256KB Flash product has an extra column of balls which are required for mechanical integrity purposes in
the Chip-Scale package. With consideration for this difference, the land pattern on the PCB may be designed such
that either product may be used with no change to the PCB design.
Figure 8 shows the 128KB and 256 KB Flash CSP packages.
128-K Bluetooth® LE
128K BLE
256-K Bluetooth® LE
256K BLE
CONNECTED PADS
NC PADS
PACKAGE CENTER
PACK BOUNDARY
FIDUCIAL FOR128K
FIDUCIAL FOR256K
Figure 8
128KB and 256 KB Flash CSP packages
The rightmost column of (all NC, No Connect) balls in the 256K Bluetooth® LE WLCSP is for mechanical integrity
purposes. The package is thus wider (3.2 mm versus 2.8 mm). All other dimensions are identical. Infineon will
provide layout symbols for printed circuit board (PCB) layout.
The scheme in Figure 8 is implemented to design the PCB for the 256K Bluetooth® LE package with the
appropriate space requirements thus allowing use of either package at a later time without redesigning the PCB.
Datasheet
59
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Packaging
001-92343 *A
Figure 9
68-ball WLCSP package outline
SIDE VIEW
TOP VIEW
1
2
3
4
5
6
7
8
BOTTOM VIEW
8
7
6
5
4
3
2
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
NOTES:
1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18
2. ALL DIMENSIONS ARE IN MILLIMETERS
Figure 10
Datasheet
001-99408 **
68-ball thin WLCSP
60
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Packaging
PIN #1 MARK
7
1
2
3
4
5
6
7
8
B
9
9
8
7
6
5
4
3
2
1
A
A
B
B
6
C
C
SD
D
E
D
D1
D
E
F
F
G
G
eD
H
H
J
J
SE
A
E
eE
6
E1
TOP VIEW
BOTTOM VIEW
0.10 C
A1
0.05 C
C
76XØb
DETAIL A
5
Ø0.06 M C A B
Ø0.03 M C
A
DETAIL A
SIDE VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
MIN.
NOM.
MAX.
A
-
-
0.55
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
A1
0.18
0.21
0.24
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
D
3.87 BSC
E
4.04 BSC
D1
3.20 BSC
E1
3.20 BSC
MD
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
9
ME
9
N
76
b
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
0.23
0.26
eD
0.40 BSC
eE
0.40 BSC
SD
0.381 BSC
SE
0.321 BSC
6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
0.29
"SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
9. JEDEC SPECIFICATION NO. REF : N/A
Figure 11
Datasheet
001-96603 *B
76-ball WLCSP package outline
61
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Packaging
PIN #1 MARK
7
1
2
3
4
5
6
7
8
B
9
9
8
7
6
5
4
3
2
1
A
A
B
B
6
C
C
SD
D
E
D
D1
D
E
F
F
G
G
eD
H
H
J
J
SE
A
E
eE
6
E1
TOP VIEW
BOTTOM VIEW
0.10 C
A1
0.05 C
C
76XØb
DETAIL A
5
Ø0.06 M C A B
Ø0.03 M C
A
DETAIL A
SIDE VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
MIN.
NOM.
MAX.
A
-
-
0.40
A1
0.072
0.08
0.088
D
3.87 BSC
E
4.04 BSC
D1
3.20 BSC
E1
3.20 BSC
MD
9
ME
9
N
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
76
b
0.22
0.25
eD
0.40 BSC
eE
0.40 BSC
SD
0.381
SE
0.321
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
0.28
"SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
Figure 12
Datasheet
002-10658 **
76-ball thin WLCSP package outline
62
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Acronyms
8
Acronyms
Table 62
Acronyms used in this document
Acronym
Description
ABUS
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm® data transfer
bus
ALU
arithmetic logic unit
AMUXBUS
analog multiplexer bus
API
application programming interface
APSR
®
application program status register
Arm®
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications protocol
CMRR
common-mode rejection ratio
CPU
central processing unit
CRC
cyclic redundancy check, an error-checking protocol
DAC
digital-to-analog converter, see also IDAC, VDAC
DFB
digital filter block
DIO
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
DMIPS
Dhrystone million instructions per second
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DNU
do not use
DR
port write data registers
DSI
digital system interconnect
DWT
data watchpoint and trace
ECC
error correcting code
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only memory
EMI
electromagnetic interference
EMIF
external memory interface
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
ETM
embedded trace macrocell
FET
field-effect transistor
FIR
finite impulse response, see also IIR
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Acronyms
Table 62
Acronyms used in this document (continued)
Acronym
Description
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC™ pin
HCI
host controller interface
HVI
high-voltage interrupt, see also LVI, LVD
IC
integrated circuit
IDAC
current DAC, see also DAC, VDAC
IDE
integrated development environment
I2C, or IIC
Inter-Integrated Circuit, a communications protocol
IIR
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
I/O
input/output, see also GPIO, DIO, SIO, USBIO
IPOR
initial power-on reset
IPSR
interrupt program status register
IRQ
interrupt request
ITM
instrumentation trace macrocell
LCD
liquid crystal display
LIN
Local Interconnect Network, a communications protocol.
LR
link register
LUT
lookup table
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
LVTTL
low-voltage transistor-transistor logic
MAC
multiply-accumulate
MCU
microcontroller unit
MISO
master-in slave-out
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
Opamp
operational amplifier
PAL
programmable array logic, see also PLD
PC
program counter
PCB
printed circuit board
PGA
programmable gain amplifier
PHUB
peripheral hub
PHY
physical layer
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Acronyms
Table 62
Acronyms used in this document (continued)
Acronym
Description
PICU
port interrupt control unit
PLA
programmable logic array
PLD
programmable logic device, see also PAL
PLL
phase-locked loop
PMDD
package material declaration data sheet
POR
power-on reset
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC™
Programmable system on chip
UDB
universal digital block
USB
Universal Serial Bus
USBIO
USB input/output, PSoC™ pins used to connect to a USB port
VDAC
voltage DAC, see also DAC, IDAC
WDT
watchdog timer
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
STN
super twisted nematic
SWD
serial wire debug, a test protocol
SWV
single-wire viewer
Datasheet
65
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Acronyms
Table 62
Acronyms used in this document (continued)
Acronym
Description
TD
transaction descriptor, see also DMA
THD
total harmonic distortion
TIA
transimpedance amplifier
TN
twisted nematic
TRM
technical reference manual
TTL
transistor-transistor logic
TX
transmit
UART
Universal Asynchronous Transmitter Receiver, a communications protocol
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Document conventions
9
Document conventions
9.1
Units of measure
Table 63
Units of measure
Symbol
Units of measure
°C
degrees Celsius
dB
decibel
dBm
decibel-milliwatts
fF
femtofarads
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Revision history
Revision histor y
Document
revision
Date
Description of changes
**
2018-02-22
New datasheet
*A
2021-06-16
Updated datasheet to IFX template.
Changed title to “PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE
Family Datasheet”
2023-03-29
Updated to the latest template
Added Table 2 for 68-ball WLCSP package
Removed the following part numbers from Table 57:
CY8C4248LQI-BL473, CY8C4248FLI-BL483, CY8C4248FNI-BL543,
CY8C4248FNI-BL563, CY8C4248FLI-BL583, CY8C4248FNQ-BL583, and
CY8C4248FNI-BL593
*B
Datasheet
68
002-23053 Rev. *B
2023-03-29
Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2023-03-29
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2023 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
Email:
erratum@infineon.com
Document reference
002-23053 Rev. *B
IMPORTANT NOTICE
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event be regarded as a guarantee of conditions or
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Technologies hereby disclaims any and all
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