PSoC CY8CTMG20x, CY8CTMG20xA, CY8CTST200,
CY8CTST200A TRM
PSoC® CY8CTMG20x, CY8CTMG20xA,
CY8CTST200, CY8CTST200A
Technical Reference Manual (TRM)
Document No. 001-53603 Rev. *C
December 11, 2009
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone (USA): 800.858.1810
Phone (Intnl.): 408.943.2600
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Copyrights
Copyrights
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress
Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress
product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor
intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express
written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use
and in doing so indemnifies Cypress against all charges.
PSoC® is a registered trademark and PSoC Designer™, TrueTouch™, and PSoC Express™ are trademarks of Cypress
Semiconductor Corporation (Cypress), along with Cypress® and Cypress Semiconductor™. All other trademarks or registered trademarks referenced herein are the property of their respective owners.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by
and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty
provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create
derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source
Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described
herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein.
Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure
may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all
charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Flash Code Protection
Note the following details of the Flash code protection features on Cypress devices.
Cypress products meet the specifications contained in their particular Cypress Data Sheets. Cypress believes that its family of
products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be
methods that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously improving the code protection features of our products.
2
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
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Contents Overview
Section A: Overview
1.
Section B: PSoC Core
2.
3.
4.
5.
6.
7.
8.
9.
10.
13
Pin Information .......................................................................................................................... 19
23
CPU Core (M8C) ........................................................................................................................ 27
Supervisory ROM (SROM) ......................................................................................................... 33
RAM Paging ............................................................................................................................... 39
Interrupt Controller ..................................................................................................................... 45
General Purpose I/O (GPIO) ...................................................................................................... 55
Internal Main Oscillator (IMO) ..................................................................................................... 63
Internal Low Speed Oscillator (ILO) ............................................................................................ 67
External Crystal Oscillator (ECO) ............................................................................................... 69
Sleep and Watchdog .................................................................................................................. 73
Section C: TrueTouch System
83
11. TrueTouch Module ..................................................................................................................... 85
12. I/O Analog Multiplexer ................................................................................................................ 99
13. Comparators ............................................................................................................................ 101
Section D: System Resources
14.
15.
16.
17.
18.
19.
20.
105
Digital Clocks ........................................................................................................................... 109
I2C Slave ................................................................................................................................. 117
System Resets ......................................................................................................................... 135
POR and LVD .......................................................................................................................... 143
SPI ......................................................................................................................................... 145
Programmable Timer ................................................................................................................ 161
Full-Speed USB ....................................................................................................................... 165
Section E: Registers
183
21. Register Reference .................................................................................................................. 187
Section F: Glossary
287
Section F: Index
303
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Contents Overview
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Contents
Section A: Overview
1. Pin Information
1.1
Pinouts....................................................................................................................................19
1.1.1 CY8CTMG200-16LGXI, CY8CTMG200A-16LGXI, CY8CTST200-16LGXI,
CY8CTST200A-16LGXI PSoC 16-Pin Part Pinout 19
1.1.2 CY8CTMG200-24LQXI, CY8CTMG200A-24LQXI, CY8CTST200-24LQXI,
CY8CTST200A-24LQXI PSoC 24-Pin Part Pinout 20
1.1.3 CY8CTMG200-32LQXI, CY8CTMG200A-32LQXI, CY8CTST200-32LQXI,
CY8CTST200A-32LQXI, CY8CTMG201-32LQXI, CY8CTMG201A-32LQXI PSoC 32Pin Part Pinout21
1.1.4 CY8CTMG200-48LTXI, CY8CTMG200A-48LTXI, CY8CTST200-48LTXI,
CY8CTST200A-48LTXI, CY8CTMG201-48LTXI, CY8CTMG201A-48LTXI PSoC
48-Pin Part Pinout22
Section B: PSoC Core
2. CPU Core (M8C)
2.1
2.2
2.3
2.4
2.5
2.6
3.
23
27
Overview.................................................................................................................................27
Internal Registers....................................................................................................................27
Address Spaces......................................................................................................................27
Instruction Set Summary ........................................................................................................28
Instruction Formats .................................................................................................................30
2.5.1 One-Byte Instructions ................................................................................................30
2.5.2 Two-Byte Instructions ................................................................................................30
2.5.3 Three-Byte Instructions..............................................................................................31
Register Definitions.................................................................................................................32
2.6.1 CPU_F Register ........................................................................................................32
2.6.2 Related Registers ......................................................................................................32
Supervisory ROM (SROM)
3.1
13
19
33
Architectural Description.........................................................................................................33
3.1.1 Additional SROM Feature ..........................................................................................34
3.1.2 SROM Function Descriptions ....................................................................................34
3.1.2.1 SWBootReset Function ...............................................................................34
3.1.2.2 ReadBlock Function ....................................................................................35
3.1.2.3 WriteBlock Function.....................................................................................35
3.1.2.4 EraseBlock Function....................................................................................36
3.1.2.5 ProtectBlock Function..................................................................................36
3.1.2.6 TableRead Function ....................................................................................36
3.1.2.7 EraseAll Function ........................................................................................36
3.1.2.8 Checksum Function.....................................................................................37
3.1.2.9 Calibrate0 Function .....................................................................................37
3.1.2.10 Calibrate1 Function .....................................................................................37
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3.2
4.
RAM Paging
4.1
4.2
5.
5.2
5.3
6.2
45
Architectural Description......................................................................................................... 45
5.1.1 Posted versus Pending Interrupts ............................................................................. 46
Application Overview .............................................................................................................. 46
Register Definitions ................................................................................................................ 48
5.3.1 INT_CLR0 Register .................................................................................................. 48
5.3.2 INT_CLR1 Register ................................................................................................... 49
5.3.3 INT_CLR2 Register .................................................................................................. 50
5.3.4 INT_MSK0 Register................................................................................................... 51
5.3.5 INT_MSK1 Register................................................................................................... 51
5.3.6 INT_MSK2 Register................................................................................................... 52
5.3.7 INT_SW_EN Register ............................................................................................... 52
5.3.8 INT_VC Register ...................................................................................................... 52
5.3.9 Related Registers ...................................................................................................... 53
General Purpose I/O (GPIO)
6.1
39
Architectural Description......................................................................................................... 39
4.1.1 Basic Paging..............................................................................................................39
4.1.2 Stack Operations ....................................................................................................... 40
4.1.3 Interrupts ................................................................................................................... 40
4.1.4 MVI Instructions......................................................................................................... 40
4.1.5 Current Page Pointer................................................................................................. 40
4.1.6 Index Memory Page Pointer ...................................................................................... 41
Register Definitions ................................................................................................................ 42
4.2.1 TMP_DRx Registers ................................................................................................. 42
4.2.2 CUR_PP Register ..................................................................................................... 42
4.2.3 STK_PP Register ..................................................................................................... 43
4.2.4 IDX_PP Register ...................................................................................................... 43
4.2.5 MVR_PP Register .................................................................................................... 43
4.2.6 MVW_PP Register .................................................................................................... 44
4.2.7 Related Registers ...................................................................................................... 44
Interrupt Controller
5.1
6.
3.1.2.11 WriteAndVerify Function.............................................................................. 37
3.1.2.12 HWBootReset Function............................................................................... 38
Register Definitions ................................................................................................................ 38
55
Architectural Description......................................................................................................... 55
6.1.1 General Description................................................................................................... 56
6.1.2 Digital I/O................................................................................................................... 56
6.1.3 Analog and Digital Inputs........................................................................................... 56
6.1.4 Port 1 Distinctions...................................................................................................... 56
6.1.5 Port 0 Distinctions...................................................................................................... 57
6.1.6 GPIO Block Interrupts................................................................................................ 57
6.1.6.1 Interrupt Modes ........................................................................................... 57
6.1.7 Data Bypass .............................................................................................................. 58
Register Definitions ................................................................................................................ 59
6.2.1 PRTxDR Registers ................................................................................................... 59
6.2.2 PRTxIE Registers ..................................................................................................... 59
6.2.3 PRTxDMx Registers ................................................................................................. 60
6.2.4 IO_CFG1 Register..................................................................................................... 61
6.2.5 IO_CFG2 Register..................................................................................................... 61
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7.
Internal Main Oscillator (IMO)
7.1
7.2
7.3
8.
Internal Low Speed Oscillator (ILO)
8.1
8.2
9.
67
Architectural Description.........................................................................................................67
Register Definitions.................................................................................................................68
8.2.1 ILO_TR Register .......................................................................................................68
External Crystal Oscillator (ECO)
9.1
9.2
9.3
63
Architectural Description.........................................................................................................63
Application Overview ..............................................................................................................63
7.2.1 Trimming the IMO ......................................................................................................63
7.2.2 Engaging Slow IMO ...................................................................................................63
Register Definitions.................................................................................................................64
7.3.1 IMO_TR Register .......................................................................................................64
7.3.2 IMO_TR1 Register ....................................................................................................64
7.3.3 CPU_SCR1 Register .................................................................................................65
7.3.4 OSC_CR2 Register ...................................................................................................65
7.3.5 Related Registers ......................................................................................................66
69
Architectural Description.........................................................................................................69
Application Overview ..............................................................................................................70
Register Definitions.................................................................................................................71
9.3.1 ECO_ENBUS Register .............................................................................................71
9.3.2 ECO_TRIM Register .................................................................................................71
9.3.3 ECO_CFG Register ..................................................................................................71
9.3.4 Related Registers ......................................................................................................72
10. Sleep and Watchdog
73
10.1 Architectural Description.........................................................................................................73
10.1.1 Sleep Control Implementation Logic ..........................................................................74
10.1.1.1 Wakeup Logic..............................................................................................74
10.1.2 Sleep Timer................................................................................................................76
10.2 Application Overview ..............................................................................................................76
10.3 Register Definitions.................................................................................................................77
10.3.1 RES_WDT Register ..................................................................................................77
10.3.2 SLP_CFG Register ...................................................................................................77
10.3.3 SLP_CFG2 Register .................................................................................................78
10.3.4 SLP_CFG3 Register .................................................................................................78
10.3.5 Related Registers ......................................................................................................78
10.4 Timing Diagrams.....................................................................................................................79
10.4.1 Sleep Sequence ........................................................................................................79
10.4.2 Wakeup Sequence.....................................................................................................80
10.4.3 Bandgap Refresh.......................................................................................................80
10.4.4 Watchdog Timer.........................................................................................................81
Section C: TrueTouch System
11. TrueTouch Module
83
85
11.1 Architectural Description.........................................................................................................85
11.1.1 Types of TrueTouch Approaches ...............................................................................85
11.1.1.1 Positive Charge Integration .........................................................................85
11.1.1.2 Relaxation Oscillator....................................................................................86
11.1.1.3 Successive Approximation ..........................................................................87
11.1.1.4 Negative Charge Integration........................................................................88
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11.1.1.5 Sigma Delta................................................................................................. 89
11.1.2 IDAC .......................................................................................................................... 90
11.1.3 TrueTouch Counter ................................................................................................... 90
11.1.3.1 Operation .................................................................................................... 91
11.2 Register Definitions ............................................................................................................... 92
11.2.1 CS_CR0 Register ..................................................................................................... 92
11.2.2 CS_CR1 Register ..................................................................................................... 93
11.2.3 CS_CR2 Register ..................................................................................................... 93
11.2.4 CS_CR3 Register ..................................................................................................... 94
11.2.5 CS_CNTL Register ................................................................................................... 94
11.2.6 CS_CNTH Register .................................................................................................. 94
11.2.7 CS_STAT Register ................................................................................................... 95
11.2.8 CS_TIMER Register ................................................................................................. 95
11.2.9 CS_SLEW Register .................................................................................................. 96
11.2.10 PRS_CR Register ..................................................................................................... 96
11.2.11 IDAC_D Register ...................................................................................................... 97
11.3 Timing Diagrams .................................................................................................................... 97
12. I/O Analog Multiplexer
99
12.1 Architectural Description......................................................................................................... 99
12.2 Register Definitions ..............................................................................................................100
12.2.1 MUX_CRx Registers ...............................................................................................100
13. Comparators
101
13.1 Architectural Description ......................................................................................................101
13.2 Register Definitions .............................................................................................................103
13.2.1 CMP_RDC Register ...............................................................................................103
13.2.2 CMP_MUX Register ...............................................................................................103
13.2.3 CMP_CR0 Register ................................................................................................104
13.2.4 CMP_CR1 Register ................................................................................................104
13.2.5 CMP_LUT Register ................................................................................................104
Section D: System Resources
14. Digital Clocks
105
109
14.1 Architectural Description.......................................................................................................109
14.1.1 Internal Main Oscillator............................................................................................109
14.1.2 Internal Low Speed Oscillator.................................................................................. 110
14.1.3 External Clock ......................................................................................................... 110
14.1.3.1 Switch Operation .......................................................................................110
14.2 Register Definitions ..............................................................................................................112
14.2.1 USB_MISC_CR Register ........................................................................................ 112
14.2.2 OUT_P0 Register ................................................................................................... 113
14.2.3 OUT_P1 Register ................................................................................................... 113
14.2.4 OSC_CR0 Register ................................................................................................ 113
14.2.5 OSC_CR2 Register ................................................................................................ 115
15. I2C Slave
117
15.1 Architectural Description.......................................................................................................117
15.1.1 Basic I2C Data Transfer .......................................................................................... 118
15.2 Application Overview ............................................................................................................118
15.2.1 Slave Operation....................................................................................................... 118
15.2.2 EZI2C Mode ............................................................................................................ 119
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15.3 Register Definitions...............................................................................................................122
15.3.1 I2C_XCFG Register .................................................................................................122
15.3.2 I2C_XSTAT Register................................................................................................123
15.3.3 I2C_ADDR Register.................................................................................................123
15.3.4 I2C_BP Register ......................................................................................................123
15.3.5 I2C_CP Register ......................................................................................................124
15.3.6 CPU_BP Register ....................................................................................................124
15.3.7 CPU_CP Register....................................................................................................124
15.3.8 I2C_BUF Register....................................................................................................125
15.3.9 I2C_CFG Register ..................................................................................................126
15.3.10 I2C_SCR Register ..................................................................................................128
15.3.11 I2C_DR Register .....................................................................................................129
15.4 Timing Diagrams...................................................................................................................130
15.4.1 Clock Generation .....................................................................................................130
15.4.2 Basic I/O Timing.......................................................................................................130
15.4.3 Status Timing ...........................................................................................................131
15.4.4 Slave Stall Timing ....................................................................................................132
15.4.5 Implementation ........................................................................................................132
15.4.6 Compatibility Mode Configuration ............................................................................133
16. System Resets
135
16.1 Architectural Description.......................................................................................................135
16.2 Pin Behavior During Reset ...................................................................................................135
16.2.1 GPIO Behavior on Power Up...................................................................................135
16.2.2 Powerup External Reset Behavior ...........................................................................136
16.2.3 GPIO Behavior on External Reset ...........................................................................136
16.3 Register Definitions...............................................................................................................137
16.3.1 CPU_SCR1 Register ...............................................................................................137
16.3.2 CPU_SCR0 Register ...............................................................................................138
16.4 Timing Diagrams...................................................................................................................139
16.4.1 Power On Reset ......................................................................................................139
16.4.2 External Reset .........................................................................................................139
16.4.3 Watchdog Timer Reset ............................................................................................139
16.4.4 Reset Details ...........................................................................................................141
16.5 Power Modes........................................................................................................................141
17. POR and LVD
143
17.1 Architectural Description.......................................................................................................143
17.2 Register Definitions...............................................................................................................144
17.2.1 VLT_CR Register .....................................................................................................144
17.2.2 VLT_CMP Register ..................................................................................................144
18. SPI
145
18.1 Architectural Description.......................................................................................................145
18.1.1 SPI Protocol Function ..............................................................................................145
18.1.1.1 SPI Protocol Signal Definitions..................................................................146
18.1.2 SPI Master Function ................................................................................................146
18.1.2.1 Usability Exceptions ..................................................................................146
18.1.2.2 Block Interrupt ...........................................................................................146
18.1.3 SPI Slave Function ..................................................................................................146
18.1.3.1 Usability Exceptions ..................................................................................146
18.1.3.2 Block Interrupt ...........................................................................................147
18.1.4 Input Synchronization ..............................................................................................147
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18.2 Register Definitions ..............................................................................................................147
18.2.1 SPI_TXR Register ...................................................................................................147
18.2.2 SPI_RXR Register...................................................................................................148
18.2.2.1 SPI Master Data Register Definitions........................................................148
18.2.2.2 SPI Slave Data Register Definitions..........................................................148
18.2.3 SPI_CR Register .....................................................................................................149
18.2.3.1 SPI Control Register Definitions................................................................149
18.2.4 SPI_CFG Register...................................................................................................150
18.2.4.1 SPI Configuration Register Definitions ......................................................150
18.2.5 Related Registers ....................................................................................................150
18.3 Timing Diagrams ..................................................................................................................151
18.3.1 SPI Mode Timing .....................................................................................................151
18.3.2 SPIM Timing ............................................................................................................152
18.3.3 SPIS Timing.............................................................................................................157
19. Programmable Timer
161
19.1 Architectural Description.......................................................................................................161
19.1.1 Operation.................................................................................................................161
19.2 Register Definitions ..............................................................................................................163
19.2.1 PT0_CFG Register ..................................................................................................163
19.2.2 PT1_CFG Register ..................................................................................................163
19.2.3 PT2_CFG Register ..................................................................................................164
19.2.4 PTx_DATA0 Register...............................................................................................164
19.2.5 PTx_DATA1 Register...............................................................................................164
20. Full-Speed USB
165
20.1 Architectural Description.......................................................................................................165
20.2 Application Description .........................................................................................................165
20.2.1 USB SIE ..................................................................................................................165
20.2.2 USB SRAM..............................................................................................................166
20.2.2.1 PSoC Memory Arbiter ...............................................................................166
20.2.3 Oscillator Lock .........................................................................................................168
20.2.4 Transceiver ..............................................................................................................168
20.2.5 USB Suspend ..........................................................................................................168
20.2.5.1 Using Standby I2C-USB Sleep Mode for USB Suspend...........................169
20.2.5.2 Using Standby or Deep Sleep Modes for USB Suspend ..........................169
20.2.5.3 Wakeup from Suspend..............................................................................169
20.2.6 Regulator .................................................................................................................169
20.3 Register Definitions ..............................................................................................................171
20.3.1 USB_SOF0 Register ...............................................................................................171
20.3.2 USB_CR0 Register..................................................................................................171
20.3.3 USBIO_CR0 Register..............................................................................................172
20.3.4 USBIO_CR1 Register..............................................................................................172
20.3.5 EP0_CR Register ....................................................................................................173
20.3.6 EP0_CNT Register ..................................................................................................174
20.3.7 EP0_DRx Register ..................................................................................................174
20.3.8 EPx_CNT1 Register ................................................................................................175
20.3.9 EPx_CNT0 Register ................................................................................................176
20.3.10 EPx_CR0 Register ..................................................................................................177
20.3.11 PMAx_WA Register .................................................................................................178
20.3.12 PMAx_DR Register .................................................................................................179
20.3.13 PMAx_RA Register..................................................................................................180
20.3.14 USB_CR1 Register..................................................................................................180
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20.3.15 IMO_TR1 Register...................................................................................................181
20.3.16 Related Registers ....................................................................................................181
Section E: Registers
21. Register Reference
183
187
21.1 Maneuvering Around the Registers ......................................................................................187
21.2 Register Conventions ...........................................................................................................187
21.3 Bank 0 Registers ..................................................................................................................188
21.3.1 PRTxDR ..................................................................................................................188
21.3.2 PRTxIE ...................................................................................................................189
21.3.3 SPI_TXR .................................................................................................................190
21.3.4 SPI_RXR ................................................................................................................191
21.3.5 SPI_CR ...................................................................................................................192
21.3.6 USB_SOF0 .............................................................................................................193
21.3.7 USB_SOF1 .............................................................................................................194
21.3.8 USB_CR0 ...............................................................................................................195
21.3.9 USBIO_CR0 ...........................................................................................................196
21.3.10 USBIO_CR1 ...........................................................................................................197
21.3.11 EP0_CR ..................................................................................................................198
21.3.12 EP0_CNT ................................................................................................................199
21.3.13 EP0_DRx ................................................................................................................200
21.3.14 EPx_CNT0 ..............................................................................................................201
21.3.15 EPx_CNT1 ..............................................................................................................202
21.3.16 PMAx_DR ...............................................................................................................203
21.3.17 AMUX_CFG ............................................................................................................204
21.3.18 CMP_RDC ..............................................................................................................205
21.3.19 CMP_MUX ..............................................................................................................206
21.3.20 CMP_CR0 ...............................................................................................................207
21.3.21 CMP_CR1 ...............................................................................................................208
21.3.22 CMP_LUT ...............................................................................................................210
21.3.23 CS_CR0 ..................................................................................................................211
21.3.24 CS_CR1 ..................................................................................................................212
21.3.25 CS_CR2 ..................................................................................................................213
21.3.26 CS_CR3 ..................................................................................................................214
21.3.27 CS_CNTL ...............................................................................................................215
21.3.28 CS_CNTH ...............................................................................................................216
21.3.29 CS_STAT ................................................................................................................217
21.3.30 CS_TIMER ..............................................................................................................218
21.3.31 CS_SLEW ...............................................................................................................219
21.3.32 PRS_CR .................................................................................................................220
21.3.33 PT0_CFG ................................................................................................................221
21.3.34 PTx_DATA1 ............................................................................................................222
21.3.35 PTx_DATA0 ............................................................................................................223
21.3.36 PT1_CFG ................................................................................................................224
21.3.37 PT2_CFG ................................................................................................................225
21.3.38 I2C_XCFG ..............................................................................................................226
21.3.39 I2C_XSTAT .............................................................................................................227
21.3.40 I2C_ADDR ..............................................................................................................228
21.3.41 I2C_BP ...................................................................................................................229
21.3.42 I2C_CP ...................................................................................................................230
21.3.43 CPU_BP .................................................................................................................231
21.3.44 CPU_CP .................................................................................................................232
21.3.45 I2C_BUF .................................................................................................................233
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21.3.46 CUR_PP .................................................................................................................234
21.3.47 STK_PP ..................................................................................................................235
21.3.48 IDX_PP ...................................................................................................................236
21.3.49 MVR_PP .................................................................................................................237
21.3.50 MVW_PP ................................................................................................................238
21.3.51 I2C_CFG ................................................................................................................239
21.3.52 I2C_SCR ................................................................................................................240
21.3.53 I2C_DR ...................................................................................................................241
21.3.54 INT_CLR0 ...............................................................................................................242
21.3.55 INT_CLR1 ...............................................................................................................244
21.3.56 INT_CLR2 ...............................................................................................................246
21.3.57 INT_MSK2 ..............................................................................................................248
21.3.58 INT_MSK1 ..............................................................................................................249
21.3.59 INT_MSK0 ..............................................................................................................250
21.3.60 INT_SW_EN ...........................................................................................................251
21.3.61 INT_VC ...................................................................................................................252
21.3.62 RES_WDT ..............................................................................................................253
21.3.63 CPU_F ....................................................................................................................254
21.3.64 IDAC_D ..................................................................................................................256
21.3.65 CPU_SCR1 ............................................................................................................257
21.3.66 CPU_SCR0 ............................................................................................................258
21.4 Bank 1 Registers ..................................................................................................................259
21.4.1 PRTxDM0 ...............................................................................................................259
21.4.2 PRTxDM1 ...............................................................................................................260
21.4.3 SPI_CFG ................................................................................................................261
21.4.4 USB_CR1 ...............................................................................................................262
21.4.5 PMAx_WA ..............................................................................................................263
21.4.6 PMAx_RA ...............................................................................................................264
21.4.7 EPx_CR0 ................................................................................................................265
21.4.8 TMP_DRx ...............................................................................................................266
21.4.9 USB_MISC_CR ......................................................................................................267
21.4.10 OUT_P0 ..................................................................................................................268
21.4.11 ECO_ENBUS .........................................................................................................269
21.4.12 ECO_TRIM .............................................................................................................270
21.4.13 MUX_CRx ...............................................................................................................271
21.4.14 IO_CFG1 ................................................................................................................272
21.4.15 OUT_P1 ..................................................................................................................273
21.4.16 IO_CFG2 ................................................................................................................275
21.4.17 OSC_CR0 ...............................................................................................................276
21.4.18 ECO_CFG ..............................................................................................................277
21.4.19 OSC_CR2 ...............................................................................................................278
21.4.20 VLT_CR ..................................................................................................................279
21.4.21 VLT_CMP ...............................................................................................................280
21.4.22 IMO_TR ..................................................................................................................281
21.4.23 ILO_TR ...................................................................................................................282
21.4.24 SLP_CFG ...............................................................................................................283
21.4.25 SLP_CFG2 .............................................................................................................284
21.4.26 SLP_CFG3 .............................................................................................................285
21.4.27 IMO_TR1 ................................................................................................................286
Section F: Glossary
Section F: Index
287
303
12
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Section A:
Overview
The PSoC® family consists of many Programmable System-on-Chip with On-Chip Controller devices. The CY8CTMG20x and
CY8CTST200 PSoC devices have fixed analog and digital resources in addition to a fast CPU, Flash program memory, and
SRAM data memory to support various TrueTouch™ algorithms.
For the most up-to-date ordering, pinout, packaging, or electrical specification information, refer to the PSoC device’s data
sheet. For the most current technical reference manual information and newest product documentation, go to the Cypress
web site at http://www.cypress.com >> Documentation.
This section contains:
■
Pin Information on page 19.
Document Organization
This manual is organized into sections and chapters, according to PSoC functionality. Each section contains a top-level architectural diagram and a register summary (if applicable). Most chapters within the sections have an introduction, an architectural/application description, register definitions, and timing diagrams. The sections are as follows:
■
Overview – Presents the top-level architecture, helpful information to get started, and document history and
conventions. The PSoC device pinouts are detailed in the chapter Pin Information, on page 19.
■
PSoC Core – Describes the heart of the PSoC device in various chapters, beginning with an architectural overview and a
summary list of registers pertaining to the PSoC core.
■
TrueTouch System – Describes the configurable PSoC TrueTouch system in various chapters, beginning with an architectural overview and a summary list of registers pertaining to the TrueTouch system.
■
System Resources – Presents additional PSoC system resources, beginning with an overview and a summary list of
registers pertaining to system resources.
■
Registers – Lists all PSoC device registers in register mapping tables, and presents bit-level detail of each register in its
own Register Reference chapter. Where applicable, detailed register descriptions are also located in each chapter.
■
Glossary – Defines the specialized terminology used in this manual. Glossary terms are presented in bold, italic font
throughout this manual.
■
Index – Lists the location of key topics and elements that constitute and empower the PSoC devices.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
13
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Section A: Overview
Top Level Architecture
The PSoC block diagram on the next page illustrates the
top-level architecture of the CY8CTMG20x and
CY8CTST200 devices. Each major grouping in the diagram
is covered in this manual in its own section: PSoC Core,
TrueTouch System, and the System Resources. Banding
these three main areas together is the communication network of the system bus.
TrueTouch™ System
PSoC Core
System Resources
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses the SRAM for data storage,
an interrupt controller for easy program execution to new
addresses, sleep and watchdog timers, a regulated 3.0V
output option is provided for Port 1 I/Os, and multiple clock
sources that include the IMO (internal main oscillator) and
ILO (internal low speed oscillator) for precision, programmable clocking.
The System Resources provide additional PSoCcapability.
These system resources include:
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architecture microprocessor. Within the CPU core are
the SROM and Flash memory components that provide
flexible programming.
PSoC GPIOs provide connection to the CPU and the TrueTouch resources of the device. Each pin’s drive mode is
selectable from four options, allowing great flexibility in
external interfacing. Every pin also has the capability to generate a system interrupt on low level and change from last
read.
14
The TrueTouch System is composed of comparators, reference drivers, I/O multiplexers, and digital logic to support
various capacitive sensing algorithms. Various reference
selections are provided. Digital logic is mainly comprised of
counters and timers.
■
Digital clocks to increase the flexibility of the PSoC programmable system-on-chip.
■
I2C functionality with "no bus stalling.”
■
Various system resets supported by the M8C.
■
Power-On-Reset (POR) circuit protection.
■
SPI master and slave functionality.
■
A programmable timer to provide periodic interrupts.
■
Clock boost network providing a stronger signal to
switches.
■
Full-speed USB interface for USB 2.0 communication
with 512 bytes of dedicated buffer memory and an internal 3V regulator.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
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Section A: Overview
PSoC Core Top-Level Block Diagram
Port 4
Port 3
Port 2
Port 1
Port 0
1.8/2.5/3V PWRSYS
LDO
(Regulator)
CORE
SYSTEM BUS
1K, 2K
SRAM
Supervisory ROM (SROM)
Interrupt
Controller
8K, 16K, 32K Flash
Nonvolatile Memory
Sleep and
Watchdog
CPU Core (M8C)
6/12/24 MHz Internal Main Oscillator (IMO)
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
SYSTEM BUS
USB
I2C
Slave
System
Resets
POR
and
LVD
SPI
Master/
Slave
Three 16-Bit
Programmable
Timers
Digital
Clocks
SYSTEM RESOURCES
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
15
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Section A: Overview
Getting Started
The quickest path to understanding PSoC is by reading the PSoC device’s data sheet and using PSoC Designer™ Integrated
Development Environment (IDE). This manual is useful for understanding the details of the PSoC integrated circuit.
Important Note For the most up-to-date Ordering, Packaging, or Electrical Specification information, refer to the individual
PSoC device’s data sheet or go to http://www.cypress.com.
Support
Free support for PSoC products is available online at http://www.cypress.com. Resources include Training Seminars, Discussion Forums, Application Notes, TightLink Technical Support Email/Knowledge Base, and Application Support Technicians.
Technical Support can be reached at http://www.cypress.com/support.
Product Upgrades
Cypress provides scheduled upgrades and version enhancements for PSoC Designer free of charge. You can order the
upgrades from your distributor on CD-ROM or download them directly from http://www.cypress.com under Software. Also provided are critical updates to system documentation under http://www.cypress.com >> Documentation.
Development Kits
The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the
Cypress Online Store web site at http://www.cypress.com under Order >> PSoC Kits.
Document History
This section serves as a chronicle of the PSoC® CY8CTMG20x, CY8CTMG20xA, CY8CTST200, CY8CTST200A Technical
Reference Manual.
Technical Reference Manual History
Version/
Release Date
Originator
Description of Change
** May 2009
DSG
First release of the CY8CTMG20x, CY8CTST200 Technical Reference Manual.
*A August 2009
DSG
Second release of the CY8CTMG20x, CY8CTST200 Technical Reference Manual.
*B November 2009
FSU
Multiple fixes, primarily to the sleep and I2C chapters.
*C December 2009
FSU
Multiple fixes, primarily to the External Crystal Oscillator chapter.
16
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
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Section A: Overview
Documentation Conventions
Numeric Naming
There are only four distinguishing font types used in this
manual, besides those found in the headings.
■
The first is the use of italics when referencing a document title or file name.
■
The second is the use of bold italics when referencing a
term described in the Glossary of this manual.
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example,
‘14h’ or ‘3Ah’) and hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary
numbers have an appended lowercase ‘b’ (for example,
01010100b’ or ‘01000011b’). Numbers not indicated by an
‘h’ or ‘b’ are decimal.
■
The third is the use of Times New Roman font, distinguishing equation examples.
Units of Measure
■
The fourth is the use of Courier New font, distinguishing code examples.
Units of Measure
Register Conventions
Symbol
The following table lists the register conventions that are
specific to this manual. A more detailed set of register conventions is located in the Register Reference chapter on
page 187.
Register Conventions
Convention
Example
This table lists the units of measure used in this manual.
Description
‘x’ in a register
name
Multiple instances/address ranges of the
same register
PRTxIE
R
R : 00
Read register or bit(s)
W
W : 00
Write register or bit(s)
Unit of Measure
°C
degree Celsius
dB
decibels
fF
femtofarad
Hz
hertz
k
kilo, 1000
K
210, 1024
KB
1024 bytes
Kbit
1024 bits
kHz
kilohertz (32.000)
kΩ
kilohm
O
RO : 00
Only a read/write register or bit(s).
L
RL : 00
Logical register or bit(s)
MHz
megahertz
C
RC : 00
Clearable register or bit(s)
MΩ
megaohm
00
RW : 00
Reset value is 0x00 or 00h
μA
microampere
XX
RW : XX
Register is not reset
μF
microfarad
0,
0,04h
Register is in bank 0
μs
microsecond
1,
1,23h
Register is in bank 1
μV
microvolt
x,
x,F7h
Register exists in register bank 0 and register bank 1
Empty, grayedout table cell
Reserved bit or group of bits, unless otherwise stated
μVrms
microvolts root-mean-square
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoamphere
ns
nanosecond
nV
nanovolt
Ω
ohm
pF
picofarad
pp
peak-to-peak
ppm
parts per million
sps
samples per second
σ
sigma: one standard deviation
V
volt
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
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Section A: Overview
Acronyms
Acronyms (continued)
This table lists the acronyms that are used in this manual.
Acronyms
Acronym
Description
ABUS
analog output bus
AC
alternating current
ADC
analog-to-digital converter
API
Application Programming Interface
BC
broadcast clock
BR
bit rate
BRA
bus request acknowledge
BRQ
bus request
CBUS
comparator bus
CI
carry in
CMP
compare
CO
carry out
CPU
central processing unit
CRC
cyclic redundancy check
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
DI
digital or data input
DMA
direct memory access
DO
digital or data output
ECO
external crystal oscillator
FB
feedback
GIE
global interrupt enable
GPIO
general purpose I/O
ICE
in-circuit emulator
IDE
integrated development environment
ILO
internal low speed oscillator
IMO
internal main oscillator
I/O
input/output
IOR
I/O read
IOW
I/O write
IPOR
imprecise power on reset
IRQ
interrupt request
ISR
interrupt service routine
ISSP
in system serial programming
IVR
interrupt vector read
LFSR
linear feedback shift register
LRb
last received bit
LRB
last received byte
LSb
least significant bit
LSB
least significant byte
LUT
look-up table
MISO
master-in-slave-out
MOSI
master-out-slave-in
MSb
most significant bit
MSB
most significant byte
PC
program counter
18
Acronym
Description
PCH
program counter high
PCL
program counter low
PD
power down
PMA
PSoC® memory arbiter
POR
power on reset
PPOR
precision power on reset
PRS
pseudo random sequence
PSoC®
Programmable System-on-Chip
PSSDC
power system sleep duty cycle
PWM
pulse width modulator
RAM
random access memory
RETI
return from interrupt
RO
relaxation oscillator
ROM
read only memory
RW
read/write
SAR
successive approximation register
SC
switched capacitor
SIE
serial interface engine
SE0
single-ended zero
SOF
start of frame
SP
stack pointer
SPI
serial peripheral interconnect
SPIM
serial peripheral interconnect master
SPIS
serial peripheral interconnect slave
SRAM
static random access memory
SROM
supervisory read only memory
SSADC
single slope ADC
SSC
supervisory system call
TC
terminal count
USB
universal serial bus
WDT
watchdog timer
WDR
watchdog reset
XRES
external reset
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
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1.
Pin Information
This chapter lists, describes, and illustrates all pins and pinout configurations for the CY8CTMG20x, CY8CTMG20xA,
CY8CTST200, and CY8CTST200A PSoC devices. For up-to-date ordering, pinout, and packaging information, refer to the
individual PSoC device’s data sheet or go to http://www.cypress.com.
1.1
Pinouts
The CY8CTMG20x, CY8CTMG20xA, CY8CTST200, and CY8CTST200A PSoC devices are available in a variety of packages. Every port pin (labeled with a “P”), except for Vss, Vdd, and XRES in the following tables and illustrations, is capable
of Digital I/O.
1.1.1
CY8CTMG200-16LGXI, CY8CTMG200A-16LGXI, CY8CTST200-16LGXI,
CY8CTST200A-16LGXI PSoC 16-Pin Part Pinout
Table 1-1. 16-Pin QFN/COL Part Pinout
P2[5]
XTAL Out
I
P2[3]
XTAL In
3
IOHR
I
P1[7]
I2C SCL, SPI SS
4
IOHR
I
P1[5]
I2C SDA, SPI MISO
5
IOHR
I
P1[3]
SPI CLK
6
IOHR
I
P1[1]
TC CLK*, I2C SCL, SPI MOSI
Vss
Ground pin
TC DATA*, I2C SDA, SPI CLK
Power
IOHR
I
P1[0]
9
IOHR
I
P1[2]
10
IOHR
I
P1[4]
EXTCLK
XRES
Active high external reset with internal pull down
11
12
Input
IOH
13
I
Power
P0[4]
Vdd
1
2
3
4
QFN
(Top View)
12
11
10
9
5
6
7
8
8
P2[5]
P2[3]
P1[7]
P1[5]
P0[4]
XRES
P1[4]
P1[2]
P1[1]
Vss
P1[0]
7
Vdd
I
IO
CY8CTMG200-16LGXI, CY8CTMG200A-16LGXI,
CY8CTST200-16LGXI CY8CTST200A-16LGXI PSoC
Devices
P0[3]
P0[7]
IO
2
Description
14
13
1
Name
P0[1]
Analog
16
15
Digital
P1[3]
Type
Pin
No.
Power pin
14
IOH
I
P0[7]
15
IOH
I
P0[3]
Integrating input
16
IOH
I
P0[1]
Integrating input
LEGEND A = Analog, I = Input, O = Output, H = 5 mA High Output Drive, R = Regulated Output Option.
*
These are the ISSP pins, which are not High Z at POR (Power On Reset).
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
19
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Pin Information
1.1.2
CY8CTMG200-24LQXI, CY8CTMG200A-24LQXI, CY8CTST200-24LQXI,
CY8CTST200A-24LQXI PSoC 24-Pin Part Pinout
Table 1-2. 24-Pin QFN Part Pinout **
Analog
1
IO
I
P2[5]
XTAL Out
2
IO
I
P2[3]
XTAL In
3
IO
I
P2[1]
4
IOHR
I
P1[7]
I2C SCL, SPI SS
5
IOHR
I
P1[5]
I2C SDA, SPI MISO
6
IOHR
I
P1[3]
SPI CLK
7
IOHR
I
P1[1]
TC CLK*, I2C SCL, SPI MOSI
NC
No connection
9
Power
Ground pin
TC DATA*, I2C SDA, SPI CLK
IOHR
I
P1[0]
11
IOHR
I
P1[2]
12
IOHR
I
P1[4]
13
IOHR
I
P1[6]
Input
XRES
15
IO
I
P2[0]
16
IOH
I
P0[0]
17
IOH
I
P0[2]
18
IOH
I
P0[4]
19
IOH
I
P0[6]
20
Power
Vdd
CY8CTMG200-24LQXI, CY8CTMG200A-24LQXI,
CY8CTST200-24LQXI, CY8CTST200-24LQXI
PSoC Device
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
EXTCLK
Active high external reset with internal pull down
1
2
3
4
5
6
24
23
22
21
20
19
P0[1]
Vss
10
14
Description
18
17
16
QFN
(Top View) 15
14
13
7
8
9
10
11
12
8
Name
P0[3]
P0[5]
P0[7]
Vdd
P0[6]
Digital
P0[4]
P0[2]
P0[0]
P2[0]
XRES
P1[6]
P1[1]
NC
Vss
P1[0]
P1[2]
P1[4]
Type
Pin
No.
Power pin
21
IOH
I
P0[7]
22
IOH
I
P0[5]
23
IOH
I
P0[3]
Integrating input
24
IOH
I
P0[1]
Integrating input
LEGEND A = Analog, I = Input, O = Output, H = 5 mA High Output Drive, R = Regulated Output Option.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
** The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal.
20
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
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Pin Information
1.1.3
CY8CTMG200-32LQXI, CY8CTMG200A-32LQXI, CY8CTST200-32LQXI,
CY8CTST200A-32LQXI, CY8CTMG201-32LQXI, CY8CTMG201A-32LQXI PSoC
32-Pin Part Pinout
P0[1]
I
P2[7]
3
IO
I
P2[5]
XTAL Out
4
IO
I
P2[3]
XTAL In
5
IO
I
P2[1]
6
IO
I
P3[3]
7
IO
I
P3[1]
8
IOHR
I
P1[7]
I2C SCL, SPI SS
9
IOHR
I
P1[5]
I2C SDA, SPI MISO
10
IOHR
I
P1[3]
SPI CLK
11
IOHR
I
P1[1]
TC CLK*, I2C SCL, SPI MOSI
Vss
Ground pin
TC DATA*, I2C SDA, SPI CLK
12
Power
13
IOHR
I
P1[0]
14
IOHR
I
P1[2]
15
IOHR
I
P1[4]
16
IOHR
I
P1[6]
17
Input
XRES
18
IO
I
P3[0]
19
IO
I
P3[2]
20
IO
I
P2[0]
21
IO
I
P2[2]
22
IO
I
P2[4]
23
IO
I
P2[6]
24
IOH
I
P0[0]
25
IOH
I
P0[2]
26
IOH
I
P0[4]
27
IOH
I
P0[6]
28
Power
Vdd
29
IOH
I
P0[7]
30
IOH
I
P0[5]
31
IOH
I
P0[3]
32
Power
Vss
Integrating input
Vss
P0[3]
P0[5]
P0[7]
Vdd
P0[6]
P0[4]
P0[2]
I
IO
CY8CTMG200-32LQXI, CY8CTMG200A-32LQXI,
CY8CTST200-32LQXI, CY8CTST200A-32LQXI,
CY8CTMG201-32LQXI, CY8CTMG201A-32LQXI PSoC
Devices
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
P3[1]
P1[7]
EXTCLK
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
IOH
2
Description
QFN
(Top View)
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
Analog
1
Name
P0[0]
P2[6]
P2[4]
P2[2]
P2[0]
P3[2]
P3[0]
XRES
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
Pin
No.
Digital
Table 1-3. 32-Pin QFN Part Pinout **
Active high external reset with internal pull down
Power pin
Ground pin
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
* ISSP pin which is not High Z at POR (Power On Reset).
** The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not
connected to ground, it must be electrically floated and not connected to any other signal.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
21
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Pin Information
1.1.4
CY8CTMG200-48LTXI, CY8CTMG200A-48LTXI, CY8CTST200-48LTXI,
CY8CTST200A-48LTXI, CY8CTMG201-48LTXI, CY8CTMG201A-48LTXI PSoC
48-Pin Part Pinout
I
P2[5]
XTAL Out
IO
I
P2[3]
XTAL In
5
IO
I
P2[1]
6
IO
I
P4[3]
7
IO
I
P4[1]
8
IO
I
P3[7]
IO
I
P3[5]
IO
I
P3[3]
11
IO
I
P3[1]
12
IOHR
I
P1[7]
I2C SCL, SPI SS
13
IOHR
I
P1[5]
I2C SDA, SPI MISO
14
NC
No connection
15
NC
No connection
16
IOHR
I
P1[3]
SPI CLK
17
IOHR
I
P1[1]
TC CLK*, I2C SCL, SPI MOSI
Vss
Ground pin
USB PHY
18
Power
19
IO
D+
20
IO
D-
USB PHY
Vdd
Power pin
TC DATA*, I2C SDA, SPI CLK
21
Power
22
IOHR
I
P1[0]
23
IOHR
I
P1[2]
24
IOHR
I
P1[4]
25
IOHR
I
P1[6]
26
Input
XRES
1
2
3
4
5
6
QFN
7
8
9
10
11
12
P1[5]
NC
9
10
NC
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
NC
Vdd
P0[6]
P0[4]
P0[2]
P0[0]
IO
4
No connection
P2[7]
42
41
40
39
38
37
3
NC
(Top View)
36
35
34
33
32
31
30
29
28
27
26
25
P2[6]
P2[4]
P2[2]
P2[0]
P4[2]
P4[0]
P3[6]
P3[4]
P3[2]
P3[0]
XRES
P1[6]
NC
P1[3]
P1[1]
Vss
D+
DVdd
P1[0]
P1[2]
P1[4]
I
CY8CTMG200-48LTXI, CY8CTMG200A-48LTXI,
CY8CTST200-48LTXI, CY8CTST200A-48LTXI,
CY8CTMG201-48LTXI, CY8CTMG201A-48LTXI PSoC
Devices
Description
P0[1]
Vss
P0[3]
P0[5]
P0[7]
NC
IO
1
Name
48
47
46
45
44
43
Analog
2
Pin
No.
13
14
15
16
17
18
19
20
21
22
23
24
Digital
Table 1-4. 48-Pin Part Pinout **
EXTCLK
Active high external reset with internal pull down
I
P3[0]
28
IO
I
P3[2]
29
IO
I
P3[4]
30
IO
I
P3[6]
31
IO
I
P4[0]
32
IO
I
P4[2]
33
IO
I
P2[0]
41
Vdd
Power pin
34
IO
I
P2[2]
42
NC
No connection
35
IO
I
P2[4]
43
NC
No connection
36
IO
I
P2[6]
44
IOH
I
P0[7]
37
IOH
I
P0[0]
45
IOH
I
P0[5]
38
IOH
I
P0[2]
46
IOH
I
P0[3]
39
IOH
I
P0[4]
47
40
IOH
I
P0[6]
48
Pin
No.
Analog
IO
Digital
27
Power
Power
IOH
I
Name
Description
Integrating input
Vss
Ground pin
P0[1]
Integrating input
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
* ISSP pin which is not High Z at POR (Power On Reset).
** The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not
connected to ground, it must be electrically floated and not connected to any other signal.
22
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
[+] Feedback
Section B: PSoC Core
The PSoC Core section discusses the core components of a PSoC device with a base part number of CY8CTMG20x or
CY8CTST200 and the registers associated with those components. The core section covers the heart of the PSoC device,
which includes the M8C microcontroller; SROM, interrupt controller, GPIO, and SRAM paging; multiple clock sources such
as IMO and ILO; and sleep and watchdog functionality. This section includes these chapters:
■
CPU Core (M8C) on page 27.
■
Internal Main Oscillator (IMO) on page 63.
■
Supervisory ROM (SROM) on page 33.
■
Internal Low Speed Oscillator (ILO) on page 67.
■
RAM Paging on page 39.
■
External Crystal Oscillator (ECO), on page 69
■
Interrupt Controller on page 45.
■
Sleep and Watchdog on page 73.
■
General Purpose I/O (GPIO) on page 55.
Top-Level Core Architecture
This figure displays the top level architecture of the PSoC core. Each component of the figure is discussed at length in this
section.
PSoC Core Block Diagram
Port 4
Port 3
Port 2
Port 1
Port 0
1.8/2.5/3V PWRSYS
LDO
(Regulator)
CORE
SYSTEM BUS
1K, 2K
SRAM
Interrupt
Controller
Supervisory ROM (SROM)
8K, 16K, 32K Flash
Nonvolatile Memory
CPU Core (M8C)
6/12/24 MHz Internal Main Oscillator (IMO)
Sleep and
Watchdog
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
23
[+] Feedback
Section B: PSoC Core
Core Register Summary
This table lists all the PSoC registers for the CPU core in address order within their system resource configuration. The
grayed out bits are reserved bits. If you write these bits always write them with a value of ‘0’. For the core registers, the first ‘x’
in some register addresses represents either bank 0 or bank 1. These registers are listed throughout this manual in bank 0,
even though they are also available in bank 1.
Summary Table of the Core Registers
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
Carry
Zero
GIE
RL : 02
M8C REGISTER (page 27)
PgMode[1:0]
XIO_1
XIO
x,F7h
CPU_F
x,6Ch
TMP_DR0
Data[7:0]
RW : 00
x,6Dh
TMP_DR1
Data[7:0]
RW : 00
x,6Eh
TMP_DR2
Data[7:0]
RW : 00
x,6Fh
TMP_DR3
Data[7:0]
0,D0h
CUR_PP
Page Bits[2:0]
RW : 0
0,D1h
STK_PP
Page Bits[2:0]
RW : 0
0,D3h
IDX_PP
Page Bits[2:0]
RW : 0
0,D4h
MVR_PP
Page Bits[2:0]
RW : 0
0,D5h
MVW_PP
Page Bits[2:0]
RW : 0
0,DAh
INT_CLR0
I2C
0,DBh
INT_CLR1
Endpoint3
0,DCh
RAM PAGING (SRAM) REGISTERS (page 39)
RW : 00
INTERRUPT CONTROLLER REGISTERS (page 45)
Sleep
SPI
Timer0
TrueTouch
Analog
V Monitor
RW : 00
USB SOF
USB Bus Rst Timer2
Timer1
RW : 00
INT_CLR2
USB_WAKE Endpoint8
Endpoint7
Endpoint6
Endpoint5
Endpoint4
RW : 00
0,DEh
INT_MSK2
USB
Wakeup
Endpoint8
Endpoint7
Endpoint6
Endpoint5
Endpoint4
RW : 00
0,DFh
INT_MSK1
Endpoint1
Endpoint0
USB SOF
USB Bus
Reset
Timer2
Timer1
RW : 00
0,E0h
INT_MSK0
0,E1h
INT_SW_EN
0,E2h
INT_VC
0,00h
PRT0DR
Data[7:0]
RW : 00
0,01h
PRT0IE
Interrupt Enables[7:0]
RW : 00
0,04h
PRT1DR
Data[7:0]
RW : 00
0,05h
PRT1IE
Interrupt Enables[7:0]
RW : 00
0,08h
PRT2DR
Data[7:0]
RW : 00
0,09h
PRT2IE
Interrupt Enables[7:0]
RW : 00
0,0Ch
PRT3DR
Data[7:0]
RW : 00
0,0Dh
PRT3IE
Interrupt Enables[7:0]
RW : 00
1,00h
PRT0DM0
Drive Mode 0[7:0]
RW : 00
1,01h
PRT0DM1
Drive Mode 1[7:0]
RW : FF
1,04h
PRT1DM0
Drive Mode 0[7:0]
RW : 00
1,05h
PRT1DM1
Drive Mode 1[7:0]
RW : FF
1,08h
PRT2DM0
Drive Mode 0[7:0]
RW : 00
1,09h
PRT2DM1
Drive Mode 1[7:0]
RW : FF
1,0Ch
PRT3DM0
Drive Mode 0[7:0]
RW : 00
1,0Dh
PRT3DM1
Drive Mode 1[7:0]
RW : FF
0,10h
PRTxDR
Data[7:0]
RW : 00
0,11h
PRTxIE
Interrupt Enables[7:0]
RW : 00
1,10h
PRTxDM0
Drive Mode 0[7:0]
RW : 00
1,11h
PRTxDM1
Drive Mode 0[7:0]
RW : 00
I2C
Endpoint2
Sleep
Endpoint1
GPIO
Endpoint0
Endpoint3
Endpoint2
SPI
GPIO
Timer0
TrueTouch
Analog
V Monitor
ENSWINT
Pending Interrupt[7:0]
RW : 00
RW : 0
RC : 00
GENERAL PURPOSE I/O (GPIO) REGISTERS (page 59)
24
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
[+] Feedback
Section B: PSoC Core
Summary Table of the Core Registers (continued)
Address
1,DCh
Name
IO_CFG1
Bit 7
Bit 6
StrongP
Bit 5
Bit 4
Range[1:0]
Bit 3
Bit 2
Bit 1
Bit 0
Access
P1_LOW_
THRS
SPICLK_ON
_P10
REG_EN
IOINT
RW : 00
INTERNAL MAIN OSCILLATOR (IMO) REGISTER (page 64)
1,E8h
IMO_TR
1,FAh
IMO_TR1
x,FEh
CPU_SCR1
1,E2h
OSC_CR2
Trim[7:0]
W: 00
Fine Trim[2:0]
IRESS
SLIM[1:O]
RW : 00
IRAMDIS
CLK48MEN
EXTCLKEN
IMODIS
# : 00
RW : 00
INTERNAL LOW SPEED OSCILLATOR (ILO) REGISTER (page 68)
1,E9h
ILO_TR
PD_MODE
ILOFREQ
SATBIASB
Freq Trim[3:0]
RW : 18
EXTERNAL CRYSTAL OSCILLATOR (ECO) REGISTERS (page 69)
1,D2h
ECO_ENBUS
1,D3h
ECO_TRIM
1,E1h
ECO_CFG
ECO_ENBUS[2:0]
ECO_XGM[2:0]
RW : 07
ECO_PL[1:0]
ECO_LPM
ECO_EXW
ECO_EX
RW : 00
RW : 00
SLEEP AND WATCHDOG REGISTERS (page 77)
0,E3h
RES_WDT
1,EBh
SLP_CFG
1,ECh
SLP_CFG2
1,EDh
SLP_CFG3
WDSL_Clear[7:0]
W : 00
PSSDC[1:0]
RW : 0
ALT_Buzz [1:0]
DBL_TAPS
T2TAP [1:0]
T1TAP [1:0]
I2C_ON
LSO_OFF
T0TAP [1:0]
RW : 00
RW : 0x7F
LEGEND
L The and f, expr; or f, expr; and xor f, expr instructions can be used to modify this register.
x An “x” before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used.
C Clearable register or bit(s).
R Read register or bit(s).
W Write register or bit(s).
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
25
[+] Feedback
Section B: PSoC Core
26
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
[+] Feedback
2. CPU Core (M8C)
This chapter explains the CPU Core, called the M8C, and its associated register. It covers the internal M8C registers, address
spaces, instruction set and formats. For additional information concerning the M8C instruction set, refer to the PSoC
Designer Assembly Language User Guide available at the Cypress web site (http://www.cypress.com). For a quick reference
of all PSoC registers in address order, refer to the Register Reference chapter on page 187.
2.1
Overview
The M8C is a four MIPS 8-bit Harvard architecture microprocessor. Selectable processor clock speeds up to 24 MHz
enable you to tune the M8C to a particular application’s performance and power requirements. The M8C supports a rich
instruction set that allows for efficient low-level language
support.
2.2
Internal Registers
The M8C has five internal registers that are used in program
execution. Here is a list of these registers.
■
Accumulator (A)
■
Index (X)
■
Program Counter (PC)
■
Stack Pointer (SP)
■
Flags (F)
All the internal M8C registers are 8 bits in width, except for
the PC which is 16 bits wide. Upon reset, A, X, PC, and SP
are reset to 00h. The Flag register (F) is reset to 02h, indicating that the Z flag is set.
With each stack operation, the SP is automatically incremented or decremented so that it always points to the next
stack byte in RAM. If the last byte in the stack is at address
FFh, the stack pointer wraps to RAM address 00h. It is the
firmware developer’s responsibility to ensure that the stack
does not overlap with user defined variables in RAM.
The F register is read by using address F7h in either register
bank.
2.3
Address Spaces
The M8C has three address spaces: ROM, RAM, and registers. The ROM address space includes the Supervisory
ROM (SROM) and the Flash. The ROM address space is
accessed through its own address and data bus.
The ROM address space is composed of the Supervisory
ROM and the on-chip Flash program store. Flash is organized into 128-byte blocks. Program store page boundaries
are not an issue because the M8C automatically increments
the 16-bit PC on every instruction. This makes the block
boundaries invisible to user code. Instructions occurring on
a 128-byte Flash page boundary (with the exception of JMP
instructions) incur an extra M8C clock cycle, since the upper
byte of the PC is incremented.
The register address space is used to configure the PSoC
microcontroller’s programmable blocks. It consists of two
banks of 256 bytes each. To switch between banks, the XIO
bit in the Flag register is set or cleared (set for Bank1,
cleared for Bank0). The common convention is to leave the
bank set to Bank0 (XIO cleared), switch to Bank1 as needed
(set XIO), then switch back to Bank0.
With the exception of the F register, the M8C internal registers are not accessible via an explicit register address. The
internal M8C registers are accessed using these instructions:
■
MOV A, expr
■
MOV X, expr
■
SWAP A, SP
■
OR F, expr
■
JMP LABEL
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
27
[+] Feedback
CPU Core (M8C)
2.4
Instruction Set Summary
The instruction set is summarized in both Table 2-1 and Table 2-2 (in numeric and mnemonic order, respectively), and serves
as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC
Designer Assembly Language User Guide (refer to the http://www.cypress.com web site).
Opcode Hex
Cycles
8
2 OR [X+expr], A
Z
5A
5
2 MOV [expr], X
2 ADD A, expr
C, Z
2E
9
3 OR [expr], expr
Z
5B
4
1 MOV A, X
02
6
2 ADD A, [expr]
C, Z
2F 10
3 OR [X+expr], expr
Z
5C
4
1 MOV X, A
03
7
2 ADD A, [X+expr]
C, Z
30
9
1 HALT
5D
6
2 MOV A, reg[expr]
Z
04
7
2 ADD [expr], A
C, Z
31
4
2 XOR A, expr
Z
5E
7
2 MOV A, reg[X+expr]
Z
05
8
2 ADD [X+expr], A
C, Z
32
6
2 XOR A, [expr]
Z
5F 10
3 MOV [expr], [expr]
06
9
Flags
Instruction Format
Flags
Bytes
Cycles
2D
4
Instruction Format
Bytes
Opcode Hex
1 SSC
01
Bytes
00 15
Cycles
Opcode Hex
Table 2-1. Instruction Set Summary Sorted Numerically by Opcode
Instruction Format
Flags
Z
3 ADD [expr], expr
C, Z
33
7
2 XOR A, [X+expr]
Z
60
5
2 MOV reg[expr], A
07 10
3 ADD [X+expr], expr
C, Z
34
7
2 XOR [expr], A
Z
61
6
2 MOV reg[X+expr], A
08
4
1 PUSH A
35
8
2 XOR [X+expr], A
Z
62
8
3 MOV reg[expr], expr
09
4
2 ADC A, expr
C, Z
36
9
3 XOR [expr], expr
Z
63
9
3 MOV reg[X+expr], expr
0A
6
2 ADC A, [expr]
C, Z
37 10
3 XOR [X+expr], expr
Z
64
4
1 ASL A
C, Z
0B
7
2 ADC A, [X+expr]
C, Z
38
5
2 ADD SP, expr
65
7
2 ASL [expr]
C, Z
0C
7
2 ADC [expr], A
C, Z
39
5
2 CMP A, expr
66
8
2 ASL [X+expr]
C, Z
0D
8
2 ADC [X+expr], A
C, Z
3A
7
2 CMP A, [expr]
67
4
1 ASR A
C, Z
0E
9
3 ADC [expr], expr
C, Z
3B
8
2 CMP A, [X+expr]
68
7
2 ASR [expr]
C, Z
0F 10
3 ADC [X+expr], expr
C, Z
3C
8
3 CMP [expr], expr
69
8
2 ASR [X+expr]
C, Z
10
4
1 PUSH X
3D
9
3 CMP [X+expr], expr
6A
4
1 RLC A
C, Z
11
4
2 SUB A, expr
C, Z
3E 10
2 MVI A, [ [expr]++ ]
6B
7
2 RLC [expr]
C, Z
12
6
2 SUB A, [expr]
C, Z
3F 10
2 MVI [ [expr]++ ], A
6C
8
2 RLC [X+expr]
C, Z
13
7
2 SUB A, [X+expr]
C, Z
40
4
1 NOP
6D
4
1 RRC A
C, Z
14
7
2 SUB [expr], A
C, Z
41
9
3 AND reg[expr], expr
Z
6E
7
2 RRC [expr]
C, Z
15
8
2 SUB [X+expr], A
C, Z
42 10
3 AND reg[X+expr], expr
Z
6F
8
2 RRC [X+expr]
C, Z
16
9
3 SUB [expr], expr
C, Z
43
3 OR reg[expr], expr
Z
70
4
2 AND F, expr
C, Z
17 10
3 SUB [X+expr], expr
C, Z
44 10
3 OR reg[X+expr], expr
Z
71
4
2 OR F, expr
C, Z
18
5
1 POP A
45
3 XOR reg[expr], expr
Z
72
4
2 XOR F, expr
C, Z
19
4
2 SBB A, expr
C, Z
46 10
3 XOR reg[X+expr], expr
Z
73
4
1 CPL A
Z
1A
6
2 SBB A, [expr]
C, Z
47
8
3 TST [expr], expr
Z
74
4
1 INC A
C, Z
Z
9
9
if (A=B) Z=1
if (A
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