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CY9AF154MAPMC-G-JNE2

CY9AF154MAPMC-G-JNE2

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

  • 描述:

    IC MCU 32BIT 288KB FLASH 80LQFP

  • 数据手册
  • 价格&库存
CY9AF154MAPMC-G-JNE2 数据手册
MB9A150RA Series TM 32-bit ARM CortexTM-M3 based Microcontroller MB9AF154MA/NA/RA, MB9AF155MA/NA/RA, MB9AF156MA/NA/RA Data Sheet (Full Production) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. Publication Number MB9AF156RA_DS706-00047 Revision 2.0 Issue Date April 4, 2014 D a t a S h e e t Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office. MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 MB9A150RA Series 32-bit ARMTM CortexTM-M3 based Microcontroller MB9AF154MA/NA/RA, MB9AF155MA/NA/RA, MB9AF156MA/NA/RA Data Sheet (Full Production)  DESCRIPTION The MB9A150RA Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, and Communication Interfaces (UART, CSIO, I2C). The products which are described in this data sheet are placed into TYPE8 product categories in "FM3 Family PERIPHERAL MANUAL". Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries. Publication Number MB9AF156RA_DS706-00047 Revision 2.0 Issue Date April 4, 2014 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. D a t a S h e e t  FEATURES • 32-bit ARM Cortex-M3 Core  Processor version: r2p1  Up to 40 MHz Frequency Operation  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management • On-chip Memories [Flash memory]  Dual operation Flash memory  Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously.  Main area: Up to 512Kbytes (Upto 496Kbytes upper bank + 16Kbytes lower bank)  Work area: 32Kbytes (lower bank)  Read cycle: 0 wait-cycle  Security function for code protection [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus or D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.  SRAM0: Up to 32 Kbytes  SRAM1: Up to 32 Kbytes • External Bus Interface  Supports SRAM, NOR NAND Flash memory device  Up to 8 chip selects  8/16-bit Data width  Up to 25-bit Address bit  Maximum area size : Up to 256 Mbytes  Supports Address/Data multiplex  Supports external RDY function • Multi-function Serial Interface (Max 16channels)  16 channels with 16steps×9-bit FIFO  Operation mode is selectable from the followings for each channel.  UART  CSIO  I2C [UART]  Full-duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4)  Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO]  Full-duplex double buffer  Built-in dedicated baud rate generator  Overrun error detection function available 2 [I C] Standard-mode (Max 100kbps) / Fast-mode (Max 400kbps) supported 4 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t • DMA Controller (8channels) The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.        8 independently configured and operated channels Transfer can be started by software or request from the built-in peripherals Transfer address area: 32-bit (4 Gbytes) Transfer mode: Block transfer/Burst transfer/Demand transfer Transfer data type: byte/half-word/word Transfer block count: 1 to 16 Number of transfers: 1 to 65536 • A/D Converter (Max 24channels) [12-bit A/D Converter]  Successive Approximation type  Built-in 2units  Conversion time: 2.0μs @ 2.7V to 3.6V  Priority conversion available (priority at 2levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) • Base Timer (Max 16channels) Operation mode is selectable from the followings for each channel.     16-bit PWM timer 16-bit PPG timer 16/32-bit reload timer 16/32-bit PWC timer • General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.      Capable of pull-up control per pin Capable of reading pin level directly Built-in the port relocate function Up to 103 high-speed general-purpose I/O Ports@120pin Package Some ports are 5V tolerant I/O See " LIST OF PIN FUNCTIONS" and " I/O CIRCUIT TYPE" to confirm the corresponding pins. • Dual Timer (32/16-bit Down Counter) The Dual Timer consists of two programmable 32/16-bit down counters. Operation mode is selectable from the followings for each channel.  Free-running  Periodic (=Reload)  One-shot April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 3 D a t a S h e e t • Multi-function Timer The Multi-function timer is composed of the following blocks.       16-bit free-run timer × 3ch. Input capture × 4ch. Output compare × 6ch. A/D activation compare × 2ch. Waveform generator × 3ch. 16-bit PPG timer × 3ch. The following function can be used to achieve the motor control.       PWM signal output function DC chopper waveform output function Dead time function Input capture function A/D convertor activate function DTIF (Motor emergency stop) interrupt function • Quadrature Position/Revolution Counter (QPRC) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use as the up/down counter.     The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. 16-bit position counter 16-bit revolution counter Two 16-bit compare registers • HDMI-CEC/Remote Control Reception (Up to 2channels)  HDMI-CEC transmission  Header block automatic transmission by judging Signal free  Generating status interrupt by detecting Arbitration lost  Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data  Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)  HDMI-CEC reception  Automatic ACK reply function available  Line error detection function available  Remote control reception  4 bytes reception buffer  Repeat code detection function available • Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.  The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available. • Watch Counter The Watch counter is used for wake up from sleep and timer mode. Interval timer: up to 64s (Max) @ Sub Clock : 32.768 kHz 4 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t • External Interrupt Controller Unit  Up to 24 external interrupt input pins  Include one non-maskable interrupt (NMI) input pin • Watchdog Timer (2channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. The "Hardware" watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the "Hardware" watchdog is active in any low-power consumption modes except RTC, STOP, Deep standby RTC and Deep standby STOP modes. • CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  CCITT CRC16 Generator Polynomial: 0x1021  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 • Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).      Main Clock Sub Clock Built-in high-speed CR Clock Built-in low-speed CR Clock Main PLL Clock : 4 MHz to 48 MHz : 32.768 kHz : 4 MHz : 100 kHz [Resets]  Reset requests from INITX pin  Power-on reset  Software reset  Watchdog timers reset  Low-voltage detection reset  Clock Super Visor reset • Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.  If external clock failure (clock stop) is detected, reset is asserted.  If external frequency anomaly is detected, interrupt or reset is asserted. • Low-Voltage Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 5 D a t a S h e e t • Low-Power Consumption Mode Six low-power consumption modes supported.       SLEEP TIMER RTC STOP Deep standby RTC (selectable between keeping the value of RAM and not) Deep standby STOP (selectable between keeping the value of RAM and not) • Debug  Serial Wire JTAG Debug Port (SWJ-DP)  Embedded Trace Macrocells (ETM).* *: MB9AF154MA, F155MA and F156MA support only SWJ-DP. • Unique ID Unique value of the device (41-bit) is set. • Power Supply Wide range voltage: VCC = 1.65V to 3.6V 6 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t  PRODUCT LINEUP • Memory size Product name On-chip Flash memory On-chip SRAM MB9AF154MA/NA/RA MB9AF155MA/NA/RA MB9AF156MA/NA/RA Main area 256 Kbytes 384 Kbytes 512 Kbytes Work area 32 Kbytes 32 Kbytes 32 Kbytes SRAM0 SRAM1 Total 16 Kbytes 16 Kbytes 32 Kbytes 24 Kbytes 24 Kbytes 48 Kbytes 32 Kbytes 32 Kbytes 64 Kbytes April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 7 D a t a S h e e t  Function Product name Pin count MB9AF154MA MB9AF155MA MB9AF156MA 80/96 CPU Freq. Power supply voltage range DMAC External Bus Interface Multi-function Serial Interface (UART/CSIO/I2C) 100/112 Cortex-M3 40 MHz 1.65V to 3.6V 8ch. Addr: 21-bit (Max) Addr: 25-bit (Max) R/W R/W Data: 8-bit (Max) Data: 8/16-bit (Max) CS: CS: 4 (Max) 8 (Max) Support: SRAM, Support: SRAM, NOR Flash memory NOR Flash memory 10ch. (Max) Enabled channels : ch.0 to ch.7, ch.10, ch.11 Base Timer (PWC/Reload timer/PWM/PPG) A/D activation 2ch. compare Input capture 4ch. Free-run timer 3ch. MFTimer Output compare 6ch. Waveform 3ch. generator PPG 3ch. QPRC Dual Timer HDMI-CEC/ Remote Control Reception Real-Time Clock Watch Counter CRC Accelerator Watchdog timer External Interrupts MB9AF154NA MB9AF155NA MB9AF156NA 14ch. (Max) Enabled channels : ch.0 to ch.13 MB9AF154RA MB9AF155RA MB9AF156RA 120 Addr: 25-bit (Max) R/W Data: 8/16-bit (Max) CS: 8 (Max) Support: SRAM, NOR Flash memory, NAND Flash memory 16ch. (Max) Enabled channels : ch.0 to ch.15 16ch. (Max) 1 unit (Max) 2ch. (Max) 1 unit 2ch. (Max) 1 unit 1 unit Yes 1ch. (SW) + 1ch. (HW) 23pins (Max) + NMI × 1 66pins (Max) 17ch. (2 units) 24pins (Max) + NMI × 1 I/O ports 83pins (Max) 103pins (Max) 12-bit A/D converter 24ch. (2 units) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2ch. High-speed 4 MHz Built-in CR Low-speed 100 kHz Debug Function SWJ-DP SWJ-DP/ETM Unique ID Yes Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See " ELECTRICAL CHARACTERISTICS 4.AC Characteristics (3)Built-in CR Oscillation Characteristics" for accuracy of built-in CR. 8 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t  PACKAGES Product name Package LQFP: FPT-80P-M37 (0.5mm pitch) BGA: BGA-96P-M07 (0.5mm pitch) LQFP: FPT-100P-M23 (0.5mm pitch) BGA: BGA-112P-M04 (0.8mm pitch) LQFP: FPT-120P-M37 (0.5mm pitch)  : Supported MB9AF154MA MB9AF155MA MB9AF156MA MB9AF154NA MB9AF155NA MB9AF156NA MB9AF154RA MB9AF155RA MB9AF156RA   -   -  Note: See "PACKAGE DIMENSIONS" for detailed information on each package. April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 9 D a t a S h e e t  PIN ASSIGNMENT • FPT-120P-M37 VCC 91 92 P02/TDI/SOT8_0/TIOB14_2/MCSX6_0 P00/TRSTX/SCK8_0/TIOA14_2/MCSX7_0 93 P04/TDO/SWO P03/TMS/SWDIO P05/AN20/TRACED0/SIN8_0/SIN4_2/TIOA5_2/INT00_1/MCSX5_0 P06/AN21/TRACED1/SOT4_2/TIOB5_2/INT01_1/MCSX4_0 P07/AN22/ADTG_0/TRACED2/SCK4_2/INT23_1/MCLKOUT_0 P08/AN23/TRACED3/CTS4_2/TIOA0_2/INT16_0/MCSX3_0 P09/TRACECLK/RTS4_2/TIOB0_2/INT17_0/MCSX2_0 P0A/SIN4_0/INT00_2/WKUP5/MCSX1_0 P0B/SOT4_0/TIOB6_1/INT18_0/CEC0_1/MCSX0_0 P0C/SCK4_0/TIOA6_1/INT19_0/MALE_0 P0D/RTS4_0/TIOA3_2/INT20_0/MDQM0_0 P0E/CTS4_0/TIOB3_2/INT21_0/MDQM1_0 P0F/NMIX/CROUT_1/RTCCO_0/SUBO UT_0/WKUP0 P68/SCK3_0/TIOB7_2/INT12_2 P01/TCK/SWCLK 94 95 96 97 98 99 100 101 102 103 104 105 106 P64/SOT5_1/TIOA7_0/INT10_2 112 P67/SOT3_0/TIOA7_2/INT22_0 P63/SIN5_1/TIOB15_1/INT03_0/MWEX_0 113 107 P62/ADTG_3/SCK5_0/TIOA15_1/INT07_1/MOEX_0 114 P66/SIN3_0/TIOA12_2/INT11_2 P61/SOT5_0/TIOB2_2 115 108 P60/SIN5_0/IGTRG_1/TIOA2_2/INT15_1/WKUP3/CEC1_0/MRDY_0 116 P65/SCK5_1/TIOB7_0/TIOB12_2/INT23_0 VCC 117 109 P80/TIOB15_0/INT16_1 118 110 P81/TIOA15_0/INT17_1 119 111 VSS 120 (TOP VIEW) VCC 1 90 VSS P50/SIN3_1/AIN0_2/TIOB8_0/INT 00_0/MADAT A00_0 2 89 P20/AN19/CROUT _0/AIN1_1/TIOA10_2/INT 05_0/MAD24_0 P51/SOT 3_1/BIN0_2/TIOB9_0/INT 01_0/MADAT A01_0 3 88 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT 06_1/WKUP2 P52/SCK3_1/ZIN0_2/TIOB10_0/INT 02_0/MADAT A02_0 4 87 P22/AN17/SOT 0_0/ZIN1_1/TIOB7_1 P53/SIN6_0/TIOB11_0/TIOA1_2/INT 07_2/MADAT A03_0 5 86 P23/AN16/SCK0_0/RT O00_1/TIOA7_1 P54/SOT 6_0/TIOB12_0/TIOB1_2/INT 18_1/MADAT A04_0 6 85 P24/SIN2_1/RT O01_1/TIOB14_1/INT 01_2 P55/ADT G_1/SCK6_0/TIOB13_0/INT 19_1/MADAT A05_0 7 84 P25/SOT 2_1/RT O02_1/TIOA14_1/TIOB11_2 P56/SIN1_0/TIOA8_0/INT 08_2/CEC1_1/M ADAT A06_0 8 83 P26/SCK2_1/RT O03_1/TIOA11_2 P57/SOT 1_0/TIOA9_0/MADAT A07_0 9 82 P27/SIN15_0/RT O04_1/TIOA6_2/INT 02_2 P58/SCK1_0/TIOA10_0/M ADAT A08_0 10 81 P28/ADT G_4/SOT 15_0/RT O05_1/TIOB6_2 P59/SIN7_0/TIOA11_0/INT 09_2/MADAT A09_0 11 80 P1F/AN15/ADT G_5/SCK15_0/FRCK0_1/TIOB9_2/MAD23_0 P5A/SOT 7_0/TIOA12_0/INT 16_2/MADAT A10_0 12 79 P1E/AN14/RT S4_1/DT TI0X_1/TIOA9_2/INT 23_2/MAD22_0 P5B/SCK7_0/TIOA13_0/INT 17_2/MADAT A11_0 13 78 P1D/AN13/CT S4_1/IC03_1/TIOA13_1/INT 22_2/MAD21_0 77 P1C/AN12/SCK4_1/IC02_1/TIOA12_1/INT 21_2/M AD20_0 LQFP - 120 P30/AIN0_0/TIOB0_1/TIOA13_2/INT 03_2/WKUP4/MADAT A12_0 14 P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT 04_2/MADAT A13_0 15 76 P32/SOT 6_1/ZIN0_0/TIOB2_1/INT 05_2/MADAT A14_0 16 75 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT 05_1/MAD18_0 P33/ADT G_6/SIN9_0/SIN6_1/TIOB3_1/INT 04_0/MADAT A15_0 17 74 P19/AN09/SCK2_2/TIOA9_1/MAD17_0 P34/SOT 9_0/FRCK0_0/TIOB4_1/TIOA15_2/MNALE_0 18 73 P18/AN08/SOT 2_2/TIOA8_1/MAD16_0 P35/SCK9_0/IC03_0/TIOB5_1/TIOB15_2/INT 08_1/MNCLE_0 P1B/AN11/SOT 4_1/IC01_1/TIOA11_1/INT 20_2/MAD19_0 19 72 AVSS P36/SIN5_2/IC02_0/TIOB14_0/INT 09_1/MNWEX_0 20 71 AVRH P37/SOT 5_2/IC01_0/TIOA14_0/INT 10_1/MNREX_0 21 70 AVCC P38/SCK5_2/IC00_0/TIOA8_2/INT 11_1 22 69 P17/AN07/SIN2_2/INT 04_1/MAD15_0 60 59 VSS 57 58 PE3/X1 MD0 PE2/X0 56 55 PE0/MD1 P74/SCK2_0 54 53 P73/SOT2_0/TIOB6_0/INT15_2 52 P72/SIN2_0/TIOA6_0/INT14_2 51 P71/SCK14_0/TIOB4_2/INT13_2 50 P70/SOT14_0/TIOA4_2 P4E/SIN14_0/SIN7_1/ZIN1_2/TIOB5_0/INT06_2/MAD08_0 49 48 P4D/SOT7_1/BIN1_2/TIOB4_0/INT13_0/MAD07_0 47 P4C/SCK7_1/AIN1_2/TIOB3_0/INT12_0/CEC0_0/MAD06_0 46 P4B/IGTRG_0/ZIN0_1/TIOB2_0/INT22_1/MAD05_0 45 P4A/SCK3_2/BIN0_1/TIOB1_0/INT21_1/MAD04_0 44 P49/SOT3_2/AIN0_1/TIOB0_0/INT20_1/MAD03_0 INITX P48/SIN3_2/INT14_1/MAD02_0 P47/X1A 43 VCC 42 61 41 30 40 P10/AN00 VSS P46/X0A 62 39 29 VSS VCC P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT 02_1/WKUP1/MAD09_0 P3F/RT O05_0/TIOA5_1 38 63 C 28 P45/SCK13_0/TIOA5_0/INT11_0/MAD01_0 P12/AN02/SOT 1_1/IC00_2/TIOB9_1/MAD10_0 P3E/SCK11_0/RT O04_0/TIOA4_1/INT 19_2 37 64 36 27 P44/SOT13_0/TIOA4_0/INT10_0/MAD00_0 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RT CCO_1/SUBOUT _1/MAD11_0 P3D/SOT 11_0/RT O03_0/TIOA3_1 35 65 P43/ADTG_7/SIN13_0/TIOA3_0/INT09_0 26 34 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT 03_1/MAD12_0 P3C/SIN11_0/RT O02_0/TIOA2_1/INT 18_2 P42/SCK12_0/TIOA2_0/INT08_0 66 33 25 32 P15/AN05/SOT 0_1/IC03_2/TIOB12_1/INT 14_0/MAD13_0 P3B/SCK10_0/RT O01_0/TIOA1_1 31 P16/AN06/SCK0_1/TIOB13_1/INT 15_0/MAD14_0 67 VCC 68 24 P40/SIN12_0/TIOA0_0/INT12_1 23 P41/SOT12_0/TIOA1_0/INT13_1 P39/ADT G_2/SIN10_0/DT T I0X_0/TIOB8_2/INT 06_0 P3A/SOT 10_0/RT O00_0/TIOA0_1/INT 07_0/RT CCO_2/SUBOUT _2 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 1 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t • FPT-100P-M23 P00/TRSTX/SCK8_0/TIOA14_2/MCSX7_0 P01/TCK/SWCLK P02/TDI/SOT8_0/TIOB14_2/MCSX6_0 P04/TDO/SWO P03/TMS/SWDIO P06/AN21/TRACED1/SOT4_2/TIOB5_2/INT01_1/MCSX4_0 P05/AN20/TRACED0/SIN8_0/SIN4_2/TIOA5_2/INT00_1/MCSX5_0 P07/AN22/ADTG_0/TRACED2/SCK4_2/INT23_1/MCLKOUT_0 P08/AN23/TRACED3/CTS4_2/TIOA0_2/INT16_0/MCSX3_0 P09/TRACECLK/RTS4_2/TIOB0_2/INT17_0/MCSX2_0 VCC 76 77 78 79 80 81 82 83 84 P0A/SIN4_0/INT00_2/WKUP5/MCSX1_0 P0E/CTS4_0/TIOB3_2/INT21_0/MDQM1_0 91 85 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 92 P0B/SOT4_0/TIOB6_1/INT18_0/CEC0_1/MCSX0_0 P63/TIOB15_1/INT03_0/MWEX_0 93 86 P62/ADTG_3/SCK5_0/TIOA15_1/INT07_1/MOEX_0 94 P0C/SCK4_0/TIOA6_1/INT19_0/MALE_0 P61/SOT5_0/TIOB2_2 95 87 P60/SIN5_0/IGTRG_1/TIOA2_2/INT15_1/WKUP3/CEC1_0/MRDY_0 96 P0D/RTS4_0/TIOA3_2/INT20_0/MDQM0_0 VCC 97 88 P80/TIOB15_0/INT16_1 98 89 P81/TIOA15_0/INT17_1 99 90 VSS 100 (TOP VIEW) VCC 1 75 VSS P50/SIN3_1/AIN0_2/TIOB8_0/INT 00_0/MADAT A00_0 2 74 P20/AN19/CROUT_0/AIN1_1/TIOA10_2/INT05_0/MAD24_0 3 73 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2 P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADAT A02_0 4 72 P22/AN17/SOT 0_0/ZIN1_1/TIOB7_1 P51/SOT 3_1/BIN0_2/TIOB9_0/INT01_0/MADAT A01_0 P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADAT A03_0 5 71 P23/AN16/SCK0_0/TIOA7_1 P54/SOT 6_0/TIOB12_0/TIOB1_2/INT18_1/MADAT A04_0 6 70 P1F/AN15/ADT G_5/FRCK0_1/TIOB9_2/MAD23_0 P55/ADT G_1/SCK6_0/TIOB13_0/INT19_1/MADAT A05_0 7 69 P1E/AN14/RT S4_1/DTTI0X_1/TIOA9_2/INT23_2/MAD22_0 8 68 P1D/AN13/CT S4_1/IC03_1/TIOA13_1/INT22_2/MAD21_0 9 67 P1C/AN12/SCK4_1/IC02_1/TIOA12_1/INT21_2/MAD20_0 10 66 P1B/AN11/SOT 4_1/IC01_1/TIOA11_1/INT 20_2/MAD19_0 P32/SOT 6_1/ZIN0_0/TIOB2_1/INT05_2/MADAT A09_0 11 65 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT05_1/MAD18_0 P33/ADT G_6/SIN9_0/SIN6_1/TIOB3_1/INT 04_0/MADAT A10_0 12 64 P19/AN09/SCK2_2/TIOA9_1/MAD17_0 P34/SOT 9_0/FRCK0_0/TIOB4_1/TIOA15_2/MADAT A11_0 13 63 P18/AN08/SOT 2_2/TIOA8_1/MAD16_0 P56/INT08_2/CEC1_1/MADAT A06_0 P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADAT A07_0 P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT04_2/MADAT A08_0 LQFP - 100 14 62 AVSS P36/SIN5_2/IC02_0/TIOB14_0/INT09_1/MADAT A13_0 15 61 AVRH P37/SOT 5_2/IC01_0/TIOA14_0/INT10_1/MADAT A14_0 16 60 AVCC P38/SCK5_2/IC00_0/TIOA8_2/INT11_1/MADAT A15_0 17 59 P17/AN07/SIN2_2/INT 04_1/MAD15_0 P39/ADT G_2/SIN10_0/DTTI0X_0/TIOB8_2/INT06_0 18 58 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0 P3A/SOT 10_0/RT O00_0/TIOA0_1/INT 07_0/RTCCO_2/SUBOUT _2 P35/SCK9_0/IC03_0/TIOB5_1/TIOB15_2/INT08_1/MADAT A12_0 50 49 VSS PE3/X1 48 47 46 MD0 PE2/X0 PE0/MD1 45 44 P4E/SIN7_1/ZIN1_2/TIOB5_0/INT06_2/MAD08_0 43 P4D/SOT7_1/BIN1_2/TIOB4_0/INT13_0/MAD07_0 42 P4C/SCK7_1/AIN1_2/TIOB3_0/INT12_0/CEC0_0/MAD06_0 P4B/IGTRG_0/ZIN0_1/TIOB2_0/INT22_1/MAD05_0 41 40 P4A/SCK3_2/BIN0_1/TIOB1_0/INT21_1/MAD04_0 39 38 P48/SIN3_2/INT14_1/MAD02_0 P49/SOT3_2/AIN0_1/TIOB0_0/INT20_1/MAD03_0 INITX 37 35 P46/X0A 36 34 P47/X1A 33 C VSS VCC VCC 32 51 P45/SCK13_0/TIOA5_0/INT11_0/MAD01_0 25 31 P10/AN00 VSS P43/ADTG_7/SIN13_0/TIOA3_0/INT09_0 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0 52 P44/SOT13_0/TIOA4_0/INT10_0/MAD00_0 53 24 30 23 P3F/RT O05_0/TIOA5_1 29 P12/AN02/SOT 1_1/IC00_2/TIOB9_1/MAD10_0 P3E/SCK11_0/RT O04_0/TIOA4_1/INT19_2 P42/SCK12_0/TIOA2_0/INT08_0 54 28 22 P41/SOT12_0/TIOA1_0/INT13_1 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT_1/MAD11_0 P3D/SOT 11_0/RT O03_0/TIOA3_1 27 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0 55 26 P15/AN05/SOT 0_1/IC03_2/TIOB12_1/INT 14_0/MAD13_0 56 21 VCC 57 20 P40/SIN12_0/TIOA0_0/INT12_1 19 P3B/SCK10_0/RT O01_0/TIOA1_1 P3C/SIN11_0/RT O02_0/TIOA2_1/INT18_2 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 11 D a t a S h e e t • FPT-80P-M37 P02/TDI/TIOB14_2/MCSX6_0 P01/TCK/SWCLK P03/TMS/SWDIO P04/TDO/SWO P07/AN22/ADTG_0/INT23_1/MCLKOUT_0 P0A/SIN4_0/INT00_2/WKUP5/MCSX1_0 P0B/SOT4_0/TIOB6_1/INT18_0/CEC0_1/MCSX0_0 P00/TRSTX/TIOA14 2/MCSX7 0 61 62 63 64 65 66 67 P0D/RTS4_0/TIOA3_2/INT20_0/MDQM0_0 P0E/CTS4_0/TIOB3_2/INT21_0/MDQM1_0 P0C/SCK4_0/TIOA6_1/INT19_0/MALE_0 68 69 P62/ADTG_3/SCK5_0/TIOA15_1/INT07_1/MOEX_0 74 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P61/SOT5_0/TIOB2_2 75 70 P60/SIN5_0/IGTRG_1/TIOA2_2/INT15_1/WKUP3/CEC1_0/MRDY_0 76 P63/TIOB15_1/INT03_0/MWEX_0 VCC 77 71 P80/TIOB15_0/INT16_1 78 72 P81/TIOA15_0/INT17_1 79 73 VSS 80 (TOP VIEW) VCC 1 60 P20/AN19/CROUT _0/AIN1_1/TIOA10_2/INT 05_0/MAD24_0 P50/SIN3_1/AIN0_2/TIOB8_0/INT00_0/MADATA00_0 2 59 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2 P51/SOT 3_1/BIN0_2/TIOB9_0/INT01_0/MADATA01_0 3 58 P22/AN17/SOT 0_0/ZIN1_1/TIOB7_1 P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADATA02_0 4 57 P23/AN16/SCK0_0/TIOA7_1 P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADATA03_0 5 56 P1B/AN11/SOT 4_1/IC01_1/TIOA11_1/INT 20_2/MAD19_0 P54/SOT 6_0/TIOB12_0/TIOB1_2/INT18_1/MADATA04_0 6 55 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT 05_1/MAD18_0 P55/ADT G_1/SCK6_0/TIOB13_0/INT19_1/MADATA05_0 7 54 P19/AN09/SCK2_2/TIOA9_1/MAD17_0 P56/INT08_2/CEC1_1/MADAT A06_0 8 53 P18/AN08/SOT 2_2/TIOA8_1/MAD16_0 P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADATA07_0 9 52 AVSS P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT 04_2/MADATA08_0 10 51 AVRH P32/SOT 6_1/ZIN0_0/TIOB2_1/INT05_2/MADAT A09_0 11 50 AVCC P33/ADT G_6/SIN6_1/TIOB3_1/INT04_0/MADATA10_0 12 49 P17/AN07/SIN2_2/INT04_1/MAD15_0 P39/ADT G_2/SIN10_0/DTTI0X_0/INT06_0 13 48 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0 P3A/SOT10_0/RTO00_0/TIOA0_1/INT07_0/RTCCO_2/SUBOUT _2 14 47 P15/AN05/SOT 0_1/IC03_2/TIOB12_1/INT14_0/MAD13_0 P3B/SCK10_0/RT O01_0/TIOA1_1 15 46 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0 P3C/SIN11_0/RT O02_0/TIOA2_1/INT18_2 16 45 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT _1/MAD11_0 P3D/SOT 11_0/RTO03_0/TIOA3_1 17 44 P12/AN02/SOT 1_1/IC00_2/TIOB9_1/MAD10_0 P3E/SCK11_0/RTO04_0/TIOA4_1/INT19_2 18 43 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0 P3F/RTO05_0/TIOA5_1 19 42 P10/AN00 VSS 20 41 VCC 40 VSS 39 PE3/X1 PE2/X0 38 37 MD0 PE0/MD1 36 35 P4E/SIN7_1/ZIN1_2/TIOB5_0/INT06_2/MAD08_0 34 P4D/SOT7_1/BIN1_2/TIOB4_0/INT13_0/MAD07_0 33 P4C/SCK7_1/AIN1_2/TIOB3_0/INT12_0/CEC0_0/MAD06_0 32 28 INITX P4A/SCK3_2/BIN0_1/TIOB1_0/INT21_1/MAD04_0 27 P47/X1A P4B/IGTRG_0/ZIN0_1/TIOB2_0/INT22_1/MAD05_0 26 P46/X0A 31 25 VCC P49/SOT3_2/AIN0_1/TIOB0_0/INT20_1/MAD03_0 24 VSS 30 23 C 29 22 P45/TIOA5_0/INT11_0/MAD01_0 P48/SIN3_2/INT14_1/MAD02_0 21 P44/TIOA4_0/INT10_0/MAD00_0 LQFP - 80 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 1 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t • BGA-112P-M04 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A VSS P81 P80 VCC P0E P0B P07 TMS/ SWDIO TRSTX VCC VSS B VCC VSS P52 P61 P0C P08 TDO/ TCK/ SWCLK VSS TDI C P50 P51 VSS P60 P62 P0D P09 P05 VSS P20 P21 D P53 P54 P55 VSS P56 P63 P0A VSS P06 P23 AN15 E P30 P31 P32 P33 Index P22 AN14 AN12 AN11 F P34 P35 P36 P39 AN13 AN10 AN09 AVRH G P37 P38 P3A P3D AN08 AN07 AN06 AVSS H P3B P3C P3E VSS P44 P4C AN05 VSS AN04 AN03 AVCC J VCC P3F VSS P40 P43 P49 P4D AN02 VSS AN01 AN00 K VCC VSS X1A INITX P42 P48 P4B P4E MD1 VSS VCC L VSS C X0A VSS P41 P45 P4A MD0 X0 X1 VSS P0F SWO The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 13 D a t a S h e e t • BGA-96P-M07 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A VSS P81 P80 VCC VSS P0F VSS P07 TMS/ SWDIO TRSTX VSS B VCC VSS P52 P61 P63 P0D P0C TDO/ TCK/ SWCLK VSS TDI C P50 P51 VSS P60 P0E P0B VSS P20 P21 D P53 P54 P55 Index P22 P23 VSS E P56 P30 P31 AN11 AN10 AN09 F VSS VSS VSS AN08 AN07 AVRH G P32 P33 P39 AN06 AN05 AVSS H P3A P3B P3C AN04 AN03 AVCC J P3D P3E VSS P3F P48 P4A P4D AN02 VSS AN01 AN00 K VCC VSS X1A INITX P45 P49 P4C P4E MD1 VSS VCC L VSS C X0A VSS P44 VSS P4B MD0 X0 X1 VSS P62 SWO P0A The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 1 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t  LIST OF PIN FUNCTION • List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQFP-120 LQFP-100 BGA-112 1 1 B1 LQFP-80 1 BGA-96 B1 2 2 C1 2 C1 3 3 C2 3 C2 4 4 B3 4 B3 5 5 D1 5 D1 6 6 D2 6 D2 7 7 D3 7 D3 April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin Name VCC P50 SIN3_1 AIN0_2 TIOB8_0 INT00_0 MADATA00_0 P51 SOT3_1 (SDA3_1) BIN0_2 TIOB9_0 INT01_0 MADATA01_0 P52 SCK3_1 (SCL3_1) ZIN0_2 TIOB10_0 INT02_0 MADATA02_0 P53 SIN6_0 TIOB11_0 TIOA1_2 INT07_2 MADATA03_0 P54 SOT6_0 (SDA6_0) TIOB12_0 TIOB1_2 INT18_1 MADATA04_0 P55 ADTG_1 SCK6_0 (SCL6_0) TIOB13_0 INT19_1 MADATA05_0 I/O circuit Pin state type type - E K E K E K E K E K E K 15 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 8 D5 8 BGA-96 E1 8 1 - - - - 9 - - - - 10 - - - - 11 - - - - 12 - - - - 13 - - - - 14 - - - - - 9 E1 9 E2 Pin Name P56 INT08_2 CEC1_1 MADATA06_0 SIN1_0 TIOA8_0 P57 SOT1_0 (SDA1_0) TIOA9_0 MADATA07_0 P58 SCK1_0 (SCL1_0) TIOA10_0 MADATA08_0 P59 SIN7_0 TIOA11_0 INT09_2 MADATA09_0 P5A SOT7_0 (SDA7_0) TIOA12_0 INT16_2 MADATA10_0 P5B SCK7_0 (SCL7_0) TIOA13_0 INT17_2 MADATA11_0 P30 AIN0_0 TIOB0_1 TIOA13_2 INT03_2 WKUP4 MADATA12_0 P30 AIN0_0 TIOB0_1 TIOA13_2 INT03_2 WKUP4 MADATA07_0 I/O circuit Pin state type type H* R H* J H* J E K E K E K E S E S MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 15 - - - - - 10 E2 10 E3 16 - - - - - 11 E3 11 G1 17 - - - - - 12 E4 12 G2 - - April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin Name P31 SCK6_1 (SCL6_1) BIN0_0 TIOB1_1 TIOB13_2 INT04_2 MADATA13_0 P31 SCK6_1 (SCL6_1) BIN0_0 TIOB1_1 TIOB13_2 INT04_2 MADATA08_0 P32 SOT6_1 (SDA6_1) ZIN0_0 TIOB2_1 INT05_2 MADATA14_0 P32 SOT6_1 (SDA6_1) ZIN0_0 TIOB2_1 INT05_2 MADATA09_0 P33 ADTG_6 SIN9_0 SIN6_1 TIOB3_1 INT04_0 MADATA15_0 P33 ADTG_6 SIN6_1 TIOB3_1 INT04_0 MADATA10_0 SIN9_0 I/O circuit type Pin state type E K E K E K E K E K E K 17 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 1 18 - - - - - 13 F1 - - 19 - - - - - 14 F2 - - 20 - - - - - 15 F3 - - - - - - F1 F2 F3 Pin Name P34 SOT9_0 (SDA9_0) FRCK0_0 TIOB4_1 TIOA15_2 MNALE_0 P34 SOT9_0 (SDA9_0) FRCK0_0 TIOB4_1 TIOA15_2 MADATA11_0 P35 SCK9_0 (SCL9_0) IC03_0 TIOB5_1 TIOB15_2 INT08_1 MNCLE_0 P35 SCK9_0 (SCL9_0) IC03_0 TIOB5_1 TIOB15_2 INT08_1 MADATA12_0 P36 SIN5_2 IC02_0 TIOB14_0 INT09_1 MNWEX_0 P36 SIN5_2 IC02_0 TIOB14_0 INT09_1 MADATA13_0 VSS VSS VSS I/O circuit Pin state type type E J E J E K E K E K E K - MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 21 - - - - - 16 G1 - - 17 G2 - - 18 F4 13 G3 - - 22 - 23 24 19 G3 14 H1 25 20 H1 15 H2 26 21 H2 16 H3 April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin Name P37 SOT5_2 (SDA5_2) IC01_0 TIOA14_0 INT10_1 MNREX_0 P37 SOT5_2 (SDA5_2) IC01_0 TIOA14_0 INT10_1 MADATA14_0 P38 SCK5_2 (SCL5_2) IC00_0 TIOA08_2 INT11_1 MADATA15_0 P39 ADTG_2 SIN10_0 DTTI0X_0 INT06_0 TIOB8_2 P3A SOT10_0 (SDA10_0) RTO00_0 TIOA0_1 INT07_0 RTCCO_2 SUBOUT_2 P3B SCK10_0 (SCL10_0) RTO01_0 TIOA1_1 P3C SIN11_0 RTO02_0 TIOA2_1 INT18_2 I/O circuit Pin state type type E K E K E K E K E K E J E K 19 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 27 22 G4 17 J1 - - B2 - B2 28 23 H3 18 J2 29 24 J2 19 J4 30 31 25 26 L1 J1 20 - L1 - 32 27 J4 - - 33 28 L5 - - 34 29 K5 - - 35 30 J5 - - 21 L5 - - 36 37 31 32 H5 21 L5 22 - K5 - L6 22 2 BGA-96 K5 Pin Name P3D SOT11_0 (SDA11_0) RTO03_0 TIOA3_1 VSS P3E SCK11_0 (SCL11_0) RTO04_0 TIOA4_1 INT19_2 P3F RTO05_0 TIOA5_1 VSS VCC P40 SIN12_0 TIOA0_0 INT12_1 P41 SOT12_0 (SDA12_0) TIOA1_0 INT13_1 P42 SCK12_0 (SCL12_0) TIOA2_0 INT08_0 P43 ADTG_7 SIN13_0 TIOA3_0 INT09_0 P44 SOT13_0 (SDA13_0) TIOA4_0 INT10_0 MAD00_0 P45 SCK13_0 TIOA5_0 INT11_0 MAD01_0 I/O circuit Pin state type type E J - E K E J - E K E K E K E K E K E K MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 K2 K2 J3 J3 H4 L6 38 33 L2 23 L2 39 34 L4 24 L4 40 35 K1 25 K1 41 36 L3 26 L3 42 37 K3 27 K3 43 38 K4 28 K4 44 39 K6 29 J5 45 40 J6 30 K6 46 41 L7 31 J6 47 42 K7 32 L7 48 43 H6 33 K7 April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin Name VSS VSS VSS VSS C VSS VCC P46 X0A P47 X1A INITX P48 SIN3_2 INT14_1 MAD02_0 P49 SOT3_2 (SDA3_2) AIN0_1 TIOB0_0 INT20_1 MAD03_0 P4A SCK3_2 (SCL3_2) BIN0_1 TIOB1_0 INT21_1 MAD04_0 P4B IGTRG_0 ZIN0_1 TIOB2_0 INT22_1 MAD05_0 P4C SCK7_1 (SCL7_1) AIN1_2 TIOB3_0 INT12_0 CEC0_0 MAD06_0 I/O circuit type Pin state type - D F D G B C E K E K E K E K H* R 21 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 49 BGA-96 44 J7 34 J7 45 K8 35 K8 - - - - 51 - - - - 52 - - - - 53 - - - - 54 - - - - 55 - - - - 56 46 K9 36 K9 57 47 L8 37 L8 58 48 L9 38 L9 59 49 L10 39 L10 60 61 50 51 L11 K11 40 41 L11 K11 62 52 J11 42 J11 50 2 LQFP-80 Pin Name P4D SOT7_1 (SDA7_1) BIN1_2 TIOB4_0 INT13_0 MAD07_0 P4E SIN7_1 ZIN1_2 TIOB5_0 INT06_2 MAD08_0 SIN14_0 P70 SOT14_0 (SDA14_0) TIOA4_2 P71 SCK14_0 (SCL14_0) TIOB4_2 INT13_2 P72 SIN2_0 TIOA6_0 INT14_2 P73 SOT2_0 (SDA2_0) TIOB6_0 INT15_2 P74 SCK2_0 (SCL2_0) MD1 PE0 MD0 X0 PE2 X1 PE3 VSS VCC P10 AN00 I/O circuit Pin state type type H* K H* K E J E K E K E K E J C E G D A A A B - F L MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 63 53 J10 43 J10 64 54 J8 44 J8 - - K10 J9 - K10 J9 65 55 H10 45 H10 66 56 H9 46 H9 67 57 H7 47 G10 April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin Name P11 AN01 SIN1_1 FRCK0_2 TIOB8_1 INT02_1 WKUP1 MAD09_0 P12 AN02 SOT1_1 (SDA1_1) IC00_2 TIOB9_1 MAD10_0 VSS VSS P13 AN03 SCK1_1 (SCL1_1) IC01_2 TIOB10_1 RTCCO_1 SUBOUT_1 MAD11_0 P14 AN04 SIN0_1 IC02_2 TIOB11_1 INT03_1 MAD12_0 P15 AN05 SOT0_1 (SDA0_1) IC03_2 TIOB12_1 INT14_0 MAD13_0 I/O circuit Pin state type type F P F L - F L F M F M 23 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 2 BGA-96 68 58 G10 48 G9 69 59 G9 49 F10 70 71 72 60 61 62 H11 F11 G11 50 51 52 H11 F11 G11 73 63 G8 53 F9 74 64 F10 54 E11 - - H8 - - 75 65 F9 55 E10 76 66 E11 56 E9 Pin Name P16 AN06 SCK0_1 (SCL0_1) TIOB13_1 INT15_0 MAD14_0 P17 AN07 SIN2_2 INT04_1 MAD15_0 AVCC AVRH AVSS P18 AN08 SOT2_2 (SDA2_2) TIOA8_1 MAD16_0 P19 AN09 SCK2_2 (SCL2_2) TIOA9_1 MAD17_0 VSS P1A AN10 SIN4_1 IC00_1 TIOA10_1 INT05_1 MAD18_0 P1B AN11 SOT4_1 (SDA4_1) IC01_1 TIOA11_1 INT20_2 MAD19_0 I/O circuit Pin state type type F M F M - F L F L - F M F M MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 77 67 E10 - - 78 68 F8 - - 79 69 E9 - - 70 D11 - - 80 - - - - - - B10 C9 - - B10 C9 D11 81 - - - - 82 - - - - April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin Name P1C AN12 SCK4_1 (SCL4_1) IC02_1 TIOA12_1 INT21_2 MAD20_0 P1D AN13 CTS4_1 IC03_1 TIOA13_1 INT22_2 MAD21_0 P1E AN14 RTS4_1 DTTI0X_1 TIOA9_2 INT23_2 MAD22_0 P1F AN15 ADTG_5 FRCK0_1 TIOB9_2 MAD23_0 SCK15_0 (SCL15_0) VSS VSS VSS P28 ADTG_4 SOT15_0 (SDA15_0) RTO05_1 TIOB6_2 P27 SIN15_0 RTO04_1 TIOA6_2 INT02_2 I/O circuit Pin state type type F M F M F M F L - E J E K 25 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 83 - - - - 84 - - - - 85 - - - - 71 D10 57 D10 - - - - 87 72 E8 58 D9 88 73 C11 59 C11 89 74 C10 60 C10 90 91 75 76 A11 A10 - A11 - 86 2 Pin Name P26 SCK2_1 (SCL2_1) RTO03_1 TIOA11_2 P25 SOT2_1 (SDA2_1) RTO02_1 TIOA14_1 TIOB11_2 P24 SIN2_1 RTO01_1 TIOB14_1 INT01_2 P23 AN16 SCK0_0 (SCL0_0) TIOA7_1 RTO00_1 P22 AN17 SOT0_0 (SDA0_0) ZIN1_1 TIOB7_1 P21 AN18 SIN0_0 BIN1_1 TIOB10_2 INT06_1 WKUP2 P20 AN19 CROUT_0 AIN1_1 TIOA10_2 INT05_0 MAD24_0 VSS VCC I/O circuit Pin state type type E J E J E K F L F L F P F M - MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 61 92 77 BGA-96 A10 A9 93 78 B9 94 79 B11 - - 62 B9 63 B11 - - 95 80 A8 64 A9 96 81 B8 65 B8 97 82 C8 - - - - D8 - - 98 83 D9 - - 66 A8 99 - 84 - A7 - April 4, 2014, MB9AF156RA_DS706-00047-2v0-E - - - A7 Pin Name P00 TRSTX TIOA14_2 MCSX7_0 SCK8_0 (SCL8_0) P01 TCK SWCLK P02 TDI TIOB14_2 MCSX6_0 SOT8_0 P03 TMS SWDIO P04 TDO SWO P05 AN20 TRACED0 SIN8_0 SIN4_2 TIOA5_2 INT00_1 MCSX5_0 VSS P06 AN21 TRACED1 SOT4_2 (SDA4_2) TIOB5_2 INT01_1 MCSX4_0 P07 AN22 ADTG_0 MCLKOUT_0 INT23_1 TRACED2 SCK4_2 (SCL4_2) VSS I/O circuit Pin state type type E I E I E I E I E I F O - F O F O - 27 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 2 BGA-96 100 85 B7 - - 101 86 C7 - - 102 87 D7 67 C8 103 88 A6 68 C7 104 89 B6 69 B7 - - D4 C3 - C3 105 90 C6 70 B6 106 91 A5 71 C6 - - - - A5 Pin Name P08 AN23 TRACED3 CTS4_2 TIOA0_2 INT16_0 MCSX3_0 P09 TRACECLK RTS4_2 TIOB0_2 INT17_0 MCSX2_0 P0A SIN4_0 INT00_2 WKUP5 MCSX1_0 P0B SOT4_0 (SDA4_0) TIOB6_1 INT18_0 CEC0_1 MCSX0_0 P0C SCK4_0 (SCL4_0) TIOA6_1 INT19_0 MALE_0 VSS VSS P0D RTS4_0 TIOA3_2 INT20_0 MDQM0_0 P0E CTS4_0 TIOB3_2 INT21_0 MDQM1_0 VSS I/O circuit Pin state type type F O E N H* S H* R H* K - E K E K - MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 107 92 B5 72 A6 108 - - - - 109 - - - - 110 - - - - 111 - - - - 112 - - - - 93 D6 73 B5 - - - - 94 C5 74 C5 113 114 April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin Name P0F NMIX CROUT_1 RTCCO_0 SUBOUT_0 WKUP0 P68 SCK3_0 (SCL3_0) TIOB7_2 INT12_2 P67 SOT3_0 (SDA3_0) TIOA7_2 INT22_0 P66 SIN3_0 TIOA12_2 INT11_2 P65 SCK5_1 (SCL5_1) TIOB7_0 TIOB12_2 INT23_0 P64 SOT5_1 (SDA5_1) TIOA7_0 INT10_2 P63 TIOB15_1 INT03_0 MWEX_0 SIN5_1 P62 ADTG_3 SCK5_0 (SCL5_0) TIOA15_1 INT07_1 MOEX_0 I/O circuit Pin state type type E H E K E K E K E K E K E K E K 29 D a t a S h e e t Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 3 BGA-96 115 95 B4 75 B4 116 96 C4 76 C4 117 97 A4 77 A4 118 98 A3 78 A3 119 99 A2 79 A2 120 100 *: 5V tolerant I/O A1 80 A1 Pin Name P61 SOT5_0 (SDA5_0) TIOB2_2 P60 SIN5_0 IGTRG_1 TIOA2_2 INT15_1 WKUP3 CEC1_0 MRDY_0 VCC P80 TIOB15_0 INT16_1 P81 TIOA15_0 INT17_1 VSS I/O circuit Pin state type type E J H* Q E K E K - MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t • List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function ADC Pin name ADTG_0 ADTG_1 ADTG_2 ADTG_3 ADTG_4 ADTG_5 ADTG_6 ADTG_7 ADTG_8 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 Function description A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 99 84 A7 66 7 7 D3 7 23 18 F4 13 114 94 C5 74 81 80 70 D11 17 12 E4 12 35 30 J5 62 52 J11 42 63 53 J10 43 64 54 J8 44 65 55 H10 45 66 56 H9 46 67 57 H7 47 68 58 G10 48 69 59 G9 49 73 63 G8 53 74 64 F10 54 75 65 F9 55 76 66 E11 56 77 67 E10 78 68 F8 79 69 E9 80 70 D11 86 71 D10 57 87 72 E8 58 88 73 C11 59 89 74 C10 60 97 82 C8 98 83 D9 99 84 A7 66 100 85 B7 - BGA96 A8 D3 G3 C5 G2 J11 J10 J8 H10 H9 G10 G9 F10 F9 E11 E10 E9 D10 D9 C11 C10 A8 - 31 D a t a S h e e t Pin function Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 3 Pin name TIOA0_0 TIOA0_1 TIOA0_2 TIOB0_0 TIOB0_1 TIOB0_2 TIOA1_0 TIOA1_1 TIOA1_2 TIOB1_0 TIOB1_1 TIOB1_2 TIOA2_0 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 TIOA3_0 TIOA3_1 TIOA3_2 TIOB3_0 TIOB3_1 TIOB3_2 TIOA4_0 TIOA4_1 TIOA4_2 TIOB4_0 TIOB4_1 TIOB4_2 TIOA5_0 TIOA5_1 TIOA5_2 TIOB5_0 TIOB5_1 TIOB5_2 TIOA6_0 TIOA6_1 TIOA6_2 TIOB6_0 TIOB6_1 TIOB6_2 TIOA7_0 TIOA7_1 TIOA7_2 TIOB7_0 TIOB7_1 TIOB7_2 Function description Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 32 27 J4 24 19 G3 14 100 85 B7 45 40 J6 30 14 9 E1 9 101 86 C7 33 28 L5 25 20 H1 15 5 5 D1 5 46 41 L7 31 15 10 E2 10 6 6 D2 6 34 29 K5 26 21 H2 16 116 96 C4 76 47 42 K7 32 16 11 E3 11 115 95 B4 75 35 30 J5 27 22 G4 17 105 90 C6 70 48 43 H6 33 17 12 E4 12 106 91 A5 71 36 31 H5 21 28 23 H3 18 51 49 44 J7 34 18 13 F1 52 37 32 L6 22 29 24 J2 19 97 82 C8 50 45 K8 35 19 14 F2 98 83 D9 53 104 89 B6 69 82 54 103 88 A6 68 81 112 86 71 D10 57 109 111 87 72 E8 58 108 - BGA96 H1 K6 E2 H2 D1 J6 E3 D2 H3 C4 L7 G1 B4 J1 B6 K7 G2 C6 L5 J2 J7 K5 J4 K8 B7 C7 D10 D9 - MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin function Base Timer 8 Base Timer 9 Base Timer 10 Base Timer 11 Base Timer 12 Base Timer 13 Base Timer 14 Base Timer 15 Pin name TIOA8_0 TIOA8_1 TIOA8_2 TIOB8_0 TIOB8_1 TIOB8_2 TIOA9_0 TIOA9_1 TIOA9_2 TIOB9_0 TIOB9_1 TIOB9_2 TIOA10_0 TIOA10_1 TIOA10_2 TIOB10_0 TIOB10_1 TIOB10_2 TIOA11_0 TIOA11_1 TIOA11_2 TIOB11_0 TIOB11_1 TIOB11_2 TIOA12_0 TIOA12_1 TIOA12_2 TIOB12_0 TIOB12_1 TIOB12_2 TIOA13_0 TIOA13_1 TIOA13_2 TIOB13_0 TIOB13_1 TIOB13_2 TIOA14_0 TIOA14_1 TIOA14_2 TIOB14_0 TIOB14_1 TIOB14_2 TIOA15_0 TIOA15_1 TIOA15_2 TIOB15_0 TIOB15_1 TIOB15_2 Function description Base timer ch.8 TIOA pin Base timer ch.8 TIOB pin Base timer ch.9 TIOA pin Base timer ch.9 TIOB pin Base timer ch.10 TIOA pin Base timer ch.10 TIOB pin Base timer ch.11 TIOA pin Base timer ch.11 TIOB pin Base timer ch.12 TIOA pin Base timer ch.12 TIOB pin Base timer ch.13 TIOA pin Base timer ch.13 TIOB pin Base timer ch.14 TIOA pin Base timer ch.14 TIOB pin Base timer ch.15 TIOA pin Base timer ch.15 TIOB pin April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 8 8 D5 8 73 63 G8 53 22 17 G2 2 2 C1 2 63 53 J10 43 23 18 F4 9 74 64 F10 54 79 69 E9 3 3 C2 3 64 54 J8 44 80 70 D11 10 75 65 F9 55 89 74 C10 60 4 4 B3 4 65 55 H10 45 88 73 C11 59 11 76 66 E11 56 83 5 5 D1 5 66 56 H9 46 84 12 77 67 E10 110 6 6 D2 6 67 57 H7 47 111 13 78 68 F8 14 9 E1 9 7 7 D3 7 68 58 G10 48 15 10 E2 10 21 16 G1 84 92 77 A9 61 20 15 F3 85 94 79 B11 63 119 99 A2 79 114 94 C5 74 18 13 F1 118 98 A3 78 113 93 D6 73 19 14 F2 - BGA96 E1 F9 C1 J10 E11 C2 J8 E10 C10 B3 H10 C11 E9 D1 H9 D2 G10 E2 D3 G9 E3 A10 B11 A2 C5 A3 B5 - 33 D a t a S h e e t Pin function Debugger Pin name SWCLK SWDIO SWO TCK TDI TDO TMS External Bus 3 TRACECLK TRACED0 TRACED1 TRACED2 TRACED3 TRSTX MAD00_0 MAD01_0 MAD02_0 MAD03_0 MAD04_0 MAD05_0 MAD06_0 MAD07_0 MAD08_0 MAD09_0 MAD10_0 MAD11_0 MAD12_0 MAD13_0 MAD14_0 MAD15_0 MAD16_0 MAD17_0 MAD18_0 MAD19_0 MAD20_0 MAD21_0 MAD22_0 MAD23_0 MAD24_0 Function description Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin J-TAG test clock input pin J-TAG test data input pin J-TAG debug data output pin J-TAG test mode state input/output pin Trace CLK output pin of ETM Trace data output pin of ETM J-TAG test reset input pin External bus interface address bus Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 BGA96 93 78 B9 62 B9 95 80 A8 64 A9 96 93 94 96 81 78 79 81 B8 B9 B11 B8 65 62 63 65 B8 B9 B11 B8 95 80 A8 64 A9 101 97 98 99 100 92 36 37 44 45 46 47 48 49 50 63 64 65 66 67 68 69 73 74 75 76 77 78 79 80 89 86 82 83 84 85 77 31 32 39 40 41 42 43 44 45 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 74 C7 C8 D9 A7 B7 A9 H5 L6 K6 J6 L7 K7 H6 J7 K8 J10 J8 H10 H9 H7 G10 G9 G8 F10 F9 E11 E10 F8 E9 D11 C10 61 21 22 29 30 31 32 33 34 35 43 44 45 46 47 48 49 53 54 55 56 60 A10 L5 K5 J5 K6 J6 L7 K7 J7 K8 J10 J8 H10 H9 G10 G9 F10 F9 E11 E10 E9 C10 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin function External Bus Pin name MCSX0_0 MCSX1_0 MCSX2_0 MCSX3_0 MCSX4_0 MCSX5_0 MCSX6_0 MCSX7_0 MDQM0_0 MDQM1_0 Function description External bus interface chip select output pin External bus interface byte mask signal output pin Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 103 88 A6 68 102 87 D7 67 101 86 C7 100 85 B7 98 83 D9 97 82 C8 94 79 B11 63 92 77 A9 61 105 90 C6 70 106 91 A5 71 BGA96 C7 C8 B11 A10 B6 C6 MOEX_0 External bus interface read enable signal for SRAM 114 94 C5 74 C5 MWEX_0 External bus interface write enable signal for SRAM 113 93 D6 73 B5 18 - - - - 19 - - - - 21 - - - - 20 - - - - 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 104 116 99 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 89 96 84 C1 C2 B3 D1 D2 D3 D5 E1 E2 E3 E4 F1 F2 F3 G1 G2 B6 C4 A7 2 3 4 5 6 7 8 9 10 11 12 69 76 66 C1 C2 B3 D1 D2 D3 E1 E2 E3 G1 G2 B7 C4 A8 MNALE_0 MNCLE_0 MNREX_0 MNWEX_0 MADATA00_0 MADATA01_0 MADATA02_0 MADATA03_0 MADATA04_0 MADATA05_0 MADATA06_0 MADATA07_0 MADATA08_0 MADATA09_0 MADATA10_0 MADATA11_0 MADATA12_0 MADATA13_0 MADATA14_0 MADATA15_0 MALE_0 MRDY_0 MCLKOUT_0 External bus interface ALE signal to control NAND Flash memory output pin External bus interface CLE signal to control NAND Flash memory output pin External bus interface read enable signal to control NAND Flash memory External bus interface write enable signal to control NAND Flash memory External bus interface data bus Latch enable signal for multiplex External RDY input signal External bus clock output pin April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 35 D a t a S h e e t Pin function Pin name External Interrupt 3 INT00_0 INT00_1 INT00_2 INT01_0 INT01_1 INT01_2 INT02_0 INT02_1 INT02_2 INT03_0 INT03_1 INT03_2 INT04_0 INT04_1 INT04_2 INT05_0 INT05_1 INT05_2 INT06_0 INT06_1 INT06_2 INT07_0 INT07_1 INT07_2 INT08_0 INT08_1 INT08_2 INT09_0 INT09_1 INT09_2 INT10_0 INT10_1 INT10_2 INT11_0 INT11_1 INT11_2 INT12_0 INT12_1 INT12_2 INT13_0 INT13_1 INT13_2 INT14_0 INT14_1 INT14_2 Function description External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 08 input pin External interrupt request 09 input pin External interrupt request 10 input pin External interrupt request 11 input pin External interrupt request 12 input pin External interrupt request 13 input pin External interrupt request 14 input pin LQFP120 2 97 102 3 98 85 4 63 82 113 66 14 17 69 15 89 75 16 23 88 50 24 114 5 34 19 8 35 20 11 36 21 112 37 22 110 48 32 108 49 33 52 67 44 53 LQFP100 2 82 87 3 83 4 53 93 56 9 12 59 10 74 65 11 18 73 45 19 94 5 29 14 8 30 15 31 16 32 17 43 27 44 28 57 39 - Pin No BGA112 C1 C8 D7 C2 D9 B3 J10 D6 H9 E1 E4 G9 E2 C10 F9 E3 F4 C11 K8 G3 C5 D1 K5 F2 D5 J5 F3 H5 G1 L6 G2 H6 J4 J7 L5 H7 K6 - LQFP80 2 67 3 4 43 73 46 9 12 49 10 60 55 11 13 59 35 14 74 5 8 21 22 33 34 47 29 - BGA96 C1 C8 C2 B3 J10 B5 H9 E2 G2 F10 E3 C10 E10 G1 G3 C11 K8 H1 C5 D1 E1 L5 K5 K7 J7 G10 J5 - MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin function Pin name External Interrupt INT15_0 INT15_1 INT15_2 INT16_0 INT16_1 INT16_2 INT17_0 INT17_1 INT17_2 INT18_0 INT18_1 INT18_2 INT19_0 INT19_1 INT19_2 INT20_0 INT20_1 INT20_2 INT21_0 INT21_1 INT21_2 INT22_0 INT22_1 INT22_2 INT23_0 INT23_1 INT23_2 NMIX Function description External interrupt request 15 input pin External interrupt request 16 input pin External interrupt request 17 input pin External interrupt request 18 input pin External interrupt request 19 input pin External interrupt request 20 input pin External interrupt request 21 input pin External interrupt request 22 input pin External interrupt request 23 input pin Non-Maskable Interrupt input pin April 4, 2014, MB9AF156RA_DS706-00047-2v0-E LQFP120 68 116 54 100 118 12 101 119 13 103 6 26 104 7 28 105 45 76 106 46 77 109 47 78 111 99 79 LQFP100 58 96 85 98 86 99 88 6 21 89 7 23 90 40 66 91 41 67 42 68 84 69 107 92 Pin No BGA112 G10 C4 B7 A3 C7 A2 A6 D2 H2 B6 D3 H3 C6 J6 E11 A5 L7 E10 K7 F8 A7 E9 B5 LQFP80 48 76 78 79 68 6 16 69 7 18 70 30 56 71 31 32 66 - BGA96 G9 C4 A3 A2 C7 D2 H3 B7 D3 J2 B6 K6 E9 C6 J6 L7 A8 - 72 A6 37 D a t a S h e e t Pin function GPIO 3 Pin name P00 P01 P02 P03 P04 P05 P06 P07 P08 P09 P0A P0B P0C P0D P0E P0F P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P1A P1B P1C P1D P1E P1F P20 P21 P22 P23 P24 P25 P26 P27 P28 Function description General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 92 77 A9 61 93 78 B9 62 94 79 B11 63 95 80 A8 64 96 81 B8 65 97 82 C8 98 83 D9 99 84 A7 66 100 85 B7 101 86 C7 102 87 D7 67 103 88 A6 68 104 89 B6 69 105 90 C6 70 106 91 A5 71 107 92 B5 72 62 52 J11 42 63 53 J10 43 64 54 J8 44 65 55 H10 45 66 56 H9 46 67 57 H7 47 68 58 G10 48 69 59 G9 49 73 63 G8 53 74 64 F10 54 75 65 F9 55 76 66 E11 56 77 67 E10 78 68 F8 79 69 E9 80 70 D11 89 74 C10 60 88 73 C11 59 87 72 E8 58 86 71 D10 57 85 84 83 82 81 - BGA96 A10 B9 B11 A9 B8 A8 C8 C7 B7 B6 C6 A6 J11 J10 J8 H10 H9 G10 G9 F10 F9 E11 E10 E9 C10 C11 D9 D10 - MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin function GPIO Pin name P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P3A P3B P3C P3D P3E P3F P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P4A P4B P4C P4D P4E P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P5A P5B P60 P61 P62 P63 P64 P65 P66 P67 P68 Function description General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 14 9 E1 9 15 10 E2 10 16 11 E3 11 17 12 E4 12 18 13 F1 19 14 F2 20 15 F3 21 16 G1 22 17 G2 23 18 F4 13 24 19 G3 14 25 20 H1 15 26 21 H2 16 27 22 G4 17 28 23 H3 18 29 24 J2 19 32 27 J4 33 28 L5 34 29 K5 35 30 J5 36 31 H5 21 37 32 L6 22 41 36 L3 26 42 37 K3 27 44 39 K6 29 45 40 J6 30 46 41 L7 31 47 42 K7 32 48 43 H6 33 49 44 J7 34 50 45 K8 35 2 2 C1 2 3 3 C2 3 4 4 B3 4 5 5 D1 5 6 6 D2 6 7 7 D3 7 8 8 D5 8 9 10 11 12 13 116 96 C4 76 115 95 B4 75 114 94 C5 74 113 93 D6 73 112 111 110 109 108 - BGA96 E2 E3 G1 G2 G3 H1 H2 H3 J1 J2 J4 L5 K5 L3 K3 J5 K6 J6 L7 K7 J7 K8 C1 C2 B3 D1 D2 D3 E1 C4 B4 C5 B5 39 D a t a S h e e t Pin function GPIO 4 Pin name P70 P71 P72 P73 P74 P80 P81 PE0 PE2 PE3 Function description General-purpose I/O port 7 General-purpose I/O port 8 General-purpose I/O port E Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 51 52 53 54 55 118 98 A3 78 119 99 A2 79 56 46 K9 36 58 48 L9 38 59 49 L10 39 BGA96 A3 A2 K9 L9 L10 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin function Multifunction Serial 0 Pin name SIN0_0 SIN0_1 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) Multifunction Serial 1 SIN1_0 SIN1_1 SOT1_0 (SDA1_0) SOT1_1 (SDA1_1) SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) Function description Multi-function serial interface ch.0 input pin Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 input pin Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I2C (operation mode 4). April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 88 73 C11 59 66 56 H9 46 BGA96 C11 H9 87 72 E8 58 D9 67 57 H7 47 G10 86 71 D10 57 D10 68 58 G10 48 G9 8 63 53 J10 43 J10 9 - - - - 64 54 J8 44 J8 10 - - - - 65 55 H10 45 H10 41 D a t a S h e e t Pin function Multifunction Serial 2 Pin name SIN2_0 SIN2_1 SIN2_2 SOT2_0 (SDA2_0) SOT2_1 (SDA2_1) SOT2_2 (SDA2_2) SCK2_0 (SCL2_0) SCK2_1 (SCL2_1) SCK2_2 (SCL2_2) Multifunction Serial 3 SIN3_0 SIN3_1 SIN3_2 SOT3_0 (SDA3_0) SOT3_1 (SDA3_1) SOT3_2 (SDA3_2) SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) SCK3_2 (SCL3_2) 4 Function description Multi-function serial interface ch.2 input pin Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 53 85 69 59 G9 49 BGA96 F10 Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA2 when it is used in an I2C (operation mode 4). 54 - - - - 84 - - - - 73 63 G8 53 F9 Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL2 when it is used in an I2C (operation mode 4). 55 - - - - 83 - - - - 74 64 F10 54 E11 110 2 44 2 39 C1 K6 2 29 C1 J5 Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA3 when it is used in an I2C (operation mode 4). 109 - - - - 3 3 C2 3 C2 45 40 J6 30 K6 Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I2C (operation mode 4). 108 - - - - 4 4 B3 4 B3 46 41 L7 31 J6 Multi-function serial interface ch.3 input pin MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin function Pin name Multifunction Serial 4 SIN4_0 SIN4_1 SIN4_2 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) SOT4_2 (SDA4_2) SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) SCK4_2 (SCL4_2) RTS4_0 RTS4_1 RTS4_2 CTS4_0 CTS4_1 CTS4_2 Function description Multi-function serial interface ch.4 input pin Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 102 87 D7 67 75 65 F9 55 97 82 C8 - BGA96 C8 E10 - Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA4 when it is used in an I2C (operation mode 4). 103 88 A6 68 C7 76 66 E11 56 E9 98 83 D9 - - Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL4 when it is used in an I2C (operation mode 4). 104 89 B6 69 B7 77 67 E10 - - 99 84 A7 - - 105 79 101 106 78 100 90 69 86 91 68 85 C6 E9 C7 A5 F8 B7 70 71 - B6 C6 - Multi-function serial interface ch.4 RTS output pin Multi-function serial interface ch.4 CTS input pin April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 43 D a t a S h e e t Pin function Multifunction Serial 5 Pin name SIN5_0 SIN5_1 SIN5_2 SOT5_0 (SDA5_0) SOT5_1 (SDA5_1) SOT5_2 (SDA5_2) SCK5_0 (SCL5_0) SCK5_1 (SCL5_1) SCK5_2 (SCL5_2) 4 Function description Multi-function serial interface ch.5 input pin Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 116 96 C4 76 113 20 15 F3 - BGA96 C4 - Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA5 when it is used in an I2C (operation mode 4). 115 95 B4 75 B4 112 - - - - 21 16 G1 - - Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I2C (operation mode 4). 114 94 C5 74 C5 111 - - - - 22 17 G2 - - MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin function Multifunction Serial 6 Pin name SIN6_0 SIN6_1 SOT6_0 (SDA6_0) SOT6_1 (SDA6_1) SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) Multifunction Serial 7 SIN7_0 SIN7_1 SOT7_0 (SDA7_0) SOT7_1 (SDA7_1) SCK7_0 (SCL7_0) SCK7_1 (SCL7_1) Function description Multi-function serial interface ch.6 input pin Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 input pin Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I2C (operation mode 4). April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 5 5 D1 5 17 12 E4 12 BGA96 D1 G2 6 6 D2 6 D2 16 11 E3 11 G1 7 7 D3 7 D3 15 10 E2 10 E3 11 50 45 K8 35 K8 12 - - - - 49 44 J7 34 J7 13 - - - - 48 43 H6 33 K7 45 D a t a S h e e t Pin function Multifunction Serial 8 Pin name SIN8_0 SOT8_0 (SDA8_0) SCK8_0 (SCL8_0) Multifunction Serial 9 SIN9_0 SOT9_0 (SDA9_0) SCK9_0 (SCL9_0) Multifunction Serial 10 SIN10_0 SOT10_0 (SDA10_0) SCK10_0 (SCL10_0) 4 Function description Multi-function serial interface ch.8 input pin Multi-function serial interface ch.8 output pin. This pin operates as SOT8 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA8 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.8 clock I/O pin. This pin operates as SCK8 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL8 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.9 input pin Multi-function serial interface ch.9 output pin. This pin operates as SOT9 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA9 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.9 clock I/O pin. This pin operates as SCK9 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL9 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.10 input pin Multi-function serial interface ch.10 output pin. This pin operates as SOT10 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA10 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.10 clock I/O pin. This pin operates as SCK10 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL10 when it is used in an I2C (operation mode 4). Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 BGA96 97 82 C8 - - 94 79 B11 - - 92 77 A9 - - 17 12 E4 - - 18 13 F1 - - 19 14 F2 - - 23 18 F4 13 G3 24 19 G3 14 H1 25 20 H1 15 H2 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin function Multifunction Serial 11 Pin name SIN11_0 SOT11_0 (SDA11_0) SCK11_0 (SCL11_0) Multifunction Serial 12 SIN12_0 SOT12_0 (SDA12_0) SCK12_0 (SCL12_0) Multifunction Serial 13 SIN13_0 SOT13_0 (SDA13_0) SCK13_0 (SCL13_0) Function description Multi-function serial interface ch.11 input pin Multi-function serial interface ch.11 output pin. This pin operates as SOT11 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA11 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.11 clock I/O pin. This pin operates as SCK11 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL11 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.12 input pin Multi-function serial interface ch.12 output pin. This pin operates as SOT12 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA12 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.12 clock I/O pin. This pin operates as SCK12 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL12 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.13 input pin Multi-function serial interface ch.13 output pin. This pin operates as SOT13 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA13 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.13 clock I/O pin. This pin operates as SCK13 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL13 when it is used in an I2C (operation mode 4). April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 BGA96 26 21 H2 16 H3 27 22 G4 17 J1 28 23 H3 18 J2 32 27 J4 - - 33 28 L5 - - 34 29 K5 - - 35 30 J5 - - 36 31 H5 - - 37 32 L6 - - 47 D a t a S h e e t Pin function Multifunction Serial 14 Pin name SIN14_0 SOT14_0 (SDA14_0) SCK14_0 (SCL14_0) Multifunction Serial 15 SIN15_0 SOT15_0 (SDA15_0) SCK15_0 (SCL15_0) 4 Function description Multi-function serial interface ch.14 input pin Multi-function serial interface ch.14 output pin. This pin operates as SOT14 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA14 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.14 clock I/O pin. This pin operates as SCK14 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL14 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.15 input pin Multi-function serial interface ch.15 output pin. This pin operates as SOT15 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA15 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.15 clock I/O pin. This pin operates as SCK15 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL15 when it is used in an I2C (operation mode 4). Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 BGA96 50 - - - - 51 - - - - 52 - - - - 82 - - - - 81 - - - - 80 - - - - MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin function Multifunction Timer 0 Pin name DTTI0X_0 Function description Input signal of waveform generator to control outputs RTO00 to RTO05 of multi-function timer 0. Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 BGA96 23 18 F4 13 G3 79 69 E9 - - 18 80 63 22 75 64 21 76 65 20 77 66 19 78 67 13 70 53 17 65 54 16 66 55 15 67 56 14 68 57 F1 D11 J10 G2 F9 J8 G1 E11 H10 F3 E10 H9 F2 F8 H7 43 55 44 56 45 46 47 J10 E10 J8 E9 H10 H9 G10 Waveform generator output pin of multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. 24 19 G3 14 H1 86 71 D10 57 D10 Waveform generator output pin of multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. 25 20 H1 15 H2 85 - - - - Waveform generator output pin of multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. 26 21 H2 16 H3 84 - - - - Waveform generator output pin of multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. 27 22 G4 17 J1 83 - - - - Waveform generator output pin of multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. 28 23 H3 18 J2 82 - - - - 29 24 J2 19 J4 RTO05_1 (PPG04_1) Waveform generator output pin of multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. 81 - - - - IGTRG_0 IGTRG_1 PPG IGMT mode external trigger input pin 46 116 41 96 L7 C4 31 76 J6 C4 DTTI0X_1 FRCK0_0 FRCK0_1 FRCK0_2 IC00_0 IC00_1 IC00_2 IC01_0 IC01_1 IC01_2 IC02_0 IC02_1 IC02_2 IC03_0 IC03_1 IC03_2 RTO00_0 (PPG00_0) RTO00_1 (PPG00_1) RTO01_0 (PPG00_0) RTO01_1 (PPG00_1) RTO02_0 (PPG02_0) RTO02_1 (PPG02_1) RTO03_0 (PPG02_0) RTO03_1 (PPG02_1) RTO04_0 (PPG04_0) RTO04_1 (PPG04_1) RTO05_0 (PPG04_0) 16-bit free-run timer ch.0 external clock input pin 16-bit input capture input pin of multi-function timer 0. ICxx describes channel number. April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 49 D a t a S h e e t Pin function Pin name Quadrature Position/ Revolution Counter 0 AIN0_0 AIN0_1 AIN0_2 BIN0_0 BIN0_1 BIN0_2 ZIN0_0 ZIN0_1 ZIN0_2 AIN1_1 AIN1_2 BIN1_1 BIN1_2 ZIN1_1 ZIN1_2 RTCCO_0 RTCCO_1 RTCCO_2 SUBOUT_0 SUBOUT_1 SUBOUT_2 Quadrature Position/ Revolution Counter 1 Real-time clock Low-Power Consumption Mode WKUP0 WKUP1 WKUP2 WKUP3 WKUP4 WKUP5 HDMICEC/ Remote Control Reception CEC0_0 CEC0_1 CEC1_0 CEC1_1 5 Function description QPRC ch.0 AIN input pin QPRC ch.0 BIN input pin QPRC ch.0 ZIN input pin QPRC ch.1 AIN input pin QPRC ch.1 BIN input pin QPRC ch.1 ZIN input pin 0.5 seconds pulse output pin of Real-time clock Sub clock output pin Deep standby mode return signal input pin 0 Deep standby mode return signal input pin 1 Deep standby mode return signal input pin 2 Deep standby mode return signal input pin 3 Deep standby mode return signal input pin 4 Deep standby mode return signal input pin 5 HDMI-CEC/Remote Control Reception ch.0 input/output pin HDMI-CEC/Remote Control Reception ch.1 input/output pin Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 14 9 E1 9 45 40 J6 30 2 2 C1 2 15 10 E2 10 46 41 L7 31 3 3 C2 3 16 11 E3 11 47 42 K7 32 4 4 B3 4 89 74 C10 60 48 43 H6 33 88 73 C11 59 49 44 J7 34 87 72 E8 58 50 45 K8 35 107 92 B5 72 65 55 H10 45 24 19 G3 14 107 92 B5 72 65 55 H10 45 24 19 G3 14 BGA96 E2 K6 C1 E3 J6 C2 G1 L7 B3 C10 K7 C11 J7 D9 K8 A6 H10 H1 A6 H10 H1 107 92 B5 72 A6 63 53 J10 43 J10 88 73 C11 59 C11 116 96 C4 76 C4 14 9 E1 9 E2 102 87 D7 67 C8 48 43 H6 33 K7 103 88 A6 68 C7 116 96 C4 76 C4 8 8 D5 8 E1 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin function Pin name RESET INITX Mode MD0 MD1 POWER GND VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Function description External Reset Input pin. A reset is valid when INITX="L". Mode 0 pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. Mode 1 pin. During serial programming to Flash memory, MD1="L" must be input. Power supply Pin Power supply Pin Power supply Pin Power supply Pin Power supply Pin Power supply Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 BGA96 43 38 K4 28 K4 57 47 L8 37 L8 56 46 K9 36 K9 1 31 40 61 91 117 30 39 60 90 120 1 26 35 51 76 97 25 34 50 75 100 B1 J1 K1 K11 A10 A4 B2 L1 K2 J3 H4 L4 L11 K10 J9 H8 B10 C9 A11 D8 D4 C3 A1 1 25 41 77 20 24 40 80 B1 K1 K11 A4 F1 F2 F3 B2 L1 K2 J3 L6 L4 L11 K10 J9 B10 C9 D11 A11 A7 C3 A5 A1 51 D a t a S h e e t Pin function CLOCK ADC POWER Pin name Function description X0 X0A X1 X1A CROUT_0 CROUT_1 Main clock (oscillation) input pin Sub clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin Built-in high-speed CR-osc clock output port A/D converter analog power supply pin A/D converter analog reference voltage input pin AVCC AVRH ADC GND C pin 5 AVSS C Pin No LQFP- LQFP- BGA- LQFP120 100 112 80 58 48 L9 38 41 36 L3 26 59 49 L10 39 42 37 K3 27 89 74 C10 60 107 92 B5 72 BGA96 L9 L3 L10 K3 C10 A6 70 60 H11 50 H11 71 61 F11 51 F11 A/D converter GND pin 72 62 G11 52 G11 Power stabilization capacity pin 38 33 L2 23 L2 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t  I/O CIRCUIT TYPE Type Circuit Remarks A It is possible to select the main oscillation / GPIO function P-ch P-ch Digital output X1 N-ch Digital output R Pull-up resistor control When the main oscillation is selected.  Oscillation feedback resistor : Approximately 1MΩ  With standby mode control When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 33kΩ  IOH= -4mA, IOL= 4mA Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control  CMOS level hysteresis input  Pull-up resistor : Approximately 33kΩ B Pull-up resistor Digital input April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 53 D a t a S h e e t Type Circuit Remarks  Open drain output  CMOS level hysteresis input C Digital input Digital output N-ch D It is possible to select the sub oscillation / GPIO function P-ch P-ch When the sub oscillation is selected.  Oscillation feedback resistor : Approximately 5MΩ  With standby mode control Digital output X1A N-ch R When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With standby mode control Pull-up resistor control  Pull-up resistor : Approximately 33kΩ Digital input  IOH= -4mA, IOL= 4mA Digital output Standby mode control Clock input Standby mode control Digital input Standby mode control R P-ch P-ch Digital output N-ch Digital output X0A Pull-up resistor control 5 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Type Circuit Remarks      E P-ch P-ch N-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 33kΩ  IOH= -4mA, IOL= 4mA  When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output R Pull-up resistor control Digital input Standby mode control F P-ch P-ch N-ch R Digital output Digital output        CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 33kΩ  IOH= -4mA, IOL= 4mA  When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control Analog input Input control G CMOS level hysteresis input Mode input April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 55 D a t a S h e e t Type Circuit Remarks       H P-ch P-ch N-ch CMOS level output CMOS level hysteresis input 5V tolerant With pull-up resistor control With standby mode control Pull-up resistor : Approximately 33kΩ  IOH= -4mA, IOL= 4mA  Available to control PZR registers.  When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output Digital output R Pull-up resistor control Digital input Standby mode control 5 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t  HANDLING PRECAUTIONS Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. • Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. • Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. • Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. • Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Code: DS00-00004-3E April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 57 D a t a S h e e t • Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. • Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. • Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed information about mount conditions, contact your sales representative. • Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. • Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion Inc. recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions. 5 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t • Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. • Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion Inc. packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. • Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125°C/24 h • Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 59 D a t a S h e e t 3. Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf 6 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t  HANDLING DEVICES • Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin near this device. • Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. • Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. • Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. • Surface mount type Size : More than 3.2mm × 1.5mm Load capacitance : Approximately 6pF to 7pF • Lead type Load capacitance : Approximately 6pF to 7pF April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 61 D a t a S h e e t • Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. • Example of Using an External Clock Device X0(X0A) Can be used as general-purpose I/O ports. Set as External clock input X1(PE3), X1A (P47) • Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. • C pin This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7uF would be recommended for this series. C Device CS VSS GND • Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistor stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. 6 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t • Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and AVSS = VSS. Turning on : VCC →AVCC → AVRH Turning off : AVRH → AVCC → VCC • Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. • Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. • Pull-Up function of 5V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O. April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 63 D a t a S h e e t  BLOCK DIAGRAM TRACEDx, TRACECLK SWJ-DP ETM* TPIU* ROM Table SRAM0 16/24/32 Kbyte Cortex-M3 Core @40 MHz(Max) I Multi-layer AHB (Max 40 MHz) TRSTX,TCK, TDI,TMS TDO D NVIC Sys AHB-APB Bridge: APB0(Max 40 MHz) Dual-Timer WatchDog Timer (Software) Clock Reset Generator INITX WatchDog Timer (Hardware) SRAM1 16/24/32 Kbyte Flash I/F Security On-Chip Flash 256+32 Kbyte/ 384+32 Kbyte/ 512+32 Kbyte DMAC 8ch. CSV X0 X1 X0A X1A Main Osc Sub Osc Source Clock PLL CR 4 MHz AHB-AHB Bridge CLK CR 100 kHz CROUT AVCC, AVSS, AVRH ANxx MADx External Bus I/F 12-bit A/D Converter Unit 0 MADATAx Unit 1 Power-On Reset ADTGx LVD Ctrl TIOAx TIOBx Base Timer 16-bit 16ch./ 32-bit 8ch. MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT LVD Regulator IRQ-Monitor CRC C BINx ZINx QPRC 2ch. A/D Activation Compare 2ch. IC0x FRCK0 16-bit Input Capture 4ch. 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. DTTI0X RTO0x AHB-APB Bridge : APB2 (Max 40 MHz) AINx AHB-APB Bridge : APB1 (Max 40 MHz) Accelerator Watch Counter Deep Standby Ctrl WKUPx HDMI-CEC/ Remote Reciver Control CEC0, CEC1 RTCCO, SUBOUT Real-Time Clock External Interrupt Controller 24-pin + NMI INTx NMIX MD0, MD1 MODE-Ctrl P0x, P1x, Waveform Generator 3ch. GPIO PIN-Function-Ctrl . . . PEx IGTRG 16-bit PPG 3ch. Multi-function Timer × 1 SCKx Multi-Function Serial I/F 16ch. HW flow control(ch.4) SINx SOTx CTS4 RTS4 *: For the MB9AF154MA, MB9AF155MA, and MB9AF156MA, ETM is not available.  MEMORY SIZE See "  Memory size" in "PRODUCT LINEUP" to confirm the memory size. 6 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t  MEMORY MAP  Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M3 Private Peripherals 0x4006_1000 0x4006_0000 DMAC Reserved 0x4004_0000 0x4003_F000 Reserved 0x4003_C000 0x4003_B000 0x4003_A000 0x7000_0000 0x6000_0000 0x4003_9000 External Device Area 0x4003_8000 0x4003_6000 Reserved 0x4400_0000 0x4200_0000 0x4000_0000 32Mbytes Bit band alias Peripherals 0x4003_5000 0x2400_0000 0x2200_0000 0x4003_3000 0x4003_2000 0x4003_1000 0x4002_F000 0x4002_E000 32Mbytes Bit band alias 0x4002_8000 0x4002_7000 Reserved 0x2008_0000 0x2000_0000 0x1FF8_0000 0x0020_8000 0x0020_0000 See "Memory Map (2)" for the memory size details. 0x0010_4000 0x0010_0000 0x4002_6000 0x4002_5000 SRAM1 SRAM0 Reserved Flash(Work area) Reserved Security/CR Trim 0x4002_4000 LVD/DS mode GPIO Reserved Int-Req.Read EXTI Reserved CR Trim Reserved A/DC QPRC Base Timer PPG Reserved 0x4002_1000 0x4002_0000 0x4001_6000 0x4001_5000 Flash(Main area) 0x4001_3000 0x0000_0000 Reserved HDMI-CEC/ 0x4003_4000 Rem ote Control Receiver 0x4003_0000 Reserved EXT-bus I/F Reserved RTC Watch Counter CRC MFS 0x4001_2000 0x4001_1000 0x4001_0000 MFT Unit0 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved 0x4000_1000 0x4000_0000 April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Flash I/F 65 D a t a S h e e t  Memory Map (2) MB9AF156MA/NA/RA 0x2008_0000 MB9AF155MA/NA/RA 0x2008_0000 Reserved MB9AF154MA/NA/RA 0x2008_0000 Reserved Reserved 0x2000_8000 0x2000_6000 SRAM1 32Kbytes 0x2000_0000 SRAM1 24Kbytes 0x2000_0000 SRAM0 32Kbytes 0x2000_4000 0x2000_0000 SRAM0 24Kbytes 0x1FFF_C000 SRAM1 16Kbytes SRAM0 16Kbytes 0x1FFF_A000 0x1FFF_8000 0x0020_8000 0x0020_0000 0x0020_8000 Flash(Work area) 32Kbytes 0x0020_0000 Reserved 0x0010_4000 0x0010_2000 0x0010_0000 0x0020_8000 Flash(Work area) 32Kbytes 0x0020_0000 Reserved 0x0010_4000 CR trimming Security Reserved Reserved Reserved 0x0010_2000 0x0010_0000 Flash(Work area) 32Kbytes Reserved 0x0010_4000 CR trimming Security 0x0010_2000 0x0010_0000 CR trimming Security Reserved Reserved 0x0008_0000 Reserved 0x0006_0000 Flash(Main area) 512Kbytes 0x0004_0000 Flash(Main area) 384Kbytes 0x0000_0000 0x0000_0000 Flash(Main area) 256Kbytes 0x0000_0000 For more information about Flash (Main area)/Flash (Work area), see "MB9AB40N/A40N/340N/140N/150R, MB9B520M/320M/120M Series Flash Programming Manual". 6 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t  Peripheral Address Map Start address End address 0x4000_0000 0x4000_0FFF 0x4000_1000 0x4000_FFFF 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF 0x4001_3000 0x4001_4FFF 0x4001_5000 0x4001_5FFF Dual Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt 0x4003_1000 0x4003_1FFF Interrupt Source Check Register 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF HDMI-CEC/Remote control Reception 0x4003_5000 0x4003_57FF Low-Voltage Detector 0x4003_5800 0x4003_5FFF 0x4003_6000 0x4003_7FFF 0x4003_8000 0x4003_8FFF Multi-function serial 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External bus interface 0x4004_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF 0x4006_1000 0x41FF_FFFF April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Bus AHB APB0 APB1 APB2 AHB Peripherals Flash memory I/F register Reserved Software Watchdog timer Reserved Quadrature Position/Revolution Counter Deep standby mode Controller Reserved DMAC register Reserved 67 D a t a S h e e t  PIN STATUS IN EACH CPU STATE The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the "L" level.  INITX=1 This is the period when the INITX pin is the "H" level.  SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".  SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".  Input enabled Indicates that the input function can be used.  Internal input fixed at "0" This is the status that the input function cannot be used. Internal input is fixed at "L".  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port. 6 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Pin status type  List of Pin Status Function group Power-on Device Run mode reset or INITX internal or SLEEP low-voltage input state reset state mode state detection state Power supply unstable - Power supply stable INITX = 0 INITX = 1 INITX = 1 Power supply stable TIMER mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 GPIO Hi-Z / Hi-Z / selected Internal Internal Internal input fixed input fixed input fixed at "0" at "0" at "0" Return from Deep standby mode state Power supply stable INITX = 1 - GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Main crystal oscillator input pin/ External main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Maintain previous state GPIO Hi-Z / Hi-Z / selected Internal Internal Internal input fixed input fixed input fixed at "0" at "0" at "0" GPIO selected Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state GPIO selected A GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Input enabled Input enabled Maintain previous state Input enabled Hi-Z / Internal input fixed at "0" Input enabled B Maintain Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous previous Hi-Z / state/When state/When state/When state/When state/When state/When Internal Hi-Z / Hi-Z / oscillation oscillation oscillation oscillation oscillation oscillation Main crystal input fixed Internal Internal stops*1, stops* 1, stops* 1, stops* 1, stops* 1, stops* 1, at "0"/ oscillator output pin input fixed input fixed Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / at "0" at "0" or Input Internal Internal Internal Internal Internal Internal enable input fixed input fixed input fixed input fixed input fixed input fixed at "0" at "0" at "0" at "0" at "0" at "0" C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled GPIO selected Hi-Z / Input enabled GPIO selected E April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 69 Pin status type D a t a S h e e t Function group Power-on Device Run mode reset or INITX internal or SLEEP low-voltage input state reset state mode state detection state TIMER mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Return from Deep standby mode state Power supply unstable - Power supply stable INITX = 0 INITX = 1 INITX = 1 - GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state GPIO Hi-Z / Hi-Z / selected Internal Internal Internal input fixed input fixed input fixed at "0" at "0" at "0" GPIO selected External sub clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Power supply stable GPIO Hi-Z / Hi-Z / selected Internal Internal Internal input fixed input fixed input fixed at "0" at "0" at "0" Power supply stable INITX = 1 - GPIO selected F Input enabled Input enabled Maintain previous state Input enabled Hi-Z/ Internal input fixed at "0" Input enabled G Hi-Z / Internal Hi-Z / Hi-Z / Internal Sub crystal oscillator input fixed Internal at "0"/ input fixed input fixed output pin at "0" at "0" or Input enable NMIX selected H 7 Resource other than above selected GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous state/When state/When state/When state/When state/When oscillation oscillation oscillation oscillation oscillation stops*2, stops*2, stops*2, stops*2, stops*2, Hi-Z/ Hi-Z / Hi-Z / Hi-Z/ Hi-Z/ Internal Internal Internal Internal Internal input fixed input fixed input fixed input fixed input fixed at "0" at "0" at "0" at "0" at "0" Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" WKUP input enabled Hi-Z / WKUP input enabled GPIO selected MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 Pin status type D a t a S h e e t Function group Power supply unstable JTAG selected I Power-on reset or Device Run mode INITX internal or SLEEP low-voltage input state reset state mode state detection state Hi-Z Pull-up / Input enabled Pull-up / Input enabled Resource selected GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Setting disabled Setting disabled Setting disabled Resource selected J GPIO selected External interrupt enabled selected K Power supply stable INITX = 0 INITX = 1 INITX = 1 Power supply stable Resource other than above selected Hi-Z GPIO selected Analog input selected Hi-Z L Resource other than above selected GPIO selected Analog input selected Setting disabled Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled TIMER mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Setting disabled Setting disabled Maintain previous state Maintain previous state GPIO Hi-Z / Hi-Z / selected Internal Internal Internal input fixed input fixed input fixed at "0" at "0" at "0" GPIO selected Hi-Z / Internal input fixed at "0" GPIO Hi-Z / selected Internal Internal input fixed input fixed at "0" at "0" GPIO Hi-Z / Hi-Z / selected Internal Internal Internal input fixed input fixed input fixed at "0" at "0" at "0" Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal Internal input fixed input fixed input fixed input fixed input fixed input fixed input fixed at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / Analog Analog Analog Analog Analog Analog Analog input input input input input input input enabled enabled enabled enabled enabled enabled enabled Setting disabled GPIO selected April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal Internal input fixed input fixed input fixed input fixed input fixed input fixed input fixed at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / Analog Analog Analog Analog Analog Analog Analog input input input input input input input enabled enabled enabled enabled enabled enabled enabled External interrupt enabled selected Setting disabled Maintain previous state Power supply stable INITX = 1 - GPIO Hi-Z / Hi-Z / selected Internal Internal Internal input fixed input fixed input fixed at "0" at "0" at "0" Maintain previous state M Resource other than above selected Maintain previous state Return from Deep standby mode state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO Hi-Z / selected Internal Internal input fixed input fixed at "0" at "0" GPIO selected Hi-Z / Internal input fixed at "0" / Analog input enabled GPIO selected Hi-Z / Internal input fixed at "0" / Analog input enabled GPIO selected 71 Pin status type D a t a S h e e t Function group Power-on Device Run mode reset or INITX internal or SLEEP low-voltage input state reset state mode state detection state Power supply unstable - Analog input selected Hi-Z Power supply stable INITX = 0 INITX = 1 INITX = 1 Power supply stable TIMER mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal Internal input fixed input fixed input fixed input fixed input fixed input fixed input fixed at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / Analog Analog Analog Analog Analog Analog Analog input input input input input input input enabled enabled enabled enabled enabled enabled enabled Return from Deep standby mode state Power supply stable INITX = 1 Hi-Z / Internal input fixed at "0" / Analog input enabled N Trace output Trace selected Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state GPIO selected Analog input selected Hi-Z Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal Internal input fixed input fixed input fixed input fixed input fixed input fixed input fixed at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / Analog Analog Analog Analog Analog Analog Analog input input input input input input input enabled enabled enabled enabled enabled enabled enabled Setting disabled Resource other than above selected P Resource other than above selected GPIO selected 7 Hi-Z WKUP enabled External interrupt enabled selected Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Analog input selected GPIO selected Hi-Z / Internal input fixed at "0" / Analog input enabled Trace output Trace selected O External interrupt enabled selected GPIO Hi-Z / selected Internal Internal Hi-Z / input fixed Internal input fixed at "0" at "0" input fixed at "0" Setting disabled GPIO Hi-Z / selected Internal Internal input fixed input fixed at "0" at "0" Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal Internal input fixed input fixed input fixed input fixed input fixed input fixed input fixed at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / Analog Analog Analog Analog Analog Analog Analog input input input input input input input enabled enabled enabled enabled enabled enabled enabled Hi-Z / WKUP WKUP input input enabled Maintain enabled previous state Maintain Maintain Setting Setting previous previous GPIO disabled disabled Hi-Z / state state selected Internal Internal input fixed Hi-Z / input fixed Internal at "0" at "0" input fixed at "0" GPIO selected Hi-Z / Internal input fixed at "0" / Analog input enabled GPIO selected MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 Pin status type D a t a S h e e t Function group Power supply unstable CEC enabled WKUP enabled Q Power-on reset or Device Run mode INITX internal or SLEEP low-voltage input state reset state mode state detection state Setting disabled Setting disabled CEC enabled External interrupt enabled selected Hi-Z / Input enabled Hi-Z / Input enabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Hi-Z GPIO selected WKUP enabled Setting disabled Hi-Z / Input enabled Setting disabled GPIO selected Hi-Z / Input enabled INITX = 1 SPL = 0 SPL = 1 Maintain Maintain previous previous state state INITX = 1 SPL = 0 SPL = 1 Maintain Maintain previous previous state state Hi-Z / WKUP WKUP input input enabled enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Setting disabled Hi-Z / Input enabled GPIO Hi-Z / selected Internal Internal Hi-Z / input fixed Internal input fixed at "0" at "0" input fixed at "0" Maintain previous state Maintain previous state Hi-Z Power supply stable Hi-Z / Input enabled External interrupt enabled selected Resource other than above selected Power supply stable Maintain previous state Maintain previous state Resource other than above selected Deep standby RTC mode or Deep standby STOP mode state Setting disabled Hi-Z GPIO selected S Setting disabled External interrupt enabled selected Resource other than above selected R Power supply stable INITX = 0 INITX = 1 INITX = 1 Maintain Setting Setting previous disabled disabled state Power supply stable TIMER mode, RTC mode, or STOP mode state Maintain previous state Maintain previous state Maintain previous state GPIO Hi-Z / selected Internal Internal input fixed input fixed at "0" at "0" WKUP input enabled Return from Deep standby mode state Power supply stable INITX = 1 Maintain previous state GPIO selected Maintain previous state GPIO selected Hi-Z / WKUP input enabled GPIO Hi-Z / selected Internal Internal Hi-Z / input fixed Internal input fixed at "0" at "0" input fixed at "0" GPIO selected *1: Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, RTC mode, STOP mode, Deep standby RTC mode, and Deep standby STOP mode. *2: Oscillation is stopped at STOP mode and Deep standby STOP mode. April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 73 D a t a S h e e t  ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter 1, 2 Power supply voltage* * Analog power supply voltage*1, *3 Analog reference voltage*1, *3 Input voltage*1 Symbol VCC AVCC AVRH VI Rating Min Max VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS + 4.6 VSS + 4.6 VSS + 4.6 VCC + 0.5 (≤ 4.6V) VSS + 6.5 AVCC + 0.5 (≤ 4.6V) VCC + 0.5 (≤ 4.6V) 10 4 100 50 - 10 -4 - 100 - 50 300 + 150 VSS - 0.5 VSS - 0.5 Analog pin input voltage*1 VIA VSS - 0.5 Output voltage*1 VO VSS - 0.5 Unit Remarks V V V V V 5V tolerant V V mA IOL "L" level maximum output current*4 mA "L" level average output current*5 IOLAV "L" level total maximum output current mA ∑IOL mA "L" level total average output current*6 ∑IOLAV 4 "H" level maximum output current* mA IOH mA "H" level average output current*5 IOHAV "H" level total maximum output current mA ∑IOH mA "H" level total average output current*6 ∑IOHAV Power consumption mW PD Storage temperature - 55 °C TSTG *1 : These parameters are based on the condition that V SS = AVSS = 0.0V. *2 : VCC must not drop below VSS - 0.5V. *3 : Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. *4 : The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5 : The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6 : The total average output current is defined as the average current value flowing through all of corresponding pins for a 100ms. Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. 7 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t 2. Recommended Operating Conditions (VSS = AVSS = 0.0V) Parameter Symbol Conditions Power supply voltage Analog power supply voltage VCC AVCC - Analog reference voltage AVRH - CS - Smoothing capacitor Value Min Max Unit 1.65*2 1.65 2.7 AVCC 3.6 3.6 AVCC AVCC V V V V 1 10 μF Remarks AVCC = VCC AVCC ≥ 2.7V AVCC < 2.7V For Regulator 1 * Operating temperature Ta - 40 + 85 °C *1 : See " C Pin" in " HANDLING DEVICES" for the connection of the smoothing capacitor. *2 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 75 D a t a S h e e t 3. DC Characteristics (1) Current rating (VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, Ta = - 40°C to + 85°C) Pin Parameter Symbol name ICC Power supply current ICCS VCC Value Unit Remarks Typ Max Conditions CPU : 40 MHz, Peripheral : 40 MHz *1, *3 Normal operation CPU : 40 MHz, (PLL) Peripheral : the clock stops NOP operation *1, *3 Normal operation CPU/ Peripheral : (built-in high-speed 4 MHz*2 1 CR) * CPU/ Peripheral : Normal operation 32 kHz (sub oscillation) *1, *4 Normal operation CPU/ Peripheral : (built-in low-speed 100 kHz 1 CR) * SLEEP operation Peripheral : 40 MHz (PLL) *1, *3 SLEEP operation Peripheral : 4 MHz*2 (built-in high-speed 1 * CR) SLEEP operation Peripheral : 32 kHz (sub oscillation) *1, *4 SLEEP operation Peripheral : 100 kHz (built-in low-speed 1 * CR) ICCH ICCT ICCR STOP mode TIMER mode (sub oscillation) RTC mode (sub oscillation) Ta = + 25°C, When LVD is off 1 * Ta = + 85°C, When LVD is off 1 * Ta = + 25°C, When LVD is off *1, *4 Ta = + 85°C, When LVD is off *1, *4 Ta = + 25°C, When LVD is off *1, *4 Ta = + 85°C, When LVD is off *1, *4 17.5 23.7 mA 8 11 mA 1.9 3.1 mA 120 810 μA 140 830 μA 11 15 mA 0.82 1.7 mA 105 800 μA 125 810 μA 11 38 μA - 370 μA 15 45 μA - 440 μA 13 40 μA - 380 μA *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3:When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) 7 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Parameter Symbol Pin name Conditions Deep Standby STOP mode ICCHD Power supply current VCC ICCRD Deep Standby RTC mode (sub oscillation) Ta = + 25°C, When LVD is off, When RAM is off *1, *3 Ta = + 25°C, When LVD is off, When RAM is on *1, *3 Ta = + 85°C, When LVD is off, When RAM is off *1, *3 Ta = + 85°C, When LVD is off, When RAM is on *1, *3 Ta = + 25°C, When LVD is off, When RAM is off *1, *3, *5 Ta = + 25°C, When LVD is off, When RAM is on *1, *3, *5 Ta = + 85°C, When LVD is off, When RAM is off *1, *3, *5 Ta = + 85°C, When LVD is off, When RAM is on *1, *3, *5 Value Unit Remarks Typ Max 1.4 10 μA 8.6 23 μA 120 μA 190 μA 2.0 12 μA 9.2 25 μA 125 μA 195 μA - - Low-voltage For detection 0.13 0.3 μA occurrence of reset circuit (LVD) At operation ICCLVD For power 0.3 0.13 μA occurrence supply of interrupt current Flash Memory 11.2 mA *4 At Write/Erase 9.5 ICCFLASH Write/Erase current *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: RAM on/off setting is on-chip SRAM only. *4: The current at which to write or erase Flash memory, "ICCFLASH" is added to "ICC". *5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 77 D a t a S h e e t (2) Pin Characteristics (VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions CMOS hysteresis input pin, MD0, MD1 V CC≥ 2.7 V V CC × 0.8 VCC < 2.7 V VCC × 0.7 VCC ≥ 2.7 V VCC × 0.8 VCC < 2.7 V VCC × 0.7 "H" level input voltage (hysteresis input) "L" level input voltage (hysteresis input) 5V tolerant input pin VILS CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin "H" level output voltage VOH "L" level output voltage VOL 4mA type IIL - RPU Pull-up pin Input leak current Pull-up resistor value Input capacitance 7 VIHS CIN 4mA type Other than VCC, VSS, AVCC, AVSS, AVRH Min Value Typ Max - VCC + 0.3 V - VSS + 5.5 V V CC ≥ 2.7 V VCC × 0.2 VSS - 0.3 - VCC < 2.7 V V VCC × 0.3 VCC ≥ 2.7 V VCC × 0.2 VSS - 0.3 - VCC < 2.7 V VCC ≥ 2.7 V, IOH = - 4mA V CC < 2.7 V, IOH = - 2mA VCC ≥ 2.7 V, IOL = 4mA Unit Remarks V VCC × 0.3 VCC - 0.5 - VCC V VSS - 0.4 V - -5 - +5 μA VCC ≥ 2.7 V 21 33 66 VCC < 2.7 V, IOL = 2mA VCC - 0.45 kΩ VCC < 2.7 V - - 134 - - 5 15 pF MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t 4. AC Characteristics (1) Main Clock Input Characteristics (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Input frequency Input clock cycle Input clock pulse width Input clock rising time and falling time Symbol Pin Conditions name Value Min Max Unit VCC ≥ 2.7V VCC < 2.7V 4 4 48 20 MHz - 4 48 MHz - 20.83 250 ns - PWH/tCYLH, PWL/tCYLH 45 55 % tCF, tCR - - 5 ns - - 40 MHz FCH tCYLH X0, X1 When crystal oscillator is connected When using external clock When using external clock When using external clock When using external clock Master clock Base clock 40 MHz FCC (HCLK/FCLK) Internal operating 40 MHz APB0 bus clock*2 clock*1 frequency FCP0 FCP1 40 MHz APB1 bus clock*2 40 MHz APB2 bus clock*2 FCP2 Base clock tCYCC 25 ns (HCLK/FCLK) Internal operating tCYCP0 25 ns APB0 bus clock*2 clock*1 cycle time tCYCP1 25 ns APB1 bus clock*2 2 tCYCP2 25 ns APB2 bus clock* *1: For more information about each internal operating clock, see "Chapter: Clock" in "FM3 Family PERIPHERAL MANUAL". *2: For about each APB bus which each peripheral is connected to, see " BLOCK DIAGRAM" in this data sheet. FCM - Remarks X0 April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 79 D a t a S h e e t (2) Sub Clock Input Characteristics (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Pin Symbol Conditions name Value Typ Min Unit Max Remarks When crystal oscillator is connected* Input frequency FCL When using 32 100 kHz X0A, external clock X1A When using Input clock cycle 10 31.25 μs tCYLL external clock Input clock pulse PWH/tCYLL, When using 45 55 % width PWL/tCYLL external clock *: For more information about crystal oscillator, see "Sub crystal oscillator" in "HANDLING DEVICES". - - 32.768 - kHz X0A (3) Built-in CR Oscillation Characteristics  Built-in high-speed CR (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Clock frequency Min Value Typ Max Ta = + 25°C, VCC ≥ 2.7V 3.94 4 4.06 Ta = - 20°C to + 85°C, VCC ≥ 2.7V 3.92 4 4.08 Ta = - 40°C to + 85°C, VCC ≥ 2.7V 3.88 4 4.12 Ta = + 25°C, VCC < 2.7V 3.9 4 4.1 3.66 4 4.20 2.8 4 5.2 Symbol FCRH Conditions Unit Remarks When trimming*1 MHz Ta = - 40°C to + 85°C VCC < 2.7V Ta = - 40°C to + 85°C When not trimming Frequency 30 μs *2 tCRWT stabilization time *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value. This period is able to use high-speed CR clock as source clock.  Built-in low-speed CR (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Clock frequency 8 Symbol Conditions FCRL - Min Value Typ Max 50 100 150 Unit Remarks kHz MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t (4-1) Operating Conditions of Main PLL (In the case of using main clock for input of PLL) (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time*1 100 μs tLOCK (LOCK UP time) PLL input clock frequency FPLLI 4 16 MHz PLL multiplication rate 5 37 multiplier PLL macro oscillation clock frequency FPLLO 75 150 MHz Main PLL clock frequency*2 40 MHz FCLKPLL *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM3 Family PERIPHERAL MANUAL". (4-2) Operating Conditions of Main PLL (In the case of using the built-in high-speed CR for input clock of main PLL) (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Min Value Typ Max Unit Remarks PLL oscillation stabilization wait time*1 100 μs tLOCK (LOCK UP time) PLL input clock frequency FPLLI 3.8 4 4.2 MHz PLL multiplication rate 19 35 multiplier PLL macro oscillation clock frequency FPLLO 72 150 MHz Main PLL clock frequency*2 40 MHz FCLKPLL *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM3 Family PERIPHERAL MANUAL". Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency has been trimmed. April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 81 D a t a S h e e t (5) Reset Input Characteristics (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Reset input time Symbol tINITX Value Pin Conditions name Min Max INITX 500 - - Unit Remarks ns (6) Power-on Reset Timing (VCC= 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Power supply rising time Tr Power supply shut down time Pin name VCC Toff Tr Value Unit Min Max 0 - ms 1 - ms Remarks Toff 1.65V VCC 0.2V 8 0.2V 0.2V MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t (7) External Bus Timing  External bus clock output characteristics (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Min Max Unit VCC ≥ 2.7 V 40 MHz VCC < 2.7 V 20 MHz *: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see "Chapter: External Bus Interface" in "FM3 Family PERIPHERAL MANUAL". Output frequency tCYCLE MCLKOUT* 0.8 × Vcc 0.8 × Vcc MCLK tCYCLE  External bus signal input/output characteristics (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Signal input characteristics Signal output characteristics Symbol Conditions VIH VIL VOH - VOL Input signal VIH VIL VIH VIL Output signal VOH VOL VOH VOL April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Value Unit 0.8 × VCC V 0.2 × VCC V 0.8 × VCC V 0.2 × VCC V Remarks 83 D a t a S h e e t  Separate Bus Access Asynchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Min VCC ≥ 2.7V MOEX MOEX tOEW MCLK×n-3 Min pulse width VCC < 2.7V -9 VCC ≥ 2.7V MCSX ↓ → Address MCSX[7:0], tCSL – AV output delay time MAD[24:0] -12 VCC < 2.7V VCC ≥ 2.7V MOEX ↑ → MOEX, tOEH - AX 0 Address hold time MAD[24:0] VCC < 2.7V MCLK×m-9 VCC ≥ 2.7V MCSX ↓ → tCSL - OEL MOEX ↓ delay time MOEX, VCC < 2.7V MCLK×m-12 MCSX[7:0] VCC ≥ 2.7V MOEX ↑ → tOEH - CSH 0 MCSX ↑ time VCC < 2.7V MCLK×m-9 VCC ≥ 2.7V MCSX ↓ → MCSX, tCSL - RDQML MDQM ↓ delay time MDQM[1:0] VCC < 2.7V MCLK×m-12 20 VCC ≥ 2.7V Data set up → MOEX, tDS - OE MOEX ↑ time MADATA[15:0] 38 VCC < 2.7V VCC ≥ 2.7V MOEX ↑ → MOEX, tDH - OE 0 Data hold time MADATA[15:0] VCC < 2.7V VCC ≥ 2.7V MWEX MWEX tWEW MCLK×n-3 Min pulse width VCC < 2.7V VCC ≥ 2.7V MWEX ↑ → Address MWEX, tWEH - AX 0 output delay time MAD[24:0] VCC < 2.7V MCLK×n-9 VCC ≥ 2.7V MCSX ↓ → tCSL - WEL MWEX ↓ delay time MCLK×n-12 MWEX, VCC < 2.7V MCSX[7:0] VCC ≥ 2.7V MWEX ↑ → tWEH - CSH 0 MCSX ↑ delay time VCC < 2.7V MCLK×n-9 MCSX ↓→ MCSX, VCC ≥ 2.7V tCSL-WDQML MDQM ↓ delay time MDQM[1:0] MCLK×n-12 VCC < 2.7V MCLK-9 VCC ≥ 2.7V MCSX ↓→ MCSX, tCSL-DV Data output time MADATA[15:0] MCLK-12 VCC < 2.7V VCC ≥ 2.7V MWEX ↑ → MWEX, tWEH - DX 0 Data hold time MADATA[15:0] VCC < 2.7V Note: When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16). 8 Max +9 +12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 - Unit ns ns ns ns ns ns ns - ns - ns MCLK×m+9 MCLK×m+12 MCLK×n+9 MCLK×n+12 MCLK×m+9 MCLK×m+12 MCLK×n+9 MCLK×n+12 MCLK+9 MCLK+12 MCLK×m+9 MCLK×m+12 ns ns ns ns ns ns MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t MCLK MCSX[7:0] MAD[24:0] MOEX MDQM[1:0] MW EX MADATA[15:0] April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 85 D a t a S h e e t  Separate Bus Access Synchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Address delay time Symbol Pin name Conditions tAV MCLK, MAD[24:0] VCC ≥ 2.7V VCC < 2.7V VCC ≥ 2.7V VCC < 2.7V V CC ≥ 2.7V VCC < 2.7V VCC ≥ 2.7V VCC < 2.7V V CC ≥ 2.7V VCC < 2.7V VCC ≥ 2.7V VCC < 2.7V VCC ≥ 2.7V VCC < 2.7V VCC ≥ 2.7V VCC < 2.7V V CC ≥ 2.7V VCC < 2.7V VCC ≥ 2.7V VCC < 2.7V VCC ≥ 2.7V VCC < 2.7V VCC ≥ 2.7V VCC < 2.7V VCC ≥ 2.7V VCC < 2.7V tCSL MCLK, MCSX[7:0] MCSX delay time tCSH tREL MCLK, MOEX MOEX delay time tREH Data set up → MCLK ↑ time MCLK ↑ → Data hold time MCLK, MADATA[15:0] MCLK, MADATA[15:0] tDS tDH tWEL MCLK, MWEX MWEX delay time tWEH MDQM[1:0] delay time tDQML t DQMH MCLK, MDQM[1:0] MCLK ↑ → MCLK, tODS Data output time MADATA[15:0] MCLK ↑ → MCLK, tOD Data hold time MADATA[15:0] Note: When the external load capacitance CL = 30pF. Value Min 1 1 1 1 1 Max 9 12 9 12 9 12 9 12 9 12 Unit ns ns ns ns ns 19 37 - ns 0 - ns 1 1 1 1 MCLK+1 1 9 12 9 12 9 12 9 12 MCLK+18 MCLK+24 18 24 ns ns ns ns ns ns tCYCLE MCLK tCSL tCSH MCSX[7:0] tAV MAD[24:0] tAV Address Address tREL tREH tDQML tDQMH MOEX tDQML tDQMH tWEL tWEH MDQM[1:0] MWEX tDS tDH tOD MADATA[15:0] RD WD Invalid tODS 8 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t  Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Min VCC ≥ 2.7V Multiplexed 0 tALE-CHMADV address delay time MALE, VCC < 2.7V MADATA[15:0] VCC ≥ 2.7V MCLK×n+0 Multiplexed tCHMADH address hold time VCC < 2.7V MCLK×n+0 Note: When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16). Max +10 +20 MCLK×n+10 MCLK×n+20 Unit ns ns MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 87 D a t a S h e e t  Multiplexed Bus Access Synchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Symbol tCHAL MALE delay time tCHAH Pin name Conditions MCLK, ALE VCC ≥ 2.7V VCC < 2.7V V CC ≥ 2.7V VCC < 2.7V MCLK ↑ → Multiplexed tCHMADV Address delay time MCLK, MADATA[15:0] MCLK ↑ → Multiplexed tCHMADX Data output time Note: When the external load capacitance CL = 30pF. VCC ≥ 2.7V Value Min Max 9 12 9 12 ns ns ns ns 1 tOD ns 1 tOD ns 1 1 VCC < 2.7V VCC ≥ 2.7V VCC < 2.7V Unit Remarks MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MW EX MADATA[15:0] 8 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t  NAND Flash Memory Mode (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Min MNREX VCC ≥ 2.7V MNREX tNREW MCLK×n-3 Min pulse width VCC < 2.7V 20 VCC ≥ 2.7V Data setup → MNREX, tDS – NRE MNREX↑time MADATA[15:0] VCC < 2.7V 38 VCC ≥ 2.7V MNREX↑→ MNREX, tDH – NRE 0 Data hold time MADATA[15:0] VCC < 2.7V MNALE↑→ MNALE, VCC ≥ 2.7V MCLK×m-9 tALEH - NWEL MNWEX delay time MNWEX VCC < 2.7V MCLK×m-12 VCC ≥ 2.7V MCLK×m-9 MNALE↓→ MNALE, tALEL - NWEL MNWEX delay time MNWEX VCC < 2.7V MCLK×m-12 VCC ≥ 2.7V MCLK×m-9 MNCLE↑→ MNCLE, tCLEH - NWEL MNWEX delay time MNWEX VCC < 2.7V MCLK×m-12 MNWEX↑→ MNCLE, VCC ≥ 2.7V tNWEH - CLEL 0 MNCLE delay time MNWEX VCC < 2.7V VCC ≥ 2.7V MNWEX MNWEX tNWEW MCLK×n-3 Min pulse width VCC < 2.7V -9 VCC ≥ 2.7V MNWEX↓→ MNWEX, tNWEL – DV Data output time MADATA[15:0] VCC < 2.7V -12 MNWEX↑→ MNWEX, VCC ≥ 2.7V tNWEH – DX 0 Data hold time MADATA[15:0] VCC < 2.7V Note: When the external load capacitance CL = 30pF (m=0 to 15, n=1 to 16). April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Max Unit - ns - ns - ns MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 +9 +12 MCLK×m+9 MCLK×m+12 ns ns ns ns ns ns ns 89 D a t a S h e e t NAND Flash Memory Read MCLK MNREX MADATA[15:0] Read NAND Flash Memory Address Write MCLK MNALE MNCLE MNW EX MADATA[15:0] 9 Write MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t NAND Flash Memory Command Write MCLK MNALE MNCLE MNW EX MADATA[15:0] April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Write 91 D a t a S h e e t  External Ready Input Timing (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter MCLK ↑ MRDY input setup time  Symbol tRDYI Pin name Conditions MCLK, MRDY Value Min VCC ≥ 2.7V 19 VCC < 2.7V 37 Max - Unit Remarks ns When RDY is input ··· MCLK Over 2cycles Original MOEX MWEX tRDYI MRDY  When RDY is released MCLK ··· ··· 2 cycles Extended MOEX MWEX tRDYI 0.5×VCC MRDY 9 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t (8) Base Timer Input Timing  Timer input timing (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Input pulse width Symbol Pin name Conditions tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - Min Value Max - 2tCYCP Unit Remarks ns tTIWL tTIWH ECK TIN  VIHS VIHS VILS VILS Trigger input timing (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Input pulse width Symbol Pin name Conditions tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS Min Value Max 2tCYCP - Unit Remarks ns tTRGL VIHS VILS VILS Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see "BLOCK DIAGRAM" in this data sheet. April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 93 D a t a S h e e t (9) CSIO Timing  Synchronous serial (SPI = 0, SCINV = 0) (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Pin Symbol Conditions name Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK falling time SCK rising time tF tR SCKx SCKx, SOTx Internal shift clock SCKx, operation SINx SCKx, SINx SCKx, External shift SOTx clock SCKx, operation SINx SCKx, SINx SCKx SCKx VCC < 2.7V Min Max VCC ≥ 2.7V Min Max Unit 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns 2tCYCP 10 tCYCP + 10 - 2tCYCP 10 tCYCP + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30pF. 9 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI tSHIXI VIH VIL VIH VIL SIN MS bit = 0 tSLSH SCK VIH tF SOT VIL tSHSL VIL VIH VIH tR tSLOVE VOH VOL SIN tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 95 D a t a S h e e t  Synchronous serial (SPI = 0, SCINV = 1) (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Pin Symbol Conditions name Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓ → SIN hold time tSLIXI SCKx SCKx, SOTx Internal shift clock SCKx, operation SINx SCKx, SINx Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓ → SIN hold time tSLIXE SCK falling time SCK rising time tF tR SCKx, External shift SOTx clock SCKx, operation SINx SCKx, SINx SCKx SCKx VCC < 2.7V Min Max VCC ≥ 2.7V Min Max Unit 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns 2tCYCP 10 tCYCP + 10 - 2tCYCP 10 tCYCP + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30pF. 9 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t tSCYC SCK VOH VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL SCK SOT VIH VIL tR tSHOVE tSLSH VIH VIL VIL tF VOH VOL SIN tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 97 D a t a S h e e t  Synchronous serial (SPI = 1, SCINV = 0) (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Pin Symbol Conditions name Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time t IVSLI SCK ↓→ SIN hold time t SLIXI SOT → SCK ↓ delay time tSOVLI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓→ SIN hold time tSLIXE SCK falling time SCK rising time tF tR SCKx SCKx, SOTx SCKx, Internal shift SINx clock operation SCKx, SINx SCKx, SOTx SCKx, External shift SOTx clock SCKx, operation SINx SCKx, SINx SCKx SCKx VCC < 2.7V Min Max VCC ≥ 2.7V Min Max Unit 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns - ns 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30pF. 9 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t tSCYC VOH VOL SCK SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL t SHOVI tSOVLI VIH VIL MS bit = 0 tSLSH SCK VIH tR VIH tSHOVE VOH VOL VOH VOL tIVSLE SIN VIH VIL tF * SOT VIL tSHSL tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 99 D a t a S h e e t  Synchronous serial (SPI = 1, SCINV = 1) (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Pin Symbol Conditions name VCC < 2.7V Min Max VCC ≥ 2.7V Min Max Unit Serial clock cycle time tSCYC SCKx 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI 0 - 0 - ns SOT → SCK ↑ delay time tSOVHI SCKx, Internal shift clock SINx operation SCKx, SINx SCKx, SOTx - ns Serial clock "L" pulse width tSLSH SCKx - ns Serial clock "H" pulse width tSHSL SCKx - ns SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK falling time SCK rising time tF tR SCKx, External shift SOTx clock SCKx, operation SINx SCKx, SINx SCKx SCKx 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30pF. 1 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t tSCYC VOH SCK VOH VOL tSOVHI tSLOVI VOH VOL SOT VOH VOL tSHIXI tIVSHI VIH VIL SIN VIH VIL MS bit = 0 SCK tSLSH tSHSL tR VIH VIL VIH tF tSHIXE t IVSHE VIH VIL VIH VIL SIN VIH t SLOVE VOH VOL VOH VOL SOT VIL VIL MS bit = 1  External clock (EXT = 1) : asynchronous only (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Value Symbol Conditions Serial clock "L" pulse width Serial clock "H" pulse width SCK falling time SCK rising time tSLSH tSHSL tF tR CL = 30pF tR SCK VIL April 4, 2014, MB9AF156RA_DS706-00047-2v0-E t V IH Min Max tCYCP + 10 tCYCP + 10 - 5 5 Unit Remarks ns ns ns ns t SHSL SLSH V IH VIL VIL V IH 101 D a t a S h e e t (10) External Input Timing (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max ADTG FRCKx - 2tCYCP*1 - ns 2tCYCP + 100*1 - ns - ns ICxx Input pulse width tINH, tINL DTIxX INT00 to INT15, NMIX - 2 500* Remarks A/D converter trigger input Free-run timer input clock Input capture Waveform generator External interrupt, NMI Deep standby wake up *1 : tCYCP indicates the APB bus clock cycle time except stop when in STOP mode, in TIMER mode. About the APB bus number which the Multi-function Timer is connected to, see "BLOCK DIAGRAM" in this data sheet. *2 : When in STOP mode, in TIMER mode. *3 : When in Deep standby RTC mode, in Deep standby STOP mode. WKUPx 1 - 600*3 - ns MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t (11) Quadrature Position/Revolution Counter timing (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Conditions Value Min Max AIN pin "H" width tAHL AIN pin "L" width tALL BIN pin "H" width tBHL BIN pin "L" width tBLL BIN rising time from PC_Mode2 or tAUBU AIN pin "H" level PC_Mode3 AIN falling time from PC_Mode2 or tBUAD BIN pin "H" level PC_Mode3 BIN falling time from PC_Mode2 or tADBD AIN pin "L" level PC_Mode3 AIN rising time from PC_Mode2 or tBDAU BIN pin "L" level PC_Mode3 AIN rising time from PC_Mode2 or tBUAU BIN pin "H" level PC_Mode3 2tCYCP* BIN falling time from PC_Mode2 or tAUBD AIN pin "H" level PC_Mode3 AIN falling time from PC_Mode2 or tBDAD BIN pin "L" level PC_Mode3 BIN rising time from PC_Mode2 or tADBU AIN pin "L" level PC_Mode3 ZIN pin "H" width tZHL QCR:CGSC="0" ZIN pin "L" width tZLL QCR:CGSC="0" AIN/BIN rising and falling time from determined ZIN QCR:CGSC="1" tZABE level Determined ZIN level from AIN/BIN rising and falling QCR:CGSC="1" tABEZ time *: tCYCP indicates the APB bus clock cycle time except stop when in STOP mode, in TIMER mode. About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see "BLOCK DIAGRAM" in this data sheet. Unit ns AIN BIN April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 103 D a t a S h e e t BIN AIN ZIN ZIN AIN/BIN 1 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t 2 (12) I C Timing (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max Parameter Symbol SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ SCL clock "L" width SCL clock "H" width (Repeated) START condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ STOP condition setup time SCL ↑ → SDA ↑ Bus free time between "STOP condition" and "START condition" FSCL 0 100 0 400 kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs 4.7 - 0.6 - μs 0 3.45*2 0 0.9*3 μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs tSUSTA tHDDAT CL = 30pF, R = (Vp/IOL)*1 2 2 ns t CYCP*4 tCYCP*4 *1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see "BLOCK DIAGRAM" in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. Noise filter tSP - SDA SCL April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 105 D a t a S h e e t (13) ETM Timing (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Data hold TRACECLK frequency Symbol Pin name tETMH TRACECLK, TRACED[3:0] 1/ tTRACE TRACECLK TRACECLK clock cycle tTRACE Conditions Value Unit Min Max VCC ≥ 2.7V 2 11 VCC < 2.7V 2 15 VCC ≥ 2.7V - 40 MHz VCC < 2.7V - 20 MHz VCC ≥ 2.7V 25 - ns VCC < 2.7V 50 - ns Remarks ns Note: When the external load capacitance CL = 30pF. HCLK TRACECLK TRACED[3:0] 1 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t (14) JTAG Timing (VCC = 1.65V to 3.6V, VSS = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC ≥ 2.7V VCC < 2.7V VCC ≥ 2.7V VCC < 2.7V VCC ≥ 2.7V TMS, TDI setup time tJTAGS TMS, TDI hold time tJTAGH TCK, TMS, TDI TCK, TMS, TDI TDO delay time tJTAGD TCK, TDO VCC < 2.7V Note: When the external load capacitance CL = 30pF. Value Min Max Unit 15 - ns 15 - ns - 25 - 45 Remarks ns TCK TMS/TDI TDO April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 107 D a t a S h e e t 5. 12-bit A/D Converter  Electrical Characteristics for the A/D Converter (VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, Ta = - 40°C to + 85°C) Parameter Resolution Integral Nonlinearity Differential Nonlinearity Zero transition voltage Full-scale transition voltage Conversion time Pin Symbol name Min Value Typ Max Unit - - - 4.5 - 12 + 4.5 bit LSB - - - 2.5 - + 2.5 LSB VZT ANxx - 15 - + 15 mV VFST ANxx AVRH - 15 - AVRH + 15 mV 2.0* 0.6 1.2 3.0 100 200 500 - - μs 10 us - 1000 ns - - 1.0 μs - 0.27 0.42 mA - 0.03 10 μA - 0.72 1.29 mA - 0.02 2.6 μA pF LSB μA - - Sampling time*2 Ts - Compare clock cycle*3 Tcck - State transition time to operation permission Tstt - Power supply current (analog + digital) - AVCC - AVRH 1 Reference power supply current (between AVRH to AVSS) Analog input capacity CAIN - - - Analog input resistor RAIN - - - Interchannel disparity Analog port input current Analog input voltage - - - - 9.4 2.2 5.5 10.5 4 - ANxx - - 5 - ANxx kΩ Remarks AVCC ≥ 2.7V AVCC ≥ 2.7V 1.8V< AVCC < 2.7V 1.65V< AVCC < 1.8V AVCC ≥ 2.7V 1.8V< AVCC < 2.7V 1.65V< AVCC < 1.8V A/D 1unit operation When A/D stop (All unit) A/D 1unit operation AVRH=3.6V When A/D stop (All unit) AVCC ≥ 2.7V 1.8V< AVCC < 2.7V 1.65V< AVCC < 1.8V AVSS AVRH V 2.7 AVCC ≥ 2.7V Reference voltage AVRH AVCC V AVCC AVCC < 2.7V *1: The conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is when the value of sampling time: 600ns, the value of compare time: 1400ns (AVCC ≥ 2.7V). Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck). For setting of the sampling time and compare clock cycle, see "Chapter: A/D Converter" in "FM3 Family PERIPHERAL MANUAL Analog Macro Part". The A/D Converter register are reflected in the operation according to the APB bus clock timing. The sampling clock and compare clock is generated from the Base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see "BLOCK DIAGRAM" in this data sheet. *2: A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1). *3: The compare time (Tc) is the value of (Equation 2). 1 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Rext ANxx Analog input pin Analog signal source RAIN Comparator CAIN (Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9 Ts : Sampling time[ns] RAIN : input resistor of A/D[kΩ] = 2.2kΩ at 2.7V < AVCC < 3.6V input resistor of A/D[kΩ] = 5.5kΩ at 1.8V < AVCC < 2.7V input resistor of A/D[kΩ] = 10.5kΩ at 1.65V < AVCC < 1.8V CAIN : input capacity of A/D[pF] = 9.4pF at 1.65V < AVCC < 3.6V Rext : Output impedance of external circuit[kΩ] (Equation 2) Tc = Tcck × 14 Tc : Compare time Tcck : Compare clock cycle April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 109 D a t a S h e e t  Definition of 12-bit A/D Converter Terms  Resolution  Integral Nonlinearity  Differential Nonlinearity : Analog variation that is recognized by an A/D converter. : Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics. : Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity Differential Nonlinearity 0xFFF Actual conversion characteristics 0xFFE 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD 0xN Actual conversion characteristics Ideal characteristics V(N+1)T 0x(N-1) (Actually-measured value) Actual conversion characteristics Ideal characteristics 0x002 VNT (Actually-measured value) 0x(N-2) 0x001 VZT (Actually-measured value) AVSS Actual conversion characteristics AVRH AVSS AVRH Analog input Integral Nonlinearity of digital output N = Analog input VNT -{1LSB×(N-1)+VZT} 1LSB Differential Nonlinearity of digital output N = 1LSB = N VZT VFST VNT 110 V(N+1)T -VNT 1LSB [LSB] - 1 [LSB] VFST -VZT 4094 : A/D converter digital output value. : Voltage at which the digital output changes from 0x000 to 0x001. : Voltage at which the digital output changes from 0xFFE to 0xFFF. : Voltage at which the digital output changes from 0x(N − 1) to 0xN. MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t 6. Low-Voltage Detection Characteristics (1) Low-Voltage Detection Reset (Ta = - 40°C to + 85°C) Parameter Symbol Conditions Min Value Typ Max Unit Remarks Detected voltage VDL 1.38 1.50 1.60 V When voltage drops SVHR*1 = 00000 Released voltage VDH 1.43 1.55 1.65 V When voltage rises Detected voltage VDL 1.43 1.55 1.65 V When voltage drops 1 SVHR* = 00001 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 1.47 1.60 1.73 V When voltage drops SVHR*1 = 00010 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 1.52 1.65 1.78 V When voltage drops SVHR*1 = 00011 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 1.56 1.70 1.84 V When voltage drops SVHR*1 = 00100 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 1.61 1.75 1.89 V When voltage drops SVHR*1 = 00101 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 1.66 1.80 1.94 V When voltage drops SVHR*1 = 00110 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 1.70 1.85 2.00 V When voltage drops SVHR*1 = 00111 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 1.75 1.90 2.05 V When voltage drops 1 SVHR* = 01000 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 1.79 1.95 2.11 V When voltage drops SVHR*1 = 01001 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 1.84 2.00 2.16 V When voltage drops SVHR*1 = 01010 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 1.89 2.05 2.21 V When voltage drops SVHR*1 = 01011 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 2.30 2.50 2.70 V When voltage drops 1 SVHR* = 01100 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 2.39 2.60 2.81 V When voltage drops SVHR*1 = 01101 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 2.48 2.70 2.92 V When voltage drops SVHR*1 = 01110 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 2.58 2.80 3.02 V When voltage drops SVHR*1 = 01111 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 2.67 2.90 3.13 V When voltage drops 1 SVHR* = 10000 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 2.76 3.00 3.24 V When voltage drops SVHR*1 = 10001 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 2.85 3.10 3.35 V When voltage drops SVHR*1 = 10010 Released voltage VDH Same as SVHR = 00000 value V When voltage rises Detected voltage VDL 2.94 3.20 3.46 V When voltage drops SVHR*1 = 10011 Released voltage VDH Same as SVHR = 00000 value V When voltage rises LVD stabilization 5200 × μs TLVDW wait time tCYCP*2 LVD detection 200 μs TLVDDL delay time *1: The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to "00000" by Low-Voltage Detection Reset. *2: tCYCP indicates the APB2 bus clock cycle time. April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 111 D a t a S h e e t (2) Interrupt of Low-Voltage Detection (Ta = - 40°C to + 85°C) Parameter Symbol Conditions Detected voltage VDL SVHI = 00100 Released voltage VDH Detected voltage VDL SVHI = 00101 Released voltage VDH Detected voltage VDL SVHI = 00110 Released voltage VDH Detected voltage VDL SVHI = 00111 Released voltage VDH Detected voltage VDL SVHI = 01000 Released voltage VDH Detected voltage VDL SVHI = 01001 Released voltage VDH Detected voltage VDL SVHI = 01010 Released voltage VDH Detected voltage VDL SVHI = 01011 Released voltage VDH Detected voltage VDL SVHI = 01100 Released voltage VDH Detected voltage VDL SVHI = 01101 Released voltage VDH Detected voltage VDL SVHI = 01110 Released voltage VDH Detected voltage VDL SVHI = 01111 Released voltage VDH Detected voltage VDL SVHI = 10000 Released voltage VDH Detected voltage VDL SVHI = 10001 Released voltage VDH Detected voltage VDL SVHI = 10010 Released voltage VDH Detected voltage VDL SVHI = 10011 Released voltage VDH LVD stabilization TLVDW wait time LVD detection delay TLVDDL time *: tCYCP indicates the APB2 bus clock cycle time. 112 Min Value Typ 1.56 1.61 1.61 1.66 1.66 1.70 1.70 1.75 1.75 1.79 1.79 1.84 1.84 1.89 1.89 1.93 2.30 2.39 2.39 2.48 2.48 2.58 2.58 2.67 2.67 2.76 2.76 2.85 2.85 2.94 2.94 3.04 1.70 1.75 1.75 1.80 1.80 1.85 1.85 1.90 1.90 1.95 1.95 2.00 2.00 2.05 2.05 2.10 2.50 2.60 2.60 2.70 2.70 2.80 2.80 2.90 2.90 3.00 3.00 3.10 3.10 3.20 3.20 3.30 - - - - Max 1.84 1.89 1.89 1.94 1.94 2.00 2.00 2.05 2.05 2.11 2.11 2.16 2.16 2.21 2.21 2.27 2.70 2.81 2.81 2.92 2.92 3.02 3.02 3.13 3.13 3.24 3.24 3.35 3.35 3.46 3.46 3.56 5200 × tCYCP* 200 Unit Remarks V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises μs μs MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t 7. Flash Memory Write/Erase Characteristics (1) Write / Erase time (VCC = 1.65V to 3.6V, Ta = - 40°C to + 85°C) Parameter Min Large Sector Sector erase time Value Typ Max 1.1 2.7 Small Sector Unit s 0.3 0.9 Half word (16-bit) write time - 30 528 μs Chip erase time - 11.2 30.5 s Remarks Includes write time prior to internal erase Not including system-level overhead time Includes write time prior to internal erase (2) Write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) 1,000 20* Remarks 10,000 10* *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at + 85°C) . April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 113 D a t a S h e e t  ORDERING INFORMATION Part number MB9AF154MAPMC MB9AF155MAPMC Package Plastic  LQFP 80-pin (0.5mm pitch), (FPT-80P-M37) MB9AF156MAPMC MB9AF154MAPMC1 MB9AF155MAPMC1 Plastic  LQFP 80-pin (0.65mm pitch), (FPT-80P-M40) MB9AF156MAPMC1 MB9AF154MABGL MB9AF155MABGL Plastic  PFBGA 96-pin (0.5mm pitch), (BGA-96P-M07) MB9AF156MABGL MB9AF154NAPMC MB9AF155NAPMC Plastic  LQFP 100-pin (0.5mm pitch), (FPT-100P-M23) MB9AF156NAPMC MB9AF154NAPQC MB9AF155NAPQC MB9AF156NAPQC MB9AF154NABGL MB9AF155NABGL Plastic  QFP 100-pin (0.65mm pitch), (FPT-100P-M36) Plastic  PFBGA 112-pin (0.8mm pitch), (BGA-112P-M04) MB9AF156NABGL MB9AF154RAPMC MB9AF155RAPMC Plastic  LQFP 120-pin (0.5mm pitch), (FPT-120P-M37) MB9AF156RAPMC 114 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t  PACKAGE DIMENSIONS 120-pin plastic LQFP (FPT-120P-M37) 120-pin plastic LQFP (FPT-120P-M37) Lead pitch 0.50 mm Package width × package length 16.0 mm × 16.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.88 g Code (Reference) P-LFQFP120-16 × 16-0.50 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 18.00±0.20(.709±.008)SQ * 16.00 ± 0.10(.630 ± .004) SQ 90 61 91 Details of "A" part 60 +0.20 +.008 1.50 –0.10 .059 –.004 (Mounting height) 0.25(.010) 0.08(.003) 0˚~8˚ INDEX 0.60 ± 0.15 (.024 ± .006) "A" 120 LEAD No. 1 30 0.50(.020) C 0.10 ± 0.05 (.004 ± .002) (Stand off) 31 +0.05 0.145 –0.03 +.002 ) ( .006–.001 0.22 ± 0.05 (.009 ± .002) 0.08(.003) 2010 FUJITSU SEMICONDUCTOR LIMITED F120037Sc(1)-1-1 April 4, 2014, MB9AF156RA_DS706-00047-2v0-E M Dimensions in mm (inches). Note: The values in parentheses are reference values 115 D a t a S h e e t 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.00 mm × 14.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.65 g (FPT-100P-M23) 100-pin plastic LQFP (FPT-100P-M23) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ *14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part 1.50 +0.20 - 0.10 (.059+.008 -.004 ) (Mounting height) INDEX 100 26 "A" 1 C 0.60±0.15 (.024±.006) 25 0.50(.020) 0.22±0.05 (.009±.002) 0.08(.003) 0°~8° 0.50±0.20 (.020±.008) M 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 0.145±0.055 (.006±.002) 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4 Dimensions in mm (inches). Note:The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 116 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t 100-pin plastic QFP Lead pitch 0.65 mm Package width × package length 14.00 mm × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP100-14 × 20-0.65 (FPT-100P-M36) 100-pin plastic QFP (FPT-100P-M36) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 81 50 0.10(.004) 17.90± 0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 1 30 0.65(.026) 0.32 ± 0.05 (.013±.002) 0.13(.005) "A" C 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8° 31 2011 FUJITSU SEMICONDUCTOR LIMITED HMbF100-36Sc-1-1 April 4, 2014, MB9AF156RA_DS706-00047-2v0-E M 0.17 ± 0.06 (.007 ±. 002) 0.80 ± 0.20 (.031 ±. 008) 0.88 ± 0.15 (.035 ±. 006) 0.25 ± 0.20 (.010 ±. 008) (Stand off) Dimensions in mm (inches). Note: The valuesin parentheses are reference values. 117 D a t a S h e e t 80-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g (FPT-80P-M37) 80-pin plastic LQFP (FPT-80P-M37) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00± 0.20(.551 ± .008)SQ 0.145 ± 0.055 (.006 ± .002) *12.00± 0.10(.472 ± .004)SQ 60 41 Details of "A" part 61 40 +0.20 1.50 –0.10 (Mounting height) +.008 .059 –.004 0.25(.010) 0~8° 0.08(.003) INDEX 80 0.50 ± 0.20 (.020 ± .008) 0.60 ± 0.15 (.024 ± .006) 0.10 ± 0.05 (.004 ± .002) (Stand off) 21 "A" 1 20 0.50(.020) 0.22 ± 0.05 0.08(.003) M (.009 ± .002) C 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 118 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t 80-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 14.00 mm × 14.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.60 mm Max. Code (Reference) P-LQFP80-14 × 14-0.65 (FPT-80P-M40) 80-pin plastic LQFP (FPT-80P-M40) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ *14.00±0.10(.551±.004)SQ 60 0.145±0.055 (.006±.002) 41 Details of "A" part 61 40 1.50±0.10 (.059±.004) 0.25(.010) 0.10(.004) 0˚~7˚ INDEX 0.50±0.20 (.020±.008) 80 21 0.10±0.05 (.004±.002) 0.60±0.15 (.024±.006) 1 20 0.65(.026) C 0.32±0.06 (.013±.002) 0.13(.005) M 2012 FUJITSU SEMICONDUCTOR LIMITED HMbF80-40Sc-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 119 D a t a S h e e t 112-ball plastic PFBGA Ball pitch 0.80 mm Package width × package length 10.00 × 10.00 mm Lead shape Soldering ball Sealing method Plastic mold Ball size Ф 0.45 mm Mounting height 1.45 mm Max. Weight 0.22 g (BGA-112P-M04) 112-ball plastic PFBGA (BGA-112P-M04) 10.00±0.10(.394±.004) 0.20(.008) S B 0.80(.031) REF B 11 0.80(.031) REF 10 9 8 A 7 10.00±0.10 (.394±.004) 6 5 4 3 2 1 L K J H G F (INDEX AREA) 0.35±0.10 (.014±.004) (Stand off) 0.20(.008) S A 1.25±0.20 (.049±.008) (Seated height) ED C B A INDEX 112-Ф0.45±010 (112-Ф0.18±.004) Ф0.08(.003) M S A B S 0.10(.004) S C 2003-2010 FUJITSU SEMICONDUCTOR LIMITED B112004S-c-2-3 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 120 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t 96-pin plastic FBGA Lead pitch 0.5 mm Package width × package length 6.00 mm × 6.00 mm Lead shape Ball Sealing method Plastic mold Mounting height 1.30 mm MAX Weight 0.08 g (BGA-96P-M07) 96-pin plastic FBGA (BGA-96P-M07) 6.00±0.10(.236±.004) 5.00(.197) REF B 0.20(.008) S B 0.50 (.020) TYP 11 10 9 8 A 7 5.00(.197) REF 6.00±0.10 (.236±.004) 6 5 0.50(.020) TYP 4 3 2 1 L K J H G F E D C B A (INDEX AREA) INDEX 0.20(.008) S A 96-ø0.30±0.10 (96-ø.012±.004) ø0.05(.002) M S A B S 0.08(.003) S 1.15±0.15 (Seated height) (.045±.006) 0.25±0.10 (Stand off) (.010±.004) C 2012 FUJITSU SEMICONDUCTOR LIMITED B96007S-c-1-1 April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Dimensions in mm (inches). Note: The values in parentheses are reference values. 121 D a t a S h e e t  MAJOR CHANGES Page Section Revision 0.1 Revision 1.0 2 8 62 Change Results - Initial release Preliminary → Data Sheet Corrected the description of "Flash memory". FEATURES On-chip Memories PRODUCT LINEUP Function HANDLING DEVICES Corrected the value of channel number of the "Base Timer". BLOCK DIAGRAM 65 71, 72 MEMORY MAP Memory Map (1) Memory Map (2) PIN STATUS IN EACH CPU STATE • List of Pin Status 77, 78 ELECTRICAL CHARACTERISTICS 3. DC Characteristics (1) Current Rating 66 67 81 85, 86 87 4. AC Characteristics (2) Sub Clock Input Characteristics (3) Built-in CR Oscillation Characteristics • Built-in high-speed CR (7) External Bus Timing • Separate Bus Access Asynchronous SRAM Mode • Separate Bus Access Synchronous Mode SRAM (9) CSIO Timming 95, 97, 99, 101 106 (12) I2C Timing 5. 12-bit A/D Converter 109 111 112 Definition of 12-bit A/D Converter Terms 6. Low-Voltage Detection Characteristics (1) Low-Voltage Detection Reset (2) Interrupt of Low-Voltage Detection 113 Revision 1.1 Revision 2.0 - - - - 2 2 4 8 122  FEATURES •External Bus Interface •Multi-function Serial Interface •Multi-function Timer PRODUCT LINEUP •Function • Added the description of "Crystal oscillator circuit". • Added the description of "Sub crystal oscillator". Corrected the figure. • TIOA: input → input/output • TIOB: output → input Corrected the value of address of "SRAM0". Added the footnote. • Corrected the Return from Deep standby mode state of "Pin status type H". • Corrected the functon group of "Pin status type I". • Revised the value of "TBD". • Revised the typical value of "Power supply voltage (ICCH, ICCT, ICCR)". • Added the "Flash Memory Write/Erase current (ICCFLASH)". • Added the footnote. • Added the description of Note of "Input frequency (FCL)". • Added the footnote. • Reviced the condition. • Corrected the value. • Added the item of "Frequency stabilization time". • Added the footnote. • Corrected the value. • Deleted the "MWEX ↓ → Data output time". • Added the "MCSX ↓ → Data output time". • Corrected the figure. • Corrected the "MCLK↑ → Data output time". • Added the "MCLK↑ → Data hold time". • Corrected the figure. Corrected the description of section title. UART Timming → CSIO Timming Corrected the description of "Note". UART is connected → Multi-function Serial is connected Added the footnote. • Revised the parameter. • Revised the symbol. • Corrected the value. • Revised the parameter. • Revised the symbol. • Corrected "Conditions" and "Value" in the table. • Added the Item. • Added the footnote. Added the Item. Company name and layout design change Corrected the Series name. MB9A150R Series → MB9A150RA Series Corrected the Product name as follows. MB9AF156MA, MB9AF155MA, MB9AF154MA MB9AF156NA, MB9AF155NA, MB9AF154NA MB9AF156RA, MB9AF155RA, MB9AF154RA Added the Item. • Maximum area size : Up to 256 Mbytes Corrected the description of "I2C" Corrected the channel count of "A/D activation compare" Added the footnote MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t Page Section Change Results 9 PACKAGES Delete the following packages. •FPT-100P-M36 •FPT-80P-M40 - PIN ASSIGNMENT FPT-100P-M36 Delete the Item FPT-80P-M37 Corrected the description of section title. FPT-80P-M37/M40 →FPT-80P-M37 12 15 – 30 31 - 52 65 75 76, 77 101 101 LIST OF PIN FUNCTION •List of numbers •List of pin functions MEMORY MAP •Memory Map (1)  ELECTRICAL CHARACTERISTICS 2.Recommended Operating Conditions 3.DC Characteristics (1)Current rating (9)CSIO Timing •Synchronous serial (SPI=1, SCINV=1) (9) CSIO Timing • External clock(EXT=1):asyntironous only 102 (10)External Input Timing 105 (12)I2C Timing 108 5.12-bit A/D Converter •Electrical Characteristics for the A/D Converter 114 ORDERING INFORMATON April 4, 2014, MB9AF156RA_DS706-00047-2v0-E Delete column of terminal number "QFP-100" Delete column of terminal number "QFP-100" Corrected the address "External Device Area" Add the footnote •Corrected the Condition •Delete the minmun value •Corrected the remarks •Add the footnote Corrected the figure of "MS bit=1" Corrected the figure Add the terminal as follows •FRCKx •ICxx •DTTIxX Corrected the description as follows. •Typical mode → Standard-mode •High-speed mode → Fast-mode •Corrected the terminal name AN00 to AN23 → ANxx •Corrected the minmum value of "Sampling time" •Corrected the max and min value of "State transition time to oprerationpermission" •Corrected the footnote Corrected the "Part number" 123 D a t a S h e e t 124 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014 D a t a S h e e t April 4, 2014, MB9AF156RA_DS706-00047-2v0-E 125 D a t a S h e e t Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2012-2014 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 126 MB9AF156RA_DS706-00047-2v0-E, April 4, 2014
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