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CY9AF314LAQN-G-AVE2

CY9AF314LAQN-G-AVE2

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    64-VFQFN Exposed Pad

  • 描述:

    IC MCU 32BIT 256KB FLASH 64QFN

  • 数据手册
  • 价格&库存
CY9AF314LAQN-G-AVE2 数据手册
Spansion® Analog and Microcontroller Products The following document contains information on Spansion analog and microcontroller products. Although the document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion will continue to offer these products to new and existing customers. Continuity of Specifications There is no change to this document as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal document improvements and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “MB”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory, analog, and microcontroller products and solutions. FUJITSU SEMICONDUCTOR DATA SHEET DS706-00012-2v0-E 32-bit ARMTM CortexTM-M3 based Microcontroller MB9A310A Series MB9AF311LA/MA/NA, MB9AF312LA/MA/NA, MB9AF314LA/MA/NA, MB9AF315MA/NA, MB9AF316MA/NA  DESCRIPTION The MB9A310A Series are a highly integrated 32-bit microcontroller that target for high-performance and cost-sensitive embedded control applications. The MB9A310A Series are based on the ARM Cortex-M3 Processor and on-chip Flash memory and SRAM, and peripheral functions, including Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I2C, LIN). The products which are described in this data sheet are placed into TYPE1 product categories in " FM3 Family PERIPHERAL MANUAL ". Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries. Copyright©2011-2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2012.6 FUJITSU SEMICONDUCTOR CONFIDENTIAL r2.1 MB9A310A Series  FEATURES  32-bit ARM Cortex-M3 Core  Processor version: r2p1  Up to 40MHz Frequency Operation  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management  On-chip Memories [Flash memory]  Up to 512 Kbyte  Read cycle: 0wait-cycle  Security function for code protection [SRAM] This Series contain a total of up to 32Kbyte on-chip SRAM memories. On-chip SRAM is composed of two independent SRAM (SRAM0,SRAM1) . SRAM0 is connected to I-code bus or D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.  SRAM0: Up to 16 Kbytes  SRAM1: Up to 16 Kbytes  External Bus Interface*       Supports SRAM, NOR Flash device Up to 8 chip selects 8/16-bit Data width Up to 25-bit Address bit Supports Address/Data multiplex Supports external RDY function * : MB9AF311LA, F312LA and F314LA do not support External Bus Interface  USB Interface USB interface is composed of Function and Host. [USB function]  USB2.0 Full-Speed supported  Max 6 EndPoint supported  EndPoint 0 is control transfer  EndPoint 1,2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer  EndPoint 3,4 and 5 can be selected Bulk-transfer, Interrupt-transfer  EndPoint1-5 is comprised Double Buffer [USB host]  USB2.0 Full/Low speed supported  Bulk-transfer, interrupt-transfer and Isochronous-transfer support  USB Device connected/dis-connected automatically detect  IN/OUT token handshake packet automatically  Max 256-byte packet-length supported  Wake-up function supported 2 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series  Multi-function Serial Interface (Max 8channels)  4 channels with 16-byte FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)  Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN  I 2C [UART]  Full-duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)*  Various error detection functions available (parity errors, framing errors, and overrun errors) * : MB9AF311LA, F312LA and F314LA do not support Hardware Flow control [CSIO]  Full-duplex double buffer  Built-in dedicated baud rate generator  Overrun error detection function available [LIN]  LIN protocol Rev.2.1 supported  Full-duplex double buffer  Master/Slave mode supported  LIN break field generation (can be changed 13-16bit length)  LIN break delimiter generation (can be changed 1-4bit length)  Various error detection functions available (parity errors, framing errors, and overrun errors) [I2C] Standard mode (Max 100kbps) / High-speed mode (Max 400Kbps) supported  DMA Controller (8channels) The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.        8 independently configured and operated channels Transfer can be started by software or request from the built-in peripherals Transfer address area: 32bit(4Gbytes) Transfer mode: Block transfer/Burst transfer/Demand transfer Transfer data type: byte/half-word/word Transfer block count: 1 to 16 Number of transfers: 1 to 65536  A/D Converter (Max 16channels) [12-bit A/D Converter]  Successive Approximation type  Built-in 3unit*  Conversion time: 1.0μs@5V  Priority conversion available (priority at 2levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) * : MB9AF311LA, F312LA, F314LA built-in 2unit DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 3 r2.1 MB9A310A Series  Base Timer (Max 8channels) Operation mode is selectable from the followings for each channel.     16-bit PWM timer 16-bit PPG timer 16/32-bit reload timer 16/32-bit PWC timer  General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.      Capable of pull-up control per pin Capable of reading pin level directly Built-in the port relocate function Up to 83 fast General Purpose I/O Ports @ 100pin Package Some ports are 5V tolerant I/O (MB9AF315MA/NA, MB9AF316MA/NA only) Please see "PIN DESCRIPTION" to confirm the corresponding pins.  Multi-function Timer (Max 2unit) The Multi-function timer is composed of the following blocks.       16-bit free-run timer × 3ch/unit Input capture × 4ch/unit Output compare × 6ch/unit A/D activating compare × 3ch/unit Waveform generator × 3ch/unit 16-bit PPG timer × 3ch/unit The following function can be used to achieve the motor control.       PWM signal output function DC chopper waveform output function Dead timer function Input capture function A/D converter activate function DTIF (Motor emergency stop) interrupt function  Quadrature Position/Revolution Counter (QPRC) (Max 2unit) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter.     The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. 16-bit position counter 16-bit revolution counter Two 16-bit compare registers  Dual Timer (32/16bit Down Counter) The Dual Timer consists of two programmable 32/16-bit down counters. Operation mode is selectable from the followings for each timer channel.  Free-running  Periodic (=Reload)  One-shot 4 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series  Watch Counter The Watch counter is used for wake up from Low-Power Consumption mode.  Interval timer: up to 64s(Max)@ Sub Clock : 32.768kHz  External Interrupt Controller Unit  Up to 16 external interrupt input pins.  Include one non-maskable interrupt (NMI) input pin.  Watch dog Timer (2channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a, "Software" watchdog. The "Hardware" watchdog timer is clocked by the built-in low speed CR oscillator. Therefore, the "Hardware" watchdog is active in any low-power consumption modes except STOP.  CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  CCITT CRC16 Generator Polynomial: 0x1021  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7  Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).  Main Clock : 4MHz to 48MHz  Sub Clock : 32.768kHz  Built-in high-speed CR Clock: 4MHz  Built-in low-speed CR Clock: 100kHz  Main PLL Clock [Resets] Reset requests from INITX pins, Power on reset, Software reset, watchdog timers reset, low-voltage detection reset and clock supervisor reset.  Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.  External clock failure (clock stop) is detected, reset is asserted.  External frequency anomaly is detected, interrupt or reset is asserted.  Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 5 r2.1 MB9A310A Series  Low-Power Consumption Mode Three Low-Power Consumption modes supported.  SLEEP  TIMER  STOP  Debug  Serial Wire JTAG Debug Port (SWJ-DP)  Embedded Trace Macrocells (ETM).* *: MB9AF311LA/MA, F312LA/MA, F314LA/MA, F315MA and F316MA support only SWJ-DP.  Power Supply  Two Power Supplies  VCC = 2.7V to 5.5V: Correspond to the wide range voltage.  USBVCC = 3.0V to 3.6V: for USB I/O power supply, when USB is used. = 2.7V to 5.5V: when GPIO is used. 6 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series  PRODUCT LINEUP  Memory size Product name MB9AF311LA/MA/NA MB9AF312LA/MA/NA MB9AF314LA/MA/NA On-chip Flash On-chip SRAM Product name 64Kbytes 16Kbytes 128Kbytes 16Kbytes MB9AF315MA/NA MB9AF316MA/NA 384Kbytes 32Kbytes 512Kbytes 32Kbytes On-chip Flash On-chip SRAM 256Kbytes 32Kbytes  Function Product name Pin count MB9AF311LA MB9AF312LA MB9AF314LA 64 CPU Freq. Power supply voltage range USB2.0 interface (Function/Host) DMAC External Bus Interface - Multi-function Serial Interface (UART/CSIO/LIN/I2C) Base Timer (PWC/ Reload timer/PWM/PPG) A/D activation 3ch. compare Input 4ch. capture Free-run MF3ch. Timer timer Output 6ch. compare Waveform 3ch. generator PPG 3ch. QPRC Dual Timer Watch Counter CRC Accelerator Watchdog timer External Interrupts I/O ports 12-bit A/D converter CSV (Clock Super Visor) MB9AF311MA MB9AF312MA MB9AF314MA MB9AF315MA MB9AF316MA MB9AF311NA MB9AF312NA MB9AF314NA MB9AF315NA MB9AF316NA 80 100 Cortex-M3 40MHz 2.7V to 5.5V 1ch. 8ch. Addr:25-bit (Max) Addr:21-bit (Max) Data:8/16-bit Data:8-bit CS:8 (Max) CS:4 (Max) Support: SRAM, NOR Support: SRAM, NOR Flash Flash 8ch. (Max) ch.4 to ch.7: FIFO (16steps × 9-bit) ch.0 to ch.3: No FIFO 8ch. (Max) 1 unit 2 units (Max) 2ch. (Max) 1 unit 1 unit Yes 1ch. (SW) + 1ch. (HW) 8pins (Max)+ NMI × 1 11pins (Max)+ NMI × 1 16pins (Max)+ NMI × 1 51pins (Max) 66pins (Max) 83pins (Max) 9ch. (2 units) 12ch. (3 units) 16ch. (3 units) Yes DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 7 r2.1 MB9A310A Series Product name MB9AF311LA MB9AF312LA MB9AF314LA MB9AF311MA MB9AF312MA MB9AF314MA MB9AF315MA MB9AF316MA MB9AF311NA MB9AF312NA MB9AF314NA MB9AF315NA MB9AF316NA LVD (Low-Voltage Detector) 2ch. High-speed 4MHz (± 2%) Built-in CR Low-speed 100kHz (Typ) Debug Function SWJ-DP SWJ-DP/ETM Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. 8 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series  PACKAGES Product name Package MB9AF311LA MB9AF312LA MB9AF314LA LQFP:FPT-64P-M24/M38 (0.5mm pitch) LQFP:FPT-64P-M23/M39 (0.65mm pitch) QFN:LCC-64P-M24 (0.5mm pitch) LQFP:FPT-80P-M21/M37 (0.5mm pitch) LQFP:FPT-100P-M20/M23 (0.5mm pitch) QFP:FPT-100P-M06 (0.65mm pitch) BGA:BGA-112P-M04 (0.8mm pitch)  *    - MB9AF311MA MB9AF312MA MB9AF314MA MB9AF315MA MB9AF316MA  - MB9AF311NA MB9AF312NA MB9AF314NA MB9AF315NA MB9AF316NA   * : Supported : MB9AF315NA, MB9AF316NA are planning Note: Refer to "PACKAGE DIMENSIONS" for detailed information on each package. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 9 r2.1 MB9A310A Series  PIN ASSIGNMENT  FPT-100P-M20/M23 VSS P81/UDP0 P80/UDM0 USBVCC P60/SIN5_0/TIOA2_2/INT15_1/MRDY_1 P61/SOT5_0/TIOB2_2/UHCONX P62/SCK5_0/ADTG_3/MOEX_1 P63/INT03_0/MWEX_1 P0F/NMIX/CROUT_1 P0E/CTS4_0/TIOB3_2/IC13_0/MDQM1_1 P0D/RTS4_0/TIOA3_2/IC12_0/MDQM0_1 P0C/SCK4_0/TIOA6_1/IC11_0/MALE_1 P0B/SOT4_0/TIOB6_1/IC10_0/MCSX0_1 P0A/SIN4_0/INT00_2/FRCK1_0/MCSX1_1 P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1 P08/TRACED3/TIOA0_2/CTS4_2/MCSX3_1 P07/TRACED2/ADTG_0/SCK4_2/MCLKOUT_1 P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/MCSX4_1 P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_1 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/MCSX6_1 P01/TCK/SWCLK P00/TRSTX/MCSX7_1 VCC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (TOP VIEW) VCC 1 75 VSS P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1 2 74 P20/INT05_0/CROUT_0/AIN1_1/MAD24_1 P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1 3 73 P21/SIN0_0/INT06_1/BIN1_1 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1 4 72 P22/SOT0_0/TIOB7_1/ZIN1_1 P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1 5 71 P23/SCK0_0/TIOA7_1/RTO00_1 P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1 6 70 P1F/AN15/ADTG_5/FRCK0_1/MAD23_1 P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1 7 69 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_1 P56/INT08_2/DTTI1X_0/MADATA06_1 8 68 P1D/AN13/CTS4_1/IC03_1/MAD21_1 P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1 9 67 P1C/AN12/SCK4_1/IC02_1/MAD20_1 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10 66 P1B/AN11/SOT4_1/IC01_1/MAD19_1 P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11 65 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12 64 P19/AN09/SCK2_2/MAD17_1 P34/FRCK0_0/TIOB4_1/MADATA11_1 13 63 P18/AN08/SOT2_2/MAD16_1 P35/IC03_0/TIOB5_1/INT08_1/MADATA12_1 14 62 AVSS P36/IC02_0/SIN5_2/INT09_1/MADATA13_1 15 61 AVRH P37/IC01_0/SOT5_2/INT10_1/MADATA14_1 16 60 AVCC P38/IC00_0/SCK5_2/INT11_1/MADATA15_1 17 59 P17/AN07/SIN2_2/INT04_1/MAD15_1 P39/DTTI0X_0/ADTG_2 18 58 P16/AN06/SCK0_1/MAD14_1 P3A/RTO00_0/TIOA0_1 19 57 P15/AN05/SOT0_1/IC03_2/MAD13_1 P3B/RTO01_0/TIOA1_1 20 56 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1 P3C/RTO02_0/TIOA2_1 21 55 P13/AN03/SCK1_1/IC01_2/MAD11_1 P3D/RTO03_0/TIOA3_1 22 54 P12/AN02/SOT1_1/IC00_2/MAD10_1 P3E/RTO04_0/TIOA4_1 23 53 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1 P3F/RTO05_0/TIOA5_1 24 52 P10/AN00 VSS 25 51 VCC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCC P40/TIOA0_0/RTO10_1/INT12_1 P41/TIOA1_0/RTO11_1/INT13_1 P42/TIOA2_0/RTO12_1 P43/TIOA3_0/RTO13_1/ADTG_7 P44/TIOA4_0/RTO14_1/MAD00_1 P45/TIOA5_0/RTO15_1/MAD01_1 C VSS VCC P46/X0A P47/X1A INITX P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_1 P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_1 P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_1 P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_1 P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_1 P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_1 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 100 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 10 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series  FPT-100P-M06 P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1 VCC VSS P81/UDP0 P80/UDM0 USBVCC P60/SIN5_0/TIOA2_2/INT15_1/MRDY_1 P61/SOT5_0/TIOB2_2/UHCONX P62/SCK5_0/ADTG_3/MOEX_1 P63/INT03_0/MWEX_1 P0F/NMIX/CROUT_1 P0E/CTS4_0/TIOB3_2/IC13_0/MDQM1_1 P0D/RTS4_0/TIOA3_2/IC12_0/MDQM0_1 P0C/SCK4_0/TIOA6_1/IC11_0/MALE_1 P0B/SOT4_0/TIOB6_1/IC10_0/MCSX0_1 P0A/SIN4_0/INT00_2/FRCK1_0/MCSX1_1 P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1 P08/TRACED3/TIOA0_2/CTS4_2/MCSX3_1 P07/TRACED2/ADTG_0/SCK4_2/MCLKOUT_1 P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/MCSX4_1 P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_1 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/MCSX6_1 P01/TCK/SWCLK P00/TRSTX/MCSX7_1 VCC VSS P20/INT05_0/CROUT_0/AIN1_1/MAD24_1 P21/SIN0_0/INT06_1/BIN1_1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (TOP VIEW) P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1 81 50 P22/SOT0_0/TIOB7_1/ZIN1_1 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1 82 49 P23/SCK0_0/TIOA7_1/RTO00_1 P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1 83 48 P1F/AN15/ADTG_5/FRCK0_1/MAD23_1 P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1 84 47 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_1 P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1 85 46 P1D/AN13/CTS4_1/IC03_1/MAD21_1 P56/INT08_2/DTTI1X_0/MADATA06_1 86 45 P1C/AN12/SCK4_1/IC02_1/MAD20_1 P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1 87 44 P1B/AN11/SOT4_1/IC01_1/MAD19_1 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 88 43 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1 P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 89 42 P19/AN09/SCK2_2/MAD17_1 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 90 41 P18/AN08/SOT2_2/MAD16_1 P34/FRCK0_0/TIOB4_1/MADATA11_1 91 40 AVSS P35/IC03_0/TIOB5_1/INT08_1/MADATA12_1 92 39 AVRH P36/IC02_0/SIN5_2/INT09_1/MADATA13_1 93 38 AVCC P37/IC01_0/SOT5_2/INT10_1/MADATA14_1 94 37 P17/AN07/SIN2_2/INT04_1/MAD15_1 P38/IC00_0/SCK5_2/INT11_1/MADATA15_1 95 36 P16/AN06/SCK0_1/MAD14_1 P39/DTTI0X_0/ADTG_2 96 35 P15/AN05/SOT0_1/IC03_2/MAD13_1 P3A/RTO00_0/TIOA0_1 97 34 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1 P3B/RTO01_0/TIOA1_1 98 33 P13/AN03/SCK1_1/IC01_2/MAD11_1 P3C/RTO02_0/TIOA2_1 99 32 P12/AN02/SOT1_1/IC00_2/MAD10_1 P3D/RTO03_0/TIOA3_1 100 31 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1 28 VSS 30 27 PE3/X1 29 26 PE2/X0 VCC 25 P10/AN00 24 MD0 16 INITX 23 15 P47/X1A PE0/MD1 14 P46/X0A P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_1 13 22 12 VSS VCC P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_1 11 C 21 10 P45/TIOA5_0/RTO15_1/MAD01_1 P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_1 9 P44/TIOA4_0/RTO14_1/MAD00_1 20 8 P43/TIOA3_0/RTO13_1/ADTG_7 P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_1 7 P42/TIOA2_0/RTO12_1 19 6 P41/TIOA1_0/RTO11_1/INT13_1 18 5 P40/TIOA0_0/RTO10_1/INT12_1 P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_1 4 VCC 17 3 VSS P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_1 2 P3F/RTO05_0/TIOA5_1 P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_1 1 P3E/RTO04_0/TIOA4_1 QFP - 100 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 11 r2.1 MB9A310A Series  FPT-80P-M21/FPT-80P-M37 VSS P81/UDP0 P80/UDM0 USBVCC P60/SIN5_0/TIOA2_2/INT15_1/MRDY_1 P61/SOT5_0/TIOB2_2/UHCONX P62/SCK5_0/ADTG_3/MOEX_1 P63/INT03_0/MWEX_1 P0F/NMIX/CROUT_1 P0E/CTS4_0/TIOB3_2/IC13_0/MDQM1_1 P0D/RTS4_0/TIOA3_2/IC12_0/MDQM0_1 P0C/SCK4_0/TIOA6_1/IC11_0/MALE_1 P0B/SOT4_0/TIOB6_1/IC10_0/MCSX0_1 P0A/SIN4_0/INT00_2/FRCK1_0/MCSX1_1 P07/ADTG_0/MCLKOUT_1 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/MCSX6_1 P01/TCK/SWCLK P00/TRSTX/MCSX7_1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 (TOP VIEW) VCC 1 60 P20/INT05_0/CROUT_0/AIN1_1/MAD24_1 P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1 2 59 P21/SIN0_0/INT06_1/BIN1_1 P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1 3 58 P22/SOT0_0/TIOB7_1/ZIN1_1 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1 4 57 P23/SCK0_0/TIOA7_1 P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1 5 56 P1B/AN11/SOT4_1/IC01_1/MAD19_1 P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1 6 55 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1 P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1 7 54 P19/AN09/SCK2_2/MAD17_1 P56/INT08_2/DTTI1X_0/MADATA06_1 8 53 P18/AN08/SOT2_2/MAD16_1 P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1 9 52 AVSS P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10 51 AVRH P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11 50 AVCC P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12 49 P17/AN07/SIN2_2/INT04_1/MAD15_1 P39/DTTI0X_0/ADTG_2 13 48 P16/AN06/SCK0_1/MAD14_1 P15/AN05/SOT0_1/IC03_2/MAD13_1 LQFP - 80 30 31 32 33 34 35 36 37 38 39 40 P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_1 P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_1 P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_1 P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_1 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS VCC P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_1 41 29 20 P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_1 VSS 28 P10/AN00 INITX 42 27 19 P47/X1A P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1 P3F/RTO05_0/TIOA5_1 26 P12/AN02/SOT1_1/IC00_2/MAD10_1 43 P46/X0A 44 18 25 17 P3E/RTO04_0/TIOA4_1 VCC P3D/RTO03_0/TIOA3_1 24 P13/AN03/SCK1_1/IC01_2/MAD11_1 VSS 45 23 16 C P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1 P3C/RTO02_0/TIOA2_1 22 46 21 47 P45/TIOA5_0/MAD01_1 14 15 P44/TIOA4_0/MAD00_1 P3A/RTO00_0/TIOA0_1 P3B/RTO01_0/TIOA1_1 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 12 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series  FPT-64P-M23/M24/M38/M39 VSS P81/UDP0 P80/UDM0 USBVCC P60/SIN5_0/TIOA2_2/INT15_1 P61/SOT5_0/TIOB2_2/UHCONX P62/SCK5_0/ADTG_3 P0F/NMIX/CROUT_1 P0C/SCK4_0/TIOA6_1 P0B/SOT4_0/TIOB6_1 P0A/SIN4_0/INT00_2 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (TOP VIEW) VCC 1 48 P21/SIN0_0/INT06_1 P50/INT00_0/AIN0_2/SIN3_1 2 47 P22/SOT0_0/TIOB7_1 P51/INT01_0/BIN0_2/SOT3_1 3 46 P23/SCK0_0/TIOA7_1 P52/INT02_0/ZIN0_2/SCK3_1 4 45 P19/AN09/SCK2_2 P30/AIN0_0/TIOB0_1/INT03_2 5 44 P18/AN08/SOT2_2 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2 6 43 AVSS 42 AVRH 41 AVCC P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2 7 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 8 P39/DTTI0X_0/ADTG_2 9 40 P17/AN07/SIN2_2/INT04_1 P3A/RTO00_0/TIOA0_1 10 39 P15/AN05/IC03_2 P3B/RTO01_0/TIOA1_1 11 38 P14/AN04/INT03_1/IC02_2 P3C/RTO02_0/TIOA2_1 12 37 P13/AN03/SCK1_1/IC01_2 P3D/RTO03_0/TIOA3_1 13 36 P12/AN02/SOT1_1/IC00_2 P3E/RTO04_0/TIOA4_1 14 35 P11/AN01/SIN1_1/INT02_1/FRCK0_2 P3F/RTO05_0/TIOA5_1 15 34 P10/AN00 VSS 16 33 VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/AIN0_1 P4A/TIOB1_0/BIN0_1 P4B/TIOB2_0/ZIN0_1 P4C/TIOB3_0/SCK7_1/AIN1_2 P4D/TIOB4_0/SOT7_1/BIN1_2 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 64 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 13 r2.1 MB9A310A Series  BGA-112P-M04 1 2 3 4 5 6 7 8 9 10 11 A VSS UDP0 UDM0 USBVCC P0E P0B P07 TMS/ SWDIO TRSTX VCC VSS B VCC VSS P52 P61 P0F P0C P08 TDO/ SWO TCK/ SWCLK VSS TDI C P50 P51 VSS P60 P62 P0D P09 P05 VSS P20 P21 D P53 P54 P55 VSS P56 P63 P0A VSS P06 P23 AN15 E P30 P31 P32 P33 Index P22 AN14 AN12 AN11 F P34 P35 P36 P39 AN13 AN10 AN09 AVRH G P37 P38 P3A P3D AN08 AN07 AN06 AVSS H P3B P3C P3E VSS P44 P4C AN05 VSS AN04 AN03 AVCC J VCC P3F VSS P40 P43 P49 P4D AN02 VSS AN01 AN00 K VCC VSS X1A INITX P42 P48 P4B P4E MD1 VSS VCC L VSS C X0A VSS P41 P45 P4A MD0 X0 X1 VSS The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 14 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series  LCC-64P-M24 VSS P81/UDP0 P80/UDM0 USBVCC P60/SIN5_0/TIOA2_2/INT15_1 P61/SOT5_0/TIOB2_2/UHCONX P62/SCK5_0/ADTG_3 P0F/NMIX/CROUT_1 P0C/SCK4_0/TIOA6_1 P0B/SOT4_0/TIOB6_1 P0A/SIN4_0/INT00_2 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (TOP VIEW) VCC 1 48 P21/SIN0_0/INT06_1 P50/INT00_0/AIN0_2/SIN3_1 2 47 P22/SOT0_0/TIOB7_1 P51/INT01_0/BIN0_2/SOT3_1 3 46 P23/SCK0_0/TIOA7_1 P52/INT02_0/ZIN0_2/SCK3_1 4 45 P19/AN09/SCK2_2 P30/AIN0_0/TIOB0_1/INT03_2 5 44 P18/AN08/SOT2_2 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2 6 43 AVSS P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2 7 42 AVRH P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 8 41 AVCC P39/DTTI0X_0/ADTG_2 9 40 P17/AN07/SIN2_2/INT04_1 P3A/RTO00_0/TIOA0_1 10 39 P15/AN05/IC03_2 P3B/RTO01_0/TIOA1_1 11 38 P14/AN04/INT03_1/IC02_2 P3C/RTO02_0/TIOA2_1 12 37 P13/AN03/SCK1_1/IC01_2 P3D/RTO03_0/TIOA3_1 13 36 P12/AN02/SOT1_1/IC00_2 P3E/RTO04_0/TIOA4_1 14 35 P11/AN01/SIN1_1/INT02_1/FRCK0_2 P3F/RTO05_0/TIOA5_1 15 34 P10/AN00 VSS 16 33 VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/AIN0_1 P4A/TIOB1_0/BIN0_1 P4B/TIOB2_0/ZIN0_1 P4C/TIOB3_0/SCK7_1/AIN1_2 P4D/TIOB4_0/SOT7_1/BIN1_2 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN - 64 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 15 r2.1 MB9A310A Series  PIN DESCRIPTION The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 1 79 B1 1 LQFP-64 QFN-64 Pin name 1 VCC P50 INT00_0 AIN0_2 SIN3_1 RTO10_0 (PPG10_0) MADATA00_1 P51 INT01_0 BIN0_2 SOT3_1 (SDA3_1) RTO11_0 (PPG10_0) MADATA01_1 P52 INT02_0 ZIN0_2 SCK3_1 (SCL3_1) RTO12_0 (PPG12_0) MADATA02_1 P53 SIN6_0 TIOA1_2 INT07_2 RTO13_0 (PPG12_0) MADATA03_1 P54 SOT6_0 (SDA6_0) TIOB1_2 RTO14_0 (PPG14_0) MADATA04_1 2 2 80 C1 2 - 3 3 81 C2 3 - 4 4 82 B3 4 - 5 83 D1 5 - 6 84 D2 6 - 16 FUJITSU SEMICONDUCTOR CONFIDENTIAL I/O circuit Pin state type type - E H E H E H E H E I DS706-00012-2v0-E r2.1 MB9A310A Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 7 85 D3 7 - 8 86 D5 8 - 9 87 E1 9 5 - 10 88 E2 10 6 - 11 89 E3 11 7 - 12 90 E4 12 8 13 91 F1 - DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL - Pin name P55 SCK6_0 (SCL6_0) ADTG_1 RTO15_0 (PPG14_0) MADATA05_1 P56 INT08_2 DTTI1X_0 MADATA06_1 P30 AIN0_0 TIOB0_1 INT03_2 MADATA07_1 P31 BIN0_0 TIOB1_1 SCK6_1 (SCL6_1) INT04_2 MADATA08_1 P32 ZIN0_0 TIOB2_1 SOT6_1 (SDA6_1) INT05_2 MADATA09_1 P33 INT04_0 TIOB3_1 SIN6_1 ADTG_6 MADATA10_1 P34 FRCK0_0 TIOB4_1 MADATA11_1 I/O circuit Pin state type type E I E H E H E H E H E H E I 17 r2.1 MB9A310A Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 14 92 F2 - - 15 93 F3 - - 16 94 G1 - - 17 95 G2 - - 18 96 F4 13 9 19 97 G3 14 10 20 98 H1 15 11 21 99 H2 16 12 22 100 G4 17 13 - - B2 - - 18 FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin name P35 IC03_0 TIOB5_1 INT08_1 MADATA12_1 P36 IC02_0 SIN5_2 INT09_1 MADATA13_1 P37 IC01_0 SOT5_2 (SDA5_2) INT10_1 MADATA14_1 P38 IC00_0 SCK5_2 (SCL5_2) INT11_1 MADATA15_1 P39 DTTI0X_0 ADTG_2 P3A RTO00_0 (PPG00_0) TIOA0_1 P3B RTO01_0 (PPG00_0) TIOA1_1 P3C RTO02_0 (PPG02_0) TIOA2_1 P3D RTO03_0 (PPG02_0) TIOA3_1 VSS I/O circuit Pin state type type E H E H E H E H E I G I G I G I G I - DS706-00012-2v0-E r2.1 MB9A310A Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 23 1 H3 18 14 24 2 J2 19 15 25 26 3 4 L1 J1 20 - 16 - 27 5 J4 - - 28 6 L5 - - 29 7 K5 - - 30 8 J5 - - 31 9 H5 21 22 32 10 L6 - - - K2 J3 H4 - DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL - Pin name P3E RTO04_0 (PPG04_0) TIOA4_1 P3F RTO05_0 (PPG04_0) TIOA5_1 VSS VCC P40 TIOA0_0 RTO10_1 (PPG10_1) INT12_1 P41 TIOA1_0 RTO11_1 (PPG10_1) INT13_1 P42 TIOA2_0 RTO12_1 (PPG12_1) P43 TIOA3_0 RTO13_1 (PPG12_1) ADTG_7 P44 TIOA4_0 MAD00_1 RTO14_1 (PPG14_1) P45 TIOA5_0 MAD01_1 RTO15_1 (PPG14_1) VSS VSS VSS I/O circuit Pin state type type G I G I - G H G H G I G I G I G I - 19 r2.1 MB9A310A Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 Pin name C VSS VCC P46 X0A P47 X1A INITX P48 DTTI1X_1 INT14_1 SIN3_2 MAD02_1 P49 TIOB0_0 AIN0_1 IC10_1 SOT3_2 (SDA3_2) MAD03_1 P4A TIOB1_0 BIN0_1 IC11_1 SCK3_2 (SCL3_2) MAD04_1 P4B TIOB2_0 ZIN0_1 IC12_1 MAD05_1 P4C TIOB3_0 SCK7_1 (SCL7_1) AIN1_2 IC13_1 MAD06_1 33 34 35 11 12 13 L2 L4 K1 23 24 25 17 18 36 14 L3 26 19 37 15 K3 27 20 38 16 K4 28 21 39 17 K6 29 - 22 40 18 J6 30 - 23 41 19 L7 31 - 24 42 20 K7 32 - 25 43 21 H6 33 - 20 FUJITSU SEMICONDUCTOR CONFIDENTIAL I/O circuit Pin state type type D M D N B C E H E I E I E I E / I* I DS706-00012-2v0-E r2.1 MB9A310A Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 26 44 22 J7 34 - 45 23 K8 35 27 46 24 K9 36 28 47 25 L8 37 29 48 26 L9 38 30 49 27 L10 39 31 50 51 28 29 L11 K11 40 41 32 33 52 30 J11 42 34 53 31 J10 43 35 - 54 32 J8 44 - - K10 J9 - DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 36 - Pin name P4D TIOB4_0 SOT7_1 (SDA7_1) BIN1_2 FRCK1_1 MAD07_1 P4E TIOB5_0 INT06_2 SIN7_1 ZIN1_2 MAD08_1 MD1 PE0 MD0 X0 PE2 X1 PE3 VSS VCC P10 AN00 P11 AN01 SIN1_1 INT02_1 FRCK0_2 MAD09_1 P12 AN02 SOT1_1 (SDA1_1) IC00_2 MAD10_1 VSS VSS I/O circuit Pin state type type E / I* I E / I* I C P J D A A A B - F K F L F K - 21 r2.1 MB9A310A Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 55 33 H10 45 LQFP-64 QFN-64 37 38 56 34 H9 46 39 57 35 H7 47 - 58 36 G10 48 59 37 G9 49 60 61 62 38 39 40 H11 F11 G11 50 51 52 63 41 G8 53 - 40 41 42 43 44 - 64 42 F10 54 - - H8 - 22 FUJITSU SEMICONDUCTOR CONFIDENTIAL 45 - Pin name P13 AN03 SCK1_1 (SCL1_1) IC01_2 MAD11_1 P14 AN04 INT03_1 IC02_2 SIN0_1 MAD12_1 P15 AN05 IC03_2 SOT0_1 (SDA0_1) MAD13_1 P16 AN06 SCK0_1 (SCL0_1) MAD14_1 P17 AN07 SIN2_2 INT04_1 MAD15_1 AVCC AVRH AVSS P18 AN08 SOT2_2 (SDA2_2) MAD16_1 P19 AN09 SCK2_2 (SCL2_2) MAD17_1 VSS I/O circuit Pin state type type F K F L F K F K F L F K F K - DS706-00012-2v0-E r2.1 MB9A310A Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 65 43 F9 55 - 66 44 E11 56 - 67 45 E10 - - 68 46 F8 - - 69 47 E9 - - 70 48 D11 - - - - B10 C9 - - DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin name P1A AN10 SIN4_1 INT05_1 IC00_1 MAD18_1 P1B AN11 SOT4_1 (SDA4_1) IC01_1 MAD19_1 P1C AN12 SCK4_1 (SCL4_1) IC02_1 MAD20_1 P1D AN13 CTS4_1 IC03_1 MAD21_1 P1E AN14 RTS4_1 DTTI0X_1 MAD22_1 P1F AN15 ADTG_5 FRCK0_1 MAD23_1 VSS VSS I/O circuit Pin state type type F L F K F K F K F K F K - 23 r2.1 MB9A310A Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 57 71 49 50 46 D10 - 72 LQFP-64 QFN-64 E8 58 47 - 73 51 C11 59 48 - 74 52 C10 60 - 75 76 53 54 A11 A10 - - 77 55 A9 61 49 - 78 56 B9 62 79 57 B11 63 50 51 - 80 58 A8 64 52 81 59 B8 65 53 82 60 C8 - - - - D8 - - 24 FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin name P23 SCK0_0 (SCL0_0) TIOA7_1 RTO00_1 (PPG00_1) P22 SOT0_0 (SDA0_0) TIOB7_1 ZIN1_1 P21 SIN0_0 INT06_1 BIN1_1 P20 INT05_0 CROUT_0 AIN1_1 MAD24_1 VSS VCC P00 TRSTX MCSX7_1 P01 TCK SWCLK P02 TDI MCSX6_1 P03 TMS SWDIO P04 TDO SWO P05 TRACED0 TIOA5_2 SIN4_2 INT00_1 MCSX5_1 VSS I/O circuit Pin state type type E I E I E H E H E E E E E E E E E E E F - DS706-00012-2v0-E r2.1 MB9A310A Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 83 61 D9 - LQFP-64 QFN-64 - 66 84 62 A7 - 85 63 B7 - - 86 64 C7 - - 87 65 D7 67 54 55 88 66 A6 68 56 89 67 B6 69 - - - D4 C3 - DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL - Pin name P06 TRACED1 TIOB5_2 SOT4_2 (SDA4_2) INT01_1 MCSX4_1 P07 ADTG_0 MCLKOUT_1 TRACED2 SCK4_2 (SCL4_2) P08 TRACED3 TIOA0_2 CTS4_2 MCSX3_1 P09 TRACECLK TIOB0_2 RTS4_2 MCSX2_1 P0A SIN4_0 INT00_2 FRCK1_0 MCSX1_1 P0B SOT4_0 (SDA4_0) TIOB6_1 IC10_0 MCSX0_1 P0C SCK4_0 (SCL4_0) TIOA6_1 IC11_0 MALE_1 VSS VSS I/O circuit Pin state type type E F E G E G E G E / I* H E / I* I E / I* I - 25 r2.1 MB9A310A Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 LQFP-64 QFN-64 90 68 C6 70 - 91 69 A5 71 - 92 70 B5 72 57 93 71 D6 73 - 94 72 C5 74 58 - 95 73 B4 75 59 96 74 C4 76 97 75 A4 77 61 98 76 A3 78 62 99 77 A2 79 63 60 100 78 A1 80 64 *: 5V tolerant I/O on MB9AF315MA/NA, MB9AF316MA/NA. 26 FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin name P0D RTS4_0 TIOA3_2 IC12_0 MDQM0_1 P0E CTS4_0 TIOB3_2 IC13_0 MDQM1_1 P0F NMIX CROUT_1 P63 INT03_0 MWEX_1 P62 SCK5_0 (SCL5_0) ADTG_3 MOEX_1 P61 SOT5_0 (SDA5_0) TIOB2_2 UHCONX P60 SIN5_0 TIOA2_2 INT15_1 MRDY_1 USBVCC P80 UDM0 P81 UDP0 VSS I/O circuit Pin state type type E I E I E J E H E I E I E / I* H H O H O - DS706-00012-2v0-E r2.1 MB9A310A Series  SIGNAL DESCRIPTION The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Module Pin name ADC ADTG_0 ADTG_1 ADTG_2 ADTG_3 ADTG_4 ADTG_5 ADTG_6 ADTG_7 ADTG_8 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 TIOA0_0 TIOA0_1 TIOA0_2 TIOB0_0 TIOB0_1 TIOB0_2 TIOA1_0 TIOA1_1 TIOA1_2 TIOB1_0 TIOB1_1 TIOB1_2 TIOA2_0 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 Base Timer 0 Base Timer 1 Base Timer 2 Function A/D converter external trigger input pin A/D converter analog input pin ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 84 7 18 94 70 12 30 52 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 27 19 85 40 9 86 28 20 5 41 10 6 29 21 96 42 11 95 62 85 96 72 48 90 8 30 31 32 33 34 35 36 37 41 42 43 44 45 46 47 48 5 97 63 18 87 64 6 98 83 19 88 84 7 99 74 20 89 73 A7 D3 F4 C5 D11 E4 J5 J11 J10 J8 H10 H9 H7 G10 G9 G8 F10 F9 E11 E10 F8 E9 D11 J4 G3 B7 J6 E1 C7 L5 H1 D1 L7 E2 D2 K5 H2 C4 K7 E3 B4 66 7 13 74 12 42 43 44 45 46 47 48 49 53 54 55 56 14 30 9 15 5 31 10 6 16 76 32 11 75 9 58 8 34 35 36 37 38 39 40 44 45 10 22 5 11 23 6 12 60 24 7 59 27 r2.1 MB9A310A Series Module Pin name Base Timer 3 TIOA3_0 TIOA3_1 TIOA3_2 TIOB3_0 TIOB3_1 TIOB3_2 TIOA4_0 TIOA4_1 TIOA4_2 TIOB4_0 TIOB4_1 TIOB4_2 TIOA5_0 TIOA5_1 TIOA5_2 TIOB5_0 TIOB5_1 TIOB5_2 TIOA6_1 TIOB6_1 TIOA7_0 TIOA7_1 TIOA7_2 TIOB7_0 TIOB7_1 TIOB7_2 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 Function Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin 28 FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 30 22 90 43 12 91 31 23 44 13 32 24 82 45 14 83 89 88 71 72 - 8 100 68 21 90 69 9 1 22 91 10 2 60 23 92 61 67 66 49 50 - J5 G4 C6 H6 E4 A5 H5 H3 J7 F1 L6 J2 C8 K8 F2 D9 B6 A6 D10 E8 - 17 70 33 12 71 21 18 34 22 19 35 69 68 57 58 - 13 25 8 14 26 15 27 56 55 46 47 - DS706-00012-2v0-E r2.1 MB9A310A Series Module Pin name Debugger SWCLK External Bus Function Serial wire debug interface clock input Serial wire debug interface data input / SWDIO output SWO Serial wire viewer output TCK J-TAG test clock input TDI J-TAG test data input TDO J-TAG debug data output TMS J-TAG test mode state input/output TRACECLK Trace CLK output of ETM TRACED0 TRACED1 Trace data output of ETM TRACED2 TRACED3 TRSTX J-TAG test reset Input MAD00_1 MAD01_1 MAD02_1 MAD03_1 MAD04_1 MAD05_1 MAD06_1 MAD07_1 MAD08_1 MAD09_1 MAD10_1 MAD11_1 MAD12_1 External bus interface address bus MAD13_1 MAD14_1 MAD15_1 MAD16_1 MAD17_1 MAD18_1 MAD19_1 MAD20_1 MAD21_1 MAD22_1 MAD23_1 MAD24_1 DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 78 56 B9 62 50 80 58 A8 64 52 81 78 79 81 80 86 82 83 84 85 77 31 32 39 40 41 42 43 44 45 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 74 59 56 57 59 58 64 60 61 62 63 55 9 10 17 18 19 20 21 22 23 31 32 33 34 35 36 37 41 42 43 44 45 46 47 48 52 B8 B9 B11 B8 A8 C7 C8 D9 A7 B7 A9 H5 L6 K6 J6 L7 K7 H6 J7 K8 J10 J8 H10 H9 H7 G10 G9 G8 F10 F9 E11 E10 F8 E9 D11 C10 65 62 63 65 64 61 21 22 29 30 31 32 33 34 35 43 44 45 46 47 48 49 53 54 55 56 60 53 50 51 53 52 49 - 29 r2.1 MB9A310A Series Module Pin name External Bus MCSX0_1 MCSX1_1 MCSX2_1 MCSX3_1 MCSX4_1 MCSX5_1 MCSX6_1 MCSX7_1 MDQM0_1 MDQM1_1 MOEX_1 MWEX_1 Function External bus interface chip select output pin External bus interface byte mask signal output External bus interface read enable signal for SRAM External bus interface write enable signal for SRAM MADATA00_1 MADATA01_1 MADATA02_1 MADATA03_1 MADATA04_1 MADATA05_1 MADATA06_1 MADATA07_1 External bus interface data bus MADATA08_1 MADATA09_1 MADATA10_1 MADATA11_1 MADATA12_1 MADATA13_1 MADATA14_1 MADATA15_1 Address Latch enable signal for multiplex MRDY_1 External RDY input signal MCLKOUT_1 External bus clock output MALE_1 30 FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 88 87 86 85 83 82 79 77 90 91 66 65 64 63 61 60 57 55 68 69 A6 D7 C7 B7 D9 C8 B11 A9 C6 A5 68 67 63 61 70 71 - 94 72 C5 74 - 93 71 D6 73 - 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 C1 C2 B3 D1 D2 D3 D5 E1 E2 E3 E4 F1 F2 F3 G1 G2 2 3 4 5 6 7 8 9 10 11 12 - - 89 67 B6 69 - 96 84 74 62 C4 A7 76 66 - DS706-00012-2v0-E r2.1 MB9A310A Series Module Pin name External Interrupt INT00_0 INT00_1 INT00_2 INT01_0 INT01_1 INT02_0 INT02_1 INT03_0 INT03_1 INT03_2 INT04_0 INT04_1 INT04_2 INT05_0 INT05_1 INT05_2 INT06_1 INT06_2 INT07_2 INT08_1 INT08_2 INT09_1 INT10_1 INT11_1 INT12_1 INT13_1 INT14_1 INT15_1 NMIX Function External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 08 input pin External interrupt request 09 input pin External interrupt request 10 input pin External interrupt request 11 input pin External interrupt request 12 input pin External interrupt request 13 input pin External interrupt request 14 input pin External interrupt request 15 input pin Non-Maskable Interrupt input DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 2 82 87 3 83 4 53 93 56 9 12 59 10 74 65 11 73 45 80 60 65 81 61 82 31 71 34 87 90 37 88 52 43 89 51 23 C1 C8 D7 C2 D9 B3 J10 D6 H9 E1 E4 G9 E2 C10 F9 E3 C11 K8 2 67 3 4 43 73 46 9 12 49 10 60 55 11 59 35 2 54 3 4 35 38 5 8 40 6 7 48 27 5 83 D1 5 - 14 8 92 86 F2 D5 8 - 15 93 F3 - - 16 94 G1 - - 17 95 G2 - - 27 5 J4 - - 28 6 L5 - - 39 17 K6 29 - 96 74 C4 76 60 92 70 B5 72 57 31 r2.1 MB9A310A Series Module Pin name GPIO P00 P01 P02 P03 P04 P05 P06 P07 P08 P09 P0A P0B P0C P0D P0E P0F P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P1A P1B P1C P1D P1E P1F P20 P21 P22 P23 Function General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 32 FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 52 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 74 73 72 71 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 30 31 32 33 34 35 36 37 41 42 43 44 45 46 47 48 52 51 50 49 A9 B9 B11 A8 B8 C8 D9 A7 B7 C7 D7 A6 B6 C6 A5 B5 J11 J10 J8 H10 H9 H7 G10 G9 G8 F10 F9 E11 E10 F8 E9 D11 C10 C11 E8 D10 61 62 63 64 65 66 67 68 69 70 71 72 42 43 44 45 46 47 48 49 53 54 55 56 60 59 58 57 49 50 51 52 53 54 55 56 57 34 35 36 37 38 39 40 44 45 48 47 46 DS706-00012-2v0-E r2.1 MB9A310A Series Module Pin name GPIO P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P3A P3B P3C P3D P3E P3F P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P4A P4B P4C P4D P4E P50 P51 P52 P53 P54 P55 P56 P60 P61 P62 P63 P80 P81 PE0 PE2 PE3 Function General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 29 30 31 32 36 37 39 40 41 42 43 44 45 2 3 4 5 6 7 8 96 95 94 93 98 99 46 48 49 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 5 6 7 8 9 10 14 15 17 18 19 20 21 22 23 80 81 82 83 84 85 86 74 73 72 71 76 77 24 26 27 E1 E2 E3 E4 F1 F2 F3 G1 G2 F4 G3 H1 H2 G4 H3 J2 J4 L5 K5 J5 H5 L6 L3 K3 K6 J6 L7 K7 H6 J7 K8 C1 C2 B3 D1 D2 D3 D5 C4 B4 C5 D6 A3 A2 K9 L9 L10 9 10 11 12 13 14 15 16 17 18 19 21 22 26 27 29 30 31 32 33 34 35 2 3 4 5 6 7 8 76 75 74 73 78 79 36 38 39 5 6 7 8 9 10 11 12 13 14 15 19 20 22 23 24 25 26 27 2 3 4 60 59 58 62 63 28 30 31 33 r2.1 MB9A310A Series Module Pin name Function Multi Function Serial 0 SIN0_0 SIN0_1 SOT0_0 (SDA0_0) Multifunction serial interface ch.0 input pin Multifunction serial interface ch.0 output pin This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). Multifunction serial interface ch.0 clock I/O pin This pin operates as SCK0 when it is used in a CSIO (operation modes 2) and as SCL0 when it is used in an I2C (operation mode 4). Multifunction serial interface ch.1 input pin Multifunction serial interface ch.1 output pin This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). Multifunction serial interface ch.1 clock I/O pin This pin operates as SCK1 when it is used in a CSIO (operation modes 2) and as SCL1 when it is used in an I2C (operation mode 4). SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) Multi Function Serial 1 SIN1_1 SOT1_1 (SDA1_1) SCK1_1 (SCL1_1) 34 FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 73 56 51 34 C11 H9 59 46 48 - 72 50 E8 58 47 57 35 H7 47 - 71 49 D10 57 46 58 36 G10 48 - 53 31 J10 43 35 54 32 J8 44 36 55 33 H10 45 37 DS706-00012-2v0-E r2.1 MB9A310A Series Module Multi Function Serial 2 Pin name SIN2_2 SOT2_2 (SDA2_2) SCK2_2 (SCL2_2) Multi Function Serial 3 SIN3_1 SIN3_2 SOT3_1 (SDA3_1) SOT3_2 (SDA3_2) SCK3_1 (SCL3_1) SCK3_2 (SCL3_2) Function Multifunction serial interface ch.2 input pin Multifunction serial interface ch.2 output pin This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). Multifunction serial interface ch.2 clock I/O pin This pin operates as SCK2 when it is used in a CSIO (operation modes 2) and as SCL2 when it is used in an I2C (operation mode 4). Multifunction serial interface ch.3 input pin Multifunction serial interface ch.3 output pin This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). Multifunction serial interface ch.3 clock I/O pin This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I2C (operation mode 4). DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 59 37 G9 49 40 63 41 G8 53 44 64 42 F10 54 45 2 39 80 17 C1 K6 2 29 2 - 3 81 C2 3 3 40 18 J6 30 - 4 82 B3 4 4 41 19 L7 31 - 35 r2.1 MB9A310A Series Module Pin name Multi Function Serial 4 SIN4_0 SIN4_1 SIN4_2 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) SOT4_2 (SDA4_2) SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) SCK4_2 (SCL4_2) RTS4_0 RTS4_1 RTS4_2 CTS4_0 CTS4_1 CTS4_2 SIN5_0 SIN5_2 SOT5_0 (SDA5_0) Multi Function Serial 5 SOT5_2 (SDA5_2) SCK5_0 (SCL5_0) SCK5_2 (SCL5_2) Function Multifunction serial interface ch.4 input pin Multifunction serial interface ch.4 output pin This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). Multifunction serial interface ch.4 clock I/O pin This pin operates as SCK4 when it is used in a CSIO (operation modes 2) and as SCL4 when it is used in an I2C (operation mode 4). Multifunction serial interface ch.4 RTS output pin Multifunction serial interface ch.4 CTS input pin Multifunction serial interface ch.5 input pin Multifunction serial interface ch.5 output pin This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). Multifunction serial interface ch.5 clock I/O pin This pin operates as SCK5 when it is used in a CSIO (operation modes 2) and as SCL5 when it is used in an I2C (operation mode 4). 36 FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 87 65 82 65 43 60 D7 F9 C8 67 55 - 54 - 88 66 A6 68 55 66 44 E11 56 - 83 61 D9 - - 89 67 B6 69 56 67 45 E10 - - 84 62 A7 - - 90 69 86 91 68 85 96 15 68 47 64 69 46 63 74 93 C6 E9 C7 A5 F8 B7 C4 F3 70 71 76 - 60 - 95 73 B4 75 59 16 94 G1 - - 94 72 C5 74 58 17 95 G2 - - DS706-00012-2v0-E r2.1 MB9A310A Series Module Pin name Function Multi Function Serial 6 SIN6_0 SIN6_1 SOT6_0 (SDA6_0) Multifunction serial interface ch.6 input pin Multifunction serial interface ch.6 output pin This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). Multifunction serial interface ch.6 clock I/O pin This pin operates as SCK6 when it is used in a CSIO (operation modes 2) and as SCL6 when it is used in an I2C (operation mode 4). Multifunction serial interface ch.7 input pin Multifunction serial interface ch.7 output pin This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). Multifunction serial interface ch.7 clock I/O pin This pin operates as SCK7 when it is used in a CSIO (operation modes 2) and as SCL7 when it is used in an I2C (operation mode 4). SOT6_1 (SDA6_1) SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) Multi Function Serial 7 SIN7_1 SOT7_1 (SDA7_1) SCK7_1 (SCL7_1) DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 5 12 83 90 D1 E4 5 12 8 6 84 D2 6 - 11 89 E3 11 7 7 85 D3 7 - 10 88 E2 10 6 45 23 K8 35 27 44 22 J7 34 26 43 21 H6 33 25 37 r2.1 MB9A310A Series Module Pin name Function Multi Function Timer 0 DTTI0X_0 Input signal of wave form generator to control outputs RTO00 to RTO05 of multi-function timer 0 DTTI0X_1 FRCK0_0 FRCK0_1 FRCK0_2 IC00_0 IC00_1 IC00_2 IC01_0 IC01_1 IC01_2 IC02_0 IC02_1 IC02_2 IC03_0 IC03_1 IC03_2 RTO00_0 (PPG00_0) RTO00_1 (PPG00_1) RTO01_0 (PPG00_0) RTO02_0 (PPG02_0) RTO03_0 (PPG02_0) RTO04_0 (PPG04_0) RTO05_0 (PPG04_0) 16-bit free-run timer ch.0 external clock input pin 16-bit input capture input pin of multi-function timer 0 ICxx describes channel number. Wave form generator output of multi-function timer 0 This pin operates as PPG00 when it is used in PPG 0 output modes. Wave form generator output of multi-function timer 0 This pin operates as PPG00 when it is used in PPG 0 output modes. Wave form generator output of multi-function timer 0 This pin operates as PPG02 when it is used in PPG 0 output modes. Wave form generator output of multi-function timer 0 This pin operates as PPG02 when it is used in PPG 0 output modes. Wave form generator output of multi-function timer 0 This pin operates as PPG04 when it is used in PPG 0 output modes. Wave form generator output of multi-function timer 0 This pin operates as PPG04 when it is used in PPG 0 output modes. 38 FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 18 96 F4 13 9 69 47 E9 - - 13 70 53 17 65 54 16 66 55 15 67 56 14 68 57 91 48 31 95 43 32 94 44 33 93 45 34 92 46 35 F1 D11 J10 G2 F9 J8 G1 E11 H10 F3 E10 H9 F2 F8 H7 43 55 44 56 45 46 47 35 36 37 38 39 19 97 G3 14 10 71 49 D10 - - 20 98 H1 15 11 21 99 H2 16 12 22 100 G4 17 13 23 1 H3 18 14 24 2 J2 19 15 DS706-00012-2v0-E r2.1 MB9A310A Series Module Pin name Function Multi Function Timer 1 DTTI1X_0 Input signal of wave form generator to control outputs RTO10 to RTO15 of multi-function timer 1 16-bit free-run timer ch.1 external clock input pin DTTI1X_1 FRCK1_0 FRCK1_1 IC10_0 IC10_1 IC11_0 IC11_1 IC12_0 IC12_1 IC13_0 IC13_1 RTO10_0 (PPG10_0) RTO10_1 (PPG10_1) RTO11_0 (PPG10_0) RTO11_1 (PPG10_1) RTO12_0 (PPG12_0) RTO12_1 (PPG12_1) RTO13_0 (PPG12_0) RTO13_1 (PPG12_1) RTO14_0 (PPG14_0) RTO14_1 (PPG14_1) RTO15_0 (PPG14_0) RTO15_1 (PPG14_1) 16-bit input capture input pin of multi-function timer 1 ICxx describes channel number. Wave form generator output of multi-function timer 1 This pin operates as PPG10 when it is used in PPG 1 output modes. Wave form generator output of multi-function timer 1 This pin operates as PPG10 when it is used in PPG 1 output modes. Wave form generator output of multi-function timer 1 This pin operates as PPG12 when it is used in PPG 1 output modes. Wave form generator output of multi-function timer 1 This pin operates as PPG12 when it is used in PPG 1 output modes. Wave form generator output of multi-function timer 1 This pin operates as PPG14 when it is used in PPG 1 output modes. Wave form generator output of multi-function timer 1 This pin operates as PPG14 when it is used in PPG 1 output modes. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 8 86 D5 8 - 39 17 K6 29 - 87 44 88 40 89 41 90 42 91 43 65 22 66 18 67 19 68 20 69 21 D7 J7 A6 J6 B6 L7 C6 K7 A5 H6 67 34 68 30 69 31 70 32 71 33 - 2 80 C1 2 - 27 5 J4 - - 3 81 C2 3 - 28 6 L5 - - 4 82 B3 4 - 29 7 K5 - - 5 83 D1 5 - 30 8 J5 - - 6 84 D2 6 - 31 9 H5 21 - 7 85 D3 7 - 32 10 L6 22 - 39 r2.1 MB9A310A Series Module Pin name Quadrature Position/ Revolution Counter 0 AIN0_0 AIN0_1 AIN0_2 BIN0_0 BIN0_1 BIN0_2 ZIN0_0 ZIN0_1 ZIN0_2 AIN1_1 AIN1_2 BIN1_1 BIN1_2 ZIN1_1 ZIN1_2 UDM0 UDP0 UHCONX Quadrature Position/ Revolution Counter 1 USB Function QPRC ch.0 AIN input pin QPRC ch.0 BIN input pin QPRC ch.0 ZIN input pin QPRC ch.1 AIN input pin QPRC ch.1 BIN input pin QPRC ch.1 ZIN input pin USB Function / HOST D – pin USB Function / HOST D + pin USB external pull-up control pin 40 FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 9 40 2 10 41 3 11 42 4 74 43 73 44 72 45 98 99 95 87 18 80 88 19 81 89 20 82 52 21 51 22 50 23 76 77 73 E1 J6 C1 E2 L7 C2 E3 K7 B3 C10 H6 C11 J7 E8 K8 A3 A2 B4 9 30 2 10 31 3 11 32 4 60 33 59 34 58 35 78 79 75 5 22 2 6 23 3 7 24 4 25 26 27 62 63 59 DS706-00012-2v0-E r2.1 MB9A310A Series Module RESET Pin name INITX Mode MD0 MD1 POWER GND CLOCK ADC POWER VCC VCC VCC VCC VCC USBVCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS X0 X0A X1 X1A CROUT_0 CROUT_1 AVCC AVRH ADC GND C pin AVSS C Function External Reset Input. A reset is valid when INITX=L Mode 0 pin During normal operation, MD0=L must be input. During serial programming to flash memory, MD0=H must be input. Mode 1 pin During serial programming to flash memory, MD1=L must be input. Power supply Pin Power supply Pin Power supply pin Power supply pin Power supply pin 3.3V Power supply port for USB I/O GND Pin GND pin GND pin GND pin GND pin GND pin GND pin GND pin GND pin GND pin GND pin GND pin GND pin GND pin GND pin GND pin GND pin Main clock (oscillation) input pin Sub clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin Built-in high-speed CR-osc clock output port A/D converter analog power supply pin A/D converter analog reference voltage input pin Pin No LQFP- QFP- BGA- LQFP- LQFP100 100 112 80 64 QFN64 38 16 K4 28 21 47 25 L8 37 29 46 24 K9 36 28 1 26 35 51 76 97 25 34 50 75 100 48 36 49 37 74 92 79 4 13 29 54 75 3 12 28 53 78 26 14 27 15 52 70 B1 J1 K1 K11 A10 A4 B2 L1 K2 J3 H4 L4 L11 K10 J9 H8 B10 C9 A11 D8 D4 C3 A1 L9 L3 L10 K3 C10 B5 1 25 41 77 20 24 40 80 38 26 39 27 60 72 1 18 33 61 16 32 64 30 19 31 20 57 60 38 H11 50 41 61 39 F11 51 42 A/D converter GND pin 62 40 G11 52 43 Power stabilization capacity pin 33 11 L2 23 17 DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 41 r2.1 MB9A310A Series  I/O CIRCUIT TYPE Type Circuit Remarks  It is possible to select the A main oscillation / GPIO function P-ch X1 P-ch Digital output N-ch Digital output R Pull-up resistor control Digital input Standby mode control When the main oscillation is selected.  Oscillation feedback resistor : Approximately 1MΩ  With Standby mode control When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH = -4mA, IOL = 4mA Clock input Standby mode control Digital input Standby mode control R X0 P-ch P-ch Digital output N-ch Digital output Pull-up resistor control  CMOS level hysteresis input  Pull-up resistor B : Approximately 50kΩ Pull-up resistor Digital input 42 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series Type Circuit C Digital input Remarks  Open drain output  CMOS level hysteresis input Digital output N-ch  It is possible to select the sub D oscillation / GPIO function P-ch X1A P-ch Digital output N-ch Digital output R Pull-up resistor control Digital input Standby mode control When the sub oscillation is selected.  Oscillation feedback resistor : Approximately 5MΩ  With Standby mode control When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH = -4mA, IOL = 4mA Clock input Standby mode control Digital input Standby mode control R X0A P-ch P-ch Digital output N-ch Digital output Pull-up resistor control DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 43 r2.1 MB9A310A Series Type Circuit Remarks      E P-ch P-ch N-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ  IOH = -4mA, IOL = 4mA Digital output R Pull-up resistor control Digital input Standby mode control F P-ch P-ch Digital output N-ch Digital output R        CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ  IOH = -4mA, IOL = 4mA Pull-up resistor control Digital input Standby mode control Analog input Input control 44 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series Type Circuit Remarks      G CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ  IOH = -12mA, IOL = 12mA P-ch P-ch Digital output N-ch Digital output R Pull-up resistor control Digital input Standby mode control  It is possible to select the H GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control UDP(+)output EBP USB full-speed, low-speed control UDP(+)input Differential EBM Differential input USB IO / GPIO function. When the USB IO is selected.  Full-speed, Low-speed control When the GPIO is selected.  CMOS level output  CMOS level hysteresis input  With standby mode control  IOH = -20.5mA, IOL = 18.5mA USB/GPIO select UDM(-)input UDM(-)output USB input/output direction GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 45 r2.1 MB9A310A Series Type Circuit Remarks      I P-ch Digital output N-ch Digital output CMOS level output CMOS level hysteresis input 5V tolerant With standby mode control IOH = -4mA, IOL = 4mA R Digital input Standby mode control CMOS level hysteresis input J Mode Input 46 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series  HANDLING PRECAUTIONS Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your FUJITSU SEMICONDUCTOR semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices.  Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.  Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand.  Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.  Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Code: DS00-00004-1Ea DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 47 r1.0 MB9A310A Series  Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.  Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.  Precautions Related to Usage of Devices FUJITSU SEMICONDUCTOR semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under FUJITSU SEMICONDUCTOR's recommended conditions. For detailed information about mount conditions, contact your sales representative.  Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to FUJITSU SEMICONDUCTOR recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.  Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. FUJITSU SEMICONDUCTOR recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with FUJITSU SEMICONDUCTOR ranking of recommended conditions. 48 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r1.0 MB9A310A Series  Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use.  Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, FUJITSU SEMICONDUCTOR packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.  Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the FUJITSU SEMICONDUCTOR recommended conditions for baking. Condition: 125°C/24 h  Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 49 r1.0 MB9A310A Series 3. Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of FUJITSU SEMICONDUCTOR products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://edevice.fujitsu.com/fj/handling-e.pdf 50 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r1.0 MB9A310A Series  HANDLING DEVICES  Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin near this device.  Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation.  Using an external clock When using an external clock, the clock signal should be driven to the X0,X0A pin only and the X1,X1A pin should be kept open.  Example of Using an External Clock Device X0(X0A) Open X1(X1A)  Handling when using Multi function serial pin as I2C pin If it is using the multi function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 51 r1.0 MB9A310A Series  C Pin As this series includes a built-in regulator, always connect a bypass capacitor of approximately 4.7 µF to the C pin for use by the regulator. C Device 4.7μF VSS GND  Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistor stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise.  Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and AVSS = VSS. Turning on : VCC → USBVCC VCC → AVCC → AVRH Turning off : USBVCC → VCC AVRH → AVCC → VCC  Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data.  Differences in features among the products with different memory sizes and between Flash products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. 52 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r1.0 MB9A310A Series  BLOCK DIAGRAM TRSTX,TCK, TDI,TMS TDO TRACED[3:0], TRACECLK SWJ-DP ETM*1 TPIU*1 ROM Table Cortex-M3 Core I @40 MHz(Max) D NVIC SRAM0 8/16 Kbyte Flash I/F Security On-Chip Flash 64/128/256/384/512 Kbyte Sys SRAM1 8/16 Kbyte Dual-Timer WatchDog Timer (Software) INITX USB2.0 (Host/ Func) Clock Reset Generator WatchDog Timer (Hardware) X0A X1A UDP0/UDM0 UHCONX RST CLK X1 USBVCC DMAC 8ch CSV X0 PHY Main Osc Sub Osc PLL CR 4 MHz CR 100 kHz MAD[24:0] AVCC, AVSS,AVRH 12-bit A/D Converter x 3 External Bus I/F*2 MADATA[15:0] MCSX[7:0], MOEX,MWEX, MALE, MRDY, MCLKOUT, MDQM[1:0] Unit 0 AN[15:0] Unit 1 ADTGx TIOA[7:0] TIOB[7:0] Unit 2*2 Base Timer 16-bit 8ch. / 32-bit 4ch. Power-On Reset LVD Ctrl LVD Regulator AIN[1:0] BIN[1:0] QPRC 2ch. ZIN[1:0] A/D Activation Compare 3ch. IC0[3:0] IC1[3:0] FRCK[1:0] DTTI[1:0]X RTO0[5:0] RTO1[5:0] C IRQ-Monitor 16-bit Input Capture 4ch. 16-bit Free-Run Timer 3ch. 16-bit Output Compare 6ch. CRC Accelerator Watch Counter External Interrupt Controller 16-pin + NMI Multi-Function Timer x 2 NMIX MODE-Ctrl GPIO Waveform Generator 3ch. 16-bit PPG 3ch. INT[15:0] Multi-Function Serial I/F 8ch. (with FIFO ch.4 to 7) 2 & HW flow control(ch.4)* MD[1:0] PIN-Function-Ctrl P0[F:0], P1[F:0], . . . Px[x:0] SCK[7:0] SIN[7:0] SOT[7:0] CTS4 RTS4 *1: For the MB9AF311LA/MA, F312LA/MA, MB9AF314LA/MA, MB9AF315MA and MB9AF316MA, ETM is not available. *2: For the MB9AF311LA, F312LA and MB9AF314LA, the External Bus Interface and 12-bit A/D Converter (unit 2) are not available. And the Multi-function Serial Interface does not support hardware flow control in these products. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 53 r2.0 MB9A310A Series  MEMORY SIZE See "Memory size" in "PRODUCT LINEUP" to confirm the memory size. 54 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.0 MB9A310A Series  MEMORY MAP  MB9A310A Series Memory Map(1) Peripherals Area 0x41FF_FFFF Reserved 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M3 Private Peripherals 0x4006_1000 0x4006_0000 0x4005_0000 0x4004_0000 0x4003_F000 External Device Area 0x4003_B000 0x4003_A000 0x4003_9000 0x4003_8000 0x4003_7000 0x6000_0000 Reserved 0x4003_6000 0x4003_5000 32Mbytes Bit band alias 0x4003_4000 0x4003_3000 Peripherals 0x4003_2000 0x4003_1000 0x4400_0000 0x4200_0000 0x4000_0000 Reserved 0x2400_0000 0x2200_0000 0x4002_E000 32Mbytes Bit band alias Reserved 0x2008_0000 0x2000_0000 0x1FF8_0000 See the next page "Memory Map (2),(3)" for the memory size details. 0x0010_2000 0x0010_0000 0x4003_0000 0x4002_F000 0x4002_8000 DMAC Reserved USB ch.0 EXT-bus I/F Reserved Watch Counter CRC MFS Reserved USB Clock Ctrl LVD Reserved GPIO Reserved Int-Req.Read EXTI Reserved CR Trim Reserved 0x4002_7000 A/DC 0x4002_6000 0x4002_5000 QPRC SRAM1 SRAM0 Reserved 0x4002_2000 0x4002_1000 Security/CR Trim 0x4002_0000 Base Timer PPG Reserved MFT Unit1 MFT Unit0 0x4001_6000 Flash 0x4001_5000 0x4001_3000 0x0000_0000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved Flash I/F 55 r2.0 MB9A310A Series  MB9A310A Series Memory Map(2) MB9AF316MA/NA 0x2008_0000 MB9AF315MA/NA 0x2008_0000 Reserved 0x2000_4000 0x2000_0000 0x1FFF_C000 Reserved SRAM0 16Kbytes 0x2000_0000 0x1FFF_C000 Reserved 0x0010_2000 0x0010_1000 0x0010_0000 0x2008_0000 0x2000_4000 SRAM1 16Kbytes Reserved 0x2000_4000 SRAM1 16Kbytes SRAM0 16Kbytes 0x2000_0000 0x1FFF_C000 Reserved 0x0010_2000 CR trimming Security MB9AF314LA/MA/NA 0x0010_1000 0x0010_0000 SRAM1 16Kbytes SRAM0 16Kbytes Reserved 0x0010_2000 CR trimming Security 0x0010_1000 0x0010_0000 CR trimming Security Reserved 0x0008_0000 Reserved Reserved 0x0006_0000 0x0004_0000 Flash 512Kbytes Flash 384Kbytes Flash 256Kbytes 0x0000_0000 0x0000_0000 56 FUJITSU SEMICONDUCTOR CONFIDENTIAL 0x0000_0000 DS706-00012-2v0-E r2.0 MB9A310A Series  MB9A310A Series Memory Map(3) MB9AF312LA/MA/NA 0x2008_0000 MB9AF311LA/MA/NA 0x2008_0000 Reserved 0x2000_2000 0x2000_0000 0x1FFF_E000 Reserved 0x2000_2000 SRAM1 8Kbytes SRAM0 8Kbytes 0x2000_0000 0x1FFF_E000 Reserved 0x0010_2000 0x0010_1000 0x0010_0000 SRAM1 8Kbytes SRAM0 8Kbytes Reserved 0x0010_2000 CR trimming Security 0x0008_0000 0x0010_1000 0x0010_0000 CR trimming Security 0x0008_0000 Reserved Reserved 0x0002_0000 0x0001_0000 Flash 128Kbytes Flash 64Kbytes 0x0000_0000 DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 0x0000_0000 57 r2.0 MB9A310A Series  Peripheral Address Map Start address End address 0x4000_0000H 0x4000_1000H 0x4001_0000H 0x4001_1000H 0x4001_2000H 0x4001_3000H 0x4001_5000H 0x4001_6000H 0x4002_0000H 0x4002_1000H 0x4002_2000H 0x4002_4000H 0x4002_5000H 0x4002_6000H 0x4002_7000H 0x4002_8000H 0x4002_E000H 0x4002_F000H 0x4003_0000H 0x4003_1000H 0x4003_2000H 0x4003_3000H 0x4003_4000H 0x4003_5000H 0x4003_6000H 0x4003_7000H 0x4003_8000H 0x4003_9000H 0x4003_A000H 0x4003_B000H 0x4003_F000H 0x4004_0000H 0x4005_0000H 0x4006_0000H 0x4006_1000H 0x4006_2000H 0x4006_3000H 0x4006_4000H 0x4000_0FFFH 0x4000_FFFFH 0x4001_0FFFH 0x4001_1FFFH 0x4001_2FFFH 0x4001_4FFFH 0x4001_5FFFH 0x4001_FFFFH 0x4002_0FFFH 0x4002_1FFFH 0x4002_3FFFH 0x4002_4FFFH 0x4002_5FFFH 0x4002_6FFFH 0x4002_7FFFH 0x4002_DFFFH 0x4002_EFFFH 0x4002_FFFFH 0x4003_0FFFH 0x4003_1FFFH 0x4003_2FFFH 0x4003_3FFFH 0x4003_4FFFH 0x4003_5FFFH 0x4003_6FFFH 0x4003_7FFFH 0x4003_8FFFH 0x4003_9FFFH 0x4003_AFFFH 0x4003_EFFFH 0x4003_FFFFH 0x4004_FFFFH 0x4005_FFFFH 0x4006_0FFFH 0x4006_1FFFH 0x4006_2FFFH 0x4006_3FFFH 0x41FF_FFFFH Bus AHB APB0 APB1 APB2 AHB 58 FUJITSU SEMICONDUCTOR CONFIDENTIAL Peripherals Flash I/F register Reserved Clock/Reset Control Hardware Watchdog timer Software Watchdog timer Reserved Dual-Timer Reserved Multi-function timer unit0 Multi-function timer unit1 Reserved PPG Base Timer Quadrature Position/Revolution Counter A/D Converter Reserved Built-in CR trimming Reserved External Interrupt Controller Interrupt Source Check Register Reserved GPIO Reserved Low-Voltage Detector USB clock generator Reserved Multi-function serial CRC Watch Counter Reserved External bus interface USB ch.0 Reserved DMAC register Reserved Reserved Reserved Reserved DS706-00012-2v0-E r2.0 MB9A310A Series  PIN STATUS IN EACH CPU STATE The terms used for pin status have the following meanings.  INITX = 0 This is the period when the INITX pin is the "L" level.  INITX = 1 This is the period when the INITX pin is the "H" level.  SPL = 0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".  SPL = 1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".  Input enabled Indicates that the input function can be used.  Internal input fixed at "0" This is the status that the input function cannot be used. Internal input is fixed at "L".  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 59 r2.0 MB9A310A Series  LIST OF PIN STATUS Pin status type Function group A GPIO selected B Main crystal oscillator input pin GPIO selected Power-on reset Run mode or INITX input Device internal Timer mode or STOP mode or low voltage sleep mode state reset state state detection state state Power supply Power supply Power supply stable Power supply stable unstable stable INITX=0 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 Setting Setting Setting Maintain Maintain Hi-Z/ disabled disabled disabled previous previous Internal state state input fixed at "0" Input enabled Input Input Input Input Input enabled enabled enabled enabled enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Main crystal oscillator output pin Hi-Z/ Internal input fixed at "0"/ or Input enabled Hi-Z/ Internal input fixed at "0" Hi-Z/ Internal input fixed at "0" Maintain previous state C INITX input pin Pull-up/ Input enabled D Mode input pin Input enabled E JTAG selected Hi-Z Setting disabled Pull-up/ Input enabled Input enabled Pull-up/ Input enabled Setting disabled Pull-up/ Input enabled Input enabled Maintain previous state GPIO selected Pull-up/ Input enabled Input enabled Pull-up/ Input enabled Setting disabled Maintain previous state/ Hi-Z at oscillation stop*1/ Internal input fixed at "0" Pull-up/ Input enabled Input enabled Maintain previous state Trace selected External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state GPIO selected, or resource other than above selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Maintain previous state/ Hi-Z at oscillation stop*1/ Internal input fixed at "0" Pull-up/ Input enabled Input enabled Maintain previous state Hi-Z/ Internal input fixed at "0" Trace output Maintain previous state Hi-Z/ Internal input fixed at "0" F 60 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.0 MB9A310A Series Pin status type Function group G Trace selected H I J GPIO selected, or resource other than above selected External interrupt enabled selected Power-on reset Run mode or INITX input Device internal Timer mode or STOP mode or low voltage sleep mode state reset state state detection state state Power supply Power supply Power supply stable Power supply stable unstable stable INITX=0 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 Setting Setting Setting Maintain Maintain Trace output disabled disabled disabled previous previous state state Hi-Z Hi-Z/ Hi-Z/ Hi-Z/ Input Input Internal enabled enabled input fixed at "0" Setting disabled Setting disabled Setting disabled Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z Hi-Z/ Input enabled NMIX selected Setting disabled GPIO selected, or resource other than above selected Hi-Z GPIO selected, or resource other than above selected GPIO selected, resource selected Maintain previous state Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Hi-Z/ Input enabled Maintain previous state Maintain previous state Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z/ Internal input fixed at "0" Maintain previous state Hi-Z/ Internal input fixed at "0" DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 61 r2.0 MB9A310A Series Pin status type K L M Function group Analog input selected GPIO selected, or resource other than above selected External interrupt enabled selected Power-on reset Run mode or INITX input Device internal Timer mode or STOP mode or low voltage sleep mode state reset state state detection state state Power supply Power supply Power supply stable Power supply stable unstable stable INITX=0 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 Hi-Z Hi-Z/ Hi-Z/ Hi-Z/ Hi-Z/ Hi-Z/ Internal Internal Internal Internal Internal input fixed input fixed input fixed input fixed input fixed at "0"/ at "0"/ at "0"/ at "0"/ at "0"/ Analog Analog Analog Analog Analog input input input input input enabled enabled enabled enabled enabled Setting Setting Setting Maintain Maintain Hi-Z/ disabled disabled disabled previous previous Internal state state input fixed at "0" Setting disabled Setting disabled Setting disabled Analog input selected Hi-Z GPIO selected, or resource other than above selected GPIO selected Setting disabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Setting disabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Setting disabled Setting disabled Setting disabled Input enabled Input enabled Sub crystal oscillator input pin 62 FUJITSU SEMICONDUCTOR CONFIDENTIAL Maintain previous state Hi-Z/ Internal input fixed at "0"/ Analog input enabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0"/ Analog input enabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0" Setting disabled Maintain previous state Maintain previous state Input enabled Input enabled Input enabled Hi-Z/ Internal input fixed at "0" Input enabled DS706-00012-2v0-E r2.0 MB9A310A Series Pin status type Function group N GPIO selected Sub crystal oscillator output pin O GPIO selected USB I/O pin P Mode input pin GPIO selected Power-on reset Run mode or INITX input Device internal Timer mode or STOP mode or low voltage sleep mode state reset state state detection state state Power supply Power supply Power supply stable Power supply stable unstable stable INITX=0 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 Setting Setting Setting Maintain Maintain Hi-Z/ disabled disabled disabled previous previous Internal state state input fixed at "0" Hi-Z/ Hi-Z/ Hi-Z/ Maintain Maintain Maintain Internal input Internal Internal previous previous previous fixed at "0"/ input fixed input fixed state state/ Hi-Z state/ Hi-Z or Input at "0" at "0" at at enabled oscillation oscillation stop*2/ stop*2/ Internal Internal input fixed input fixed at "0" at "0" Hi-Z Hi-Z/ Hi-Z/ Maintain Maintain Hi-Z/ Input Input previous previous Internal enabled enabled state state input fixed at "0" Setting Setting Setting Maintain Hi-Z at Hi-Z at disabled disabled disabled previous transmission transmission state / Input / Input enabled/ enabled/ Internal Internal input fixed input fixed at "0" at at "0" at reception reception Input enabled Input Input Input Input Input enabled enabled enabled enabled enabled Setting Setting Setting Maintain Maintain Hi-Z/Input disabled disabled disabled previous previous enabled state state *1 : Oscillation is stopped at sub timer mode, low speed CR timer mode, and stop mode. *2 : Oscillation is stopped at stop mode. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 63 r2.0 MB9A310A Series  ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage*1, *2 Power supply voltage (for USB) *1, *3 Analog power supply voltage*1, *4 Analog reference voltage*1, *4 Symbol Vcc USBVcc AVcc AVRH Rating Min Max Unit Remarks Vss - 0.5 Vss - 0.5 Vss - 0.5 Vss - 0.5 Vss + 6.5 V Vss + 6.5 V Vss + 6.5 V Vss + 6.5 V Except for Vcc + 0.5 V Vss - 0.5 USB pin (≤ 6.5V) Input voltage*1 VI USBVcc + 0.5 V USB pin Vss - 0.5 (≤ 6.5V) Vss - 0.5 Vss + 6.5 V 5V tolerant AVcc + 0.5 V Analog pin input voltage*1 VIA Vss - 0.5 (≤ 6.5V) Vcc + 0.5 V Output voltage*1 VO Vss - 0.5 (≤ 6.5V) 10 mA 4mA type "L" level maximum output current*5 IOL 20 mA 12mA type 4 mA 4mA type 6 "L" level average output current* IOLAV 12 mA 12mA type "L" level total maximum output current ∑IOL 100 mA "L" level total average output current*7 ∑IOLAV 50 mA - 10 mA 4mA type 5 "H" level maximum output current* IOH - 20 mA 12mA type -4 mA 4mA type "H" level average output current*6 IOHAV - 12 mA 12mA type "H" level total maximum output current ∑IOH - 100 mA "H" level total average output current*7 ∑IOHAV - 50 mA Power consumption PD 300 mW Storage temperature TSTG - 55 + 150 °C *1 : These parameters are based on the condition that Vss = AVss = 0.0V. *2 : Vcc must not drop below Vss - 0.5V. *3 : USBVcc must not drop below Vss - 0.5V. *4 : Be careful not to exceed Vcc + 0.5 V, for example, when the power is turned on. *5 : The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *6 : The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *7 : The total average output current is defined as the average current value flowing through all of corresponding pins for a 100ms. Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 64 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series 2. Recommended Operating Conditions (Vss = AVss = 0.0V) Parameter Power supply voltage Power supply voltage (3V power supply) for USB Analog power supply voltage Analog reference voltage FPT-100P-M20 FPT-100P-M23 FPT-80P-M21 FPT-80P-M37 FPT-64P-M24 FPT-64P-M38 FPT-64P-M23 FPT-64P-M39 LCC-64P-M24 Operating BGA-112P-M04 temperature Symbol Conditions Vcc - Value Min Max 2.7 AVcc AVRH - 2.7 AVss 5.5 3.6 (≤ Vcc) 5.5 (≤ Vcc) 5.5 AVcc Ta - - 40 + 105 3.0 USBVcc 2.7 When mounted on - 40 + 105 four-layer PCB FPT-100P-M06 Ta When - 40 + 105 mounted on double-sided - 40 + 85 single-layer PCB *1: When P81/UDP0 and P80/UDM0 pin are used as USB (UDP0, UDM0). *2: When P81/UDP0 and P80/UDM0 pin are used as GPIO (P81, P80). Unit Remarks V *1 V *2 V V °C AVcc = Vcc °C °C Icc ≤ 35mA °C Icc > 35mA The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 65 r2.1 MB9A310A Series 3. DC Characteristics  Current rating (Vcc = AVcc = 2.7V to 5.5V, USBVcc = 3.0V to 3.6V, Vss = AVss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Min Value Typ Max Unit Power supply current Vcc Iccs CPU : 40MHz, Peripheral : 40MHz, Flash 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 *1 CPU : 40MHz, Peripheral : 40MHz, Flash 3Wait FRWTR.RWT = 00 FSYNDN.SD = 011 *1 CPU/ Peripheral : 4MHz *1, *2 Flash 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU/ Peripheral : 32kHz Flash 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 *1 CPU/ Peripheral : 100kHz Flash 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 *1 - 32 41 mA - 21 28 mA Normal operation (built-in high-speed CR) Vcc = 5.5V - 3.9 7.7 mA Normal operation (sub oscillation) Vcc = 5.5V - 0.15 3.2 mA Normal operation (built-in low-speed CR) Vcc = 5.5V - 0.2 3.3 mA - 10 15 mA Peripheral : 40MHz *1 - 1.2 4.4 mA Peripheral : 4MHz *1, *2 - 0.1 3.1 mA Peripheral : 32kHz *1 - 0.1 3.1 mA Peripheral : 100kHz *1 Normal operation (PLL) Vcc = 5.5V Icc Remarks SLEEP operation (PLL) Vcc = 5.5V SLEEP operation (built-in high-speed CR) Vcc = 5.5V SLEEP operation (sub oscillation) Vcc = 5.5V SLEEP operation (built in low-speed CR) Vcc = 5.5V 66 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series Parameter Symbol Pin name Conditions Unit - 35 200 μA - - 3 mA - 60 230 μA - - 3.1 mA - 4 7 μA STOP mode Vcc = 5.5V ICCH Power supply current ICCT Min Value Typ Max Vcc TIMER mode (sub oscillation) Vcc = 5.5V Low-voltage detection At operation circuit (LVD) ICCLVD Vcc = 5.5V power supply current *1: When all ports are fixed. *2: When setting it to 4MHz by trimming. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Remarks Ta = + 25°C, When LVD is off *1 Ta = + 105°C, When LVD is off *1 Ta = + 25°C, When LVD is off *1 Ta = + 105°C, When LVD is off *1 For occurrence of interrupt 67 r2.1 MB9A310A Series  Pin Characteristics (Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name "H" level input voltage (hysteresis input) VIHS "L" level input voltage (hysteresis input) VILS CMOS hysteresis input pin, MD0,1 5V tolerant I/O pin CMOS hysteresis input pin, MD0,1 4mA type "H" level output voltage VOH 12mA type The pin doubled as USB I/O 4mA type "L" level output voltage VOL 12mA type The pin doubled as USB I/O Input leak current Pull-up resistor value Input capacitance IIL - RPU Pull-up pin CIN Other than Vcc, Vss, AVcc, AVss, AVRH Min Value Typ Max - Vcc × 0.8 - Vcc + 0.3 V - Vcc × 0.8 - Vss + 5.5 V - Vss - 0.3 - Vcc × 0.2 V Vcc - 0.5 - Vcc V Vcc - 0.5 - Vcc V Vcc - 0.4 - Vcc V Vss - 0.4 V Vss - 0.4 V Vss - 0.4 V - -5 - +5 μA Vcc ≥ 4.5 V 25 50 100 Vcc < 4.5 V 30 80 200 - - 5 15 Conditions Vcc ≥ 4.5 V IOH = - 4mA Vcc < 4.5 V IOH = - 2mA Vcc ≥ 4.5 V IOH = - 12mA Vcc < 4.5 V IOH = - 8mA Vcc ≥ 4.5 V IOH = - 20.5mA Vcc < 4.5 V IOH = - 13.0mA Vcc ≥ 4.5 V IOL = 4mA Vcc < 4.5 V IOL = 2mA Vcc ≥ 4.5 V IOL = 12mA Vcc < 4.5 V IOL = 8mA Vcc ≥ 4.5 V IOL = 18.5mA Vcc < 4.5 V IOL = 10.5mA 68 FUJITSU SEMICONDUCTOR CONFIDENTIAL Unit Remarks kΩ pF DS706-00012-2v0-E r2.1 MB9A310A Series 4. AC Characteristics (1) Main Clock Input Characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Pin Symbol Conditions name Input frequency Input clock cycle Input clock pulse width Input clock rising time and falling time Internal operating clock frequency Internal operating clock cycle time FCH tCYLH X0 X1 tCF tCR Value Min Max Unit Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V PWH/tCYLH PWL/tCYLH 4 4 4 4 20.83 50 48 20 48 20 250 250 45 55 % - - 5 ns MHz MHz ns FCM - - - 40 MHz FCC - - - 40 MHz FCP0 - - - 40 MHz FCP1 - - - 40 MHz FCP2 - - - 40 MHz tCYCC - - 25 - ns tCYCP0 - - 25 - ns tCYCP1 - - 25 - ns tCYCP2 - - 25 - ns Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock When using external clock Master clock Base clock (HCLK/FCLK) APB0 bus clock (PCLK0) APB1 bus clock (PCLK1) APB2 bus clock (PCLK2) Base clock (HCLK/FCLK) APB0 bus clock (PCLK0) APB1 bus clock (PCLK1) APB2 bus clock (PCLK2) tCYLH 0.8 × Vcc X0 0.8 × Vcc 0.8 × Vcc 0.2 × Vcc 0.2 × Vcc PWH PWL tCF tCR Note: For about each APB bus which each peripheral is connected to, see " BLOCK DIAGRAM" in this data sheet. For more information about each internal operating clock, see "Chapter: Clock" in "FM3 Family PERIPHERAL MANUAL". DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 69 r2.1 MB9A310A Series (2) Sub Clock Input Characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Min Value Typ Max - - 32.768 - kHz - 32 - 100 kHz Pin Symbol Conditions name Input frequency Unit FCL X0A X1A Input clock cycle tCYLL - 10 - 31.25 μs Input clock pulse width - PWH/tCYLL PWL/tCYLL 45 - 55 % Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock tCYLL 0.8 × Vcc 0.8 × Vcc X0A 0.8 × Vcc 0.2 × Vcc 0.2 × Vcc PWH PWL (3) Built-in CR Oscillation Characteristics  Built-in high-speed CR (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Clock frequency Symbol FCRH Min Value Typ Max Ta = + 25°C 3.96 4 4.04 Ta = 0°C to + 70°C 3.84 4 4.16 Conditions Unit Remarks When trimming* MHz Ta = 3.8 4 4.2 - 40°C to + 105°C Ta = 3 4 5 When not trimming - 40°C to + 105°C *: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.  Built-in low-speed CR (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Clock frequency Symbol Conditions FCRL - 70 FUJITSU SEMICONDUCTOR CONFIDENTIAL Min Value Typ Max 50 100 150 Unit Remarks kHz DS706-00012-2v0-E r2.1 MB9A310A Series (4-1) Operating Conditions of Main and USB PLL (In the case of using main clock for input clock of PLL) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Value Unit Min Typ Max Remarks PLL oscillation stabilization wait time tLOCK 100 μs (LOCK UP time)* PLL input clock frequency fPLLI 4 16 MHz PLL multiple rate 13 75 multiple PLL macro oscillation clock frequency fPLLO 200 300 MHz *: Time from when the PLL starts operating until the oscillation stabilizes. (4-2) Operating Conditions of Main PLL (In the case of using the built-in high speed CR for the input clock of the main PLL) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Value Unit Min Typ Max Remarks PLL oscillation stabilization wait time tLOCK 100 μs (LOCK UP time)* PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiple rate 50 71 multiple PLL macro oscillation clock frequency fPLLO 190 300 MHz *: Time from when the PLL starts operating until the oscillation stabilizes. Note: Make sure to input the built-in high-speed CR clock that has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. (5) Reset Input Characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Reset input time Symbol tINITX Value Pin Conditions name Min Max INITX 500 - - Unit Remarks ns (6) Power-on Reset Timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Power supply rising time Tr Power supply shut down time Toff Pin name Vcc Tr Value Unit Min Max 0 - ms 1 - ms Remarks Toff 2.7V Vcc 0.2V 0.2V DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 0.2V 71 r2.1 MB9A310A Series (7) External Bus Timing  External bus clock output Characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Min Max Unit Vcc ≥ 4.5 V 40 MHz Vcc < 4.5 V 32 MHz MCLKOUT Vcc ≥ 4.5 V 25 ns Minimum clock cycle time Vcc < 4.5 V 31.25 ns Note: The external bus clock output is a divided clock of HCLK. For more information about setting of clock divider, see "Chapter: External Bus Interface" in "FM3 Family PERIPHERAL MANUAL" When external bus clock is not output, this characteristics does not give any effect on external bus operation. Output frequency tCYCLE tCYCLE 0.8 × Vcc 0.8 × Vcc MCLKOUT 0.8 × Vcc 0.2 × Vcc 0.2 × Vcc PWH PWL  External bus signal input/output Characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Signal input characteristics Signal output characteristics Symbol Conditions VIH VIL VOH - VOL Input signal VIH VIL VIH VIL Output signal VOH VOL VOH VOL 72 FUJITSU SEMICONDUCTOR CONFIDENTIAL Value Unit 0.8 × VCC V 0.2 × VCC V 0.8 × VCC V 0.2 × VCC V Remarks DS706-00012-2v0-E r2.1 MB9A310A Series  Separate Bus Access Asynchronous SRAM Mode (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Min MOEX Vcc ≥ 4.5V tOEW MOEX MCLK×n-3 Min pulse width Vcc < 4.5V MCSX ↓→ Address MCSX[7:0] Vcc ≥ 4.5V -9 tCSL – AV output delay time MAD[24:0] Vcc < 4.5V -12 MOEX MOEX ↑ → Vcc ≥ 4.5V 0 tOEH - AX MAD[24:0] Address hold time Vcc < 4.5V MCSX ↓→ Vcc ≥ 4.5V MCLK×m-9 tCSL - OEL MOEX ↓ delay time MOEX Vcc < 4.5V MCLK×m-12 MCSX[7:0] MOEX ↑ → Vcc ≥ 4.5V 0 tOEH - CSH MCSX ↑ time Vcc < 4.5V MCSX MCSX ↓ → Vcc ≥ 4.5V MCLK×m-9 tCSL - RDQML MDQM[1:0] MDQM ↓ delay time Vcc < 4.5V MCLK×m-12 MOEX Data set up → Vcc ≥ 4.5V 20 tDS - OE MADATA[15:0] MOEX ↑ time Vcc < 4.5V 38 MOEX MOEX ↑ → Vcc ≥ 4.5V 0 tDH - OE MADATA[15:0] Data hold time Vcc < 4.5V MWEX Vcc ≥ 4.5V tWEW MWEX MCLK×n-3 Min pulse width Vcc < 4.5V MWEX MWEX ↑ → Address Vcc ≥ 4.5V 0 tWEH - AX MAD[24:0] output delay time Vcc < 4.5V MCSX ↓ → Vcc ≥ 4.5V MCLK×n-9 tCSL - WEL MWEX ↓ delay time MWEX Vcc < 4.5V MCLK×n-12 MCSX[7:0] MWEX ↑ → Vcc ≥ 4.5V 0 tWEH - CSH MCSX ↑ delay time Vcc < 4.5V MCSX MCSX ↓ → Vcc ≥ 4.5V MCLK×n-9 tCSL-WDQML MDQM[1:0] MDQM ↓ delay time Vcc < 4.5V MCLK×n-12 MWEX ↓ → Vcc ≥ 4.5V -9 tWEL - DV Data output time MWEX Vcc < 4.5V -12 MADATA[15:0] MWEX ↑ → Vcc ≥ 4.5V 0 tWEH - DX Data hold time Vcc < 4.5V Note: When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16). DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Max +9 + 12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 - Unit ns ns ns ns ns ns ns - ns - ns MCLK×m+9 MCLK×m+12 MCLK×n+9 MCLK×n+12 MCLK×m+9 MCLK×m+12 MCLK×n+9 MCLK×n+12 +9 + 12 MCLK×m+9 MCLK×m+12 ns ns ns ns ns ns 73 r2.1 MB9A310A Series tCYCLE MCLK tWEH - CSH tOEH - CSH MCSX[7:0] tCSL - AV MAD[24:0] tOEH - AX tCSL - AV Address Address tCSL - OEL tOEW MOEX tCSL -WDQML tCSL - RDQML MDQM[1:0] MWEX MADATA[15:0] tWEH - AX tCSL -WEL tWEW tDS - OE tDH - OE RD 74 FUJITSU SEMICONDUCTOR CONFIDENTIAL tWEL -DV tWEH -DX WD DS706-00012-2v0-E r2.1 MB9A310A Series  Separate Bus Access Synchronous SRAM Mode (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Address delay time Symbol Pin name Conditions tAV MCLK MAD[24:0] Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V tCSL MCSX delay time tCSH tREL MOEX delay time tREH Data set up → MCLK ↑ time MCLK ↑→ Data hold time tDS tDH tWEL MWEX delay time tWEH MDQM[1:0] delay time tDQML tDQMH MCLK MCSX[7:0] MCLK MOEX MCLK MADATA[15:0] MCLK MADATA[15:0] MCLK MWEX MCLK MDQM[1:0] MCLK MCLK ↑ → tOD MADATA[15:0] Data output time Note: When the external load capacitance CL = 30pF. Value Min Max 9 12 9 12 9 12 9 12 9 12 1 1 1 1 1 Unit ns ns ns ns ns 19 37 - ns 0 - ns 9 12 9 12 9 12 9 12 18 24 1 1 1 1 1 1 ns ns ns ns ns tCYCLE MCLK tCSH MCSX[7:0] MAD[24:0] MOEX tCSL tAV tAV Address Address tREL tREH tDQMH tDQML MDQM[1:0] MWEX MADATA[15:0] tDS RD DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL tDH tDQML tDQMH tWEL tWEH tOD tOD WD 75 r2.1 MB9A310A Series  Multiplexed Bus Access Asynchronous SRAM Mode (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Value Conditions Min Max Vcc ≥ 4.5V Vcc < 4.5V 0 10 20 Vcc ≥ 4.5V MCLK×n+0 MCLK×n+10 Vcc < 4.5V MCLK×n+0 Note: When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16). MCLK×n+20 Multiplexed Address delay time tALE-CHMADV Multiplexed Address hold time tCHMADH MALE MADATA[15:0] Unit ns ns tCYCLE MCLK MCSX[7:0] MALE Address MAD [24:0] Address MOEX MDQM [1:0] MWEX MADATA[15:0] Address RD tALE - CHMADV 76 FUJITSU SEMICONDUCTOR CONFIDENTIAL Address WD tALE - CHMADV tCHMADH DS706-00012-2v0-E r2.1 MB9A310A Series  Multiplexed Bus Access Synchronous SRAM Mode (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol tCHAL MALE delay time tCHAH Pin name Conditions MCLK ALE Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V MCLK ↑ → Multiplexed tCHMADV Address delay time MCLK MADATA[15:0] MCLK ↑ → tCHMADX Multiplexed Data output time Note: When the external load capacitance CL = 30pF. Vcc ≥ 4.5V Min Value Max Unit Remarks 9 12 9 12 ns ns ns ns 1 tOD ns 1 tOD ns 1 1 Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V tCYCLE MCLK MCSX[7:0] tCHAH MALE tCHAL MAD [24:0] Address Address MOEX MDQM [1:0] MWEX MADATA[15:0] tCHMADV Address Address RD tCHMADV DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL WD tCHMADX 77 r2.1 MB9A310A Series  External Ready Input Timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol MCLK ↑ MRDY input setup time tRDYI Pin name Conditions MCLK MRDY Value Min Vcc ≥ 4.5V 19 Vcc < 4.5V 37 Max - Unit Remarks ns  When RDY is input ··· MCLK Over 2cycles Original MOEX MWEX tRDYI MRDY  When RDY is released MCLK ··· ··· 2 cycles Extended MOEX MWEX tRDYI 0.5×VCC MRDY 78 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series (8) Base Timer Input Timing  Timer input timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Input pulse width Symbol Pin name Conditions tTIWH tTIWL TIOAn/TIOBn (when using as ECK,TIN) - tTIWH ECK TIN VIHS Value Min Max 2tCYCP - Unit Remarks ns tTIWL VIHS VILS VILS  Trigger input timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Input pulse width Symbol Pin name Conditions tTRGH tTRGL TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS Value Min Max 2tCYCP - Unit Remarks ns tTRGL VIHS VILS VILS Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see "BLOCK DIAGRAM" in this data sheet. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 79 r2.1 MB9A310A Series (9) UART Timing  Synchronous serial (SPI = 0, SCINV = 0) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Pin Symbol Conditions name Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑→ SIN hold time tSHIXE SCK falling time SCK rising time Notes: tF tR SCKx SCKx SOTx Internal shift clock SCKx operation SINx SCKx SINx SCKx External shift SOTx clock SCKx operation SINx SCKx SINx SCKx SCKx Vcc < 4.5V Min Max Vcc ≥ 4.5V Min Max Unit 4tcycp - 4tcycp - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns 2tcycp 10 tcycp + 10 - 2tcycp 10 tcycp + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30pF. 80 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI SIN tSHIXI VIH VIL VIH VIL MS bit = 0 tSLSH SCK VIH tF SOT SIN tSHSL VIL VIL VIH VIH tR tSLOVE VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 81 r2.1 MB9A310A Series  Synchronous serial (SPI = 0, SCINV = 1) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Pin Symbol Conditions name Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓ → SIN hold time tSLIXI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓ → SIN hold time tSLIXE SCK falling time SCK rising time Notes: tF tR SCKx SCKx SOTx Internal shift clock SCKx operation SINx SCKx SINx SCKx External shift SOTx clock SCKx operation SINx SCKx SINx SCKx SCKx Vcc < 4.5V Min Max Vcc ≥ 4.5V Min Max Unit 4tcycp - 4tcycp - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns 2tcycp 10 tcycp + 10 - 2tcycp 10 tcycp + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30pF. 82 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI SIN VIH VIL tSLIXI VIH VIL MS bit = 0 tSHSL SCK VIL tR SOT tSLSH VIH VIH VIL VIL tF tSHOVE VOH VOL tIVSLE VIH VIL SIN tSLIXE VIH VIL MS bit = 1 DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 83 r2.1 MB9A310A Series  Synchronous serial(SPI = 1, SCINV = 0) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Pin Symbol Conditions name Serial clock cycle time tSCYC SCK ↑→ SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓ → SIN hold time tSLIXI SOT → SCK ↓ delay time tSOVLI Serial clock "L" pulse width tSLSH Serial clock "H" pulse width tSHSL SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓ → SIN hold time tSLIXE SCK falling time SCK rising time Notes: tF tR Vcc < 4.5V Min Max SCKx 4tcycp SCKx - 30 SOTx SCKx Internal shift 50 clock SINx operation SCKx 0 SINx 2tcycp SCKx 30 SOTx 2tcycp SCKx 10 tcycp + SCKx 10 SCKx External shift SOTx clock SCKx operation 10 SINx SCKx 20 SINx SCKx SCKx Vcc ≥ 4.5V Min Max Unit - 4tcycp - ns + 30 - 20 + 20 ns - 30 - ns - 0 - ns - ns - ns - ns - 2tcycp 30 2tcycp 10 tcycp + 10 50 - 30 ns - 10 - ns - 20 - ns 5 5 - 5 5 ns ns  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30pF. 84 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series tSCYC VOH SCK SOT VOL tSOVLI VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI VIH VIL MS bit = 0 tSLSH SCK VIH tR VIH tSHOVE VOH VOL VOH VOL tIVSLE SIN VIH VIL tF * SOT VIL tSHSL tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 85 r2.1 MB9A310A Series  Synchronous serial (SPI = 1, SCINV = 1) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Pin Symbol Conditions name Vcc < 4.5V Min Max Vcc ≥ 4.5V Min Max Unit Serial clock cycle time tSCYC SCKx 4tcycp - 4tcycp - ns SCK ↓→ SOT delay time tSLOVI SCKx SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI 50 - 30 - ns SCK ↑ →SIN hold time tSHIXI 0 - 0 - ns SOT → SCK ↑ delay time tSOVHI - ns Serial clock "L" pulse width tSLSH SCKx - ns Serial clock "H" pulse width tSHSL SCKx - ns SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK falling time SCK rising time Notes: tF tR SCKx Internal shift clock SINx operation SCKx SINx SCKx SOTx SCKx External shift SOTx clock SCKx operation SINx SCKx SINx SCKx SCKx 2tcycp 30 2tcycp 10 tcycp + 10 - 2tcycp 30 2tcycp 10 tcycp + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance CL = 30pF. 86 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series tSCYC VOH SCK VOH VOL tSOVHI tSLOVI VOH VOL SOT VOH VOL tSHIXI tIVSHI VIH VIL SIN VIH VIL MS bit = 0 tSHSL tR SCK tSLSH VIH VIH VIL tF VIL VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE tSHIXE VIH VIL SIN VIH VIL MS bit = 1  External clock (EXT = 1) : asynchronous only (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Conditions Serial clock "L" pulse width Serial clock "H" pulse width SCK falling time SCK rising time tSLSH tSHSL tF tR CL = 30pF tR SCK VIL Min Max tcycp + 10 tcycp + 10 - 5 5 tSHSL VIH DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL VIL ns ns ns ns tF tSLSH VIH Unit Remarks VIL VIH 87 r2.1 MB9A310A Series (10) External input timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Value Unit Min Max Conditions Remarks A/D converter trigger input ns Free-run timer input 2tCYCP*1 FRCKx clock tINH Input pulse width Input capture ICxx tINL Wave form DTTIxX 2tCYCP*1 ns generator INT00 to INT15, 2tCYCP + 100*1 ns External interrupt NMIX 500*2 ns NMI *1 : tCYCP indicates the APB bus clock cycle time except stop when in stop mode, in timer mode. About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see "BLOCK DIAGRAM" in this data sheet. *2 : When in stop mode, in timer mode. ADTG tINH VILS tINL VILS 88 FUJITSU SEMICONDUCTOR CONFIDENTIAL VIHS VIHS DS706-00012-2v0-E r2.1 MB9A310A Series (11) Quadrature Position/Revolution Counter timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Value Conditions Min Max Unit AIN pin "H" width tAHL AIN pin "L" width tALL BIN pin "H" width tBHL BIN pin "L" width tBLL PC_Mode2 or BIN rise time from tAUBU PC_Mode3 AIN pin "H" level PC_Mode2 or AIN fall time from tBUAD PC_Mode3 BIN pin "H" level PC_Mode2 or BIN fall time from tADBD PC_Mode3 AIN pin "L" level PC_Mode2 or AIN rise time from tBDAU PC_Mode3 BIN pin "L" level PC_Mode2 or AIN rise time from ns 2tCYCP * tBUAU PC_Mode3 BIN pin "H" level PC_Mode2 or BIN fall time from tAUBD PC_Mode3 AIN pin "H" level PC_Mode2 or AIN fall time from tBDAD PC_Mode3 BIN pin "L" level PC_Mode2 or BIN rise time from tADBU PC_Mode3 AIN pin "L" level ZIN pin "H" width tZHL QCR:CGSC = "0" ZIN pin "L" width tZLL QCR:CGSC = "0" AIN/BIN rise and fall time tZABE QCR:CGSC = "1" from determined ZIN level Determined ZIN level from tABEZ QCR:CGSC = "1" AIN/BIN rise and fall time * :tCYCP indicates the APB bus clock cycle time except stop. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "BLOCK DIAGRAM" in this data sheet. tAHL tALL AIN tAUBU tBUAD tADBD tBDAU BIN tBHL tBLL DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 89 r2.1 MB9A310A Series tBHL tBLL BIN tBUAU tAUBD tBDAD tADBU AIN tAHL tALL tZHL ZIN tZLL ZIN tABEZ tZABE AIN/BIN 90 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series 2 (12) I C timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Conditions Typical mode Min Max High-speed mode Min Max Unit Remarks SCL clock frequency FSCL 0 100 0 400 kHz (Repeated) START condition hold time tHDSTA 4.0 0.6 μs SDA ↓→ SCL ↓ SCLclock "L" width tLOW 4.7 1.3 μs SCLclock "H" width tHIGH 4.0 0.6 μs (Repeated) START condition setup time tSUSTA 4.7 0.6 μs CL = 30pF, SCL ↑ → SDA ↓ R= Data hold time (Vp/IOL)*1 tHDDAT 0 3.45*2 0 0.9*3 μs SCL ↓ → SDA ↓ ↑ Data setup time tSUDAT 250 100 ns SDA ↓ ↑ → SCL ↑ STOP condition setup time tSUSTO 4.0 0.6 μs SCL ↑ → SDA ↑ Bus free time between "STOP condition" and tBUF 4.7 1.3 μs "START condition" Noise filter tSP 2 tCYCP*4 2 tCYCP*4 ns *1 : R and C represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2 : The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal. *3 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4 : tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see "BLOCK DIAGRAM" in this data sheet. To use I2C, set the APB bus clock at 8 MHz or more. SDA tSUDAT tLOW tSUSTA tBUF SCL tHDSTA tHDDAT tHIGH DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL tHDSTA tSP tSUSTO 91 r2.1 MB9A310A Series (13) ETM timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Data hold TRACECLK frequency Symbol Pin name tETMH TRACECLK TRACED[3:0] Conditions Value Unit Min Max Vcc ≥ 4.5V 2 9 Vcc < 4.5V 2 15 Vcc ≥ 4.5V - 40 MHz Vcc < 4.5V - 32 MHz Vcc ≥ 4.5V 25 - ns Vcc < 4.5V 31.25 - ns Remarks ns 1/tTRACE TRACECLK TRACECLK Clock cycle time tTRACE Note: When the external load capacitance CL = 30pF. tCYCC HCLK VOH VOH tTRACE TRACECLK TRACED[3:0] VOH VOL tETMH tETMH VOH VOL 92 FUJITSU SEMICONDUCTOR CONFIDENTIAL VOH VOH VOL DS706-00012-2v0-E r2.1 MB9A310A Series (14) JTAG timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name TMS, TDI setup time tJTAGS TMS, TDI hold time tJTAGH TDO delay time tJTAGD TCK TMS,TDI TCK TMS,TDI TCK TDO Conditions Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Value Min Max Unit 15 - ns 15 - ns - 25 - 45 Remarks ns Note: When the external load capacitance CL = 30pF. TCK VOH VOL tJTAGS VOH VOL TMS/TDI tJTAGH VOH VOL tJTAGD TDO DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL VOH VOL 93 r2.1 MB9A310A Series 5. 12-bit A/D Converter  Electrical Characteristics for the A/D Converter (Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 105°C) Parameter Resolution Non-linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Compare clock cycle*3 State transition time to operation permission Power supply current (analog + digital) Reference power supply current (between AVRH and AVSS) Value Typ Pin name Min - - 4.5 - 12 + 4.5 bit LSB - - 2.5 - + 2.5 LSB - + 20 mV - AVRH+20 mV - - μs AN0 to - 20 AN15 AN0 to AVRH-20 AN15 1.0*1 *2 Ts *2 Max Unit ns Tcck 50 - 2000 ns Tstt 1.0 - - μs AVCC - 0.57 0.06 0.72 20 mA μA - 1.1 1.96 mA - 0.06 4 μA 12.9 pF AVRH Analog input capacity Cin - - Analog input resistor Rin - - Interchannel disparity Analog port input current 2 3.8 4 kΩ Remarks AVRH = 2.7V to 5.5V AVcc ≥ 4.5V AVcc ≥ 4.5V AVcc < 4.5V A/D 1unit operation When A/D stops A/D 1unit operation AVRH = 5.5V When A/D stops AVcc ≥ 4.5V AVcc < 4.5V LSB AN0 to 5 μA AN15 AN0 to AVSS AVRH V Analog input voltage AN15 Reference voltage AVRH 2.7 AVCC V *1: The conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is when the value of sampling time: 300ns, the value of compare time: 700ns (AVcc ≥ 4.5V). Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck). For setting of the sampling time and compare clock cycle, see "Chapter: A/D Converter" in "FM3 Family PERIPHERAL MANUAL Analog Macro Part". The A/D Converter register is set at APB bus clock timing. The sampling clock and compare clock are set at Base clock (HCLK). *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1) *3: The compare time (Tc) is the value of (Equation 2) 94 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series Rext Analog signal source AN0 to AN31 Analog input pin Comparator Rin Cin (Equation 1) Ts ≥ (Rin + Rext) × Cin × 9 Ts Rin Cin Rext : Sampling time : input resistor of A/D = 2kΩ 4.5 ≤ AVCC ≤ 5.5 input resistor of A/D = 3.8kΩ 2.7 ≤ AVCC < 4.5 : input capacity of A/D = 12.9pF 2.7 ≤ AVCC ≤ 5.5 : Output impedance of external circuit (Equation 2) Tc = Tcck × 14 Tc Tcck : Compare time : Compare clock cycle DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 95 r2.1 MB9A310A Series  Definition of 12-bit A/D Converter Terms  Resolution  Linearity error : Analog variation that is recognized by an A/D converter. : Deviation of the line between the zero-transition point (0b000000000000←→0b000000000001) and the full-scale transition point (0b111111111110←→0b111111111111) from the actual conversion characteristics.  Differential linearity error : Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Linearity error 0xFFF Actual conversion characteristics 0xFFE Actual conversion characteristics 0x(N+1) {1 LSB(N-1) + VOT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD Differential linearity error Actual conversion characteristics Ideal characteristics 0x002 0x001 0xN Ideal characteristics (Actually-measured value) VNT (Actually-measured value) 0x(N-2) VOT (Actually-measured value) AVss V(N+1)T 0x(N-1) Actual conversion characteristics AVRH AVss AVRH Analog input Linearity error of digital output N = Analog input VNT - {1LSB × (N - 1) + VOT} 1LSB Differential linearity error of digital output N = 1LSB = N VOT VFST VNT : : : : V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VOT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. 96 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series 6. USB characteristics (Vcc = 2.7V to 5.5V,USBVcc = 3.0V to 3.6V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin Conditions name Input High level voltage VIH - Input Low level voltage Input charact- Differential input eristics sensitivity Different common mode range VIL - VDI - VCM - Min 2.0 Vss 0.3 Value Max Unit Remarks USBVcc + 0.3 V *1 0.8 V *1 0.2 - V *2 0.8 2.5 V *2 External pull-down 2.8 3.6 V *3 Output High level voltage VOH resistance = 15kΩ UDP0, External UDM0 pull-up 0.0 0.3 V *3 Output Low level voltage VOL resistance Output = 1.5kΩ charact- Crossover voltage VCRS 1.3 2.0 V *4 eristics Rising time tFR Full Speed 4 20 ns *5 Falling time tFF Full Speed 4 20 ns *5 Rise/fall time matching tFRFM Full Speed 90 111.11 % *5 Output impedance ZDRV Full Speed 28 44 Ω *6 Rising time tLR Low Speed 75 300 ns *7 Falling time tLF Low Speed 75 300 ns *7 Rise/fall time matching tLRFM Low Speed 80 125 % *7 *1 : The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8V, VIH (Min) = 2.0 V (TTL input standard). There are some hysteresis to lower noise sensitivity. Minimum differential input sensitivity [V] *2 : Use differential-Receiver to receive USB differential data signal. Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level. Above voltage range is the common mode input voltage range. 1.0 0.2 0.8 2.5 Common mode input voltage [V] DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 97 r2.1 MB9A310A Series *3 : The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to the ground and 1.5 kΩ load) at High-State (VOH). *4 : The cross voltage of the external differential output signal (D + /D −) of USB I/O buffer is within 1.3 V to 2.0 V. D+ Max 2.0V Min 1.3V D- VCRS specified range *5 : They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission. D+ 90% D- 90% 10% 10% Trise Rising time Tfall Falling time Full-speed Buffer Rs=27Ω TxD+ CL=50pF TxD- Rs=27Ω CL=50pF 3-State Enable 98 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series *6 : USB Full-speed connection is performed via twist pair cable shield with 90Ω ± 15% characteristic impedance(Differential Mode). USB standard defines that output impedance of USB driver must be in range from 28Ωto 44Ω. So, discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB FLS I/O, use it with 25Ω to 30Ω (recommendation value 27Ω) series resistor Rs. Full-speed Buffer Rs TxD+ Rs TxD3-State Enable 28Ω to 44Ω Equiv. Imped. 28Ω to 44Ω Equiv. Imped. Mount it as external resistance. Rs series resistor 25Ω to 30Ω Series resistor of 27Ω (recommendation value) must be added. And, use "resistance with an uncertainty of 5% by E24 sequence". *7 : They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. D+ 90% D- 90% 10% Trise Rising time 10% Tfall Falling time See "· Low-Speed Load (Compliance Load)" for conditions of external load. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 99 r2.1 MB9A310A Series  Low-Speed Load (Upstream Port Load) - Reference 1 Low-speed Buffer Rs=27Ω TxD+ CL = 50pF to 150pF Rpd Rs=27Ω TxD- Rpd CL = 50pF to 150pF 3-State Enable Rpd=15kΩ  Low-Speed Load (Downstream Port Load) - Reference 2 Low-speed Buffer Rs=27Ω VTERM TxD+ CL =200pF to 600pF Rs=27Ω TxD- CL =200pF to 600pF 3-State Enable Rpu Rpu=1.5kΩ VTERM=3.6V  Low-Speed Load (Compliance Load) Low-speed Buffer Rs=27Ω TxD+ CL = 200pF to 450pF TxD- Rs=27Ω CL = 200pF to 450pF 3-State Enable 100 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series 7. Low-voltage detection characteristics  Low-voltage detection reset (Ta = - 40°C to + 105°C) Parameter Detected voltage Released voltage Symbol Conditions VDL VDH - Min Value Typ Max 2.25 2.30 2.45 2.50 Min Value Typ Max 2.65 2.70 Unit V V Remarks When voltage drops When voltage rises  Interrupt of low-voltage detection (Ta = - 40°C to + 105°C) Parameter Symbol Conditions Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH LVD stabilization wait time TLVDW SVHI = 0000 SVHI = 0001 SVHI = 0010 SVHI = 0011 SVHI = 0100 SVHI = 0111 SVHI = 1000 SVHI = 1001 Unit 2.58 2.67 2.76 2.85 2.94 3.04 3.31 3.40 3.40 3.50 3.68 3.77 3.77 3.86 3.86 3.96 2.8 2.9 3.0 3.1 3.2 3.3 3.6 3.7 3.7 3.8 4.0 4.1 4.1 4.2 4.2 4.3 3.02 3.13 3.24 3.34 3.45 3.56 3.88 3.99 3.99 4.10 4.32 4.42 4.42 4.53 4.53 4.64 V V V V V V V V V V V V V V V V - - 2240 × tcycp * μs - Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises * : tCYCP indicates the APB2 bus clock cycle time. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 101 r2.1 MB9A310A Series 8. Flash Memory Write/Erase Characteristics (Vcc = 2.7V to 5.5V, Ta = - 40°C to + 105°C) Parameter Sector erase time Large Sector Small Sector Half word (16 bit) write time Chip 64K/128K/256KByte erase time 384K/512KByte Value Typ Max - 0.7 0.3 3.7 1.1 s - 12 384 μs - 5.2 8 23.6 38.4 s s Min Value Remarks Includes write time prior to internal erase Not including system-level overhead time. Includes write time prior to internal erase Write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) 1,000 20* Remarks 10,000 10* 100,000 5* *:This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at + 85°C) . 102 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r2.1 MB9A310A Series  ORDERING INFORMATION Part number MB9AF311LAPMC1 MB9AF312LAPMC1 MB9AF314LAPMC1 MB9AF311LAPMC MB9AF312LAPMC MB9AF314LAPMC MB9AF311LAQN MB9AF312LAQN MB9AF314LAQN Package Plastic  LQFP(0.5mm pitch),64-pin (FPT-64P-M24/M38) Plastic  LQFP(0.65mm pitch),64-pin (FPT-64P-M23/M39) Plastic  QFN(0.5mm pitch),64-pin (LCC-64P-M24) MB9AF311MAPMC MB9AF312MAPMC MB9AF314MAPMC MB9AF315MAPMC Plastic  LQFP(0.5mm pitch),80-pin (FPT-80P-M21/M37) MB9AF316MAPMC MB9AF311NAPMC MB9AF312NAPMC MB9AF314NAPMC MB9AF315NAPMC Plastic  LQFP(0.5mm pitch),100-pin (FPT-100P-M20/M23) MB9AF316NAPMC MB9AF311NAPF MB9AF312NAPF MB9AF314NAPF MB9AF315NAPF Plastic  QFP(0.65mm pitch), 100-pin (FPT-100P-M06) MB9AF316NAPF MB9AF311NABGL MB9AF312NABGL MB9AF314NABGL DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Plastic  PFBGA(0.8mm pitch),112-pin (BGA-112P-M04) 103 r4.0 MB9A310A Series  PACKAGE DIMENSIONS 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.0 mm × 14.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.65 g Code (Reference) P-LFQFP100-14×14-0.50 (FPT-100P-M20) 100-pin plastic LQFP (FPT-100P-M20) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ *14.00±0.10(.551±.004)SQ 51 75 76 50 0.08(.003) Details of "A" part +0.20 26 100 "A" 1 25 0.50(.020) C +.008 1.50 –0.10 .059 –.004 (Mounting height) INDEX 0.20 ±0.05 (.008 ±.002) 0.08(.003) M 0.145±0.055 (.006 ±.002) 2005 -2010 FUJITSU SEMICONDUCTOR LIMITED F100031S-c-3-5 0°~8° 0.50 ±0.20 (.020 ±.008) 0.60 ±0.15 (.024 ±.006) 0.10 ±0.10 (.004 ±.004) (Stand off) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 104 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r1.0 MB9A310A Series 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.00 mm × 14.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.65 g (FPT-100P-M23) 100-pin plastic LQFP (FPT-100P-M23) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ *14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part 1.50 +0.20 - 0.10 (.059+.008 -.004) (Mounting height) INDEX 100 26 "A" 1 C 0.60±0.15 (.024±.006) 25 0.50(.020) 0.22±0.05 (.009±.002) 0.08(.003) 0°~8° 0.50±0.20 (.020±.008) M 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 0.145±0.055 (.006±.002) 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4 Dimensions in mm (inches). Note:The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 105 r1.0 MB9A310A Series 100-pin plastic QFP Lead pitch 0.65 mm Package width × package length 14.00 × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 1 30 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" C 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8° 31 100 2002-2010 FUJITSU SEMICONDUCTOR LIMITED F100008S-c-5-7 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 106 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r1.0 MB9A310A Series 80-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 12 mm × 12 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.47 g Code (Reference) P-LFQFP80-12×12-0.50 (FPT-80P-M21) 80-pin plastic LQFP (FPT-80P-M21) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00±0.20(.551±.008)SQ * 12.00±0.10(.472±.004)SQ 60 0.145±0.055 (.006±.002) 41 40 61 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 INDEX 0°~8° 21 80 "A" LEAD No. 1 20 0.50(.020) C 0.10±0.05 (.004±.002) (Stand off) 0.20±0.05 (.008±.002) 0.08(.003) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) M 2006-2010 FUJITSU SEMICONDUCTOR LIMITED F80035S-c-2-4 Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 107 r1.0 MB9A310A Series 80-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g (FPT-80P-M37) 80-pin plastic LQFP (FPT-80P-M37) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00± 0.20(.551 ± .008)SQ *12.00± 0.10(.472 ± .004)SQ 60 0.145± 0.055 (.006 ± .002) 41 Details of "A" part 40 61 +0.20 1.50 –0.10 (Mounting height) +.008 .059 –.004 0.25(.010) 0~8° 0.08(.003) INDEX 0.50 ± 0.20 (.020 ± .008) 0.60 ± 0.15 (.024 ± .006) 0.10 ± 0.05 (.004 ± .002) (Stand off) 21 80 "A" 1 20 0.50(.020) 0.22± 0.05 (.009± .002) C 0.08(.003) M 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 108 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r1.0 MB9A310A Series 64-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 10.0 × 10.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g Code (Reference) P-LFQFP64-10×10-0.50 (FPT-64P-M24) 64-pin plastic LQFP (FPT-64P-M24) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ *10.00±0.10(.394±.004)SQ 48 0.145±0.055 (.006±.002) 33 32 49 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 INDEX 0°~8° 17 64 0.10±0.10 (.004±.004) (Stand off) "A" LEAD No. 1 16 0.50(.020) 0.20±0.05 (.008±.002) C 0.08(.003) M 2005-2010 FUJITSU SEMICONDUCTOR LIMITED F64036S-c-1-3 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 109 r1.0 MB9A310A Series 64-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 10.00 mm × 10.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g (FPT-64P-M38) 64-pin plastic LQFP (FPT-64P-M38) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ *10.00±0.10(.394±.004)SQ 48 0.145 ± 0.055 (.006 ± .002) 33 Details of "A" part 32 49 0.08(.003) +0.20 1.50 –0.10 (Mounting height) .059 +.008 –.004 0.25(.010) 0~8° INDEX 17 64 1 0.22±0.05 (.009±.002) 0.10 ± 0.10 (.004±.004) (Stand off) "A" 16 0.50(.020) C 0.50±0.20 (.020±.008) 0.60 ± 0.15 (.024±.006) 0.08(.003) M 2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 110 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r1.0 MB9A310A Series 64-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 12.0 × 12.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g Code (Reference) P-LQFP64-12 × 12-0.65 (FPT-64P-M23) 64-pin plastic LQFP (FPT-64P-M23) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00± 0.20(.551± .008)SQ *12.00± 0.10(.472± .004)SQ 48 0.145± 0.055 (.006 ± .002) 33 49 32 0.10(.004) Details of "A" part +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 0.25(.010) INDEX 0~8° 64 17 1 0.65(.026) C "A" 16 0.32 ± 0.05 (.013 ± .002) 0.13(.005) 0.50 ± 0.20 (.020 ± .008) 0.60 ± 0.15 (.024 ± .006) 0.10 ± 0.10 (.004 ± .004) (Stand off) M 2003-2010 FUJITSU SEMICONDUCTOR LIMITED F64034S-c-1-4 Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 111 r1.0 MB9A310A Series 64-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g (FPT-64P-M39) 64-pin plastic LQFP (FPT-64P-M39) Note 1) Pins width and pins thickness include plating thickness. 14.00±0.20(.551±.008)SQ 12.00±0.10(.472±.004)SQ 48 0.145±0.055 (.006±.002) 33 Details of "A" part 32 49 +0.20 1.50 –0.10 +.008 .059 –.004 0.10(.004) INDEX 1 16 0.65(.026) C 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 17 64 0.32±0.05 (.013±.002) 0~8˚ 0.10±0.10 (.004±.004) 0.25(.010)BSC "A" 0.13(.005) M 2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 112 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r1.0 MB9A310A Series 112-ball plastic PFBGA Ball pitch 0.80 mm Package width × package length 10.00 × 10.00 mm Lead shape Soldering ball Sealing method Plastic mold Ball size Ф 0.45 mm Mounting height 1.45 mm Max. Weight 0.22 g (BGA-112P-M04) 112-ball plastic PFBGA (BGA-112P-M04) 10.00±0.10(.394±.004) 0.20(.008) S B 0.80(.031) REF B 11 10 9 8 7 6 5 4 3 2 0.80(.031) REF A 10.00±0.10 (.394±.004) 1 L K J H G F (INDEX AREA) 0.35±0.10 (.014±.004) (Stand off) 0.20(.008) S A 1.25±0.20 (.049±.008) (Seated height) ED C B A INDEX 112-Ф0.45±010 (112-Ф0.18±.004) Ф0.08(.003) M S A B S 0.10(.004) S C 2003-2010 FUJITSU SEMICONDUCTOR LIMITED B112004S-c-2-3 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 113 r1.0 MB9A310A Series 64-pin plastic QFN Lead pitch 0.50 mm Package width × package length 9.00 mm × 9.00 mm Sealing method Plastic mold Mounting height 0.90 mm MAX Weight - (LCC-64P-M24) 64-pin plastic QFN (LCC-64P-M24) 9.00±0.10 (.354±.004) 6.00±0.10 (.236±.004) 9.00±0.10 (.354±.004) 0.25±0.05 (.010±.002) 6.00±0.10 (.236±.004) INDEX AREA 0.45 (.018) 1PIN ID (0.20R (.008R)) 0.85±0.05 (.033±.002) 0.05 (.002) MAX C 0.50 (.020) (TYP) 0.40±0.05 (.016±.002) (0.20 (.008)) 2011 FUJITSU SEMICONDUCTOR LIMITED HMbC64-24Sc-2-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 114 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS706-00012-2v0-E r1.0 MB9A310A Series  MAJOR CHANGES IN THIS EDITION A change on a page is indicated by a vertical line drawn on the left side of that page. Page Section Change Results  Revised series name and part number: - - MB9A310 Series → MB9A310A Series MB9AF311L → MB9AF311LA MB9AF312L → MB9AF312LA MB9AF314L → MB9AF314LA MB9AF311M → MB9AF311MA MB9AF312M → MB9AF312MA MB9AF314M → MB9AF314MA MB9AF315M → MB9AF315MA MB9AF316M → MB9AF316MA MB9AF311N → MB9AF311NA MB9AF312N → MB9AF312NA MB9AF314N → MB9AF314NA MB9AF315N → MB9AF315NA MB9AF316N → MB9AF316NA  Added the following package. LCC-64P-M24 PRODUCT LINEUP Function Multi-function Serial Added the following description. ch.4 to ch.7: FIFO (16steps × 9-bit) ch.0 to ch.3: No FIFO External Interrupts Corrected the following description. 7pins (Max) → 8pins (Max) 7 SIGNAL DESCRIPTION 34 to 37 Multi-function Serial (ch.0 to ch.7) I/O CIRCUIT TYPE Corrected the description for function.  Added "LIN pin"  Deleted "UART pin"  Corrected the following schematic for "TypeB". CMOS level hysteresis input → Digital input 42, 43  Corrected the following schematic for "TypeC". Control Pin → Digital output 51 HANDLING DEVICE  Power supply pins Corrected the description. 54 MEMORY SIZE Added "MEMORY SIZE ". 69 ELECTRICAL CHARACTERISTICS 4. AC Characteristics (1)Main Clock input Characteristics Added the items FCM to the Internal operating clock frequency. 71 (4-2) Operating Conditions of Main PLL  Added the description. 72 (7) External Bus Timing  External bus clock output Characteristics 79 (8) Base Timer Input Timing  Trigger input timing Added the Note. 88 (10) External input timing  Corrected the footnote. DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 115 r3.0 MB9A310A Series Page Section 5. 12-bit A/D Converter (1) Electrical characteristics for the A/D converter 94 Change Results  Corrected the value of "Full-scale transition voltage". Min: -20 → AVRH-20 Max: +20 → AVRH+20  Corrected the value of "Compare clock cycle". Max: 10000 → 2000  Corrected the value of "Reference voltage". Min: AVSS → 2.7 116 FUJITSU MICROELECTRONICS CONFIDENTIAL r2.0 MB9A310A Series DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 117 r3.0 MB9A310A Series 118 FUJITSU MICROELECTRONICS CONFIDENTIAL r2.0 MB9A310A Series DS706-00012-2v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 119 r3.0 MB9A310A Series FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. 30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District, Shanghai 201204, China Tel : +86-21-6146-3688 Fax : +86-21-6146-3660 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department 120 FUJITSU MICROELECTRONICS CONFIDENTIAL r2.0
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